JP2637018B2 - Programmable logic device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device (hereinafter, referred to as PLD). In particular, program data for programming the PLD
The present invention relates to a type of PLD that operates as a predetermined logic circuit by reading from an external nonvolatile storage element.

[0002]

2. Description of the Related Art In recent years, so-called PLDs in which a user can freely program its functions have been widely used. The programming for the PLD is generally performed by writing program data to a memory inside the PLD. This memory is a classic PLD
Used a ROM, but in this case, the program was limited to only one, and the
It was difficult to change the program loaded on D.

[0003] With this background, as a device for storing program data in a PLD, a volatile static RAM (hereinafter simply referred to as RA) is used instead of a nonvolatile ROM.
M), PLDs that write program data from an external nonvolatile storage element to an internal RAM and start operation after the writing is completed have come to be widely used.

Such a PLD is disclosed, for example, in US Pat.
No. 870,302. FIG. 3 shows an example of a partial configuration block diagram of the PLD. As shown in FIG. 3, the PLD includes a plurality of unit logic elements 2. The characteristic feature of the PLD is that, as shown in FIG. The program data is read from the external ROM 4 or the like every time it is turned on, and the program data is stored in the internal volatile RAM. FIG. 4 shows a state in which a plurality of PLDs to be programmed by the RAM are programmed by program data from one external nonvolatile memory element. First, program data is read into the programmable logic device 6a directly connected to the external nonvolatile storage element 4 (ROM). Next, program data is sent to the programmable logic device 6b through the data line, and the writing of the programmable logic device 6b is completed. Hereinafter, similarly,
The program data is also transferred to the logic devices 6c and 6d, and the writing to the last programmable logic device 6d is completed. The transfer and writing of the program data described above are performed simultaneously with the program data in synchronization with the clock signal sent from the programmable logic device 6a, so that the program data transfer and the program data writing without error are performed.

According to this operation, program data is sequentially written to a predetermined address of the RAM inside each unit logic element 2. The time required to write all data is about 10 msec. After the writing is completed, the PLD starts an operation having the function. A RAM for storing program data read from an external nonvolatile storage element is included in each unit logic element 2 and is not shown in FIG. FIG. 3 is a diagram showing a part of such a PLD. Although not all shown, wirings for connecting each unit logic element and circuits for input / output are included in the PLD. Have been.

When the conventional PLD shown in FIG. 3 is used in an electronic device, it is used together with an external non-volatile storage element such as a ROM storing program data to be written in the PLD. Program data is taken from the storage element into the PLD.

[0007]

In the conventional apparatus, a ROM, a floppy disk, or the like can be used as an external storage medium. In this case, for example, a method of preparing a plurality of floppy disks for one PLD and changing the program data to be loaded into the PLD as desired is possible. At the design / prototype stage, it may be necessary to test multiple program data.

[0008] When a method of using a plurality of programs is applied to one PLD as described above, there is a possibility that the user may mistake the applied external storage medium. Then, the program data stored in the wrong external storage medium is read into the PLD, and as a result, the wrong function is set in the PLD, and the device malfunctions. On the other hand, conventionally, no means has been taken to prevent it.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to write a program data from an external non-volatile memory element to define a function by writing program data.
D is to provide a PLD capable of detecting whether or not the program data is legitimate and preventing reading of the illegal program data.

[0010]

SUMMARY OF THE INVENTION According to a first aspect of the present invention, there is provided a volatile memory to which program data is to be written from the outside, and control of writing of the program data to the volatile memory. A programmable logic device, the function of which is defined by the program data written to the volatile memory, wherein a predetermined address in the volatile memory to which the program data is written is stored. The above address storage means, one or more key data storage means for storing key data, and the data in the program data specified by the address stored in the address storage means are stored in the key data storage means. Comparing means for comparing with one or more key data items, As a result of the comparison by the comparing means, if the data specified by the address does not match any of the key data stored in the key data storage means, the control means stops writing the program data. Is a programmable logic device.

According to a second aspect of the present invention, in order to solve the above-mentioned problems, a volatile memory to which program data is to be externally written, and a control means for controlling writing of the program data to the volatile memory are provided. Comprising, in a programmable logic device whose function is defined by the program data written to the volatile memory, one or more address storage means for storing a predetermined address in the volatile memory to which the program data is written; One or more key data storage means for storing key data; and one or more key data stored in the key data storage means, the data in the program data specified by the address stored in the address storage means. Comparison means for comparing with data, and a result of comparison by the comparison means An abnormality signal output unit that outputs an abnormality signal indicating that illegal program data has been written to the outside, when key data that matches data specified by the address is not stored in the key data storage unit; And a programmable logic device.

According to a third aspect of the present invention, there is provided a programmable logic device according to the first or second aspect of the present invention, wherein at least one key data stored in the key data means is stored. A programmable logic device wherein the data length is changed by an external command.

[0013]

As long as the data specified in the program data by the address stored in the address storage means in the present invention does not match any one of the key data stored in the key data storage means, a normal operation is performed. Do not do. That is, when the key data that matches the data specified by the address is not stored in the key data storage unit, the writing of the program data is stopped by the control unit, and the invalid program data is written to the programmable logic device. Can be prevented.

If no key data matching the data specified by the address is stored in the key data storage means, the abnormal signal output means outputs an abnormal signal to the outside. Therefore, it can be detected from the outside that incorrect program data has been input due to the abnormal signal.

Further, since the data length of the key data stored in the key data storage means can be changed by an external command, the data length of the key data can be changed for each program data.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a PLD 11 according to an embodiment of the present invention.
It is a partial block diagram of.

As shown in FIG. 1, P
The LD 11 includes a random access memory 13 (hereinafter, abbreviated as a RAM 13) in which program data that defines the function of the PLD 11 is stored, a control circuit 12 that controls writing of the program data to the RAM 13,
And a non-volatile memory 14. The non-volatile memory 14 stores key data and its address as described later.

A feature of this embodiment is that the control circuit 12 refers to the key data stored in the nonvolatile memory 14 when storing the program data. Thus, when the program data is externally read into the control circuit 12, the data at a predetermined address position of the program data is compared with the key data in the nonvolatile memory 14. And, as a result of comparison,
If the data specified by the address does not match any of the key data in the nonvolatile memory 14, the writing of the program data is stopped by the control circuit 12.

In this embodiment, the nonvolatile memory 14
Has an address storage unit 15 storing a predetermined address position of program data, and a key data storage unit 16 storing key data composed of an array of bit values.

The control circuit 12 comprises a program data load control means 17 and a key data sampling means 1.
8, key data comparing means 19, and processing continuation stopping means 2
0.

The program data load control means 17 comprises:
The address of the program data in the external storage medium 10 is incremented, and the data for each address is written to the RAM 13. At this time, the address stored in the address storage unit 15 in the nonvolatile memory 14 is read out, and this address is compared with and referred to the address supplied to the external storage medium 10. Program data load control means 17
When the address of the program data is incremented to the address position stored in the address storage unit 15, the key data sampling means 18 samples key data consisting of a predetermined bit value array from the head of the address position. . Then, the key data comparing means 19 reads the key data stored in the key data storage section 16 and collates the key data with the above-mentioned sampled key data. The processing continuation stopping means 20 causes the key data comparing means 19 to compare the two key data, and when they match, causes the program data load control means 17 to continue the process of writing the program data into the RAM 13, while not matching In this case, the writing of the program data to the RAM 13 by the program data load control means 17 is stopped.

A feature of the present invention is that key data is included in the program data. That is, in the PLD 11 of the present invention, a part of the program data specified by the address is regarded as key data,
By comparing the key data stored in the nonvolatile memory 14 with the key data, it is determined whether or not the program data is read into the RAM 13.

In the present embodiment, this point is a point that is significantly different from the prior art. In the conventional technology, the key data is completely distinguished from the program data as described above. However, in the present embodiment, a part of the program data is regarded as the key data, and no new data needs to be added. Do not.

Once all of the program data has been read into the RAM 13, the program data including the key data can be used as one program data for setting the functions of the PLD 11. Therefore, it is possible to prevent erroneous program data from being read due to an error.

Next, an operation when program data is loaded into the PLD 11 according to the present embodiment will be described with reference to a flowchart. FIG. 2 is a flowchart showing an operation when program data is loaded into the PLD 11 according to the present invention. Before this flowchart is executed, the address of the program data is “−”.
1 ".

First, the program data loading means 17 increments the address of the program data in the external storage medium 10 (step 30), and determines whether or not the incremented address is the last address (step 31).

If it is not the last, the program data at that address is read from the external storage medium 10 and stored in the RAM 13 (step 32). Further, it is checked whether or not this address is an address position where key data is sampled (step 3).
3). If the address is an address stored in the address storage unit 15, the key data sampling means 18 samples an array of bit values as key data having a predetermined bit width from the address (step 34). ). Then, the array of the sampled bit values and the bit value array stored in the key data storage section 16 are collated by the key data comparing means 19 (step 35). If the sampled bit value array matches any one (or more) bit value array stored in the key data storage unit 16 (step 36), the address of the program data is further incremented, Similar processing is continued (step 30).

This routine is repeated, and when the program data is the last, that is, when the program data is read to the end and stored in the RAM 13 (step 31), the circuit operation of the PLD 11 is started (step 31). Step 38). However, if there is no matching key data in the comparison in step 36, the program data reading process is stopped (step 37).

Therefore, according to the present embodiment, it is possible to prevent an illegal program from being stored in the RAM 13 in the PLD 11 of the present embodiment without adding any new data to the program data. . as a result,
The assets of the program data created so far can be used as they are in the PLD 11 of the present embodiment, and effective use of resources can be achieved.

FIG. 1 shows one set of key data storage section and its address storage section as the configuration of the nonvolatile memory. However, it is preferable to provide a plurality of these sets. This is because with such a configuration, a plurality of program data used for the PLD 11 can be prepared. Therefore, when it is desired to apply a plurality of program data to one PLD, for example, the convenience in the prototype and experimental stages of the device is improved. As a result, a plurality of program data can be switched and loaded into one PLD as desired. In this case, one PLD can be switched to a plurality of functions as desired.

Further, in this embodiment, when there is no matching key data in the key data storage unit 19, the processing continuation stopping means 20 stops the loading of the program data. It is also preferable to output an abnormal signal to the outside (along with the stop). With this configuration, it can be easily determined from the outside that the illegal program data has been loaded, and a prompt response can be made. For example, if an external display device such as an LED is provided and an erroneous program data is to be loaded, the display device is configured to display that fact, so that the operator can easily make an error. You can understand that.

Further, it is also preferable that the data length of the key data stored in the key data storage section 16 is made variable by an external command. Thus, the length of the key data can be changed according to the acceptability of the program. In particular, if the lengths of a plurality of key data are independently variable, the data length of the key data can be changed for each program data. Therefore, it is possible to accurately detect the validity of the program.

As described above, the PLD according to the present embodiment
If 11 is used in an electronic device, the risk of incorrectly loading incorrect program data into the PLD 11 is reduced. As a result, an electronic device capable of efficiently preventing malfunction of the electronic device can be obtained.

[0035]

As described above, the PLD of the present invention has the following features.
The data in the program data that defines the function of the PLD, the data specified by the address stored in the address storage unit, and one of the key data stored in the key data storage unit match Normal operation is performed only when done. Therefore, when the matching key data is not stored, it is possible to prevent the illegal program data from being written to the PLD. As a result, there is an effect that malfunction of an electronic device using the PLD can be efficiently prevented.

When the matching key data is not stored in the key data storage means, an abnormal signal output means for outputting an abnormal signal to the outside is provided. And you can recognize it quickly. As a result, it is possible to quickly take measures such as reloading of the correct program data.

Further, since the data length of the key data stored in the key data storage means is variable, the data length of the key data can be changed for each of a plurality of program data. Therefore, it is possible to accurately detect whether or not the program data is valid.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a partial configuration of a PLD according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a PLD according to an embodiment of the present invention.

FIG. 3 is a partial block diagram of a conventional PLD.

FIG. 4 is an explanatory diagram showing a state of programming of a conventional PLD.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 External storage medium 11 Programmable logic device (PLD) 12 Control circuit 13 Random access memory (RAM) 14 Nonvolatile memory 15 Address storage 16 Key data storage 17 Program data load control means 18 Key data sampling means 19 Key data Comparison means 20 Processing continuation stopping means

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-245016 (JP, A) JP-A-6-35663 (JP, A) JP-A-5-259281 (JP, A) JP-A-5-259281 235163 (JP, A)

Claims (3)

(57) [Claims] 1. A volatile memory to which program data is to be written from the outside, and control means for controlling writing of the program data to the volatile memory, wherein the program data written to the volatile memory In a programmable logic device whose function is defined, one or more address storage means for storing a predetermined address in the volatile memory to which the program data is written, and one or more key data storage means for storing key data And comparing means for comparing data in the program data specified by the address stored in the address storage means with one or more key data stored in the key data storage means. Specified by the address as a result of comparison by means Programmable logic device, characterized in that if the data does not match any of the key data stored in said key data storage means, the control means for stopping the writing of the program data. 2. A volatile memory to which program data is to be written from the outside, and control means for controlling writing of the program data to the volatile memory, wherein the program data written to the volatile memory In a programmable logic device in which a function is defined, one or more address storage means for storing a predetermined address in the volatile memory to which the program data is written, one or more key data storage means for storing key data, A comparing unit that compares data in the program data specified by the address stored in the address storage unit with one or more key data stored in the key data storage unit; As a result, the data specified by the address and When the matching key data is not stored in the key data storage means, an abnormal signal output means for outputting an abnormal signal indicating that illegal program data has been written to the outside; Programmable logic device. 3. The programmable logic device according to claim 1, wherein a data length of one or more key data stored in said key data storage means is changed by an external command. Logic device.