JP2631713B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor memory device having a structure for preventing disconnection of an aluminum wiring in a contact hole of a dynamic random access memory (DRAM). In order to prevent disconnection of a conductive layer such as aluminum wiring at a step portion of a contact hole and to provide a method of manufacturing a semiconductor device with improved yield, a plurality of conductive layers formed on a semiconductor substrate, A method of manufacturing a semiconductor device, comprising: an interlayer insulating layer formed between a plurality of conductive layers; an insulating layer formed to cover all of the plurality of conductive layers; and a wiring layer formed on the insulating layer. The one of the plurality of first conductive layers, which is located above the conductive layer that is not the uppermost part of the plurality of conductive layers, Forming a turn, removing a part of one or more interlayer insulating layers above the at least the uppermost conductive layer with the same mask pattern as the above pattern, and forming the plurality of conductive layers and Forming an insulating layer on the semiconductor substrate including a plurality of interlayer insulating films; removing the insulating layer and the one or more interlayer insulating layers on the conductive layer other than the uppermost layer; Forming and exposing the at least non-topmost conductive layer, and contacting the at least non-topmost conductive layer through the contact hole;
Forming a wiring layer extending on the insulating layer, and a transistor, a word line, a bit line, and a charge storage electrode in a first region on the semiconductor substrate. Forming a capacitor comprising a counter electrode and a conductive layer pattern comprising the same conductive layer as the word line or the bit line in a second region of the semiconductor substrate; and forming the transistor, the word line and the bit. Forming an interlayer insulating film between the line, the charge storage electrode, and the counter electrode, and using at least one of the interlayer insulating films in the second region using the same mask pattern as that for forming the counter electrode pattern. Removing a portion of the conductive pattern; forming a contact hole in the second region to expose the conductive pattern; Forming a conductive film connected to the conductive pattern via a tool.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and more specifically,
The present invention relates to a method for manufacturing a semiconductor memory device having a structure for preventing disconnection of an aluminum wiring in a contact hole of a dynamic random access memory (DRAM).

[Conventional technology]

FIG. 5 is a plan view of a cell portion of the conventional semiconductor memory device, and FIG. 6 is a sectional view taken along line AA of FIG. This semiconductor memory device is a DRAM cell having a stacked capacitor. In these figures, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a first-layer polysilicon forming a word line, and 4 is a storage electrode. Second layer polysilicon forming
Is a third-layer polysilicon forming an opposing electrode, 6 is an aluminum wiring layer forming a bit line, and is located between each of the first to third-layer polysilicon 3, 4, 5 and the aluminum wiring layer 6. Is formed with an interlayer insulating film.

Generally, in a DRAM cell, in order to accurately detect stored information, the larger the amount of charge that can be stored in a capacitor, the more preferable. However, in a multilayer capacitor cell having a conventional structure, a contact portion of a bit line cannot be used for a capacitor. Therefore, the storage electrode is formed thick and its side surface is used for a capacitor. However, in this case, the opening of the bit line contact becomes severe. Therefore, the present applicant has developed a DRAM cell in which a conventional multilayer capacitor is improved.

FIG. 3 is a sectional view of a cell portion and a peripheral circuit portion of the semiconductor memory device, and FIG. 4 is a plan view of the cell portion of FIG.

In these figures, 11 is a semiconductor substrate, 12 is a cell part,
Reference numeral 13 denotes a peripheral circuit portion, reference numeral 14 denotes a field oxide film, and a first-layer polysilicon 15 forms a gate electrode and a word line of a transfer gate of the cell portion 12 and a gate electrode of the peripheral circuit portion 13. The third polysilicon 16 forms the bit line of the cell section 12 and the wiring of the peripheral circuit section 13. The third polysilicon 17 forms one of the storage electrodes of the cell section 12, and the side wall thereof is enlarged. To increase the capacity. The fourth-layer polysilicon 18 forms the other counter electrode of the storage electrode of the cell section 12. The aluminum wiring layer 19 is used as a backing for lowering the resistance of the wiring of the peripheral circuit section 13 and the word line of the cell section 12.
Further, an interlayer insulating film is provided between each of the first to third polysilicon layers 15, 16, 17 and the aluminum wiring layer 19.
20,21,22,23 are formed. These interlayer insulating films 20, 2
The layers 1, 22, and 23 must be formed to have a predetermined thickness in order to maintain the dielectric strength. The aluminum wiring layer 19 does not form a contact with the lower layer inside the cell array, and the first layer polysilicon 1
5. Contact with second layer polysilicon 16, etc. This contact hole is, for example, a first layer polysilicon.
In the case of 15, the thickness of the interlayer insulating film 20 between the first-layer polysilicon 15 and the second-layer polysilicon 16 and the interlayer thickness between the second-layer polysilicon 16 and the third-layer polysilicon 17 The thickness of the insulating film 21, the thickness of the interlayer insulating film 22 between the third polysilicon 17 and the fourth polysilicon 18, and the interlayer insulation between the fourth polysilicon 18 and the aluminum wiring layer 19. This is the total depth of the film 23 and the film thickness.

On the other hand, the third-layer polysilicon 17 and the fourth-layer polysilicon 18 are not necessarily required in the peripheral circuit section 13, and therefore, in the peripheral circuit section 13, the second-layer polysilicon 16 and the third-layer polysilicon 18 are not necessary. Interlayer insulating film 21 between the first polysilicon 17
And a fourth-layer polysilicon 18 and an aluminum wiring layer 19
The contact hole is deep (d) by the thickness of the interlayer insulating film 23 between them.

[Problems to be solved by the invention]

In the semiconductor memory device shown in FIG. 3, when the memory cell part is formed of multi-layered polysilicon and the side wall of the storage electrode is formed large, the aluminum wiring layer 19 is formed.
The contact hole inevitably becomes deeper, the aspect ratio increases, and when formed by sputtering aluminum, the aluminum wiring layer 19 may be disconnected in the contact hole. The problem could not be solved even if the operation was performed diagonally instead of vertically.

Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a conductive layer such as an aluminum wiring at a step portion of a contact hole is prevented from being broken, and the yield is improved.

[Means to solve the problem]

The object is to repeat a step of forming a first conductor pattern and a first interlayer insulating film covering the first conductor pattern on a semiconductor substrate once or a plurality of times; Forming a second conductor film on the semiconductor substrate including an insulating film, forming a mask pattern on the second conductor film, and using the mask pattern to form a second conductor film; Etching a part or all of the first interlayer insulating film in a thickness direction, growing a second interlayer insulating film covering a second conductor pattern, and forming the second insulating film on the second insulating film. Providing a step of providing an opening exposing a part of the first conductor pattern, and forming a third conductor pattern connected to the first conductor pattern through the opening. By providing a method of manufacturing a semiconductor device It is.

[Action]

According to the present invention, a portion of the interlayer insulating film is removed at least in the vicinity of a portion where the uppermost conductive layer contacts the non-topmost conductive layer among the plurality of conductive layers. The aspect ratio of the portion can be reduced, thereby reducing the step and preventing disconnection of the conductive layer such as the uppermost aluminum wiring layer.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the drawings.

FIG. 1 is a sectional view of a peripheral circuit portion of a semiconductor memory device according to an embodiment of the present invention. Parts corresponding to the conventional example in FIG. 3 are denoted by the same reference numerals. In the figure, 11 is a semiconductor substrate, 13 is a peripheral circuit portion, 14 is a field oxide film, and 15 is a first oxide film.
Layer polysilicon, 16 is a second layer polysilicon, 19 is an aluminum wiring layer, and 20 and 23 are interlayer insulating films. After forming the conventional fourth-layer polysilicon 18, the interlayer insulating film in the region including the aluminum contact hole forming portion is formed.
Some or all of 20, 21, and 22 have been removed.

In the semiconductor memory device having the above configuration, as shown in FIG.
The depth (d ') of the contact hole is the depth (d) of the conventional example.
As a result, the step is reduced, and disconnection of the aluminum wiring layer 19 can be prevented.
On the other hand, the insulating film of the first polysilicon layer 15 and the second polysilicon layer 16 is not reduced because the second polysilicon layer 16 acts as an etching mask, and the withstand voltage does not deteriorate.

Next, a method of manufacturing the semiconductor memory device having the above configuration will be described.

FIG. 2 is a view in the middle of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention. In addition, parts corresponding to FIG. 1 and the conventional example are denoted by the same reference numerals.

First, in the same figure, after a field oxide film 14 for element isolation is grown to a thickness of about 6000 mm on a semiconductor substrate 11 by a normal selective oxidation method, a gate oxide film 24 is formed by a thermal oxidation method.
Is grown to a thickness of about 200 mm. Next, a first-layer polysilicon 15 (polycide: polysilicon + tungsten silicide (WSi)) is grown and patterned as a gate electrode and a wiring. Next, this first layer polysilicon
Using the mask 15 as a mask, arsenic (As) ions are implanted at a dose of about 1 × 10 ¹⁵ cm ⁻² by ion implantation to form source / drain regions 25. Thereafter, a silicon oxide film (SiO ₂ film) is formed as the interlayer insulating film 20 by a vapor phase growth method (CVD method).
Is deposited to a thickness of about 2000 mm to form a contact hole. Next, a second layer of polysilicon (polysilicon 1000Å + WSi 2000Å) 16 is grown by CVD,
As ion dose of 1 × 10 ¹⁵ cm ^-2 by ion implantation
After lowering the resistance by injecting at about the same level, a pattern is formed. Next, an SiO ₂ film is formed as an interlayer insulating film 21 by CVD for 2000 μm.
After depositing to a film thickness of the order of magnitude, a contact hole is formed. Next, the third-layer polysilicon 17 is deposited by CVD method for 200 hours.
After being deposited to a film thickness of about 0 °, As ions are implanted at a dose of about 1 × 10 ¹⁵ cm ⁻² by ion implantation to reduce the resistance and patterning is performed. Next, an SiO ₂ film is formed as an interlayer insulating film 22 on the third-layer polysilicon 17 by a thermal oxidation method.
After growing to a thickness of about 100 °, the fourth-layer polysilicon 18 is grown to a thickness of about 2000 ° by the CVD method. Next, phosphorus (P) is introduced into the fourth-layer polysilicon 18 by a thermal diffusion method to reduce the resistance, and then patterned.
In the present embodiment, the fourth-layer polysilicon 18 covers the entire surface of the cell array. Therefore, the resist 26 on which the pattern of the fourth-layer polysilicon 18 has been formed is used as a mask to form the interlayer insulating films 20, 21, and 22. Perform etching. This etching is CH
_{This is} performed by reactive ion etching (RIE) using ₄ gases and H ₂ gas or CHF ₃ gas. For example, this is performed by detecting a change in the intensity of the emission spectrum in the etching chamber with a spectrometer, a photomultiplier, or the like. This allows
The interlayer insulating film 20 between the first-layer polysilicon 15 and the second-layer polysilicon 16 is not etched by the second-layer polysilicon 16 as a mask, and is not etched. The breakdown voltage of the interlayer insulating film 20 between the eye polysilicon 16 does not deteriorate.

Then, in order to suppress the diffusion of phosphorus from the upper PSG film (not shown) as in the conventional example, the SiO ₂ film is
The PSG film is deposited to a thickness of about Å, and is grown to a thickness of about 6,000Å. Then, a contact hole is formed, and an aluminum wiring layer is deposited to a thickness of about 1 μm by a sputtering method. Then, wiring is performed by patterning the aluminum wiring layer.

In the above-mentioned semiconductor memory device, the depth of the contact hole is about 6500 mm, while the depth of the contact hole is 10500 mm in the conventional example.
Since it is reduced by about 40%, it is very useful for preventing disconnection of the aluminum wiring layer, and the yield is improved.

In the present invention, a plurality of conductive layers such as first to third-layer polysilicons 15, 16, and 17 formed on the semiconductor substrate 11 are formed, and an interlayer insulating layer is provided between the plurality of conductive layers. film
The present invention is applied to a semiconductor device in which 20, 21, 22, and the like are formed, and is not limited to the DRAM cell of the embodiment.

〔The invention's effect〕

As described above, according to the present invention, it is possible to reduce the step of the contact hole of the semiconductor device, prevent disconnection of a conductive layer such as an aluminum wiring layer, and realize a high yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a peripheral circuit portion of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing a manufacturing process of the semiconductor memory device according to the embodiment of the present invention, and FIG. FIG. 4 is a plan view of a cell portion of the conventional semiconductor memory device, FIG. 4 is a plan view of a cell portion of the conventional semiconductor memory device, and FIG. FIG. 3 is a sectional view taken along line AA. In the figure, 11 is a semiconductor substrate, 12 is a cell portion, 13 is a peripheral circuit portion, 14 is a field oxide film, 15 is a first layer polysilicon, and 16 is a second layer.
Layer polysilicon, 17 is a third layer polysilicon, 18 is a fourth layer polysilicon, 19 is an aluminum wiring layer, 20, 2
1, 22, and 23 are interlayer insulating films, 24 is a gate oxide film, 25 is a source / drain region, and 26 is a resist.

Claims (2)

(57) [Claims] A step of forming a first conductor pattern and a first interlayer insulating film covering the first conductor pattern on a semiconductor substrate once or a plurality of times;
Forming a second conductive film on the semiconductor substrate including the interlayer insulating film, forming a mask pattern on the second conductive film, and using the mask pattern to form a second conductive film Etching a part or all of the first interlayer insulating film in a thickness direction; growing a second interlayer insulating film covering a second conductor pattern; Forming an opening exposing a part of the first conductor pattern, and forming a third conductor pattern connected to the first conductor pattern through the opening. A method for manufacturing a semiconductor device. 2. The method according to claim 1, wherein when etching all or part of the first interlayer insulating film in the thickness direction, the first interlayer insulating film is left on the side wall of the first conductor pattern. A method for manufacturing a semiconductor device according to claim 1.