JP2608140B2 - Semiconductor dynamic RAM - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor dynamic RAM, and more particularly to a reduction in a peak current of the semiconductor dynamic RAM.

[Conventional technology]

FIG. 3 shows the configuration of a conventional memory array,
6, 10 and 11 are N-ch MOS transistors, 7 to 9 are P-ch MOS transistors
Transistors, WL ₁ , WL ₂ are word lines, BL, ▲ ▼ are non-inverting bit lines and inverting bit lines forming a bit line pair,
An N-ch sense amplifier (N-chSA) and a P-ch sense amplifier (P-chSA) are arranged between both bit lines. The N-chSA has one end grounded and a gate connected to a sense amplifier activation signal line So, and an activation transistor 6 connected to the non-inversion bit line BL and the inversion bit line ▲ ▼ connected to the transistor 6. Potential setting MOS transistor 4
And 5. The P-chSA includes an activation transistor 9 having one end connected to a power supply, a gate connected to the sense amplifier activation signal line o, and a power supply for a non-inverted bit line BL and an inverted bit line ▲ ▼ connected to the transistor 9. It is composed of potential setting MOS transistors 7 and 8.

20 and 30 are MOS transistors 2 and 3 connected in series, respectively.
And the memory cell having a memory cell capacitor 21, the memory cell 20 is connected between the non-inverted bit line BL and the cell plate voltage CP, it is connected to the gate and the word line WL ₁ of the MOS transistor 2 is The memory cell 30 is connected between the inverted bit line ▲ ▼ and the cell plate voltage CP,
A gate of the MOS transistor 3 and the word line WL ₂ is connected. 1 is connected between the bit lines BL,
A MOS transistor for short-circuiting both bit lines, the gate of which is connected to the equalizing signal line EQ.

Further, 10 is a MOS transistor connected between the non-inverted bit line BL and the I / O line, and 11 is an inverted bit line ▲ ▼ and ▲
The MOS transistor connected between the ▼ line and the gate of both transistors is connected to the output y of the column decoder, and the I / O and ▲ ▼ lines are at the potential of the I / O line.

Next, the operation principle of FIG. 3 will be described with reference to the waveform diagram of FIG.

Equalize signal EQ is made from a high level to a low level, for example, when the word line signal WL ₁ goes high, the information from the memory cell capacitor 21 to the non-inverted bit line BL is read, NCHS
In A, whether the potential of the bit line BL is maintained at 1/2 Vcc as it is or whether it is amplified to the GND level is determined by the "high" or "low" of the information. Then P
In -chSA, if the bit line level remains at 1/2 Vcc, it is amplified to the Vcc level. Thereafter WL ₁ signal goes low, when the EQ signal becomes high level, the bit line voltage, i.e. the voltage of the non-inverted bit line and the inverted bit line becomes the precharge voltage of the shorted to 1 / 2Vcc,
Refresh is performed. In addition, ▲ ▼ is a signal for controlling the DRAM and is not directly related to the above operation.

[Problems to be solved by the invention]

Since the conventional semiconductor dynamic RAM is configured as described above, when performing the refresh as described above,
When charging the bit line with P-chSA as shown in FIG.
There has been a problem that a power supply having a large peak current and a large capacity is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a dynamic RAM capable of suppressing a peak current at the time of refresh.

[Means for solving the problem]

A dynamic RAM according to the present invention includes a charge sense amplifier that charges a bit line to set a power supply potential and a discharge sense amplifier that discharges a bit line to set a ground potential, and drives each of the sense amplifiers during refresh. In a semiconductor dynamic RAM in which a bit line is precharged to a predetermined potential, a first activation transistor that activates the charge sense amplifier and becomes conductive only during normal operation, and activates the charge sense amplifier during refresh operation It has a second activation transistor which is in a conductive state and has a smaller driving ability than the first activation transistor, and a third activation transistor which activates the discharge sense amplifier. Things.

[Action]

In the present invention, the charge sense amplifier is configured to be in a conductive state with the second activation transistor whose driving capability is narrowed down from the first activation transistor only when performing the refresh operation. The speed at which the line changes from the low potential level to the high potential level is reduced, so that the peak of the power supply current at this time can be reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor dynamic device according to an embodiment of the present invention.
3 is a block diagram of the RAM, in which the same reference numerals as in FIG. 3 denote the same or corresponding parts, and 101 is connected in parallel to the P-chSA activation transistor 9 and compared to the P-chSA activation transistor 9. The auxiliary activation transistor has a reduced gate width, and its gate is connected to a sense amplifier activation signal ▲ ▼ generated only at the time of refresh.
The sense amplifier activating signal ₀ connected to the gate of the activating transistor 9 is always at a high level during refresh.

Next, the operation principle will be described with reference to the waveform diagram of FIG. Like the conventional example, the word line, for example, when the word line WL ₁ is made high, the information from the memory cell 20 is read out, the potential level of the bit line BL to the ground potential level by N-chSA accordingly, or It changes to the power supply potential level by P-chSA. Here, when the potential level of the bit line BL changes from a low level to a high level, the change speed is slow because the gate width of the auxiliary activation transistor 101 of the P-chSA is narrower than that of the activation transistor 9. . For this reason, the peak current of the power supply current is reduced as shown in FIG.

As described above, in this embodiment, the auxiliary activation transistor 101 whose gate width is narrowed in comparison with the activation transistor 9 of the P-chSA is connected in parallel, and the gate of the auxiliary activation transistor 101 has a sense generated only at the time of refresh. Amplifier activation signal ▲
▼ and the gate of the activating transistor 9 has a sense amplifier activating signal ₀ which is always at a high level during refreshing.
Is applied, the speed at which the bit line changes from the low potential level to the high potential level at the time of refreshing is reduced, so that the peak of the power supply current at this time can be suppressed.

Further, since the reduction of the peak current is performed only at the time of refresh and not at the time of normal, it is not necessary to consider the delay of the access time associated with the delay in raising the level of the bit line.

〔The invention's effect〕

As described above, the semiconductor dynamic RAM according to the present invention
According to the above, the charge sense amplifier that charges the bit line to the power supply potential is brought into conduction with the second activation transistor whose driving ability is narrowed down more than the first activation transistor only when performing the refresh operation. With this configuration, the speed at which the bit line changes from the low potential level to the high potential level is reduced only at the time of refresh. As a result, the peak current at the time of refresh can be reduced without delaying the access time. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 shows a semiconductor dynamic device according to an embodiment of the present invention.
FIG. 2 is a diagram showing an array configuration of a RAM, FIG. 2 is a waveform diagram for explaining the operation principle of the semiconductor dynamic RAM, FIG. 3 is a diagram showing an array configuration of a conventional semiconductor dynamic RAM, and FIG. FIG. 6 is a waveform diagram for explaining the operation of the conventional device. WL ₁ , WL ₂ ... word line, BL, ▲ ▼ ... non-inverting bit line, inverting bit line, N, P-ch SA ... N, P-ch sense amplifier, 6 ... N-ch activating MOS transistor , 9 ... Pc
h-activated MOS transistors, 20, 30 ... memory cells, 101 ...
... P-ch auxiliary activation MOS transistor. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A charge sense amplifier for charging a bit line to a power supply potential; and a discharge sense amplifier for discharging the bit line to a ground potential, and driving each of the sense amplifiers during refresh to form a bit line. And a first activation transistor that activates the charge sense amplifier and becomes conductive only during normal operation, and activates the charge sense amplifier and conducts only during refresh operation. A semiconductor dynamic RAM, comprising: a second activation transistor having a smaller driving capability than the first activation transistor; and a third activation transistor for activating the discharge sense amplifier. .