JP2572176B2 - Processor switching method for packet switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
N spare processors corresponding to n regular processors corresponding to each of the communication lines of the line, n +
The present invention relates to a processor switching system of a packet switch having a redundant configuration of one standby system.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a conventional processor switching method of a packet switch, which is disclosed in, for example, the Telecommunication Research Institute Research Conference Transactions No. 42 (Large-capacity packet switching method). In the figure, reference numeral 1 denotes a regular processor provided corresponding to each communication line of the packet switch and performs normal packet processing. Reference numeral 2 denotes a spare processor which is switched when any one of the regular processors 1 fails. Yes, these form an (n + 1) fixed spare switching system. Reference numeral 3 denotes a line control unit connected to each of the service processors 1, and reference numeral 4 denotes a device management processor that performs operation management of the entire packet switch. Reference numeral 5 denotes a fully duplicated system bus connecting the multiprocessors of the regular processor 1, the spare processor 2, and the device management processor 4.

Next, the operation will be described. In FIG. 10, when one of the regular processors 1 corresponding to packet processing for communication on a certain communication line has failed, n including the corresponding processor that has been performing communication processing on the communication line is used.
Switching to one spare processor 2 for one regular processor 1 resumes communication on the communication line. As a result, the remaining n
One non-reserved processor 1 is in a standby state.

[0004] After the recovery of the service processor 1 that has caused the above-mentioned failure, an operation of switching back the spare processor 2 and the service processor 1 is required as an operation of incorporating the service processor 1 into the active system.

[0005]

Since the conventional processor switching system of the packet switch is configured as described above, one of the service processors 1 is in a failure state, and the remaining n-1 processors are in a failure state. Our regular processor 1
In the event of a failure, it is impossible to switch to the spare processor 2, so even if the line on which the failed processor 1 is performing communication processing is important later, the communication failure is recovered. In order to avoid the above-mentioned no-spare state, the spare processor 2 and the corresponding regular processor 1 are used as operations for incorporating the regular processor 1 into the working system after the failed regular processor 1 is restored. If the switchback processing is executed, the packet processing is interrupted at the time of the switchback processing, so that the communication of the corresponding line is temporarily interrupted, and the above switchback work is performed locally at the packet switch installation location. However, there is a problem that a maintenance worker has to go to the site because of the maintenance work.

The invention described in claim 1 has been made in order to solve the above-mentioned problems, and a communication failure can be reliably recovered for a communication line of high importance.
It is an object of the present invention to obtain a processor switching method of a packet switch in which communication is not interrupted by another switching process.

[0007] The invention according to claims 2 and 3 provides:
It is an object of the present invention to obtain a processor switching method of a packet switch capable of executing a switchback process by remote control.

[0008]

According to the first aspect of the present invention, in the processor switching method for a packet switch, a switching priority set for each communication line processed by each service processor is registered in a definition table. In the event that a faulty working processor is temporarily switched to a spare processor and then recovered from the fault and is in standby mode, if another fault occurs in the other working processor, a communication line corresponding to the newly faulted working processor The switching control unit that executes the process of switching back the spare processor only when the priority of the standby processor is higher than that of the standby processor is provided in the device management processor.

In the processor switching method for a packet switch according to the second aspect of the present invention, when a packet for instructing a switch back from the standby processor to the regular processor is received from the network management device, the switching control unit may be provided to the switching control unit. In addition, the device management processor has a remote control interface unit for instructing execution of the switching process between the service processor and the spare processor.

Further, in the processor switching system for a packet switch according to the present invention, the remote control interface unit receives a packet for instructing switching / switchback between a spare processor and a regular processor from a network management device. And according to the contents of the packet,
The switching control unit is instructed to switch between the regular processor and the spare processor, or to execute a switchback process.

[0011]

The switching control unit according to the first aspect of the present invention is configured such that when a service processor that has failed and is once switched to a spare processor recovers from the fault and is in a standby state, a fault occurs in another service processor. In this case, referring to the definition table in which the switching priority set for each communication line processed by each service processor is registered, the priority of the communication line corresponding to the service processor that has newly failed is determined. Only when it is determined that the standby processor is higher than that of the standby processor, the switch-back processing of the spare processor is executed, so that the communication failure of the communication line with high importance is reliably recovered. In addition, it is possible to realize a processor switching method of a packet switch in which communication is not interrupted by other return processing. .

The remote control interface unit according to the second aspect of the present invention, when receiving from the network management device a packet instructing switching back from the standby processor to the standby processor, switching between the standby processor and the standby processor. By instructing the switching control unit to execute the processing of (1), a processor switching method of the packet switch which can execute the switchback processing by remote control is realized.

Further, when the remote control interface unit according to the third aspect of the present invention receives from the network management unit a packet instructing switching / returning between the standby processor and the normal processor, the remote control interface unit according to the contents of the packet. By instructing the switching control unit to switch between the backup processor and the backup processor or to execute the switchback processing, a processor switching method of the packet switch that can execute the switchback processing by remote control is realized.

[0014]

[Embodiment 1] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the invention according to the first and second aspects. In the figure, 1 is a regular processor, 2 is a spare processor, 4 is a device management processor, and 5 is a system bus, which are the same as or equivalent to those in the related art denoted by the same reference numerals in FIG. Omitted.

Reference numeral 10 denotes a packet switch which employs an (n + 1) standby switching system for n communication processors (processors) and n normal processors 1 and one standby processor 2. 20 is such a packet switch 10
Is a network management device for managing the network of the packet-switched network composed of. In the device management processor 4, reference numeral 41 denotes a switching control unit that controls the n + 1 preliminary switching, and reference numeral 42 denotes a remote control interface unit that performs a process of receiving a remote control packet from the network management device 20. Reference numeral 6 denotes a line switching unit for switching / switching back the connection destination between the regular processor 1 and the spare processor 2 with respect to the communication line 30, and 7 designates a connection between the regular processor 1 and the spare processor 2 to the system bus 5. This is a bus switching unit for switching. Reference numeral 8 denotes a processor configuration definition table as a definition table in which the switching priority of each communication line 30 processed by each regular processor 1 is registered.

Next, FIG. 2 is an explanatory diagram of the n + 1 preliminary switching system. In the figure, reference numeral 9 denotes a processor group formed by a combination of n regular processors 1 and one spare processor 2 which can be switched with them, and the other members are denoted by the same reference numerals as in FIG.

FIG. 3 is an explanatory diagram of automatic switchback / switching control based on switchback priority. In the figure, 1a to 1d are ordinary processors, 30a to 30d
Is a communication line through which the regular processors 1a to 1d perform communication processing, and 6 is a line switching unit.

FIG. 4 is an explanatory diagram showing processor configuration definition information registered in the processor configuration definition table 8. In the figure, 81 is information on the (n + 1) processor group 9, and 82 is information on each regular processor 1 and spare processor 2. Information 8
2 are 83 processor numbers. , 84 processor implementation / non-implementation distinction, 85 processor operation state, 86
Processor switching priority, and 87 processor individual information.

FIG. 5 is a sequence diagram showing a process of switching back the processor by remote control from the network management device 20. In the figure, reference numeral 50 denotes a processor switchback control instruction packet transmitted from the network management apparatus 20, 51 denotes a processor switchback control response packet returned from the packet switch 10, and 52 denotes a packet transmitted from the packet switch 10 when switchback is completed. This is a start-up notification packet of the service processor 1 and the backup processor 2 to be executed. Reference numeral 53 denotes a remote switchback process in the packet switch 10.

Next, the operation will be described. When one of the regular processors 1 of the packet switch 10 in FIG. 1 fails, the switching control unit 4 in the device management processor 4
1, the line switching unit 6 and the bus switching unit 7 operate, the corresponding line 30 is switched to the spare processor 2, and the spare processor 2 is connected to the active system bus 5.
Connected to. Thus, the communication line of the line 30 is restored. This n + 1 preliminary switching operation is performed for each of the (n + 1) processor groups 9 shown in FIG.
The degree to which the plurality of processors of one packet switch 10 are divided into n groups of processors 9 is designed based on a balance between reliability against processor failure and economical efficiency in terms of the required number of spare processors 2. .

Thereafter, the same (n + 1) processor groups 9
The case where another common processor 1 has failed will be described with reference to FIG. If the failure of the service processor 1a has been recovered in a state where the service processor 1a has failed and the line 30a has been switched to the protection processor 2, the processor configuration definition table Referring to 8, line 3
Processor 1a, 1 corresponding to the line 0b and the line 30a
b, compare processor switchback priority 86,
If the priority of the line 30b is higher than that of the line 30a, the spare processor 2 executes a switchback process, and returns the line 30a to the regular processor 1a as shown in FIG. Is switched to the line 30b again. At this time, the communication on the line 30b is restored,
The communication of 0a is interrupted by the return processing of the spare processor 2. On the other hand, if the priority of the line 30a is higher or equal to the priority of the line 30b as a result of the comparison of the switchback priority, the switchback processing of the spare processor 2 is performed as shown in FIG. Absent. Therefore, although the communication on the line 30b remains disconnected,
The communication of a can be continued.

The automatic switching back / switching operation will be described with reference to the flowchart of FIG. After the failure of the service processor 1b, first, in step ST1, the processor operation state 85 of the processor configuration definition table 8 of FIG. 4 is read, and it is checked whether or not the spare processor 2 is in the standby state. Step S if in standby state
At T8, the normal n + 1 preliminary switching operation is performed. If the standby processor is not in the standby state, it is checked in step ST2 whether or not the standby processor 2 is already in the active state due to the failure of the other normal processor 1a.
If not, the process proceeds to step ST7, and the process ends without performing the automatic switchback / switching operation. If it is in the working state, it is checked from the processor operating state 85 whether the working processor 1a, which has previously failed, is in a restored (normal) state, that is, in a standby state in step ST3. If it is not in the recovery state, the process proceeds to step ST7, and the process ends without performing the automatic switchback / switching operation. On the other hand, if it is in the recovery state, the processor configuration definition table 8
Is read, and it is checked whether the processor switching priority 86 of the post-failure regular processor 1b is higher than that of the previous failure regular processor 1a. If the priority is not high, the process proceeds to step ST7, and the process ends without performing the automatic switchback / switching operation. If the priority is higher, the process of switching back the spare processor 2 is performed in step ST5, and the process of switching between the standby processor 1b and the post-failure processor 1b is performed in step ST6.

Next, the spare processor 2 which is already switched by remote control from the network management device 20 of the packet-switched network regardless of the switching priority.
The operation of performing the switching back process will be described with reference to the sequence of FIG. When a switchback control instruction is input to the operator console of the network management device 20, the network management device 2
0 transmits the processor switchback control instruction packet 50 to the corresponding packet switch 10. When the processor switchback control instruction packet 50 is received, the remote control interface unit 42 in the device management processor 4 of the packet switch 10 uses the processor switchback control instruction packet 50 to execute the remote switchback processing 5.
3 is activated, and returns a processor switchback control response packet 51 as an acceptance response to the network management device. Thereafter, in the packet switch 10, the switching control unit 41 in the device management processor 4 starts a switching operation between the service processor 1 and the backup processor 2, and upon completion of the processing, the respective processors 1 and 2 become active. , And transmits a processor start-up notification packet 52 to the network management device 20 to notify that the system has started up in the standby state. The network management device 20 displays the reception of the processor start-up notification packet 52 on the operator console to notify the operator that the switchback has been normally performed.

Next, the operation of the remote switchback processing 53 will be described with reference to the flowchart of FIG. Processor remote switchback control instruction packet 50
Is received, it is checked in step ST11 whether the state of the standby processor 2 is in the working state. If it is not in the active state, it is determined that the contents of the instruction are invalid, and step ST1
Proceed to error processing 7. If it is in the working state, it is checked in step ST12 whether the working processor 1 to be switched back is in a restored (normal) state, that is, in a standby state. If not in the standby state, step ST1
Proceed to error processing 7. Step ST if in standby state
In step ST14, a normal reception process is performed. In step ST14, a processor remote switchback control response packet 51 is returned to the network management device 20, and in step ST15, a switchback process is started. Thereafter, when the switchback processing is completed and the service processor 1 and the backup processor 2 start up in the working state and the standby state, respectively, the processor start-up notification packet 52 is transmitted to the network management device 20.

Embodiment 2 FIG. In the first embodiment, the case where different switchback priorities are set for the regular processors 1a to 1d in FIG. 3 has been described. However, as shown in FIG. 8, the same switchback priority is set for all the regular processors 1x. You can also. In this case, the (n + 1) fixed spare switching method in which the automatic switchback process (step ST5) cannot be performed by the operation flow shown in FIG. That is,
Depending on the value set in the processor switchback priority order 86 of the processor configuration definition table 8 in FIG. 4, both the automatic switchback method according to the priority order and the n + 1 fixed spare switching method can be used properly.

Embodiment 3 FIG. Further, in the first embodiment, the sequence of the processor switchback control by the remote control shown in FIG. 5 has been described. However, as shown in FIG. / The normal processor 1 depending on the contents of the switchback control instruction packet 60
It is also possible to perform the switching to the spare processor 2 by remote control. In the figure, reference numeral 61 denotes a processor remote switching / switchback control response packet transmitted from the packet switch 10 in response to the processor remote switching / switchback control instruction packet 60;
Reference numeral 62 denotes a processor start-up notification packet transmitted from the packet switch 10 when switching or switchback processing is completed, and reference numeral 63 denotes remote switching / switchback processing in the packet switch 10.

[0027]

As described above, according to the first aspect of the present invention, when the service processor that has failed and is temporarily switched to the spare processor is recovered from the failure and is in the standby state, the other service processor is in a standby state. In the event of a processor failure, the fallback of the spare processor is executed only when the priority of the communication line corresponding to the newly failed service processor is higher than that of the standby service processor. If a failure occurs in the active processor while the standby processor is in the active state, the standby processor is processing even if the active processor that has previously failed has recovered to the standby state. If the priority of the communication line is high, the switching back process of the spare processor is not executed, and therefore, for the communication line of higher importance, Impaired recovery of communication failure can be reliably performed in the event, further has the effect of other cut-back of the processor switching method without packet switches that such communication is interrupted by the processing can be obtained.

According to the second and third aspects of the present invention, switching between the spare processor and the regular processor or execution of the switchback process is instructed according to the packet received from the network management device. In addition, there is an effect that a processor switching method of a packet switch which can execute a switching process by remote control at a timing such as after completion of communication of the communication line is obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an n + 1 preliminary switching method in the embodiment.

FIG. 3 is an explanatory diagram of automatic switchback / switching control based on a switchback priority in the embodiment.

FIG. 4 is an explanatory diagram showing processor configuration definition information in the embodiment.

FIG. 5 is a sequence diagram showing a process of switching back a processor by remote control in the embodiment.

FIG. 6 is a flowchart showing a flow of an automatic switchback / switching operation in the embodiment.

FIG. 7 is a flowchart showing a flow of an operation of switching back a processor by remote control in the embodiment.

FIG. 8 is a diagram illustrating an (n + 1) -fixed spare switching method according to a second embodiment of the present invention.

FIG. 9 is a sequence diagram of a processor switching process by remote control according to a third embodiment of the present invention.

FIG. 10 is a configuration diagram showing a processor switching method of a conventional packet switch.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Normal processor 2 Spare processor 4 Device management processor 8 Definition table (processor configuration definition table) 10 Packet switch 20 Network management device 30 Communication line 41 Switching control unit 42 Remote control interface unit

Claims (3)

(57) [Claims] 1. A redundant configuration of an (n + 1) spare system in which one spare processor is made to correspond to n regular processors corresponding to each of n communication lines of a packet switch. When a failure occurs in the processor switching method of the packet switch provided with the device management processor for switching the service processor to the spare processor when a failure occurs, a switch set for each communication line to be processed by each of the n service processors. A definition table for registering the return priority is provided, and in the device management processor, when the service processor fails and is temporarily switched to the spare processor, and when the service processor recovers from the failure and is in a standby state, another service manager is provided. In the event of a processor failure, a newly failed service processor The priority of the communication line corresponding to
A processor switching method for a packet switch, comprising: a switching control unit that executes a switching process of the spare processor only when the standby processor is higher than that of the standby processor. 2. When the device management processor receives a packet sent from an external network management device and instructing switching back from the backup processor to the service processor, the device control processor sends the packet to the switching control unit. 2. The processor switching method for a packet switch according to claim 1, further comprising a remote control interface unit for instructing execution of a switchback process between the processor and the spare processor. 3. Upon receiving a packet instructing switching / returning between the spare processor and the regular processor sent from the external network management device to the device management processor, the device management processor performs processing according to the contents of the packet. The processor switching method for a packet switch according to claim 1, further comprising a remote control interface unit that instructs the switching control unit to switch between a regular processor and a spare processor or to execute a switchback process.