JP2566793B2 - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JP2566793B2
JP2566793B2 JP62247408A JP24740887A JP2566793B2 JP 2566793 B2 JP2566793 B2 JP 2566793B2 JP 62247408 A JP62247408 A JP 62247408A JP 24740887 A JP24740887 A JP 24740887A JP 2566793 B2 JP2566793 B2 JP 2566793B2
Authority
JP
Japan
Prior art keywords
wiring board
multilayer wiring
film
insulating film
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62247408A
Other languages
Japanese (ja)
Other versions
JPS6489393A (en
Inventor
康稔 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP62247408A priority Critical patent/JP2566793B2/en
Publication of JPS6489393A publication Critical patent/JPS6489393A/en
Application granted granted Critical
Publication of JP2566793B2 publication Critical patent/JP2566793B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高周波電気信号により動作する半導体集積回
路素子を搭載する多層配線基板に関するものである。
The present invention relates to a multilayer wiring board on which a semiconductor integrated circuit element that operates by a high frequency electric signal is mounted.

〔従来の技術〕[Conventional technology]

従来、半導体集積回路素子が搭載される多層配線基板
は電気絶縁性に優れたアルミナ(Al2O3)等から成るグ
リーンシートの表面にタングステン(W)等の高融点金
属から成る導電ペーストをスクリーン印刷法により厚膜
印刷し、次いでこれらを順次積層して同時に一体焼成
し、電気配線を形成することにより多層配線基板として
いた。
Conventionally, a multilayer wiring board on which a semiconductor integrated circuit device is mounted has a conductive sheet made of a refractory metal such as tungsten (W) screened on the surface of a green sheet made of alumina (Al 2 O 3 ) having excellent electric insulation. A multilayer wiring board was obtained by printing thick films by a printing method, then sequentially laminating these and firing them simultaneously to form electric wiring.

しかし乍ら、近年に至りハイブリッドICおよびLSI
等、半導体集積回路素子の高密度化、高集積化の急激な
進歩に伴い実装密度を高めるべく前記基板のより一層の
多層化を進めるには、従来の厚膜による多層配線基板で
は導電パターンの微細化が難しく、かつ全体の厚みが厚
くなって多層化が困難となり、十分な高密度化及び高機
能化が達成できないという問題があった。また、従来技
術の他の問題点して、基体に用いるアルミナ等のセラミ
ックスは、誘電率が例えば10程度と高く回路中の抵抗分
と相俟って信号の高速伝播が困難となり、半導体集積回
路素子の高速動作が不可能になってしまうという問題点
があった。
However, in recent years, hybrid ICs and LSIs
In order to further increase the density of the semiconductor integrated circuit device and the rapid progress of high integration in order to further increase the mounting density of the substrate, in the conventional multi-layer wiring board with thick film, the conductive pattern of There is a problem that miniaturization is difficult, and the total thickness becomes thick, making it difficult to form multiple layers, and it is not possible to achieve sufficient densification and high functionality. Another problem of the prior art is that ceramics such as alumina used for the substrate has a high dielectric constant of, for example, about 10, which makes it difficult to propagate a signal at high speed in combination with the resistance component in the circuit. There is a problem that the high speed operation of the device becomes impossible.

そこで、上記従来の多層配線基板の欠点を解消するた
めに、例えばセラミックス等の基体上に誘電率が3〜3.
5と比較的小さいポリイミド樹脂等の絶縁膜を形成し、
該絶縁膜上に蒸着法、スパッタリング法等の気相成長法
による薄膜形成技術を用いて電気配線用導電層を薄膜化
し、フォトリソグラフィにより微細な導電パターンを形
成し、該絶縁膜と導電層とを多層化することにより高密
度、高機能で半導体集積回路素子の高速動作が可能とな
る多層配線基板を得んとすることが行われている。
Therefore, in order to solve the above-mentioned drawbacks of the conventional multilayer wiring board, for example, a dielectric constant of 3 to 3.
Forming an insulating film such as 5 which is relatively small with polyimide resin,
A conductive layer for electric wiring is thinned on the insulating film by using a thin film forming technique such as a vapor deposition method and a sputtering method, and a fine conductive pattern is formed by photolithography. It has been attempted to obtain a multi-layer wiring board which enables high-speed operation of a semiconductor integrated circuit device with high density and high function by making the multi-layer structure.

しかし乍ら、この多層配線基板は高周波電気信号によ
り半導体集積回路素子を動作させた場合、各回路配線が
近接して密に並んでいるため1つの回路配線上の電圧変
化が他の回路配線に雑音を誘導する、いわゆるクロスト
ークノイズを発生し、更には半導体集積回路素子と多層
配線基板の特性インピーダンスの不整合により前記電気
信号が反射してしまい、半導体集積回路素子と回路配線
との干渉や信号伝播の歪等を生じるという問題があっ
た。
However, in this multilayer wiring board, when the semiconductor integrated circuit element is operated by a high-frequency electric signal, the circuit wirings are closely arranged closely to each other, so that the voltage change on one circuit wiring is caused to the other circuit wirings. The so-called crosstalk noise that induces noise is generated, and further, the electrical signal is reflected due to the mismatch of the characteristic impedance between the semiconductor integrated circuit element and the multilayer wiring board, and the interference between the semiconductor integrated circuit element and the circuit wiring and There is a problem that distortion of signal propagation occurs.

そこで、上記問題点を解決するために、前記多層配線
基板を外部電気回路に接続するリードピンの近接もしく
は該多層配線基板の表面のパッド上に電気抵抗体を設け
終端抵抗とすることが提案されている。
Therefore, in order to solve the above problems, it has been proposed to provide an electric resistor in the vicinity of a lead pin connecting the multilayer wiring board to an external electric circuit or on a pad on the surface of the multilayer wiring board to serve as a terminating resistor. There is.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかし乍ら、前記電気抵抗体を多層配線基板のリード
ピンの近傍に設けた場合には、該電気抵抗体と多層配線
基板に搭載した半導体集積回路素子間を接続する回路配
線が距離的に長くなるため、クロストークノイズの低減
化及び歪みのない高周波電気信号の伝播にはなお不十分
であり、また前記電気抵抗体を多層配線基板の表面パッ
ド上に設けた場合であっても、上記クロストークノイズ
及び高周波電気信号の歪が解消されず、その上、該多層
配線基板を小型化できないため、高速信号伝播用の高密
度化・高集積化した多層配線基板とすることができない
とう問題があった。
However, when the electric resistor is provided in the vicinity of the lead pin of the multilayer wiring board, the circuit wiring connecting the electric resistor and the semiconductor integrated circuit element mounted on the multilayer wiring board becomes long in distance. Therefore, it is still insufficient for reducing crosstalk noise and propagating a high-frequency electric signal without distortion, and even when the electric resistor is provided on the surface pad of the multilayer wiring board, the above-mentioned crosstalk is generated. Since the noise and the distortion of the high frequency electric signal are not eliminated and the multilayer wiring board cannot be downsized, there is a problem that it cannot be a high density / integrated multilayer wiring board for high speed signal propagation. It was

〔発明の目的〕[Object of the Invention]

本発明は上記欠点に鑑み案出されたもので、その目的
とするところは半導体集積回路素子と多層配線基板の特
性インピーダンスの整合をはかり、クロストークノイズ
を低減し、歪みのない高周波電気信号の伝播が可能、か
つより一層の高速信号伝播用の高密度化・高集積化した
多層配線基板を提供することにある。
The present invention has been devised in view of the above-described drawbacks, and an object thereof is to match the characteristic impedances of the semiconductor integrated circuit element and the multilayer wiring board, reduce crosstalk noise, and distort high-frequency electrical signals. An object of the present invention is to provide a multi-layer wiring board which is capable of propagation and has a high density and high integration for further high-speed signal propagation.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は絶縁基体表面に高分子材料から成る層間絶縁
膜と主導体とを順次設けて層間絶縁膜中に主導体を埋設
して成る多層配線基板において、前記層間絶縁膜中に埋
設された主導体に接して薄膜電気抵抗体を設けたことを
特徴とするものである。
The present invention relates to a multilayer wiring board in which an interlayer insulating film made of a polymeric material and a main conductor are sequentially provided on the surface of an insulating substrate and the main conductor is embedded in the interlayer insulating film. The thin film electric resistor is provided in contact with the body.

本発明においては、主導体に接して薄膜の電気抵抗体
を設け、多層配線基板内に電気抵抗体を内蔵せしめるこ
とにより、該電気抵抗体と搭載した半導体集積回路素子
間の回路配線が距離的に極めて短くなること、終端抵抗
としての電気抵抗体の接続部のインダクタンスが小さい
こと、また層間絶縁膜上に電気抵抗体を薄膜で成膜する
ため、該電気抵抗体の抵抗値の再現性が良好であること
等から、歪みのない高周波電気信号の高速伝播が可能と
なるとともに、より一層の高密度・高集積化した多層配
線基板とすることができる。
In the present invention, a thin-film electric resistor is provided in contact with the main conductor, and the electric resistor is built in the multilayer wiring board, so that the circuit wiring between the electric resistor and the mounted semiconductor integrated circuit element is separated by distance. Is extremely short, the inductance of the connection portion of the electric resistor as a terminating resistor is small, and the electric resistor is formed as a thin film on the interlayer insulating film, so that the reproducibility of the resistance value of the electric resistor is improved. Since it is good and the like, it is possible to propagate a high-frequency electric signal without distortion at a high speed, and it is possible to obtain a multilayer wiring board with higher density and higher integration.

〔実施例〕〔Example〕

次に本発明を添付図面に示す実施例に基づき詳細に説
明する。
Next, the present invention will be described in detail based on embodiments shown in the accompanying drawings.

第1図は本発明の多層配線基板の一実施例を示す断面
図である。
FIG. 1 is a sectional view showing an embodiment of the multilayer wiring board of the present invention.

第1図において、1はムライトセラミックス等から成
る絶縁基体であり、絶縁基体1の上面にはポリイミド樹
脂等の高分子材料をスピンコーティングやロールコーテ
ィング等により被覆し、その後、加熱処理を行い絶縁膜
2を形成する。
In FIG. 1, reference numeral 1 denotes an insulating base made of mullite ceramics or the like. The upper surface of the insulating base 1 is coated with a polymer material such as polyimide resin by spin coating, roll coating, or the like, and then heat treatment is performed to form an insulating film. Form 2.

次いでスパッタリング法等により銅(Cu)・アルミニ
ウム(Al)または金(Au)等の薄膜を成膜した後、フォ
トリソグラフィにより主導体3を形成し、その上から同
様にしてタンタル系化合物等の抵抗材料と銅等の主導体
材料を順次スパッタリング法等により成膜し、その後、
フォトリソグラフィにより電気抵抗体4と主導体5を形
成する。さらにその上から前記ポリイミド樹脂等の高分
子材料を被覆し絶縁膜6を形成することにより薄膜電気
抵抗体を内蔵する多層配線基板とすることができる。
Then, after forming a thin film of copper (Cu) / aluminum (Al) or gold (Au) by a sputtering method or the like, the main conductor 3 is formed by photolithography, and a resistor such as a tantalum compound is similarly formed on the main conductor 3. The material and the main conductor material such as copper are sequentially formed into a film by a sputtering method or the like, and thereafter,
The electric resistor 4 and the main conductor 5 are formed by photolithography. Further, by coating the polymer material such as the polyimide resin on the insulating film 6 and forming the insulating film 6, a multilayer wiring board having a built-in thin film electric resistor can be obtained.

また、第2図は本発明の多層配線基板の他の実施例を
示す断面図であり、1はムライトセラミックス等から成
る絶縁基体で、絶縁基体1の上面にはポリイミド樹脂等
の高分子材料から成る絶縁膜2が形成されており、絶縁
膜2の上面に前記と同様にしてタンタル系化合物等から
成る電気抵抗体4及び銅等から成る主導体5が形成さ
れ、その上から前記ポリイミド樹脂等の高分子材料から
成る絶縁膜6を形成し、薄膜電気抵抗体を内蔵する多層
配線基板を構成している。
FIG. 2 is a sectional view showing another embodiment of the multilayer wiring board of the present invention, in which 1 is an insulating base made of mullite ceramics or the like, and the upper surface of the insulating base 1 is made of a polymer material such as polyimide resin. An insulating film 2 is formed, and an electric resistor 4 made of a tantalum compound and a main conductor 5 made of copper are formed on the upper surface of the insulating film 2 in the same manner as described above. The insulating film 6 made of the above polymer material is formed to form a multi-layer wiring board having a built-in thin film electric resistor.

本発明の多層配線基板の層間絶縁膜として使用される
高分子材料は、ポリイミド樹脂、シリコーン樹脂、ポリ
ブタジエン樹脂、ポリアミドイミド樹脂及びポリ四弗化
エチレン樹脂等が好適である。
The polymer material used as the interlayer insulating film of the multilayer wiring board of the present invention is preferably polyimide resin, silicone resin, polybutadiene resin, polyamideimide resin, polytetrafluoroethylene resin, or the like.

更に薄膜電気抵抗体として使用される材料は後述する
膜厚100乃至10000Åの範囲内でシート抵抗値が四探針法
で30乃至400Ωを示すNiCr,NiCrSi,NiCrSiO,NiCrAlSi等
のニッケル・クロム系化合物、Ta及びTaSiO2,TaN等のタ
ンタル系化合物、TiN,TiW等のチタン系化合物が好適で
ある。
Further, the material used as the thin film electric resistor is a nickel-chromium compound such as NiCr, NiCrSi, NiCrSiO, NiCrAlSi, etc., which has a sheet resistance of 30 to 400 Ω by the four-point probe method within a film thickness range of 100 to 10,000 Å described later. Tantalum compounds such as Ta, Ta and TaSiO 2 , TaN and titanium compounds such as TiN and TiW are suitable.

また、抵抗値の精度の点では、該抵抗値のバラツキが
±10%以内でないと半導体集積回路素子と多層配線基板
との特性インピーダンスの整合をはかることが困難とな
る。そのためには、薄膜電気抵抗体の膜厚が100Å以上
であることが望ましく、また、前記抵抗値のバラツキの
点ではフォトリソグラフィによって該薄膜電気抵抗体の
微細なパターンを加工するに際し、該パターンの寸法、
とりわけ巾の加工誤差が5μm以下でないと上記抵抗値
のバラツキが±10%の範囲内に収まらず、そのためには
該抵抗体の膜厚が10000Å以下であることが望ましい。
In terms of resistance value accuracy, it is difficult to match the characteristic impedance between the semiconductor integrated circuit element and the multilayer wiring board unless the variation in resistance value is within ± 10%. For that purpose, it is desirable that the film thickness of the thin film electric resistor is 100 Å or more, and in terms of the dispersion of the resistance value, when processing a fine pattern of the thin film electric resistor by photolithography, Size,
In particular, if the processing error of the width is not less than 5 μm, the variation in the resistance value cannot fall within the range of ± 10%. For that purpose, it is desirable that the film thickness of the resistor be 10,000 Å or less.

一方、前記薄膜電気抵抗体と下地と層間絶縁膜との密
着性の点では、該抵抗体の膜厚が100Å未満の場合、JIS
Z1522の規定に基づく粘着テープ試験により、該抵抗体
が下地の層間絶縁膜から剥離してしまい、該層間絶縁膜
に対する密着性が不良となるため、前記膜厚は100Å以
上であることが望ましい。
On the other hand, in terms of adhesion between the thin film electric resistor, the base and the interlayer insulating film, when the film thickness of the resistor is less than 100 Å, JIS
By the adhesive tape test based on the regulation of Z1522, the resistor is peeled off from the underlying interlayer insulating film, and the adhesion to the interlayer insulating film becomes poor. Therefore, the film thickness is preferably 100 Å or more.

即ち、本発明の薄膜電気抵抗体は、その膜厚が100〜1
0000Åであることが好適である。
That is, the thin film electric resistor of the present invention has a film thickness of 100 to 1
It is preferably 0000Å.

〔実験例〕[Experimental example]

次に実験例に基づき本発明の作用効果について説明す
る。
Next, the function and effect of the present invention will be described based on experimental examples.

洗浄した1.4インチ角のムライト質セラミックスから
なり、グランド層を内蔵したセラミック基板表面に、ポ
リイミド樹脂等から成る高分子材料を従来周知のスピン
コーティングやロールコーティング等により被覆し、30
0〜400℃の温度で熱処理を行うことにより、厚さ3〜50
μmの絶縁膜を形成する。
The surface of the ceramic substrate, which is made of washed 1.4 inch square mullite ceramics and has a built-in ground layer, is coated with a polymer material such as polyimide resin by the well-known spin coating or roll coating.
By heat treatment at a temperature of 0-400 ℃, the thickness of 3-50
An insulating film of μm is formed.

次いで該絶縁膜の上面全面にタンタル系化合物等より
成る抵抗体材料及び銅等から成る主導体材料を順次、従
来周知の蒸着法やスパッタ法等の気相成長法により電気
抵抗体膜を厚さ1000Å及び主導体膜を厚さ1〜5μm成
膜した後、フォトリソグラフィにより評価用パターンを
形成し、順次これを繰り返して、該電気抵抗体膜の抵抗
値が50Ωを示す様に設定した評価用の多層配線基板を得
た。
Next, a resistor material made of a tantalum compound and a main conductor material made of copper are sequentially formed on the entire upper surface of the insulating film, and an electric resistance film is formed by a vapor phase growth method such as a conventionally known vapor deposition method or sputtering method. After forming 1000 Å and the main conductor film to a thickness of 1 to 5 μm, a pattern for evaluation is formed by photolithography, and this is repeated in sequence, and the resistance value of the electric resistance film is set to show 50Ω. The multilayer wiring board of was obtained.

次に上記評価用基板を使用して時間領域反射計測法
(TDR法)により、ステップパルスジェネレータから多
層配線基板の信号層とセラミック基板のグランド層間に
第1表に示す立上り時間Trの1パルスの信号を印加し、
該信号の波形をオシロスコープで計測し、反射ノイズ電
圧Vnを測定し、インダクタンスLを導出した。
Next, using the above-mentioned evaluation board, by the time domain reflectometry (TDR method), from the step pulse generator to the signal layer of the multilayer wiring board and the ground layer of the ceramic board, one pulse of the rise time Tr shown in Table 1 was applied. Apply a signal,
The waveform of the signal was measured with an oscilloscope, the reflected noise voltage Vn was measured, and the inductance L was derived.

以上の結果を第1表に示す。 The above results are shown in Table 1.

なお、ムライト質セラミックスから成る絶縁基板上に
前記と同様にして薄膜形成技術及びフォトリソグラフィ
技術により、グランド層及び信号層が層間絶縁膜を介し
て積層された多層配線基板の外部に、抵抗値が50Ωのチ
ップ抵抗体を接続したものを従来例とした。
In addition, in the same manner as described above, on the insulating substrate made of mullite ceramics, by the thin film forming technique and the photolithography technique, the resistance value is provided outside the multilayer wiring substrate in which the ground layer and the signal layer are laminated via the interlayer insulating film. A conventional example is one in which a 50Ω chip resistor is connected.

第1表から明らかな様に、電気抵抗体を多層配線基板
の外部に接続した従来例ではステップパルスジュネレー
タからの1パルスの立上り時間が0.5ns以下の高速信号
では、反射ノイズの発生が大きく反射ノイズ電圧も300m
V以上と極めて高く、終端抵抗として外装したチップ抵
抗体の接続部のインダクタンスも15nHと大である。
As is apparent from Table 1, in the conventional example in which the electric resistor is connected to the outside of the multilayer wiring board, the reflection noise is largely generated in a high-speed signal whose rise time of one pulse from the step pulse generator is 0.5 ns or less. 300m reflection noise voltage
It is extremely high (V or more), and the inductance of the connection part of the chip resistor packaged as a terminating resistor is as large as 15 nH.

これに対して、本発明品の薄膜電気抵抗体を内蔵した
多層配線基板では反射ノイズ電圧が極めて低く、反射ノ
イズの発生がほとんどないことを示しており、インダク
タンスも0.5nHと小さく、信号立上り時間のより高速化
が可能となっている。
On the other hand, in the multilayer wiring board incorporating the thin film electric resistor of the present invention, the reflection noise voltage is extremely low, which indicates that almost no reflection noise is generated, the inductance is as small as 0.5 nH, and the signal rise time is low. It is possible to speed up more.

〔発明の効果〕〔The invention's effect〕

以上詳述した通り、絶縁基体表面に高分子材料から成
る層間絶縁膜と主導体とを順次設けて成る多層配線基板
において、薄膜の電気抵抗体を層間絶縁膜中に埋設され
た主導体に接して設けたものは電気抵抗体の抵抗値を精
度よく得ることができるとともに、終端抵抗の接続部に
おけるインダクタンスが小となることから、クロストー
クノイズの低減及び特性インピーダンスの制御が可能と
なり、その結果、高密度化、高集積化及び歪のない高周
波電気信号の高速伝播が可能で高信頼性の多層配線基板
を得ることができる。
As described in detail above, in a multilayer wiring board in which an interlayer insulating film made of a polymeric material and a main conductor are sequentially provided on the surface of an insulating substrate, a thin-film electric resistor is in contact with the main conductor embedded in the interlayer insulating film. Since the resistance value of the electric resistor can be obtained with high accuracy and the inductance in the connection part of the terminating resistor is small, it is possible to reduce crosstalk noise and control the characteristic impedance. It is possible to obtain a highly reliable multilayer wiring board which is capable of high density, high integration and high-speed propagation of a high frequency electric signal without distortion.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の多層配線基板の一実施例を示す断面
図、第2図は本発明の多層配線基板の他の実施例を示す
断面図である。 1……絶縁基体 2、6……層間絶縁膜 3、5……主導体
FIG. 1 is a sectional view showing an embodiment of the multilayer wiring board of the present invention, and FIG. 2 is a sectional view showing another embodiment of the multilayer wiring board of the present invention. 1 ... Insulating substrate 2, 6 ... Interlayer insulating film 3, 5 ... Main conductor

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁基体表面に比誘電率が3.5以下の高分
子材料から成る層間絶縁膜と薄膜主導体とを順次設け、
層間絶縁膜中に薄膜主導体を埋設して成る多層配線基板
であって、前記層間絶縁膜中に埋設された薄膜主導体と
面当接した状態で薄膜電気抵抗体を設けたことを特徴と
する多層配線基板。
1. An interlayer insulating film made of a polymer material having a relative dielectric constant of 3.5 or less and a thin film main conductor are sequentially provided on the surface of an insulating substrate,
A multilayer wiring board having a thin-film main conductor embedded in an interlayer insulating film, wherein a thin-film electrical resistor is provided in surface contact with the thin-film main conductor embedded in the interlayer insulating film. Multilayer wiring board.
JP62247408A 1987-09-29 1987-09-29 Multilayer wiring board Expired - Fee Related JP2566793B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62247408A JP2566793B2 (en) 1987-09-29 1987-09-29 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247408A JP2566793B2 (en) 1987-09-29 1987-09-29 Multilayer wiring board

Publications (2)

Publication Number Publication Date
JPS6489393A JPS6489393A (en) 1989-04-03
JP2566793B2 true JP2566793B2 (en) 1996-12-25

Family

ID=17162990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247408A Expired - Fee Related JP2566793B2 (en) 1987-09-29 1987-09-29 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2566793B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206646A (en) * 1992-01-29 1993-08-13 Nec Corp Printed wiring board with low resistance included in internal layer
JP3684239B2 (en) * 1995-01-10 2005-08-17 株式会社 日立製作所 Low EMI electronic equipment
JP2012211370A (en) * 2011-03-31 2012-11-01 Jx Nippon Mining & Metals Corp Method for manufacturing metal foil provided with electrical resistance layer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62171197A (en) * 1986-01-23 1987-07-28 ニチコン株式会社 High density hybrid integrated circuit

Also Published As

Publication number Publication date
JPS6489393A (en) 1989-04-03

Similar Documents

Publication Publication Date Title
US5089881A (en) Fine-pitch chip carrier
JP2000508475A (en) Ultra wideband low impedance floating plate capacitor
US5822851A (en) Method of producing a ceramic package main body
US5604658A (en) Trimmable capacitor
KR930006274B1 (en) Carrier substrate and method for manufacturing thereof
US6856516B2 (en) Ball grid array resistor capacitor network
JP2566793B2 (en) Multilayer wiring board
US5075621A (en) Capacitor power probe
JP2001015654A (en) Interposer, manufacturing thereof, and circuit module using the same
JPH0525194B2 (en)
JP2003043066A (en) Contact probe member and its production method
JP4741624B2 (en) Wiring board
JPH06104578A (en) Multilayer wiring board and production thereof
JP2565351B2 (en) Electronic circuit parts
JPS6116415A (en) Wiring unit
JP3435028B2 (en) High frequency semiconductor device
JP2530008B2 (en) Wiring board manufacturing method
JP4395227B2 (en) Wiring board
JP2565362B2 (en) Method for manufacturing multilayer wiring board
JP2004014848A (en) Thin-film circuit board and its manufacturing method
JPH05183273A (en) Multilayer wiring board and manufacture thereof and elecronic device using the same
JP2000133907A (en) Circuit board with capacitor element
JP2746798B2 (en) Wiring board
JP2001345234A (en) Thin film electronic part, laminated thin film electronic part, and substrate
JP2565351C (en)

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees