JP2555427B2 - Instruction execution serialization control method - Google Patents

Description

DETAILED DESCRIPTION [Outline] Serialization control of instruction execution using a POST instruction and a WAIT instruction in an information processing system including a plurality of scalar units and a vector unit for processing vector instructions sent from these scalar units Regarding the method, the vector ST preceding the POST instruction for each scalar unit
The purpose is to recognize the completion of the ORE instruction and to eliminate the overhead due to the influence of the instruction sequence of other scalar units. The vector unit includes a vector instruction manager and a memory controller. The storage control unit has a flag unit and a serialization control unit that separately manage the generated vector instructions for each scalar unit of the request source, and the storage control unit counts the remaining number of buffer invalidation addresses to be reflected for each scalar unit. By having a counter for the scalar unit, the POS
The end of the vector instruction preceding the T instruction is recognized in correspondence with the scalar unit, and serialization control is performed.

[Industrial applications]

The present invention relates to serialization control of instruction execution using a POST instruction and a WAIT instruction in an information processing system such as a scientific and technological computer having a plurality of scalar units and a vector unit that processes vector instructions sent from these scalar units. Regarding the scheme.

In such a system, since a scalar instruction and a vector instruction, or an instruction advance control or parallel execution between instructions may be performed between vector instructions, the main memory reference order between certain instructions may not be guaranteed. is there. Therefore, it is necessary to serialize the vector operations in order to guarantee the main memory reference order.

The serialization of a vector operation is to terminate the main memory operand access of an instruction being executed before that before the main memory operand access of the instruction to be executed later occurs.

The serialization of this vector operation has no meaning because it has a meaning between vector instructions and between main memory operand accesses of vector instructions and scalar instructions, and the order relation is originally guaranteed between scalar instructions.

Serialization control using the POST and WAIT instructions interlocks the execution of the instructions following the WAIT instruction until all the instructions preceding the POST instruction in the instruction sequence are completed. In order for the WAIT instruction to release the interlock of the subsequent instruction, it is necessary to recognize the end of the instruction preceding the POST instruction.
If it is an instruction, its end is when the store address is reflected in the buffer in the scalar unit as the buffer invalidation address.

By the way, when there are multiple scalar units, each serialization control must be performed without confusion, but the instruction execution of each scalar unit is affected by the serialization control of other scalar units, and the overhead tends to increase. .

The present invention intends to reduce the overhead associated with the serialization of vector operations in order to meet the demand for high speed in recent scientific and technological computer systems.

[Conventional technology]

FIG. 7 shows a configuration example of a conventional science and technology computer system to which the present invention is applied.

In FIG. 7, 1-0 and 1-1 are scalar units.
SU-0 and SU-1,2 are vector units VU, 3 is a vector execution unit, 4 and 5 are multiplication / addition pipelines MA, 7 are vector registers VR, 8 and 9 are load / store pipelines LOAD / STORE, 10 is main memory MSU, 11 is vector control V
CU, 12 is a vector instruction management unit Vi, 13 is a vector storage management unit
VS, 14 is a storage control unit MCU.

The scalar units SU-0 and SU-1 sequentially fetch the instructions in the program, execute the scalar instructions by themselves, and send the vector instructions to the vector unit VU for execution.

In the vector control unit VCU of the vector unit VU,
The vector instruction management unit Vi receives the vector instructions sent from the scalar units SU-0 and S-1 and manages the execution. When accessing the main memory, the vector memory management unit
VS is started, an address is generated, and the storage controller MCU
The main memory MSU is accessed via the.

LOAD / STORE processing of vector data from main memory MSU to vector register VR and STORE of vector data from vector register VR to main memory MSU
It is done using a pipeline.

On the other hand, from the scalar units SU-0 and SU-1 to the main memory device MS
Each access to U is performed via the storage control unit MCU in the vector unit VU.

It is desirable that the scalar units SU-0 and SU-1 and the vector unit VU operate in parallel as much as possible in order to improve the processing performance of the system. However, when a vector instruction or a scalar instruction in the program uses the data of the execution result of the preceding vector instruction or the scalar instruction as an operand, it is necessary to guarantee the execution order between these instructions. This control is the serialization control of vector operations.

In many conventional systems, the POST operation and WAIT instruction are used to control the serialization of vector operations. This method controls that the reference of the main memory operand of the instruction to be executed before the POST instruction is made earlier than the reference of the main memory operand of the instruction to be executed after the WAIT instruction. . Therefore, P
The main memory operand of the instruction sandwiched between the OST instruction and the WAIT instruction is excluded from the serialization target of the vector operation.

In one conventional scalar unit, serialization is guaranteed as follows for each combination of vector instruction and scalar instruction.

(1) Serialization between vector instructions and vector instructions a. Guarantee of vector LOAD instruction preceding POST instruction-until priority is taken.

b. Assurance of vector STORE instruction preceding POST instruction-until priority is taken.

(2) Serialization between scalar instruction and vector instruction a. Guarantee of scalar LOAD instruction preceding POST instruction − Originally guaranteed.

b. Guarantee of a scalar STORE instruction that precedes the POST instruction-until priority is taken.

(3) Serialization between vector instruction and scalar instruction a. Guarantee of vector LOAD instruction preceding POST instruction-until priority is taken.

b. Guarantee of vector STORE instruction preceding POST instruction-until all buffer validations to scalar unit SU are reflected in scalar unit SU.

Here, in (3) b, when the data is written to the main memory MSU by the vector STORE instruction preceding the POST instruction, if there is old data at the corresponding address in the buffer in the scalar unit SU, these are written. This means that the buffer invalidation address that invalidates all is reflected, and until it is finished, the scalar instruction with main memory reference after the WAIT instruction is not executed.

The reflection processing of this buffer invalidation address is performed from the storage control unit MCU in the vector unit VU, but in the conventional storage control unit MCU, the buffer invalidation address of the vector STORE instruction preceding the POST instruction is a scalar unit because of its mechanism. It could not be processed separately.

Therefore, if an attempt is made to serialize a scalar instruction after the WAIT instruction for a vector instruction that precedes the POST instruction in a certain scalar unit SU, those buffer invalidation addresses including those by the vector STORE instruction from another scalar unit There was no choice but to wait until the reflection process including those was completed. Specific examples are shown in FIGS. 8 and 9.

Fig. 8 shows an example of an instruction sequence for serializing control using POST and WAIT instructions in two scalar units SU-0 and SU-1, respectively. VST is a vector STORE instruction and LD is a scalar. Represents the LOAD instruction of.

In Fig. 8, the instruction sequence of SU-1 is before POST, but after WAIT until VST is completed.
LD is not executed, and the main memory reference order between these VST and LD is guaranteed. Similarly, in the SU-1 instruction sequence, PO
The succeeding instruction LD of WAIT is not executed before the ST or until VST is completed.

FIG. 9 is a flowchart showing a processing example of the two instruction sequences shown in FIG.

In the example of FIG. 9, the vector instructions VST of SU-0 and SU-1 in FIG. 8 are processed by the vector instruction management unit Vi of the vector unit VU of FIG. 7 by two LOAD / STORE pipes. Two instructions are continuously executed in parallel using a line. Then, after VST is executed and all of these buffer invalidation / addresses are reflected from the storage control unit MCU to the buffers of each scalar unit SU-0, SU-1, the SU-0 WAIT instruction is executed. The LD was completed and could be executed.

[Problems to be Solved by the Invention]

In the conventional information processing system with multiple scalar units, the buffer invalidation address reflection processing for the vector STORE instruction that precedes the POST instruction in the instruction sequence of one scalar unit, and the vector from another scalar unit that follows is performed. Since it was not possible to recognize it from the buffer invalidation address reflection processing of the STORE instruction, the WAIT instruction is the vector ST that precedes all the POST instructions from each scalar unit preceding the WAIT instruction.
Execution could not be completed until the buffer invalid address reflection processing of the ORE instruction was completed.

Therefore, the serialization control in the instruction sequence of one scalar unit has a problem that the processing of the vector STORE instruction in the other instruction sequence unrelated to the serialization becomes an overhead and the parallel processing performance deteriorates.

An object of the present invention is to make it possible to recognize the completion of a vector STORE instruction preceding the POST instruction for each scalar unit, eliminate the overhead due to the influence of the instruction sequence of other scalar units, and speed up serialization control. .

[Means for solving the problem]

According to the present invention, the vector instruction management unit in the vector unit is provided with a flag unit for displaying which scalar unit the instruction in the stage is from and a serialization control unit for each scalar unit, and a main memory control unit. By providing a serialization counter that counts the remaining number of buffer invalidation addresses to be reflected for each scalar unit in correspondence with the scalar unit, the end of the buffer invalidation address reflection processing is recognized for each scalar unit, and serialization control is performed. It can be executed without being affected by the processing of the scalar unit of.

FIG. 1 is a principle block diagram of the present invention. The configuration of the information processing system shown in the figure corresponds to that of the conventional example system shown in FIG. 7, and the same reference numerals are used for common elements.

 In FIG. 1, 1-0 is a scalar unit SU-0.

 1-1 is a scalar unit SU-1.

 2 is a vector unit VU.

3 is a vector execution unit VXU, a vector register,
Includes access pipeline and operation pipeline.

 10 is a main memory unit MSU.

Reference numeral 12 is a vector instruction management unit Vi, which performs instruction control such as decoding, transmission, and serialization of vector instructions.

A storage control unit MCU 14 performs priority control and access control of access requests to the main storage device MCU.

15-0 and 15-1 are scalar units SU-0 and SU-1, respectively.
Of the main unit MSU
It is provided for efficient access to instructions and operands in.

Reference numeral 16 is a stage, which is a Rea for controlling each stage of vector instruction fetch, predecode, start / queue, and access pipeline of the vector execution unit VXU
Includes instruction execution management stages such as d, Store, Terminate (simplified in the figure).

Reference numeral 17 denotes a POST flag, which is provided for each of the instruction execution management stages described above in order to recognize a vector instruction preceding the POST instruction.

Reference numeral 18 denotes an SU flag, which is provided in the instruction execution management stage and other necessary stages to identify SU-0 and SU-1.

19-0 and 19-1 are serialization control units corresponding to the scalar units SU-0 and SU-1, respectively.
When the POST instruction is activated for each -1, the POST flag 17 of all the preceding vector instructions is set to ON, the execution end is detected when all the POST flags 17 are OFF, and serialized to the storage control unit MCU. Send a start signal. When a Bi-Pending signal (not shown) indicating the end of reflection of the buffer invalidation address is received from the storage control unit MCU, a WAIT_ACK signal for notifying execution completion of the WAIT instruction is sent to the corresponding scalar unit.

20-0 and 20-1 are SU-0 and SU provided in the MCU, respectively.
-1 TAG, SU-0, SU-1 buffers 15-0,15-
It is used to hold the address of the data being fetched at 1 and to detect the buffer invalidation address when storing.

21 is buffer invalidation address stack
It is a BiAS, and the buffer invalidation address of the executed vector STORE instruction is stored and read sequentially and SU-0, SU-
The reflection process of the 1 into the buffers 15-0 and 15-1 is performed.

22-0 and 22-1 are serialization counters, and serialization control units 19-0 and 19 of the vector instruction management unit Vi, respectively.
When the serialization activation signal is received from -1, the number of remaining addresses in BiAS is set. Thereafter, each time the address is read from the BiAS and the buffer invalidation reflection processing is performed, it is decremented by 1, and when it becomes 0, the serialization end signal is sent to the corresponding SU-0, SU-1.

Furthermore, after starting serialization from the MCU to Vi, Bi
A BiAS_Pending signal that is ON until AS becomes empty is sent.

It is turned on by sending a POST command from Vi to each SU and BiAS
Is empty, that is, OF when the serialization counter becomes "0"
The POST_Pending signal that becomes F is sent.

WAIT_ that turns ON when a WAIT command is issued from Vi to each SU
The ACK signal is sent.

[Action]

In FIG. 1, the scalar units SU-0 and SU-1 operate independently of each other, and when a vector instruction is detected in the instruction sequence, request processing to the vector unit VU.

In the vector instruction management unit Vi in the vector unit VU,
The input vector instruction sequentially flows through the plurality of stages 16 and performs the control defined in each stage.
Each stage can control a plurality of vector instructions that are continuously input in parallel.

The sequential stages control the input (fetch) of vector instructions, the identification of vector instructions by predecoding, the start / queue for starting instruction execution, and the instruction execution management of the corresponding pipeline of the vector execution unit VXU. It has become.

The SU flag SUF is set to "0" or "1" depending on whether the vector instruction is input from SU-0 or SU-1.

When a POST instruction is detected in the predecode stage (not shown) provided before the stage 16, the POST instruction is detected.
The serialization control unit (19-0, 19-1) corresponding to the scalar unit that has sent the command is activated.

The activated serialization control unit displays the POST flags of all valid vector instructions existing in the instruction execution management stage in stage 16 that belong to the self-scalar unit.
Set POS to ON. In other words, all vector instructions preceding the POST instruction are marked in the instruction sequence of the scalar unit that issued the POST instruction.

Next, the serialization control unit
The POST flag POS of each stage having the SU flag SUF is monitored, and when all of them are turned off, a serialization activation signal is sent to the storage control unit MCU.

The storage control unit MCU consists of SU-0 and SU-1 buffers 15-0 and 15
It has TAGs 20-0 and 20-1 corresponding to the contents of -1.

The buffers 15-0 and 15-1 operate by a so-called store-through method. Therefore, the address when the corresponding scalar unit SU-0, SU-1 fetches the instruction or operand is registered in TAG 20-0, 20-1, and when the vector unit VU stores, the store Referenced using an address. If a matching address is detected by the reference by this store address, the TA
Since the old data to be invalidated exists in the buffer in the scalar unit corresponding to G, that address is temporarily stored in the buffer invalidation address stack BiAS as the buffer invalidation address.

The BiAS buffer invalidation address is read sequentially and sent to the corresponding scalar unit.

The serialization activation signal output from Vi described above is P
This is performed at the timing when the buffer invalidation addresses of all vector STORE instructions VST preceding the OST instruction have been stored in BiAS. Therefore, the serialization ends when all the reflection processing of the buffer invalidation address remaining in BiAS is completed at this point.

Therefore, one of the serialization counters 22-0 and 22-1 corresponding to the scalar unit to be serialized
It presets the number of remaining addresses in BiAS, counts down each time an address is read from BiAS, and sends a serialization end signal to the corresponding scalar unit when it reaches "0". At this time, BiAS_Pending against Vi
OFF is notified.

When the WAIT instruction is issued (input to the instruction execution management stage), the serialization control units 19-0 and 19-1 notify the requesting scalar unit that WAIT_ACK is ON, and BiAS_Pendi
When ng turns OFF, the OFF of POST_Pending is notified to the same scalar unit.

In the scalar unit, WAIT_ACK is ON and POST_Pending is O.
When FF is detected, execution of the subsequent instruction interlocked by the WAIT instruction starts.

FIG. 2 is a processing flow when the instruction sequence example of FIG. 8 is executed by the method of the present invention. Compared to the conventional processing method shown in FIG. 9, a scalar unit
It can be seen that the execution timing of the instruction LD in SU-0 is significantly accelerated.

〔Example〕

 FIG. 3 is a configuration diagram of a system according to an embodiment of the present invention.

In FIG. 3, 1-0 and 1-1 are scalar units SU-0 and S
U-1, 2 is the vector unit VU, 12 is the vector instruction management unit V
Reference numerals i and 14 denote storage control unit MCUs having the same configuration as that shown in FIG.

Next, signals or signals indicated by arrows between blocks in FIG. 3 will be described.

: Serialization activation signal (Vi → MCU) − All STORE instructions preceding the POST instruction are BiA
Send it from Vi to the MCU at a timing when it can be guaranteed that S has entered.

: BiAS_Pending signal (MCU → Vi) -Turns on until BiAS becomes empty after serialization is started by the serialization start signal.

, ′: POST_Pending signal (Vi → SU-0, SU-1) -ON when the POST command is issued. It turns off when the BiAS buffer invalidation address by all STORE instructions preceding the POST instruction becomes empty and the priority of all STORE instructions preceding the POST instruction can be obtained.

, ′: Serialization end signal (MCU → SU-0, SU-
1) -When BiAS is empty, send from MCU to SU. In SU, buffer invalidation Bi is performed by this signal.

(Inhibit CPU_ACK during that period.), ′: WAIT_ACK signal (Vi → SU-0, SU-1) -Turns on when WAIT command is issued. In SU, after this signal PO
The instruction is interlocked until the ST_Pending signal turns off.

FIG. 4 shows an example configuration of the vector instruction management unit Vi,
FIG. 5 shows a part of the output logic circuit of the serialization control section.

In FIG. 4, 16 is a stage, 19-0 and 19-1 are serialization control units, and 23 is a command transmission control unit.

F0 and F1 are instruction fetch stages, and S
It serves as an entrance for receiving vector instructions from U-0 and SU-1.

P is a predecode stage, which decodes vector instructions and performs exception checking.

Q is a start / cue stage and sends a vector command.

R, S, and T are instruction execution management stages for access instructions, of which R is the Read stage, S is the Store stage, and T is T.
It is the erminate stage. Instruction execution management stages for other vector instructions are not shown.

 U is the instruction end stage.

Each of the above stages has a VALiD flag, and R,
A POST flag POS is added to the S and T stages, and a SU flag SUF is added to the P, Q, R, S, and T stages.

When the POST instruction or the WAIT instruction is transmitted from the start / queue stage Q to the instruction execution management stage, the instruction transmission control section 23 serializes the control section 19-0 or 19.
Send POST_START or WAIT_START to -1.

The serialization control units 19-0 and 19-1 use POST_START, WAIT
_START, BiAS_Pending signals and POS of R, S, T stages
Using the T flag POS and the AND output of the VALiD flag V as inputs,
POST flag set, POST_Pending, according to a certain logic
Outputs WAIT_ACK and serialization activation signals.

FIG. 5 shows a part of the logic in the serialization control units 19-0 and 19-1, where FIG. 5A shows the output logic of POST_Pending, and FIG. 5B shows the output logic of serialization activation. ing.

When POST_START is transmitted from the command transmission control unit 23 by START (transmission) of the POST command from SU-0 or SU-1, the serialization control unit 19-0 or 19-1 on the activated side executes the command. VALiD flag V of management stage
Turns on the OPST flag POS of the stage where is ON and turns on the POST_Pending signal for the corresponding SU.

When all the POST flags of the instruction execution management stage are turned off, the serialization control unit 19- that has been activated
0 or 19-1 sends a serialization activation signal to the MCU.

After that, the WAIT command is transmitted and the command transmission control unit 23 waits.
When _START is transmitted, the serialization control unit 19-0 or 19-1 returns a WAIT_ACK signal to SU-0 or SU-1. In SU-0 and SU-1, a signal that matches this signal with POST_Pending is used to interlock the subsequent main memory reference scalar instruction.

When BiAS-Pending sent from the MCU is turned off, the serialization controller 19-0 or 19-1
Set Pending to OFF and cancel the interlock at SU-0 or SU1.

 FIG. 6 shows the configuration of an embodiment of the storage control unit MCU.

The MCU has four ports A, B, C and D, and performs parallel control. Here, each port will be described by using the port A as a representative.

 In FIG. 6, 24 is the store address stack STAS.

 25 is a selector SEL-1.

26 is buffer validation 1 register Bi1R
Is.

27-0 and 27-1 are tag registers TAGR-0 and TAGR-1.

 28-0 and 28-1 are tag TAGs composed of RAM.

 29-0 and 29-1 are coincidence circuits.

30 is buffer invalidation 2 register Bi2R
Is.

31-0 and 31-1 are match flags MATCH-0 and MATCH-1.

32 is a buffer invalidation address stack BiAS.

 33 is an input pointer INQ_COUNT.

 34 is an output pointer OUTQ_COUNT.

 35 is a subtraction circuit.

36-0 and 36-1 are serialization counters COUNT-0 and COU
It is NT-1.

 37-0 and 37-1 are selectors SEL-2.

28-0 and 38-1 are buffer invalidation address registers BiAR-0 and BiAR-1.

 39-0 and 39-1 are "0" detection circuits.

STAS is a register for storing an address during store access on the VU side, and SEL-1 is a circuit for selecting the output of STAS and the registered address from SU.

Bi1R is a register that receives the output of SEL-1. Bi
TAGR-0 and TAGR-1 in parallel with 1R are SU-0 and SU-1 respectively.
Register for TAG, and indicates a reference address for TAG at the time of store access from VU, and shows a registration address and registration data for TAG at the time of fetch access from SU-0 and SU-1.

The coincidence circuits 29-0 and 29-1 are circuits that compare the address from Bi1R with the respective addresses of TAG 28-0 and 28-1 at the time of store access from VU, and the outputs thereof are MATCH flag MATCH-0, MATCH-1 is shipped by air and written in BiAS.

INQ_COUNT under BiAS indicates the number of times MATCH-0 and MATCH-1 were written to BiAS, and OUTQ_COUNT indicates the number of times read from BiAS. The subtraction circuit 35 subtracts the value of OUTQ_COUNT from the value of INQ_COUNT to obtain the number of flags (addresses) remaining in BiAS.

When a serialization activation signal from the serialization control units 19-0 and 19-1 (FIG. 4) of Vi is received, the number remaining in the BiAS is determined by the corresponding serialization counter COUNT-0.
Alternatively, it is set to COUNT-1 and the value of the serialization counter is decremented by 1 each time the address is read from BiAS, and when the value becomes "0" is detected by the "0" detection circuit and the serialization end signal is output. Send to SU.

Further, the "0" detection circuit 39-0 or 39-1 sends the BiAS_Pending signal to Vi until the value of BiAS becomes "0" after being activated by the serialization activation signal.

〔The invention's effect〕

In the serialization control according to the present invention, since the completion of the vector STORE instruction preceding the POST instruction is distinguished and recognized for each scalar unit, the overhead of the WAIT instruction due to the vector STORE instruction from other scalar units can be eliminated, and The processing efficiency in the scalar unit SU is improved and the parallel processing performance with the vector unit VU is also improved.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a process flow diagram based on the serialization control method of the present invention, FIG. 3 is a block diagram of a system of one embodiment of the present invention, and FIG. 4 is vector instruction management. FIG. 5 is a block diagram of an output logic circuit of a part of the serialization control unit in FIG. 4, FIG. 6 is a block diagram of an embodiment of the storage control unit, and FIG. 8 is a block diagram of a computer system, FIG. 8 is an explanatory diagram of an example of an instruction sequence serialized using POST / WAIT, and FIG. 9 is a processing flow diagram based on the conventional serialization control method for the example of the instruction sequence of FIG. Is. In FIG. 1, 1-0,1-1: Scalar unit SU-0, SU-1 2: Vector unit VU 3: Vector execution unit VXU 10: Main memory MSU 12: Vector instruction management unit Vi 14: Storage control unit MCU 15-0, 15-1: Buffer 16: Stage 17: POST flag POS 18: SU flag SUF 19-0, 19-1: Serialization control block 20-0, 20-1: TAG 21: Buffer invalidation address Stack BiA
S 22-0, 22-1: Serialization counter

Claims (1)

(57) [Claims] 1. A POST comprising: a main memory device (10); a plurality of scalar units (1-0, 1-1); and a vector unit (2) for processing vector instructions requested by each scalar unit. In an information processing system having a function of serializing instruction execution using instructions and WAIT instructions, a vector unit (2) includes a vector instruction management unit (12) and a storage control unit (14), and a vector instruction management unit ( 1
2) has flag means (18) and serialization control means (19-0, 19-1) for separately managing the input vector instructions for each requesting scalar unit, and also has a storage control section (14). Has a serialization counter (22-0, 22-1) that counts the remaining number of buffer invalidation addresses that should be reflected for each scalar unit in correspondence with the scalar unit, so that the vector instruction management unit (12) Is input, the serialization control means corresponding to the scalar unit that has sent the POST command is activated, and the activated serialization control means refers to the flag means (18) and the previously input vector is input. PO above in the order
All vector instructions that belong to the scalar unit that sent the ST instruction are detected, and when these vector instructions have finished executing, the serialization control of the storage control unit (14) is activated, and the storage control unit (14) Performing serialization control by sending the buffer invalidation address to the scalar unit to be serialized according to the remaining number of buffer invalidation addresses indicated by the serialization counter corresponding to the scalar unit, and causing the buffer invalidation address to be reflected. A serialization control method for instruction execution.