JP2024541743A - デジタル時間コンバータのオンライン利得較正のためのシステム及び方法 - Google Patents
デジタル時間コンバータのオンライン利得較正のためのシステム及び方法 Download PDFInfo
- Publication number
- JP2024541743A JP2024541743A JP2024533008A JP2024533008A JP2024541743A JP 2024541743 A JP2024541743 A JP 2024541743A JP 2024533008 A JP2024533008 A JP 2024533008A JP 2024533008 A JP2024533008 A JP 2024533008A JP 2024541743 A JP2024541743 A JP 2024541743A
- Authority
- JP
- Japan
- Prior art keywords
- dtc
- calibration
- output
- code
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Analogue/Digital Conversion (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/541,781 | 2021-12-03 | ||
| US17/541,781 US11843392B2 (en) | 2021-12-03 | 2021-12-03 | Systems and methods for online gain calibration of digital-to-time converters |
| PCT/US2022/051601 WO2023102154A1 (en) | 2021-12-03 | 2022-12-02 | Systems and methods for online gain calibration of digital-to-time converters |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2024541743A true JP2024541743A (ja) | 2024-11-11 |
| JP2024541743A5 JP2024541743A5 (https=) | 2025-12-04 |
| JPWO2023102154A5 JPWO2023102154A5 (https=) | 2025-12-04 |
Family
ID=84943206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024533008A Pending JP2024541743A (ja) | 2021-12-03 | 2022-12-02 | デジタル時間コンバータのオンライン利得較正のためのシステム及び方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US11843392B2 (https=) |
| EP (1) | EP4441897A1 (https=) |
| JP (1) | JP2024541743A (https=) |
| CN (1) | CN118318395A (https=) |
| WO (1) | WO2023102154A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12278643B2 (en) * | 2021-09-22 | 2025-04-15 | Intel Corporation | Calibration for DTC fractional frequency synthesis |
| US11843392B2 (en) * | 2021-12-03 | 2023-12-12 | Texas Instruments Incorporated | Systems and methods for online gain calibration of digital-to-time converters |
| US12147201B2 (en) * | 2022-11-17 | 2024-11-19 | Cisco Technology, Inc. | Segmented digital-to-time converter |
| US20250323648A1 (en) * | 2024-04-10 | 2025-10-16 | Shaoxing Yuanfang Semiconductor Co., Ltd. | Gain calibration of digital-to-time converter (dtc) used in fractional frequency dividers |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7292618B2 (en) * | 2005-05-10 | 2007-11-06 | Texas Instruments Incorporated | Fast hopping frequency synthesizer using an all digital phased locked loop (ADPLL) |
| US7813462B2 (en) * | 2005-10-19 | 2010-10-12 | Texas Instruments Incorporated | Method of defining semiconductor fabrication process utilizing transistor inverter delay period |
| US8830001B2 (en) * | 2007-06-22 | 2014-09-09 | Texas Instruments Incorporated | Low power all digital PLL architecture |
| US8193866B2 (en) * | 2007-10-16 | 2012-06-05 | Mediatek Inc. | All-digital phase-locked loop |
| US8045669B2 (en) * | 2007-11-29 | 2011-10-25 | Qualcomm Incorporated | Digital phase-locked loop operating based on fractional input and output phases |
| US8497716B2 (en) * | 2011-08-05 | 2013-07-30 | Qualcomm Incorporated | Phase locked loop with phase correction in the feedback loop |
| US9071304B2 (en) * | 2013-08-16 | 2015-06-30 | Intel IP Corporation | Digital-to-time converter and methods for generating phase-modulated signals |
| US9209958B1 (en) * | 2014-06-30 | 2015-12-08 | Intel Corporation | Segmented digital-to-time converter calibration |
| WO2016029058A1 (en) * | 2014-08-20 | 2016-02-25 | Zaretsky, Howard | Fractional-n frequency synthesizer incorporating cyclic digital-to-time and time -to-digital circuit pair |
| US9379719B1 (en) * | 2015-03-31 | 2016-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Phase locked loop device |
| US9531394B1 (en) * | 2015-06-22 | 2016-12-27 | Silicon Laboratories Inc. | Calibration of digital-to-time converter |
| US9520890B1 (en) * | 2015-12-23 | 2016-12-13 | Intel IP Corporation | Dual digital to time converter (DTC) based differential correlated double sampling DTC calibration |
| US9678481B1 (en) * | 2016-06-17 | 2017-06-13 | Integrated Device Technologies, Inc. | Fractional divider using a calibrated digital-to-time converter |
| US9791834B1 (en) * | 2016-12-28 | 2017-10-17 | Intel Corporation | Fast digital to time converter linearity calibration to improve clock jitter performance |
| KR102527388B1 (ko) * | 2018-04-06 | 2023-04-28 | 삼성전자주식회사 | 디지털-타임 컨버터 회로를 포함하는 위상 고정 루프 회로, 클럭 신호 생성기 및 이의 동작 방법 |
| US10693482B2 (en) * | 2018-06-27 | 2020-06-23 | Silicon Laboratories Inc. | Time-to-voltage converter with extended output range |
| US10459407B1 (en) * | 2018-06-29 | 2019-10-29 | Intel Corporation | DTC based carrier shift—online calibration |
| US10495407B1 (en) * | 2018-11-05 | 2019-12-03 | RailScales LLC | Panel attachable to a firearm |
| US10594329B1 (en) * | 2018-12-07 | 2020-03-17 | Si-Ware Systems S.A.E. | Adaptive non-linearity identification and compensation using orthogonal functions in a mixed signal circuit |
| US11223362B2 (en) * | 2020-05-14 | 2022-01-11 | Mediatek Inc. | Phase-locked loop circuit and digital-to-time convertor error cancelation method thereof |
| US11271584B2 (en) * | 2020-07-08 | 2022-03-08 | Korean Advanced Institute Of Science And Technology | Integrated circuit, electronic device including the same, and operating method thereof |
| US11843392B2 (en) * | 2021-12-03 | 2023-12-12 | Texas Instruments Incorporated | Systems and methods for online gain calibration of digital-to-time converters |
-
2021
- 2021-12-03 US US17/541,781 patent/US11843392B2/en active Active
-
2022
- 2022-12-02 WO PCT/US2022/051601 patent/WO2023102154A1/en not_active Ceased
- 2022-12-02 EP EP22843553.3A patent/EP4441897A1/en active Pending
- 2022-12-02 CN CN202280078777.2A patent/CN118318395A/zh active Pending
- 2022-12-02 JP JP2024533008A patent/JP2024541743A/ja active Pending
-
2023
- 2023-12-11 US US18/534,861 patent/US12375094B2/en active Active
-
2025
- 2025-07-02 US US19/257,581 patent/US20250337427A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US11843392B2 (en) | 2023-12-12 |
| US12375094B2 (en) | 2025-07-29 |
| US20230179215A1 (en) | 2023-06-08 |
| CN118318395A (zh) | 2024-07-09 |
| EP4441897A1 (en) | 2024-10-09 |
| WO2023102154A1 (en) | 2023-06-08 |
| US20250337427A1 (en) | 2025-10-30 |
| US20240113722A1 (en) | 2024-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2024541743A (ja) | デジタル時間コンバータのオンライン利得較正のためのシステム及び方法 | |
| TWI463804B (zh) | 時脈資料回復電路 | |
| US9897976B2 (en) | Fractional divider using a calibrated digital-to-time converter | |
| CN112803944B (zh) | 数字时间转换器校准方法、装置、数字锁相环及电子设备 | |
| EP1551102B1 (en) | Device for calibrating the frequency of an oscillator, phase looked loop circuit comprising said calibration device and related frequency calibration method. | |
| US8437441B2 (en) | Phase locked loop capable of fast locking | |
| US7812678B2 (en) | Digital calibration techniques for segmented capacitor arrays | |
| JP2009296571A (ja) | 発振器および位相同期回路のループ帯域補正方法 | |
| US8149033B2 (en) | Phase control device, phase-control printed board, and control method | |
| CN101729063A (zh) | 延迟锁相环电路及调整输出时钟信号相位的方法 | |
| US7893741B2 (en) | Multiple-stage, signal edge alignment apparatus and methods | |
| US11728799B2 (en) | Measuring pin-to-pin delays between clock routes | |
| WO2007084876A2 (en) | Systems and methods for reducing static phase error | |
| US12445117B2 (en) | Dynamic phase adjustment for high speed clock signals | |
| CN108667455B (zh) | 具有通过未修整振荡器提供的参考信号的锁定环电路 | |
| TW201820790A (zh) | 頻率合成裝置及其方法 | |
| TWI613890B (zh) | 數位控制振盪器的頻率校正方法及其頻率校正裝置 | |
| US7782927B2 (en) | Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillator | |
| US8132040B1 (en) | Channel-to-channel deskew systems and methods | |
| Deka et al. | A 1Gbps–10 Gbps multi-standard auto-calibrated all digital phase interpolator in 14nm CMOS | |
| US20260019072A1 (en) | Systems and methods for duty-cycle and phase error detector (dped) with chopping cancellation technique | |
| US12218672B2 (en) | Frequency multiplier calibration | |
| TWI408895B (zh) | 濾波器截止頻率校正電路 | |
| CN120074468A (zh) | 时钟和数据恢复电路系统 | |
| KR101000738B1 (ko) | 디지털 방식을 이용한 필터의 차단 주파수 보정 회로 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20251126 |
|
| A625 | Written request for application examination (by other person) |
Free format text: JAPANESE INTERMEDIATE CODE: A625 Effective date: 20251126 |