JP2024516742A5 - - Google Patents

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Publication number
JP2024516742A5
JP2024516742A5 JP2023568590A JP2023568590A JP2024516742A5 JP 2024516742 A5 JP2024516742 A5 JP 2024516742A5 JP 2023568590 A JP2023568590 A JP 2023568590A JP 2023568590 A JP2023568590 A JP 2023568590A JP 2024516742 A5 JP2024516742 A5 JP 2024516742A5
Authority
JP
Japan
Application number
JP2023568590A
Other languages
Japanese (ja)
Other versions
JP2024516742A (ja
JPWO2022235914A5 (https=
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2022/027846 external-priority patent/WO2022235914A1/en
Publication of JP2024516742A publication Critical patent/JP2024516742A/ja
Publication of JPWO2022235914A5 publication Critical patent/JPWO2022235914A5/ja
Publication of JP2024516742A5 publication Critical patent/JP2024516742A5/ja
Pending legal-status Critical Current

Links

JP2023568590A 2021-05-07 2022-05-05 マイクロエレクトロニクスパッケージアセンブリおよび作製方法 Pending JP2024516742A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202163185768P 2021-05-07 2021-05-07
US63/185,768 2021-05-07
PCT/US2022/027846 WO2022235914A1 (en) 2021-05-07 2022-05-05 Microelectronics package assemblies and processes for making

Publications (3)

Publication Number Publication Date
JP2024516742A JP2024516742A (ja) 2024-04-16
JPWO2022235914A5 JPWO2022235914A5 (https=) 2025-05-07
JP2024516742A5 true JP2024516742A5 (https=) 2025-05-07

Family

ID=81927461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023568590A Pending JP2024516742A (ja) 2021-05-07 2022-05-05 マイクロエレクトロニクスパッケージアセンブリおよび作製方法

Country Status (6)

Country Link
US (1) US12074099B2 (https=)
JP (1) JP2024516742A (https=)
KR (1) KR102914493B1 (https=)
CN (1) CN117280457A (https=)
TW (1) TW202249583A (https=)
WO (1) WO2022235914A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12224218B2 (en) * 2022-02-11 2025-02-11 Wolfspeed, Inc. Semiconductor packages with increased power handling
USD1056862S1 (en) 2022-08-24 2025-01-07 Wolfspeed, Inc. Semiconductor package
GB2635648A (en) * 2023-10-17 2025-05-28 Trak Microwave Ltd Radio frequency components and manufacturing of radio-frequency components
TWI866712B (zh) * 2023-12-21 2024-12-11 矽品精密工業股份有限公司 散熱結構及其電子封裝件

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819385B2 (ja) * 1974-09-04 1983-04-18 日本電気株式会社 ロウヅケホウホウ
JPS58500463A (ja) * 1981-03-23 1983-03-24 モトロ−ラ・インコ−ポレ−テッド めっきのしてないパッケ−ジを含む半導体デバイス
SG157957A1 (en) * 2003-01-29 2010-01-29 Interplex Qlp Inc Package for integrated circuit die
US6903013B2 (en) * 2003-05-16 2005-06-07 Chartered Semiconductor Manufacturing Ltd. Method to fill a trench and tunnel by using ALD seed layer and electroless plating
US7731078B2 (en) * 2004-11-13 2010-06-08 Stats Chippac Ltd. Semiconductor system with fine pitch lead fingers
JP2006196810A (ja) * 2005-01-17 2006-07-27 Kyocera Corp セラミック回路基板および電子部品モジュール
JP4816049B2 (ja) * 2005-12-13 2011-11-16 大日本印刷株式会社 センサーパッケージおよびその製造方法
US8617926B2 (en) * 2010-09-09 2013-12-31 Advanced Micro Devices, Inc. Semiconductor chip device with polymeric filler trench
EP2973672B1 (en) 2013-03-15 2018-07-11 Materion Corporation Method of spot-welding a die bond sheet preform containing gold and tin to a die bond area on a semiconductor package
US10211115B2 (en) 2014-05-21 2019-02-19 Materion Corporation Method of making a ceramic combo lid with selective and edge metallizations
US20170069560A1 (en) 2014-05-23 2017-03-09 Materion Corporation Air cavity package
US9543170B2 (en) * 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
WO2017201260A1 (en) * 2016-05-20 2017-11-23 Materion Corporation Copper flanged air cavity packages for high frequency devices
US11646255B2 (en) * 2021-03-18 2023-05-09 Taiwan Semiconductor Manufacturing Company Limited Chip package structure including a silicon substrate interposer and methods for forming the same

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