JP2024006013A - Printer - Google Patents

Abstract

To provide a printer which can suppress increase in the size of an amplification circuit for amplifying a drive waveform.SOLUTION: A printer includes an amplification circuit for amplifying a drive waveform, and an energy imparting element which is driven by the drive waveform amplified by the amplification circuit, imparts energy to a liquid, and discharges the liquid from nozzles, wherein the amplification circuit includes a comparator in which the drive waveform is input to a plus input terminal, a gate driver to which output of the comparator is input, a first N type MOSFET driven by the gate driver, and a second N type MOSFET driven by the gate driver, the drain of the first N type MOSFET is connected to a power source, the source of the first N type MOSFET is connected to the drain of the second N type MOSFET, and the source of the second N type MOSFET is connected to the ground, and includes negative feedback wiring for connecting the minus input terminal of the comparator, the source of the first N type MOSFET and the drain of the second N type MOSFET.SELECTED DRAWING: Figure 8

Description

The present technology relates to a printing device that ejects liquid from a nozzle.

2. Description of the Related Art Printing devices have been proposed that drive piezoelectric elements to eject liquid from nozzles. The piezoelectric element is driven by a drive circuit. The drive circuit includes a digital amplifier. The digital amplifier includes an arithmetic circuit that outputs an error signal based on a drive waveform signal and a feedback signal, and a modulation circuit that pulse-modulates the error signal from the arithmetic circuit and converts it into a modulation signal. The modulation circuit compares the error signal and the triangular wave. That is, the digital amplifier is a separately excited type digital amplifier.

Since the digital amplifier amplifies the pulse waveform as it is, power loss can be suppressed compared to the case where the error signal is amplified as it is in the analog waveform (see Patent Document 1).

Japanese Patent Application Publication No. 2013-140084

However, a separately excited digital amplifier requires a large number of circuits such as an arithmetic circuit and a modulation circuit, and the circuit size tends to increase.

The present disclosure has been made in view of such circumstances, and it is an object of the present disclosure to provide a printing device that can suppress the increase in size of an amplifier circuit that amplifies a drive waveform.

A printing device according to an embodiment of the present disclosure includes an amplification circuit that amplifies a drive waveform, and an energy imparting element that is driven by the drive waveform amplified by the amplification circuit to impart energy to a liquid and eject it from a nozzle. The amplifier circuit includes a comparator to which the drive waveform is input to a positive input terminal, a gate driver to which the output of the comparator is input, a first N-type MOSFET driven by the gate driver, and a first N-type MOSFET driven by the gate driver. a second N-type MOSFET driven by a driver, the drain of the first N-type MOSFET is connected to a power supply, the source of the first N-type MOSFET is connected to the drain of the second N-type MOSFET, and the second N-type MOSFET The source of the negative feedback wiring is connected to the ground, and the negative input terminal of the comparator is connected to the source of the first N-type MOSFET and the drain of the second N-type MOSFET.

In the printing device according to an embodiment of the present disclosure, the configuration of the amplifier circuit is simplified, and it is possible to suppress the increase in size of the amplifier circuit.

1 is a plan view schematically showing a printing apparatus according to a first embodiment; FIG. FIG. 2 is a schematic partially enlarged sectional view of an inkjet head. FIG. 2 is a block diagram of a control device. It is an explanatory diagram explaining an example of a drive waveform. FIG. 2 is an explanatory diagram illustrating an example of time series data, an analog signal, and a time division multiplexed signal. FIG. 2 is an explanatory diagram illustrating the relationship between a time division multiplex signal and a synchronization signal. FIG. 6 is a schematic diagram of a drive waveform input to an actuator by opening and closing an n-th switch. FIG. 2 is a circuit diagram schematically showing the configuration of an amplifier. FIG. 2 is a circuit diagram schematically showing the configurations of a gate driver circuit, an NMOS circuit, and a bootstrap circuit. 3 is a circuit diagram schematically showing the configuration of an amplifier, a control circuit, and a detection circuit of a printing apparatus according to a second embodiment. FIG. It is a graph showing the output voltage of the amplifier when the first process is not executed. It is a graph which shows the output voltage of an amplifier when performing a 1st process. FIG. 7 is a circuit diagram schematically showing the configuration of an amplifier and a control circuit of a printing apparatus according to a third embodiment. It is a graph showing the output voltage of the amplifier when the second process is not executed. It is a graph which shows the output voltage of an amplifier when performing a 2nd process. 12 is a circuit diagram schematically showing the configuration of an amplifier, a control circuit, and a detection circuit of a printing apparatus according to a fourth embodiment. FIG.

(Embodiment 1)
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on drawings showing a printing apparatus according to a first embodiment. FIG. 1 is a plan view schematically showing a printing apparatus. In the following description, the front, rear, left, and right directions shown in FIG. 1 will be used. The front-back direction corresponds to the transport direction, and the left-right direction corresponds to the scanning direction. In addition, the front side of FIG. 1 corresponds to the upper side, the back side corresponds to the lower side, and the upper and lower sides are also used.

As shown in FIG. 1, the printing device 1 includes a platen 2, an ink discharge device 3, conveyance rollers 4 and 5, and the like. A recording paper 200, which is a recording medium, is placed on the upper surface of the platen 2. The ink ejection device 3 ejects ink onto the recording paper 200 placed on the platen 2 to record an image. The ink ejection device 3 includes a carriage 6, a sub-tank 7, four inkjet heads 8, a circulation pump (not shown), and the like.

Two guide rails 11 and 12 extending left and right for guiding the carriage 6 are provided above the platen 2. An endless belt 13 extending left and right is connected to the carriage 6. The endless belt 13 is driven by a carriage drive motor 14. By driving the endless belt 13, the carriage 6 is guided by the guide rails 11 and 12 and reciprocated in the scanning direction in an area facing the platen 2. More specifically, while supporting the four inkjet heads 8, the carriage 6 performs two movements: a first movement in which the heads are moved from one position to another from left to right in the scanning direction; A second movement is performed in which the head is moved from another position to a certain position from the right to the left in the direction.

A cap 20 and a flushing receiver 21 are provided between the guide rails 11 and 12. The cap 20 and the flushing receiver 21 are arranged below the ink ejection device 3. The cap 20 is arranged at the right end of the guide rails 11, 12, and the flushing receiver 21 is arranged at the left end of the guide rails 11, 12. Note that the cap 20 and the flushing receiver 21 may be arranged with the right and left sides reversed.

The sub-tank 7 and four inkjet heads 8 are mounted on a carriage 6 and reciprocate together with the carriage 6 in the scanning direction. The sub-tank 7 is connected to the cartridge holder 15 via a tube 17. Ink cartridges 16 of one or more colors (four colors in this embodiment) are attached to the cartridge holder 15 . Examples of the four colors include black, yellow, cyan, and magenta.

Four ink chambers (not shown) are formed inside the sub-tank 7. Four color inks supplied from four ink cartridges 16 are stored in the four ink chambers, respectively.

The four inkjet heads 8 are arranged below the sub-tank 7 in the scanning direction. A plurality of nozzles 80 (see FIG. 2) are formed on the lower surface of each inkjet head 8. One inkjet head 8 corresponds to one color of ink and is connected to one ink chamber. That is, the four inkjet heads 8 correspond to four colors of ink, and are connected to four ink chambers, respectively.

The inkjet head 8 is provided with an ink supply port and an ink discharge port. The ink supply port and the ink discharge port are connected to the ink chamber via a tube or the like. A circulation pump is interposed between the ink supply port and the ink chamber.

Ink sent out from the ink chamber by the circulation pump flows into the inkjet head 8 through the ink supply port and is ejected from the nozzle 80. Ink that is not ejected from the nozzle 80 returns to the ink chamber through the ink discharge port. Ink circulates between the ink chamber and the inkjet head 8. The four inkjet heads 8 eject four color inks supplied from the sub-tank 7 onto the recording paper 200 while moving in the scanning direction together with the carriage 6 .

As shown in FIG. 1, the conveyance roller 4 is arranged upstream (rear) of the platen 2 in the conveyance direction. The conveyance roller 5 is arranged downstream (front side) of the platen 2 in the conveyance direction. The two transport rollers 4 and 5 are driven synchronously by a motor (not shown). The two transport rollers 4 and 5 transport the recording paper 200 placed on the platen 2 in a transport direction perpendicular to the scanning direction. The printing device 1 includes a control device 50 . The control device 50 includes a control circuit 51 (see FIG. 3) having a CPU or a logic circuit (for example, FPGA), a memory 55 such as a nonvolatile memory and a RAM, a network interface 56, and the like. Network interface 56 receives print jobs and drive waveform data from external device 100, and memory 55 stores the received print jobs and drive waveform data. The control device 50 controls the driving of the ink ejection device 3, the conveyance roller 4, etc. based on the print job, and executes printing processing. The control circuit 51 corresponds to a control section, and the network interface 56 corresponds to a reception section.

FIG. 2 is a schematic partially enlarged sectional view of the inkjet head 8. As shown in FIG. The inkjet head 8 includes a plurality of pressure chambers 81. A diaphragm 82 is formed above the pressure chamber 81 . A layered piezoelectric material 83 is formed above the diaphragm 82 . A first common electrode 84 is formed above each pressure chamber 81 and between the piezoelectric body 83 and the diaphragm 82 .

A second common electrode 86 is provided inside the piezoelectric body 83 . The second common electrode 86 is arranged above each pressure chamber 81 and above the first common electrode 84 . The second common electrode 86 is arranged at a position not facing the first common electrode 84. Individual electrodes 85 are formed above each pressure chamber 81 and on the top surface of the piezoelectric body 83 . The individual electrodes 85, the first common electrode 84, and the second common electrode 86 are vertically opposed to each other with the piezoelectric body 83 in between. The diaphragm 82, the piezoelectric body 83, the first common electrode 84, the individual electrodes 85, and the second common electrode 86 constitute an actuator 88.

A nozzle plate 87 is provided at the bottom of each pressure chamber 81. A plurality of nozzles 80 are formed in the nozzle plate 87, passing through the nozzle plate 87 vertically. Each nozzle 80 is arranged below each pressure chamber 81.

The first common electrode 84 is connected to a COM terminal, which in this embodiment is ground, and the second common electrode 86 is connected to a VCOM terminal. The VCOM voltage is higher than the COM voltage. Individual electrodes 85 are connected to switch group 54 (see FIG. 3). A high or low voltage is applied to the individual electrodes 85, the piezoelectric body 83 is deformed, and the diaphragm 82 vibrates. Vibration of the diaphragm 82 causes ink to be ejected from the pressure chamber 81 via the nozzle 80 .

The individual electrode 85 corresponds to the first electrode, the second common electrode 86 corresponds to the second electrode, and the first common electrode 84 corresponds to the third electrode. Further, the first portion 83a between the individual electrode 85 and the second common electrode 86 in the piezoelectric body 83 corresponds to the first piezoelectric layer, and the first portion 83a between the second common electrode 86 and the first common electrode 84 in the piezoelectric body 83 corresponds to the first piezoelectric layer. The second portion 83b corresponds to the second piezoelectric layer. The diaphragm 82 corresponds to the third piezoelectric layer. That is, the actuator 88 has a three-layer structure.

FIG. 3 is a block diagram of the control device 50. The control device 50 includes a control circuit 51, a D/A converter 52, an amplifier 53, a switch group 54, and a memory 55. The memory 55 stores drive waveform data. The drive waveform data is data indicating a voltage waveform applied to the individual electrode 85, that is, a drive waveform for driving the actuator 88, and is quantized data. In this embodiment, drive waveform data Da, Db, and Dc are stored in the memory 55.

D/A converter 52 converts the digital signal into an analog signal. The amplifier 53 is an amplifier circuit that amplifies analog signals. The switch group 54 includes a plurality of nth switches 54(n) (n=1, 2, . . . ). The n-th switch 54(n) is configured by, for example, an analog switch IC. One end of the plurality of n-th switches 54(n) is connected to the amplifier 53 via a common bus. The other end of each n-th switch 54(n) is connected to each individual electrode 85 corresponding to a plurality of nozzles 80. That is, one n-th switch 54 (n) is provided for one actuator 88.

The individual electrode 85, the first common electrode 84, and the piezoelectric body 83 constitute a first capacitor 89a. The individual electrode 85, the second common electrode 86, and the piezoelectric body 83 constitute a second capacitor 89b.

FIG. 4 is an explanatory diagram illustrating examples of drive waveforms A, B, and C. Drive waveforms A, B, and C deform the piezoelectric body 83, vibrate the diaphragm 82, and the vibration of the diaphragm 82 causes the ink in the pressure chamber 81 to pass through the descender through the nozzle 80. This is a waveform for ejecting. For example, drive waveform A is a waveform for dispensing large balls, drive waveform B is a waveform for dispensing medium balls, and drive waveform C is a waveform for discharging large balls. The ejection timing is different from waveform A. In FIG. 4, the right side shows a more past state than the left side. The same applies to FIGS. 5 to 7. Drive waveform data Da is quantized data of drive waveform A, drive waveform data Db is quantized data of drive waveform B, and drive waveform data Dc is quantized data of drive waveform C. The drive waveform data Da has quantized data Ak (k=0, 1, 2,...), the drive waveform data Db has quantized data Bk, and the drive waveform data Dc has quantized data Ak (k=0, 1, 2, ...). It has the data Ck.

FIG. 5 is an explanatory diagram illustrating an example of time series data, an analog signal, and a time division multiplexed signal. In FIG. 5, A, B, and C correspond to drive waveforms A, B, and C, respectively. When driving the actuator 88, the control circuit 51 accesses the memory 55, obtains drive waveform data Da, Db, and Dc, and creates time series data. The time series data is data Ak, Bk, Ck arranged in order with time interval Δt, and arranged in the order of A0, B0, C0, A1, B1, C1, ..., Ak, Bk, Ck. It is something. Time series data is a digital signal. Note that the time interval Δt is the reciprocal of the predetermined sampling frequency. The quantized data Ak, Bk, and Ck are arranged in the order of A0, B0, C0, A1, B1, C1, ..., Ak, Bk, Ck for each time corresponding to the reciprocal of a predetermined sampling frequency. . In other words, the data length of the quantized data Ak, Bk, and Ck is less than or equal to the length corresponding to the reciprocal of the predetermined sampling frequency. Further, quantized data A0 and quantized data B0 are continuous, quantized data B0 and quantized data C0 are continuous, and quantized data C0 and quantized data It is continuous with A1. That is, quantized data C0, other quantized data, and other waveform data are not present between quantized data A0 and quantized data B0. Further, between the quantized data B0 and the quantized data C0, there is no quantized data A0, other quantized data, or other waveform data. Further, between the quantized data C0 and the quantized data A1, there is no quantized data B0, other quantized data, or other waveform data. Note that the sampling frequency is 24 MHz, and the data length of the quantized data Ak, Bk, and Ck is approximately 41 nS.

Control circuit 51 outputs time series data to D/A converter 52. As shown in FIG. 5, the D/A converter 52 converts the time series data into an analog signal and outputs it to the amplifier 53. The amplifier 53 amplifies the input analog signal and outputs it to the switch group 54. As shown in FIG. 5, the analog signal amplified by the amplifier 53 constitutes a time division multiplexed signal. That is, the time division multiplexed signal is not an analog signal corresponding only to data Ak, an analog signal corresponding only to data Bk, or an analog signal corresponding only to data Ck. Further, the time division multiplexed signal includes at least an analog signal corresponding to a total of three data sets of one data Ak, one data Bk, and one data Ck, one data Ak+1, one data Bk+1, and one data Analog signals corresponding to a total of three data sets of Ck+1 are continuous signals in time series. For example, there is one time division multiplexed signal in FIG. In FIG. 5, the analog signal corresponding to data C0 appears to be isolated, but the analog signal corresponds to a total of three data sets, data A0, data B0, and data C0, and data A0 and data B0 are The analog signal in the 0 state is an analog signal corresponding to a total of three data sets of data A1, data B1, and data C1, and the result is that data A1 is continuous in time series with the analog signal in the 0 state. . Furthermore, although the analog signals corresponding to the data Ak and data Bk sets appear to be isolated, the analog signals corresponding to a total of three data sets of data Ak-1, data Bk-1, and data Ck-1 The result is that an analog signal in which data Ck-1 is 0 is time-sequentially followed by an analog signal corresponding to a total of three data sets of data Ak, data Bk, and data Ck. Further, the reason why the analog signal corresponding to the set of data Ak-1 and data Bk-1 appears to be isolated is also the same. Therefore, the analog signal in FIG. 5 can be handled as one time division multiplexed signal. In the time division multiplexed signal, a part corresponding to data Ak-1 is a first part, a part corresponding to data Ak is a second part, a part corresponding to data Bk-1 is a third part, and a part corresponding to data Bk is a part corresponding to data Bk. Assuming the fourth part, there is a third part between the first part and the second part, and a second part is between the third part and the fourth part. In other words, the first part and the third part are continuous, the third part and the second part are continuous, and the second part and the fourth part are continuous. That is, in the time division multiplexed signal, there are no second part, fourth part, or other waveforms between the first part and the third part. Further, in the time division multiplexed signal, there are no first part, fourth part, or other waveforms between the third part and the second part. Further, in the time division multiplexed signal, there are no first part, third part, or other waveforms between the second part and the fourth part. Note that a similar relationship holds true between data Ak and Ck, and a similar relationship holds true between data Bk and Ck. One time division multiplexed signal falls within one ejection drive cycle. For example, if the ejection drive frequency (injection frequency) is 100 kHz, one ejection drive period (injection period) is 10 μS, and one time division multiplexed signal has a length of less than 10 μS. It is preferable that one time division multiplexed signal has three or more data Ak, data Bk, and data Ck each. The reason will be explained later.

The control circuit 51 generates a switch control signal S1 that controls opening and closing of the plurality of n-th switches 54(n), a synchronization signal S2a corresponding to the drive waveform A, a synchronization signal S2b corresponding to the drive waveform B, and a drive waveform C. A synchronizing signal S2c corresponding to the synchronizing signal S2c is output to the switch group 54. Note that the three synchronization signals S2a, S2b, and S2c are also simply referred to as synchronization signal S2 (see FIG. 3). The switch control signal S1 includes first selection information indicating that one of the plurality of n-th switches 54(n) is selected, and second selection information indicating that one of the three synchronization signals S2a, S2b, and S2c is selected. selection information. The first selection information and the second selection information are linked.

Note that the control device 50 is provided with a synchronization signal generation circuit that generates three synchronization signals S2a, S2b, and S2c, and when a trigger signal is received from the control circuit 51, the three synchronization signals S2a are transmitted from the synchronization signal generation circuit to the switch group 54. , S2b and S2c may be output. The switch group 54 may also generate synchronization signals S2a, S2b, and S2c. Further, when receiving a trigger signal from the control circuit 51, the switch group 54 may generate synchronization signals S2a, S2b, and S2c.

FIG. 6 is an explanatory diagram illustrating the relationship between the time division multiplexed signal and the synchronization signals S2a, S2b, and S2c. The synchronizing signals S2a, S2b and S2c are pulse waves. A time interval Δt is provided between the rising time of the pulse of the synchronizing signal S2a and the rising time of the pulse of the synchronizing signal S2b. Further, a time interval Δt is provided between the rising time of the pulse of the synchronizing signal S2b and the rising time of the pulse of the synchronizing signal S2c, and the time interval Δt is provided between the rising time of the pulse of the synchronizing signal S2c and the rising time of the pulse of the synchronizing signal S2a. A time interval Δt is provided in between. As described above, the data Ak, Bk, and Ck constituting the time series data are arranged in order with a time interval Δt. Therefore, when the time division multiplexed signal is accessed at the rising edge of the pulse of the synchronization signal S2a, the drive waveform signal Pa corresponding to the data Ak and indicating the drive waveform A can be obtained. If the time division multiplexed signal is accessed at the rising edge of the pulse of the synchronization signal S2b, the drive waveform signal Pb corresponding to the data Bk and indicating the drive waveform B can be obtained. If the time division multiplexed signal is accessed at the rising edge of the pulse of the synchronization signal S2c, the drive waveform signal Pc corresponding to the data Ck and indicating the drive waveform C can be obtained. In other words, one n-th switch 54 (n) receives one type of time-division multiplexed signal and outputs a drive waveform signal Pa indicating drive waveform A, a drive waveform signal Pb indicating drive waveform B, and a drive waveform C. Any one of the drive waveform signals Pc shown is separated.

The switch group 54 opens and closes the selected nth switch 54(n) at the opening/closing timing indicated by the selected synchronization signals S2a to S2c. In other words, the switch group 54 opens and closes the n-th switch 54(n) at a predetermined sampling frequency.

FIG. 7 is a schematic diagram of a drive waveform input to the actuator 88 by opening and closing the n-th switch 54(n). When the synchronization signal S2a is selected, the switch group 54 closes the nth switch 54(n) when the pulse of the synchronization signal S2a is in a high level section, and closes the nth switch 54(n) when the pulse of the synchronization signal S2a is in a low level section. Open switch 54(n). The charge applied to the individual electrode 85 when the n-th switch 54(n) is closed is held by the first capacitor 89a and the second capacitor 89b, and as shown in FIG. 7, the drive waveform A1 is input to the actuator 88. be done. In other words, the drive waveform signal Pa is separated from the time division multiplexed signal using a predetermined sampling frequency, and the actuator 88 is driven by the drive waveform signal Pa. Note that three or more pieces of data Ak are required to represent the unevenness of the drive waveform signal Pa.

When the synchronization signal S2b is selected, the switch group 54 closes the nth switch 54(n) when the pulse of the synchronization signal S2b is in a high level section, and closes the nth switch 54(n) when the pulse of the synchronization signal S2b is in a low level section. Open switch 54(n). The charge applied to the individual electrode 85 when the n-th switch 54(n) is closed is held by the first capacitor 89a and the second capacitor 89b, and as shown in FIG. 7, the drive waveform B1 is input to the actuator 88. be done. In other words, the drive waveform signal Pb is separated from the time division multiplexed signal at a predetermined sampling frequency, and the actuator 88 is driven by the drive waveform signal Pb. Note that three or more pieces of data Bk are required to represent the unevenness of the drive waveform signal Pb.

When the synchronization signal S2c is selected, the switch group 54 closes the nth switch 54(n) when the pulse of the synchronization signal S2c is in a high level section, and closes the nth switch 54(n) when the pulse of the synchronization signal S2c is in a low level section. Open switch 54(n). The charge applied to the individual electrode 85 when the n-th switch 54(n) is closed is held by the first capacitor 89a and the second capacitor 89b, and as shown in FIG. 7, the drive waveform C1 is input to the actuator 88. be done. In other words, the drive waveform signal Pc is separated from the time division multiplexed signal at a predetermined sampling frequency, and the actuator 88 is driven by the drive waveform signal Pc. Note that three or more pieces of data Ck are required to represent the unevenness of the drive waveform signal Pc.

The predetermined sampling frequency is equal to or higher than the resonance frequency of the inkjet head 8. The resonance frequency of the inkjet head 8 is the resonance frequency when the pressure chamber 81 is not filled with ink (liquid), or the resonance frequency when the pressure chamber 81 is filled with ink. For example, if the resonance frequency of the inkjet head 8 when the pressure chamber 81 is not filled with ink is 100kHz, the resonance frequency of the inkjet head 8 when the pressure chamber 81 is filled with ink is less than 100kHz. Specifically, the resonance frequency of the inkjet head 8 is 90 kHz when the pressure chamber 81 is filled with ink. That is, the resonance frequency of the inkjet head 8 when the pressure chamber 81 is not filled with ink is higher than the resonance frequency of the inkjet head 8 when the pressure chamber 81 is filled with ink.

FIG. 8 is a circuit diagram schematically showing the configuration of the amplifier 53. The amplifier 53 is a self-excited digital amplifier. The amplifier 53 includes a comparator 53a, a gate driver circuit 53b, an NMOS circuit 53c, a bootstrap circuit 53d, a low-pass filter 53e, and a negative feedback wiring 53h.

A positive input terminal of the comparator 53a is connected to the D/A converter 52, and an analog signal from the D/A converter 52 is input to the positive input terminal of the comparator 53a. The output terminal of the comparator 53a is connected to the gate driver circuit 53b, and the output signal of the comparator 53a is input to the gate driver circuit 53b. The gate driver circuit 53b is connected to the NMOS circuit 53c, and outputs an on or off signal to the NMOS circuit 53c based on the output signal from the comparator 53a. The NMOS circuit 53c is driven by an on or off signal from the gate driver circuit 53b, and outputs a signal to a low pass filter (LPF) 53e.

The low-pass filter 53e includes an inductor 53f and a capacitor 53g. One end of the inductor 53f is connected to the NMOS circuit 53c, and the other end is connected to one end of the capacitor 53g. The other end of the capacitor 53g is connected to ground. The other end of the inductor 53f and one end of the capacitor 53g are connected to the switch group 54(n). That is, the low-pass filter 53e outputs a signal, that is, a time division multiplexed signal generated by amplifying the analog signal to the switch group 54(n). One end of the negative feedback wiring 53h is connected to the other end of the inductor 53f and one end of the capacitor 53g, and the other end of the negative feedback wiring 53h is connected to the negative input terminal of the comparator 53a. The bootstrap circuit 53d is connected to the gate driver circuit 53b and the NMOS circuit 53c.

FIG. 9 is a circuit diagram schematically showing the configurations of the gate driver circuit 53b, the NMOS circuit 53c, and the bootstrap circuit 53d. The gate driver circuit 53b includes a first gate driver 53b1 and a second gate driver 53b2. The NMOS circuit 53c includes a first N-type MOSFET 53c1 and a second N-type MOSFET 53c2. The first gate driver 53b1 is connected to the gate of the first N-type MOSFET 53c1. The second gate driver 53b2 is connected to the gate of the second N-type MOSFET 53c2. The drain of the first N-type MOSFET 53c1 is connected to the first power supply 53k. The source of the first N-type MOSFET 53c1 is connected to the drain of the second N-type MOSFET 53c2. The source of the second N-type MOSFET 53c2 is connected to ground. The source of the first N-type MOSFET 53c1 and the drain of the second N-type MOSFET 53c2 are connected to one end of a low-pass filter (LPF) 53e, that is, an inductor 53f. That is, the negative feedback wiring 53h is connected to the source of the first N-type MOSFET 53c1 and the drain of the second N-type MOSFET 53c2 via the low-pass filter 53e.

The bootstrap circuit 53d includes a second power supply 53d1, a diode 53d2, and a bootstrap capacitor 53d3. The negative terminal of the second power source 53d1 is connected to the ground, and the positive terminal of the second power source 53d1 is connected to the anode of the diode 53d2. The cathode of the diode 53d2 is connected to one end of the bootstrap capacitor 53d3. The other end of the bootstrap capacitor 53d3 is connected to the source of the first N-type MOSFET 53c1 and the drain of the second N-type MOSFET 53c2. Further, the cathode of the diode 53d2 and one end of the bootstrap capacitor 53d3 are connected to the first gate driver 53b1.

When the voltage input to the plus input terminal of the comparator 53a is lower than the voltage input to the minus input terminal, the comparator 53a outputs a Low signal to the gate driver circuit 53b. When a Low signal is input to the gate driver circuit 53b, the second gate driver 53b2 outputs an on signal to the gate of the second N-type MOSFET 53c2, and the first gate driver 53b1 does not output an on signal to the gate of the first N-type MOSFET 53c1. . That is, the second N-type MOSFET 53c2 is conductive, and the first N-type MOSFET 53c1 is not conductive. Therefore, the other end of the bootstrap capacitor 53d3 is connected to ground, and the bootstrap capacitor 53d3 is charged by the second power supply 53d1. In other words, the bootstrap capacitor 53d3 is charged by the conduction of the second N-type MOSFET 53c2.

After charging of the bootstrap capacitor 53d3 is completed, if the voltage input to the plus input terminal of the comparator 53a becomes higher than the voltage input to the minus input terminal, the comparator 53a outputs a High signal to the gate driver circuit 53b. . When a High signal is input to the gate driver circuit 53b, the first gate driver 53b1 outputs an ON signal to the gate of the first N-type MOSFET 53c1, and the second gate driver 53b2 does not output an ON signal to the gate of the second N-type MOSFET 53c2. . That is, the first N-type MOSFET 53c1 is conductive, and the second N-type MOSFET 53c2 is not conductive.

If the voltage at the source of the first N-type MOSFET 53c1 when the second N-type MOSFET 53c2 is non-conducting is VS, and the voltage applied across the charged bootstrap capacitor 53d3 is VC, then the voltage at one end of the bootstrap capacitor 53d3 is as follows: It becomes VS+VC. Therefore, the first gate driver 53b1 can output a signal of a voltage higher than the voltage VS of the source of the first N-type MOSFET 53c1, that is, an ON signal, to the gate of the first N-type MOSFET 53c1. That is, the first gate driver 53b1 makes the first N-type MOSFET 53c1 conductive using the voltage after charging the bootstrap capacitor 53d3. In other words, the first N-type MOSFET 53c1 cannot be made conductive until after the bootstrap capacitor 53d3 is charged. By conducting the first N-type MOSFET 53c1, a signal based on the voltage of the first power supply 53k is output to the low-pass filter 53e.

When the network interface 56 receives the print job, that is, when the print job is received via the network interface 56 and the print job is stored in the memory 55, the control circuit 51 makes the second N-type MOSFET 53c2 conductive and starts booting. Charge the strap capacitor 53d3. That is, the control circuit 51 can charge the bootstrap capacitor 53d3 before starting printing.

In the printing apparatus 1 according to the first embodiment, the amplifier 53 (amplification circuit) is a self-excited digital amplifier, and its configuration is simplified compared to a separately excited digital amplifier. Therefore, it is possible to suppress the increase in size of the amplifier circuit.

(Embodiment 2)
The present invention will be described below based on drawings showing a printing apparatus 1 according to a second embodiment. FIG. 10 is a circuit diagram schematically showing the configuration of the amplifier 53, the control circuit 51, and the detection circuit 57. Among the configurations of the second embodiment, configurations similar to those of the first embodiment are given the same reference numerals, and detailed description thereof will be omitted.

In the second embodiment, the gate driver circuit 53b has an enable function. When the enable function of the gate driver circuit 53b is turned on, that is, when the gate driver circuit 53b is in a valid state in which it outputs an output according to the output of the comparator 53a, the first gate driver 53b1 responds to the output of the comparator 53a. can turn on or off the first N-type MOSFET 53c1, and the second gate driver 53b2 can turn on or off the second N-type MOSFET 53c2.

When the enable function of the gate driver circuit 53b is turned off, that is, when the gate driver circuit 53b is in an invalid state in which it does not output according to the output of the comparator 53a, the first gate driver 53b1 forces the first N-type MOSFET 53c1. The second gate driver 53b2 forcibly turns off the second N-type MOSFET 53c2. The control circuit 51 turns on or off the enable function of the gate driver circuit 53b. That is, the gate driver circuit 53b can be switched between a valid state and an invalid state, and the control circuit 51 can set the gate driver circuit 53b to be a valid state or an invalid state.

The second embodiment differs from the first embodiment in that it includes a switch 531 and a detection circuit 57. The switch 531 connects the output terminal of the comparator 53a and ground, or disconnects the two. The control circuit 51 controls opening and closing of the switch 531.

The detection circuit 57 detects the output voltage of the amplifier 53 and outputs it to the control circuit 51. The detection circuit 57 corresponds to a voltage detection section. When the detection circuit 57 detects the first voltage with reference to 0 volts, the control circuit 51 closes the switch 531. That is, the control circuit 51 connects the output terminal of the comparator 53a and the ground. The first voltage is a voltage within a predetermined range based on 0 volts, for example, a voltage within a range of 0 to 0.5V.

When the detection circuit 57 detects a second voltage based on a voltage other than 0 volts, the control circuit 51 turns off the enable function of the gate driver circuit 53b. That is, the control circuit 51 disables the gate driver circuit 53b. The second voltage is a substantially constant voltage that the amplifier 53 should output for a predetermined period of time, and is, for example, a voltage within a predetermined range based on the maximum voltage value Vs that is input to the positive input terminal of the comparator 53a for a predetermined period of time. For example, the voltage is within the range of Vs-0.5 to Vs+0.5V. Note that the maximum value Vs is stored in the memory 55 in advance. The second voltage is not limited to a voltage within a predetermined range based on the maximum voltage value Vs, but may be a voltage within a predetermined range based on a voltage other than 0 volt. Hereinafter, the process of closing the switch 531 and the process of turning off the enable function of the gate driver circuit 53b described above will be referred to as a first process.

FIG. 11 is a graph showing the output voltage of the amplifier 53 when the first process is not executed. The horizontal axis in FIG. 11 shows time, with the right side showing the past and the left side showing the future. The same applies to FIGS. 12, 14, and 15, which will be described later. When the first process is not executed, the control circuit 51 always opens the switch 531 and always turns on the enable function of the gate driver circuit 53b. In other words, when the first process is not executed, the state is the same as if the amplifier 53 does not include the switch 531 and the gate driver circuit 53b does not include the enable function.

As shown in A of FIG. 11, the output waveform of the amplifier 53 pulsates in the vicinity of Vs. As shown in FIG. 11B, the output waveform of the amplifier 53 pulsates in the vicinity of 0 volts. That is, when the amplifier 53 should output a substantially constant voltage, the output waveform of the amplifier 53 waveforms. This is due to the following reasons.

A substantially constant voltage is input to the positive input terminal of the amplifier 53. When the voltage input to the minus input terminal of the comparator 53a becomes higher than the voltage input to the plus input terminal, the comparator 53a outputs a Low signal. The second N-type MOSFET 53c2 is turned on, the first N-type MOSFET 53c1 is turned off, and the output voltage of the NMOS circuit 53c decreases. The voltage input to the minus input terminal of the comparator 53a via the negative feedback wiring 53h decreases and becomes lower than the voltage input to the plus input terminal. The comparator 53a outputs a High signal, the second N-type MOSFET 53c2 is turned off, and the first N-type MOSFET 53c1 is turned on, thereby increasing the output voltage of the NMOS circuit 53c. The voltage input to the minus input terminal of the comparator 53a via the negative feedback wiring 53h increases and becomes higher than the voltage input to the plus input terminal. The comparator 53a outputs a Low signal again, the second N-type MOSFET 53c2 is turned on, and the first N-type MOSFET 53c1 is turned off, thereby decreasing the output voltage of the NMOS circuit 53c.

The waveform generated by the above-described operation in the NMOS circuit 53c is averaged through the low-pass filter 53e and output. Therefore, the output waveform of the amplifier 53 has a pulsating waveform. When the amplifier 53 should output a substantially constant voltage, the output waveform of the amplifier 53 is wavy, which impedes the generation of accurate drive waveforms and deteriorates the accuracy of ink ejection and the accuracy of the image formed on the recording paper 200. There is a risk of

FIG. 12 is a graph showing the output voltage of the amplifier 53 when the first process is executed. The control circuit 51 executes the first process. When the detection circuit 57 detects the first voltage, the control circuit 51 closes the switch 531, and when the detection circuit 57 does not detect the first voltage, the control circuit 51 opens the switch 531. When the detection circuit 57 detects the second voltage, the enable function of the gate driver circuit 53b is turned off, and when the detection circuit 57 does not detect the second voltage, the enable function of the gate driver circuit 53b is turned on.

As shown in A' in FIG. 12, when the detection circuit 57 detects the second voltage for a predetermined period of time, the enable function of the gate driver circuit 53b is turned off for a predetermined period of time. The voltage input to the input terminal remains approximately constant for a predetermined period of time, and the output waveform of the amplifier 53 has a linear shape near Vs.

As shown in B' of FIG. 12, when the detection circuit 57 detects the first voltage for a predetermined time, the control circuit 51 closes the switch 531 for a predetermined time, so that the output voltage of the comparator 53a is maintained at approximately 0V for a predetermined time. , the second N-type MOSFET 53c2 remains on for a predetermined time, and the output waveform of the amplifier 53 has a linear shape near 0V. That is, when the amplifier 53 should output a substantially constant voltage, the amplifier 53 outputs a substantially constant voltage. Therefore, accurate generation of drive waveforms can be achieved.

(Embodiment 3)
The present invention will be described below based on drawings showing a printing apparatus according to a third embodiment. Among the configurations according to Embodiment 3, configurations similar to those in Embodiment 1 or 2 are given the same reference numerals, and detailed description thereof will be omitted. FIG. 13 is a circuit diagram schematically showing the configuration of the amplifier 53 and the control circuit 51. In the third embodiment, the power supply configuration of the amplifier 53 is a single power supply configuration to which a voltage of 0 volt or more is supplied. The voltage of the first power supply 53k is variable. The control circuit 51 can change the voltage of the first power supply 53k. The control circuit 51 reads the drive waveform data stored in the memory 55 and outputs the drive waveform data to the D/A converter 52 as digital data. The drive waveform data includes information indicating a plurality of signal levels. The D/A converter 52 outputs an analog signal at any signal level. The amplification factor of the amplifier 53 is a variable value, and is, for example, 10 times. The user can set the amplification factor of the amplifier 53 in advance.

The control circuit 51 acquires drive waveform data from the memory 55, and when the acquired drive waveform data is a signal indicating 0 volts, that is, a signal indicating 0 volts as a signal indicating the target voltage to be output from the amplifier 53. is input to the control circuit 51, the control circuit 51 outputs a signal indicating a voltage less than 0 volts to the D/A converter 52. That is, a voltage of less than 0 volts is inputted to the positive terminal of the comparator 53a via the D/A converter 52.

When the control circuit 51 acquires drive waveform data from the memory 55, and the acquired drive waveform data is a voltage higher than 0 volts and indicates a substantially constant voltage that the amplifier 53 should output for a predetermined period, for example, the comparator 53a When the maximum voltage value Vs input to the positive input terminal for a predetermined period is indicated, the control circuit 51 changes the supply voltage of the first power supply 53k to the target voltage Vs. The control circuit 51 also controls the D/A converter 52 so that the product of the voltage input to the positive terminal of the comparator 53a and the amplification factor of the amplifier 53 is higher than the target voltage Vs, that is, the supply voltage. The level of the signal output from 52 is selected. In other words, when the target voltage is higher than 0 volts, the control circuit 51 sets the supply voltage of the first power supply 52k to the target voltage, which is the voltage input to the positive terminal of the comparator 53a and the voltage of the amplifier 53. Change the voltage to be lower than the product of the amplification factor. Hereinafter, the process of changing the supply voltage to the target voltage and the process of making the product of the voltage input to the positive terminal of the comparator 53a and the amplification factor of the amplifier 53 higher than the target voltage will be referred to as second process.

FIG. 14 is a graph showing the output voltage of the amplifier when the second process is not executed. When the second process is not executed, the control circuit 51 does not always change the supply voltage of the first power supply 52k and does not change the level of the signal output to the D/A converter 52. In other words, when the second process is not executed, the voltage of the first power supply 52k is not variable, and the D/A converter 52 is in the same state as not having the function of changing the level of the output signal.

As shown in FIG. 14C, the output waveform of the amplifier 53 pulsates in the vicinity of 0 volts. As shown in D of FIG. 14, the output waveform of the amplifier 53 pulsates in the vicinity of Vs. Note that in FIG. 14, the supply voltage Vk of the first power supply 53k is larger than the maximum voltage value Vs. That is, when the amplifier 53 should output a substantially constant voltage, the output waveform of the amplifier 53 waveforms. The reason is the same as the reason described in the second embodiment.

FIG. 15 is a graph showing the output voltage of the amplifier when the second process is executed. The control circuit 51 executes the second process. When a signal indicating 0 volts is input to the control circuit 51, the control circuit 51 inputs a voltage less than 0 volts to the positive terminal of the comparator 53a via the D/A converter 52. As described above, the power supply configuration of the amplifier 53 is a single power supply configuration in which a voltage of 0 volts or more is supplied, and the comparator 53a cannot output a voltage of less than 0 volts. Therefore, as shown in C' in FIG. 15, when a voltage of less than 0 volts is input to the positive terminal for a predetermined period of time, the comparator 53a outputs 0 volts, that is, a Low signal, and the amplifier 53 outputs 0 volts for a predetermined period of time. do.

As shown in FIG. 15, when the acquired drive waveform data indicates the maximum voltage value Vs that is input to the positive input terminal of the comparator 53a for a predetermined period, the control circuit 51 adjusts the supply voltage Vk of the first power supply 53k to the target voltage Vs. change. Further, as shown by the dashed line in FIG. 15, the control circuit 51 changes the level of the output signal of the D/A converter 52, so that the product Vp of the voltage input to the positive terminal of the comparator 53a and the amplification factor of the amplifier 53 is The target voltage Vs is set to be higher than the supply voltage Vk. As shown at D' in FIG. 15, since the amplifier 53 cannot amplify more than the supply voltage Vk, the output voltage of the amplifier 53 is fixed to the supply voltage Vk. By executing the second process as described above, when the amplifier 53 should output a substantially constant voltage, the amplifier 53 outputs a substantially constant voltage. Therefore, accurate generation of drive waveforms can be achieved.

(Embodiment 4)
The present invention will be described below based on drawings showing a printing apparatus 1 according to a fourth embodiment. FIG. 16 is a circuit diagram schematically showing the configuration of the amplifier 53, the control circuit 51, and the detection circuit 57. Among the configurations according to Embodiment 4, configurations similar to those in Embodiment 2 or 3 are given the same reference numerals, and detailed description thereof will be omitted. In the fourth embodiment, the printing apparatus 1 includes a detection circuit 57. The detection circuit 57 detects the output voltage of the amplifier 53 and outputs it to the control circuit 51.

When the detection circuit 57 detects the first voltage (see Embodiment 2) based on 0 volts, the control circuit 51 outputs a signal indicating a voltage less than 0 volts to the D/A converter 52. That is, a voltage of less than 0 volts is inputted to the positive terminal of the comparator 53a via the D/A converter 52.

When the detection circuit 57 detects the second voltage (see Embodiment 2) based on a voltage other than 0 volts, the control circuit 51 changes the voltage supplied by the first power source 53k to the target voltage Vs. The control circuit 51 also changes the level of the output signal of the D/A converter 52, so that the product of the voltage input to the positive terminal of the comparator 53a and the amplification factor of the amplifier 53 becomes higher than the target voltage Vs, that is, the supply voltage. Do it like this. In other words, when the target voltage is higher than 0 volts, the control circuit 51 sets the supply voltage of the first power supply 52k to the target voltage, which is the voltage input to the positive terminal of the comparator 53a and the voltage of the amplifier 53. Change the voltage to be lower than the product of the amplification factor. That is, based on the detection result of the detection circuit 57, the second process (see Embodiment 3) is executed.

In the first to fourth embodiments, the diaphragm 82, the piezoelectric body 83, the first common electrode 84, the individual electrode 85, and the second common electrode 86 constitute the actuator 88, but the present invention is not limited thereto. There may be one common electrode. That is, it may be a two-layer material. The two-layer material is composed of a diaphragm 82, a piezoelectric body 83, a common electrode, and individual electrodes 85.

The embodiments disclosed herein are illustrative in all respects and should be considered not to be restrictive. The scope of the present invention is intended to include all modifications within the scope of the claims and the range of equivalents to the scope of the claims. Items described in each embodiment can be combined with each other. Moreover, the independent claims and dependent claims recited in the claims may be combined with each other in any and all combinations, regardless of the form in which they are cited. Further, although the scope of claims uses a format in which claims refer to two or more other claims (multi-claim format), the invention is not limited to this format. It may be written using a multi-claim format that cites at least one multi-claim.

1 Printing device 51 Control circuit (control unit)
53 Amplifier (amplification circuit)
53a Comparator 53b Gate driver circuit 53c NMOS circuit 53c1 1st N-type MOSFET
53c2 2nd N-type MOSFET
53h Negative feedback wiring 531 Switch 57 Detection circuit (voltage detection section)
88 Actuator (energy imparting element)

Claims (8)

an amplifier circuit that amplifies the drive waveform;
an energy imparting element that is driven by the drive waveform amplified by the amplifier circuit, imparts energy to the liquid, and causes the liquid to be ejected from the nozzle;
The amplification circuit includes:
a comparator to which the drive waveform is input to a positive input terminal;
a gate driver into which the output of the comparator is input;
a first N-type MOSFET driven by the gate driver;
a second N-type MOSFET driven by the gate driver;
Equipped with
The drain of the first N-type MOSFET is connected to a power supply,
The source of the first N-type MOSFET is connected to the drain of the second N-type MOSFET,
The source of the second N-type MOSFET is connected to ground,
A printing device comprising a negative feedback wiring connecting a negative input terminal of the comparator, a source of the first N-type MOSFET, and a drain of the second N-type MOSFET. The printing apparatus according to claim 1, wherein the negative feedback wiring is connected to the source of the first N-type MOSFET and the drain of the second N-type MOSFET via a low-pass filter. a switch connecting the output terminal of the comparator and ground;
a voltage detection unit that detects the output voltage of the amplifier circuit;
Equipped with a control unit and
The printing apparatus according to claim 1 , wherein the control unit closes the switch when the voltage detection unit detects a first voltage based on 0 volts. a voltage detection unit that detects the output voltage of the amplifier circuit;
Equipped with a control unit and
The gate driver is capable of switching between a valid state in which it outputs an output according to the output of the comparator and an invalid state in which it does not output in accordance with the output of the comparator,
The printing apparatus according to claim 1 , wherein when the voltage detection unit detects a second voltage based on a voltage other than 0 volts, the control unit disables the gate driver. Equipped with a control unit,
A signal indicating a target voltage to be output from the amplifier circuit is input to the control unit,
The printing apparatus according to claim 1 , wherein when the target voltage is 0 volts, the control unit inputs a voltage lower than 0 volts to the positive terminal of the comparator. a voltage detection unit that detects the output voltage of the amplifier circuit;
Equipped with a control unit and
The printing apparatus according to claim 1 , wherein when the voltage detection unit detects a first voltage based on 0 volts, the control unit inputs a voltage lower than 0 volts to the positive terminal of the comparator. Equipped with a control unit,
The power supply is a power supply whose supply voltage can be changed,
A signal indicating a target voltage to be output from the amplifier circuit is input to the control unit,
When the target voltage is higher than 0 volts, the control unit sets the supply voltage of the power source to the target voltage, which is equal to the voltage input to the positive terminal of the comparator and the amplification factor of the amplifier circuit. The printing apparatus according to claim 1 or 2, wherein the voltage is changed to a voltage lower than the product of . a voltage detection unit that detects the output voltage of the amplifier circuit;
Equipped with a control unit and
The power supply is a power supply whose supply voltage can be changed,
When the voltage detection unit detects a second voltage based on a voltage other than 0 volts, the control unit sets the supply voltage of the power supply to the target voltage to be output from the amplifier circuit, and the controller The printing apparatus according to claim 1 or 2, wherein the voltage is changed to a voltage lower than the product of the voltage input to the positive terminal of the printer and the amplification factor of the amplifier circuit.

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