JP2022188285A5 - Semiconductor device manufacturing method - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 80
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 1
Description
本発明は、半導体装置の製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor device .
深さの異なる複数のトレンチを有する半導体装置の製造方法を提供する。 A method of manufacturing a semiconductor device having a plurality of trenches with different depths is provided.
本発明の一つの態様においては、半導体基板のおもて面の上方に面積が異なる第1開口および第2開口を有するマスクを形成する工程と、前記第1開口を通じて前記半導体基板をエッチングし第1トレンチを形成すると共に、前記第2開口を通じて前記半導体基板をエッチングし前記第1トレンチと深さが異なる第2トレンチを形成する工程と、前記第1トレンチの内壁に第1絶縁膜を形成すると共に、前記第2トレンチの内壁に第2絶縁膜を形成する工程と、前記第1トレンチの内部に第1導電材料を充填すると共に、前記第2トレンチの内部に第2導電材料を充填する工程と、前記半導体基板の前記おもて面よりも深い位置まで前記第1導電材料をエッチングして第1導電部を形成すると共に、前記半導体基板の前記おもて面よりも深い位置まで前記第2導電材料をエッチングして第2導電部を形成する工程と、を含む半導体装置の製造方法を提供する。本発明の他の態様においては、半導体基板をエッチングし第1トレンチを形成すると共に、前記半導体基板をエッチングし前記第1トレンチと深さが異なる第2トレンチを形成する工程と、前記第1トレンチの内壁に第1絶縁膜を形成すると共に、前記第2トレンチの内壁に第2絶縁膜を形成する工程と、前記第1トレンチの内部に第1導電部を形成すると共に、前記第2トレンチの内部に第2導電部を形成する工程と、を含み、前記第1トレンチおよび前記第2トレンチは、第1方向に配列され、前記第1方向および前記半導体基板の深さ方向の両方に平行ないずれかの断面において、前記半導体基板のおもて面から前記第1導電部の上端までの距離が、前記おもて面から前記第2導電部の上端までの距離と異なるように、前記第1導電部および前記第2導電部が形成される半導体装置の製造方法を提供する。本発明の他の態様においては、半導体基板をエッチングし第1トレンチを形成すると共に、前記半導体基板をエッチングし前記第1トレンチと深さが異なる第2トレンチを形成する工程と、前記第1トレンチの内壁に第1絶縁膜を形成すると共に、前記第2トレンチの内壁に第2絶縁膜を形成する工程と、前記第1トレンチの内部に第1導電部を形成すると共に、前記第2トレンチの内部に第2導電部を形成する工程と、を含み、前記第1トレンチおよび前記第2トレンチは、第1方向に配列され、前記第1方向および前記半導体基板の深さ方向の両方に平行ないずれかの断面において、前記半導体基板のおもて面から前記第1導電部の表面の最も深い部分までの距離が、前記おもて面から前記第2導電部の表面の最も深い部分までの距離と異なるように、前記第1導電部および前記第2導電部が形成される半導体装置の製造方法を提供する。本発明の他の態様に係る半導体装置は、第1導電型の半導体基板のおもて面側に形成された第2導電型の第1半導体領域と、第1半導体領域よりもおもて面側の一部に選択的に形成された第1導電型の第2半導体領域と、を備えてよい。半導体装置は、複数のトレンチを備えてよい。トレンチは、半導体基板のおもて面側において予め定められた延伸方向に延び、且つ、第1半導体領域の下方まで至ってよい。半導体装置は、導電部を備えてよい。導電部は、複数のトレンチの内部に充填されてよい。半導体装置は、層間絶縁膜を備えてよい。層間絶縁膜は、半導体基板のおもて面を所定のパターンで覆ってよい。半導体装置は、第1電極を備えてよい。第1電極は、トレンチに挟まれたメサ領域において、層間絶縁膜から露出する露出領域を介して半導体基板に接続してよい。半導体装置は、延伸方向と垂直な断面において、第1トレンチ部を含んでよい。第1トレンチ部は、半導体基板の表面から導電部の表面の最も深い部分までが所定距離である。半導体装置は、延伸方向と垂直な断面において、第2トレンチ部を含んでよい。第2トレンチ部は、半導体基板の表面から導電部の表面の最も深い部分までが所定距離よりも長くてよい。第1トレンチ部および第2トレンチ部は、それぞれのトレンチが、トレンチの側壁の傾斜よりも露出領域側に傾斜した肩部を上端に有してよい。 In one aspect of the present invention, the steps of forming a mask having a first opening and a second opening having different areas above the front surface of a semiconductor substrate; forming a first trench, etching the semiconductor substrate through the second opening to form a second trench having a depth different from that of the first trench, and forming a first insulating film on an inner wall of the first trench. forming a second insulating film on the inner wall of the second trench; filling the interior of the first trench with a first conductive material; filling the interior of the second trench with a second conductive material; and etching the first conductive material to a position deeper than the front surface of the semiconductor substrate to form a first conductive portion, and etching the first conductive material to a position deeper than the front surface of the semiconductor substrate. and etching the conductive material to form a second conductive portion. In another aspect of the present invention, the steps of etching a semiconductor substrate to form a first trench and etching the semiconductor substrate to form a second trench having a depth different from that of the first trench; forming a first insulating film on the inner wall of the second trench and forming a second insulating film on the inner wall of the second trench; forming a first conductive portion inside the first trench; and forming a second conductive portion therein, wherein the first trench and the second trench are arranged in a first direction and parallel to both the first direction and the depth direction of the semiconductor substrate. In any cross section, the distance from the front surface of the semiconductor substrate to the upper end of the first conductive portion is different from the distance from the front surface to the upper end of the second conductive portion. A method of manufacturing a semiconductor device is provided in which one conductive portion and the second conductive portion are formed. In another aspect of the present invention, the steps of etching a semiconductor substrate to form a first trench and etching the semiconductor substrate to form a second trench having a depth different from that of the first trench; forming a first insulating film on the inner wall of the second trench and forming a second insulating film on the inner wall of the second trench; forming a first conductive portion inside the first trench; and forming a second conductive portion therein, wherein the first trench and the second trench are arranged in a first direction and parallel to both the first direction and the depth direction of the semiconductor substrate. In any cross section, the distance from the front surface of the semiconductor substrate to the deepest part of the surface of the first conductive part is the distance from the front surface to the deepest part of the surface of the second conductive part. A method for manufacturing a semiconductor device is provided in which the first conductive portion and the second conductive portion are formed with different distances. A semiconductor device according to another aspect of the present invention includes: a first semiconductor region of a second conductivity type formed on a front surface side of a semiconductor substrate of a first conductivity type; and a second semiconductor region of the first conductivity type selectively formed in a portion of the side. A semiconductor device may comprise a plurality of trenches. The trench may extend in a predetermined extending direction on the front surface side of the semiconductor substrate and reach below the first semiconductor region. The semiconductor device may comprise a conductive portion. The conductive portion may be filled inside the plurality of trenches. The semiconductor device may include an interlayer insulating film. The interlayer insulating film may cover the front surface of the semiconductor substrate in a predetermined pattern. The semiconductor device may comprise a first electrode. The first electrode may be connected to the semiconductor substrate through an exposed region exposed from the interlayer insulating film in the mesa region sandwiched between the trenches. The semiconductor device may include a first trench section in a cross section perpendicular to the extending direction. The first trench part has a predetermined distance from the surface of the semiconductor substrate to the deepest part of the surface of the conductive part. The semiconductor device may include a second trench portion in a cross section perpendicular to the extending direction. In the second trench portion, the distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion may be longer than a predetermined distance. Each of the first trench portion and the second trench portion may have a shoulder portion at an upper end that slopes toward the exposed region side with respect to the slope of the sidewall of the trench.
Claims (15)
前記第1開口を通じて前記半導体基板をエッチングし第1トレンチを形成すると共に、前記第2開口を通じて前記半導体基板をエッチングし前記第1トレンチと深さが異なる第2トレンチを形成する工程と、 etching the semiconductor substrate through the first opening to form a first trench, and etching the semiconductor substrate through the second opening to form a second trench having a depth different from that of the first trench;
前記第1トレンチの内壁に第1絶縁膜を形成すると共に、前記第2トレンチの内壁に第2絶縁膜を形成する工程と、 forming a first insulating film on the inner wall of the first trench and forming a second insulating film on the inner wall of the second trench;
前記第1トレンチの内部に第1導電材料を充填すると共に、前記第2トレンチの内部に第2導電材料を充填する工程と、 filling the interior of the first trench with a first conductive material and filling the interior of the second trench with a second conductive material;
前記半導体基板の前記おもて面よりも深い位置まで前記第1導電材料をエッチングして第1導電部を形成すると共に、前記半導体基板の前記おもて面よりも深い位置まで前記第2導電材料をエッチングして第2導電部を形成する工程と、 Etching the first conductive material to a position deeper than the front surface of the semiconductor substrate to form a first conductive part, and forming the second conductive part to a position deeper than the front surface of the semiconductor substrate. etching the material to form a second conductive portion;
を含む半導体装置の製造方法。A method of manufacturing a semiconductor device comprising:
前記第1方向および前記半導体基板の深さ方向の両方に平行ないずれかの断面において、前記おもて面から前記第1導電部の上端までの距離が、前記おもて面から前記第2導電部の上端までの距離と異なるように、前記第1導電部および前記第2導電部が形成される In any cross section parallel to both the first direction and the depth direction of the semiconductor substrate, the distance from the front surface to the upper end of the first conductive portion is the second distance from the front surface. The first conductive portion and the second conductive portion are formed so that the distance to the upper end of the conductive portion is different.
請求項1に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1.
前記おもて面から前記第1導電部の上端までの距離が、前記おもて面から前記第2導電部の上端までの距離よりも浅い前記断面を有するように、前記第1導電部および前記第2導電部が形成される The first conductive portion and the the second conductive portion is formed
請求項2に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2.
前記第1トレンチの内壁に第1絶縁膜を形成すると共に、前記第2トレンチの内壁に第2絶縁膜を形成する工程と、 forming a first insulating film on the inner wall of the first trench and forming a second insulating film on the inner wall of the second trench;
前記第1トレンチの内部に第1導電部を形成すると共に、前記第2トレンチの内部に第2導電部を形成する工程と、 forming a first conductive portion inside the first trench and forming a second conductive portion inside the second trench;
を含み、including
前記第1トレンチおよび前記第2トレンチは、第1方向に配列され、 the first trench and the second trench are arranged in a first direction;
前記第1方向および前記半導体基板の深さ方向の両方に平行ないずれかの断面において、前記半導体基板のおもて面から前記第1導電部の上端までの距離が、前記おもて面から前記第2導電部の上端までの距離と異なるように、前記第1導電部および前記第2導電部が形成される In any cross section parallel to both the first direction and the depth direction of the semiconductor substrate, the distance from the front surface of the semiconductor substrate to the upper end of the first conductive portion is The first conductive part and the second conductive part are formed so that the distance to the upper end of the second conductive part is different.
半導体装置の製造方法。 A method of manufacturing a semiconductor device.
前記第1方向および前記半導体基板の深さ方向の両方に平行ないずれかの断面において、前記おもて面から前記第1導電部の表面の最も深い部分までの距離が、前記おもて面から前記第2導電部の表面の最も深い部分までの距離と異なるように、前記第1導電部および前記第2導電部が形成される In any cross section parallel to both the first direction and the depth direction of the semiconductor substrate, the distance from the front surface to the deepest part of the surface of the first conductive part is the front surface. to the deepest part of the surface of the second conductive part, the first conductive part and the second conductive part are formed so as to be different from the distance from
請求項1に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1.
前記おもて面から前記第1導電部の表面の最も深い部分までの距離が、前記おもて面から前記第2導電部の表面の最も深い部分までの距離よりも浅い前記断面を有するように、前記第1導電部および前記第2導電部が形成される The distance from the front surface to the deepest part of the surface of the first conductive part is such that the cross section is shallower than the distance from the front surface to the deepest part of the surface of the second conductive part. The first conductive portion and the second conductive portion are formed in
請求項5に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5.
前記第1トレンチの内壁に第1絶縁膜を形成すると共に、前記第2トレンチの内壁に第2絶縁膜を形成する工程と、 forming a first insulating film on the inner wall of the first trench and forming a second insulating film on the inner wall of the second trench;
前記第1トレンチの内部に第1導電部を形成すると共に、前記第2トレンチの内部に第2導電部を形成する工程と、 forming a first conductive portion inside the first trench and forming a second conductive portion inside the second trench;
を含み、including
前記第1トレンチおよび前記第2トレンチは、第1方向に配列され、 the first trench and the second trench are arranged in a first direction;
前記第1方向および前記半導体基板の深さ方向の両方に平行ないずれかの断面において、前記半導体基板のおもて面から前記第1導電部の表面の最も深い部分までの距離が、前記おもて面から前記第2導電部の表面の最も深い部分までの距離と異なるように、前記第1導電部および前記第2導電部が形成される In any cross section parallel to both the first direction and the depth direction of the semiconductor substrate, the distance from the front surface of the semiconductor substrate to the deepest portion of the surface of the first conductive portion is The first conductive portion and the second conductive portion are formed so as to be different from the distance from the front surface to the deepest part of the surface of the second conductive portion.
半導体装置の製造方法。 A method of manufacturing a semiconductor device.
請求項1から7のいずれか1項に記載の半導体装置の製造方法。 8. The method of manufacturing a semiconductor device according to claim 1.
請求項1から8のいずれか1項に記載の半導体装置の製造方法。 9. The method of manufacturing a semiconductor device according to claim 1.
請求項1から9のいずれか1項に記載の半導体装置の製造方法。 10. The method of manufacturing a semiconductor device according to claim 1.
少なくとも前記肩部を含んだ範囲に不俊物を注入して、前記ドリフト領域よりも不純物濃度が高い第1導電型の第1半導体領域を形成する工程を含む forming a first conductivity type first semiconductor region having an impurity concentration higher than that of the drift region by implanting an impurity into a range including at least the shoulder portion;
請求項10に記載の半導体装置の製造方法。 11. The method of manufacturing a semiconductor device according to claim 10.
少なくとも前記肩部を含んだ範囲に不俊物を注入して、前記第2半導体領域よりも不純物濃度が高い第2導電型のコンタクト領域を形成する工程と、 forming a contact region of a second conductivity type having a higher impurity concentration than the second semiconductor region by implanting an impurity into a range including at least the shoulder portion;
を含む請求項10または11に記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 10, comprising:
前記半導体基板の前記おもて面側に第2導電型の第2半導体領域を形成する工程と、 forming a second semiconductor region of a second conductivity type on the front surface side of the semiconductor substrate;
前記ドリフト領域よりも不純物濃度が高い第1導電型の第1半導体領域を、前記第2半導体領域よりもおもて面側の一部に選択的に形成する工程と、 a step of selectively forming a first conductivity type first semiconductor region having an impurity concentration higher than that of the drift region in a portion closer to the front surface than the second semiconductor region;
前記第2半導体領域よりも不純物濃度が高い第2導電型のコンタクト領域を、前記第2半導体領域よりも前記おもて面側の一部に選択的に形成する工程と、 a step of selectively forming a contact region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region in a portion closer to the front surface than the second semiconductor region;
を含み、 including
前記第1トレンチおよび前記第2トレンチは、第2方向に延伸し、 the first trench and the second trench extend in a second direction;
前記第2方向において、前記第1半導体領域と前記コンタクト領域とが交互に配置される The first semiconductor regions and the contact regions are alternately arranged in the second direction.
請求項10に記載の半導体装置の製造方法。 11. The method of manufacturing a semiconductor device according to claim 10.
前記メサ領域において前記層間絶縁膜から露出する露出領域を介して前記半導体基板に接続する上面電極を形成する工程と、 forming a top electrode connected to the semiconductor substrate through an exposed region exposed from the interlayer insulating film in the mesa region;
を含む請求項10から13のいずれか1項に記載の半導体装置の製造方法。14. The method of manufacturing a semiconductor device according to any one of claims 10 to 13, comprising:
前記第2トレンチ、前記第2絶縁膜および前記第2導電部は、第2トレンチ部であり、 the second trench, the second insulating film and the second conductive portion are a second trench portion;
前記第1トレンチ部および前記第2トレンチ部は、ゲート電極に接続されたゲートトレンチ部または前記上面電極に接続されたダミートレンチ部である The first trench portion and the second trench portion are a gate trench portion connected to the gate electrode or a dummy trench portion connected to the upper surface electrode.
請求項14に記載の半導体装置の製造方法。 15. The method of manufacturing a semiconductor device according to claim 14.
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---|---|---|---|---|
JP3281847B2 (en) * | 1997-09-26 | 2002-05-13 | 三洋電機株式会社 | Method for manufacturing semiconductor device |
US6351009B1 (en) * | 1999-03-01 | 2002-02-26 | Fairchild Semiconductor Corporation | MOS-gated device having a buried gate and process for forming same |
JP2002314081A (en) | 2001-04-12 | 2002-10-25 | Denso Corp | Trench-gate type semiconductor device and its manufacturing method |
JP4398185B2 (en) * | 2003-06-24 | 2010-01-13 | セイコーインスツル株式会社 | Vertical MOS transistor |
JP4829473B2 (en) * | 2004-01-21 | 2011-12-07 | オンセミコンダクター・トレーディング・リミテッド | Insulated gate semiconductor device and manufacturing method thereof |
JP2007266133A (en) * | 2006-03-27 | 2007-10-11 | Toyota Central Res & Dev Lab Inc | Semiconductor device |
JP2008098593A (en) * | 2006-09-15 | 2008-04-24 | Ricoh Co Ltd | Semiconductor device and manufacturing method thereof |
JP5089191B2 (en) | 2007-02-16 | 2012-12-05 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JP5405089B2 (en) * | 2008-11-20 | 2014-02-05 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP2010182857A (en) | 2009-02-05 | 2010-08-19 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
US8497551B2 (en) * | 2010-06-02 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned contact for trench MOSFET |
JP2012004156A (en) * | 2010-06-14 | 2012-01-05 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
JP5630090B2 (en) | 2010-06-17 | 2014-11-26 | 富士電機株式会社 | Manufacturing method of semiconductor device |
JP2012009671A (en) | 2010-06-25 | 2012-01-12 | Panasonic Corp | Semiconductor device and method of manufacturing the same |
JP5894383B2 (en) * | 2011-06-30 | 2016-03-30 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
JP2013258333A (en) | 2012-06-13 | 2013-12-26 | Toshiba Corp | Power semiconductor device |
JP2014099484A (en) | 2012-11-13 | 2014-05-29 | Toshiba Corp | Semiconductor device |
US8980714B2 (en) * | 2013-07-03 | 2015-03-17 | Infineon Technologies Dresden Gmbh | Semiconductor device with buried gate electrode structures |
JP6177154B2 (en) * | 2013-07-16 | 2017-08-09 | 株式会社東芝 | Semiconductor device |
JP2015095466A (en) * | 2013-11-08 | 2015-05-18 | サンケン電気株式会社 | Semiconductor device and manufacturing method of the same |
-
2016
- 2016-07-08 JP JP2016135985A patent/JP6844138B2/en active Active
-
2021
- 2021-02-24 JP JP2021027966A patent/JP7284202B2/en active Active
-
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- 2022-10-18 JP JP2022166811A patent/JP7537478B2/en active Active
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