JP2021077674A - Trench gate type switching element, and manufacturing method for trench gate type switching element - Google Patents

Abstract

To provide a technique for homogenizing the temperature distribution on a semiconductor substrate in a trench gate type switching element.SOLUTION: A trench gate type switching element includes a semiconductor substrate including a central part and an outer peripheral part disposed around the central part, a trench provided on an upper surface of the semiconductor substrate and distributing over the central part and the outer peripheral part, a gate insulating film covering an inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. Each of the central part and the outer peripheral part includes a source region, a body region, and a drift region. Within each of the central part and the outer peripheral part, the gate electrode extends from a position above a lower end of the source region to a position below an upper end of the drift region. An upper end of the gate electrode at the central part exists lower than the upper end of the gate electrode at the outer peripheral part.SELECTED DRAWING: Figure 2

Description

The techniques disclosed herein relate to trench gate type switching elements and methods for manufacturing trench gate type switching elements.

Patent Document 1 discloses a trench gate type switching element. This switching element has a semiconductor substrate having a trench on the upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode arranged in the trench and insulated from the semiconductor substrate by the gate insulating film. There is. In this switching element, the semiconductor substrate has an n-type source region, a p-type base region, and an n-type drift region. The source region is in contact with the gate insulating film. The base region is in contact with the gate insulating film below the source region. The drift region is in contact with the gate insulating film below the body region.

When this switching element is turned on, the potential of the gate electrode is made higher than the gate threshold value. Then, a channel is formed in the base region near the gate insulating film. The switching element is turned on by the flow of electrons from the source region to the drift region via the channel.

Japanese Unexamined Patent Publication No. 2012-16601

When the switching element is turned on, the semiconductor substrate generates heat. Heat is less likely to escape in the central portion of the semiconductor substrate than in the outer peripheral portion. Therefore, the temperature of the central portion of the semiconductor substrate tends to rise. The present specification provides a technique for making the temperature distribution of a semiconductor substrate uniform in a trench gate type switching element.

The trench gate type switching element disclosed in the present specification is provided on a central portion, a semiconductor substrate having an outer peripheral portion arranged around the central portion, and an upper surface of the semiconductor substrate, and the central portion and the said A trench distributed over the outer peripheral portion, a gate insulating film covering the inner surface of the trench, and a gate electrode arranged in the trench and insulated from the semiconductor substrate by the gate insulating film are provided. There is. Each of the central portion and the outer peripheral portion has a source region, a body region, and a drift region. The source region is a first conductive type region in contact with the gate insulating film. The body region is a second conductive type region that is in contact with the gate insulating film below the source region. The drift region is a first conductive type region that is in contact with the gate insulating film below the body region. In each of the central portion and the outer peripheral portion, the gate electrode extends from a position above the lower end of the source region to a position below the upper end of the drift region. The upper end of the gate electrode in the central portion is located below the upper end of the gate electrode in the outer peripheral portion.

In the trench gate type switching element described above, the upper end of the gate electrode in the central portion is located below the upper end of the gate electrode in the outer peripheral portion. Therefore, when a voltage is applied to the gate electrode, an electric field is less likely to be applied to the upper end portion of the body region in the range in contact with the gate insulating film than the outer peripheral portion in the central portion. Therefore, the gate threshold is higher in the central portion than in the outer peripheral portion. As a result, the current is less likely to flow in the central portion than in the outer peripheral portion. As described above, in the above-mentioned switching element, the current flowing through the central portion of the semiconductor substrate is reduced, so that the amount of heat generated in the central portion is reduced. As a result, the temperature rise in the central portion of the semiconductor substrate where heat cannot easily escape is suppressed. Therefore, in this switching element, the temperature difference between the central portion and the outer peripheral portion becomes smaller than before, and the temperature distribution of the semiconductor substrate can be made more uniform than before.

Further, the present specification discloses a method for manufacturing a trench gate type switching element. The manufacturing method includes a step of forming a trench distributed across the central portion and the outer peripheral portion on the upper surface of a semiconductor substrate having a central portion and an outer peripheral portion arranged around the central portion, and in the trench. In addition, a step of forming a gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film, and a first conductivity in contact with the gate insulating film at each of the central portion and the outer peripheral portion. The source region of the mold, the second conductive type body region which is in contact with the gate insulating film below the source region, and the first conductive mold region which is in contact with the gate insulating film below the body region. It has a step of forming a structure including a drift region and a step of heating the semiconductor substrate in an atmosphere containing oxygen after forming the gate insulating film and the gate electrode. In the step of forming the gate insulating film and the gate electrode, the gate electrode is formed so that the upper surface of the gate electrode is located below the upper surface of the semiconductor substrate. In the step of forming the gate insulating film and the gate electrode, the gate electrode is formed so that the gate electrode extends from a position above the lower end of the source region to a position below the upper end of the drift region. To do. In the step of forming the gate insulating film and the gate electrode, the gate electrode is formed so that the upper end of the gate electrode in the central portion is located below the upper end of the gate electrode in the outer peripheral portion. ..

The order of the steps of forming the trench and the step of forming the structure including the source region and the like is not particularly limited. That is, the source region or the like may be formed after the trench is formed, or the source region or the like may be formed before the trench is formed.

In the above manufacturing method, after forming the gate insulating film and the gate electrode, the semiconductor substrate is heated in an atmosphere containing oxygen. As a result, the semiconductor substrate is oxidized near the upper end of the trench, and crystal defects are formed around the oxidized region. In the central portion, the upper end of the gate electrode is located below the outer peripheral portion. Therefore, crystal defects are formed in the central portion to a position deeper than the outer peripheral portion. Therefore, the channel resistance is higher in the central portion than in the outer peripheral portion. As a result, when the trench gate type switching element manufactured by this method is turned on, the current density is lower in the central portion than in the outer peripheral portion, and the calorific value is smaller in the central portion than in the outer peripheral portion. As a result, the temperature rise in the central portion of the semiconductor substrate, from which heat cannot easily escape, is suppressed. As described above, in this manufacturing method, a switching element in which the temperature difference between the central portion and the outer peripheral portion is smaller than the conventional one can be manufactured, and the temperature distribution of the semiconductor substrate can be made more uniform than the conventional one.

Top view of the switching element 10. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. The figure for demonstrating the manufacturing process of a switching element 10. The figure for demonstrating the manufacturing process of a switching element 10. The figure for demonstrating the manufacturing process of a switching element 10. The figure for demonstrating the manufacturing process of a switching element 10. The figure for demonstrating the manufacturing process of a switching element 10. The figure for demonstrating the manufacturing process of a switching element 10. The figure for demonstrating the manufacturing process of a switching element 10.

The switching element 10 of this embodiment will be described with reference to the drawings. The switching element 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and has a semiconductor substrate 12. The semiconductor substrate 12 is made of, for example, SiC (silicon carbide). As shown in FIG. 1, two upper electrodes 70 are provided on the upper surface 12a of the semiconductor substrate 12. Each upper electrode 70 is arranged near the center of the upper surface 12a of the semiconductor substrate 12. In the following, within the range in which the upper electrode 70 is provided, the region located on the central side of the semiconductor substrate 12 is referred to as the central portion 14, and the region located around the central portion 14 is referred to as the outer peripheral portion 16. As shown in FIG. 1, the central portion 14 and the outer peripheral portion 16 are distributed so as to straddle the two upper electrodes 70.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. In FIG. 2, the left side is the central portion 14, and the right side is the outer peripheral portion 16. As shown in FIG. 2, a lower electrode 72 is arranged on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 covers substantially the entire area of the lower surface 12b of the semiconductor substrate 12.

A plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. The trenches 22 extend parallel to each other in the direction perpendicular to the paper surface of FIG. The inner surface of each trench 22 is covered with a gate insulating film 24. The gate insulating film 24 has a portion 24a and a portion 24b. The portion 24a is a portion that is arranged at the upper end of the trench 22 and the thickness of the gate insulating film 24 increases from the lower side to the upper side. The portion 24b is arranged below the portion 24a. In the portion 24b, the thickness of the gate insulating film 24 is substantially constant. The thickness of the gate insulating film 24 in the portion 24b is substantially equal to the thickness of the gate insulating film 24 at the lower end of the portion 24a. In the thickness direction of the semiconductor substrate 12, the length of the portion 24a at the central portion 14 is longer than the length of the portion 24a at the outer peripheral portion 16. A gate electrode 26 is arranged in each trench 22. The gate electrode 26 is made of polysilicon, for example. Each gate electrode 26 is insulated from the semiconductor substrate 12 by a gate insulating film 24. An oxide film 27 is formed on the surface of each gate electrode 26. The surface of the oxide film 27 is covered with an interlayer insulating film 28. Each gate electrode 26 is insulated from the upper electrode 70 by an interlayer insulating film 28. The upper end 26a of the gate electrode 26 in the central portion 14 is located below the upper end 26b of the gate electrode 26 in the outer peripheral portion 16.

A plurality of source regions 30, body regions 32, drift regions 34, and drain regions 35 are provided inside the semiconductor substrate 12. The source region 30, the body region 32, the drift region 34, and the drain region 35 are provided in both the central portion 14 and the outer peripheral portion 16.

Each source area 30 is an n-type area. Each source region 30 is exposed on the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the gate insulating film 24. In each of the central portion 14 and the outer peripheral portion 16, the lower end of each source region 30 is located below the upper ends 26a and 26b of the gate electrode 26.

The body region 32 is a p-type region. The body region 32 is in contact with each source region 30. The body region 32 extends from the range sandwiched between the two source regions 30 to the lower side of each source region 30. The body region 32 has a contact region 32a and a main body region 32b. The contact region 32a has a higher p-type impurity concentration than the main body region 32b. The contact region 32a is arranged in a range sandwiched between the two source regions 30. The contact region 32a is in ohmic contact with the upper electrode 70. The main body region 32b is in contact with the gate insulating film 24 on the side surface of the trench 22. The main body region 32b is in contact with the gate insulating film 24 on the lower side of the source region 30. In each of the central portion 14 and the outer peripheral portion 16, the upper end of the main body region 32b (the position of the boundary between the source region 30 and the main body region 32b in the range in contact with the gate insulating film 24) is from the upper ends 26a and 26b of the gate electrode 26. Is also located on the lower side.

The drift region 34 is an n-type region. The drift region 34 is arranged below the body region 32. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is in contact with the gate insulating film 24 at the lower end portion of the trench 22. The drift region 34 covers the lower end of the trench 22. In each of the central portion 14 and the outer peripheral portion 16, the upper end of the drift region 34 (the position of the boundary between the main body region 32b and the drift region 34 in the range in contact with the gate insulating film 24) is located above the lower end of the gate electrode 26. doing.

The drain region 35 is an n-type region. The drain region 35 is arranged below the drift region 34. The drain region 35 has an n-type impurity concentration higher than that of the drift region 34. The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72.

Next, a method of manufacturing the switching element 10 will be described. First, as shown in FIG. 3, a semiconductor substrate 12x having an n-type drift region 34 is prepared. Next, as shown in FIG. 4, a conventionally known method (for example, ion implantation) is used to form an n-type source region 30, a p-type contact region 32a, and a p-type main body region 32b.

Next, as shown in FIG. 5, a trench 22 is formed on the upper surface of the semiconductor substrate 12x by selectively dry etching the semiconductor substrate 12x. The trench 22 is formed so as to penetrate the source region 30 and the body region 32 and reach the drift region 34. In this step, crystal defects 80 are formed in the semiconductor region near the inner surface of the trench 22 due to dry etching. After forming the trench 22, a step of forming a sacrificial oxide film on the inner surface of the trench 22 and removing the sacrificial oxide film by wet etching may be provided. Thereby, the damage due to the dry etching formed on the inner surface of the trench 22 may be removed.

Next, as shown in FIG. 6, a gate insulating film 24 is formed on the inner surface of the trench 22 by CVD (Chemical Vapor Deposition). Then, the semiconductor substrate 12x is heat-treated in an atmosphere containing nitrogen. The heat treatment is carried out, for example, at 1300 ° C. As a result, the crystal defect 80 formed in the semiconductor region near the inner surface of the trench 22 is terminated by the nitrogen atom.

Next, as shown in FIG. 7, the gate electrode 26 is formed in the trench 22. In this step, polysilicon is first deposited in the trench 22 and on the semiconductor substrate 12x. Then, for example, by dry etching, the polysilicon on the semiconductor substrate 12x is removed, and the polysilicon remains in the trench 22. The polysilicon remaining in the trench 22 becomes the gate electrode 26. Next, as shown in FIG. 8, a resist having an opening 60a only in the upper part of the trench in the central portion 14 is formed on the upper surface of the semiconductor substrate 12x. That is, the upper part of the trench 22 in the outer peripheral portion 16 is covered with the resist 60. Next, the upper surface of the gate electrode 26 in the central portion 14 is etched by dry etching, for example. As a result, the upper end 26a of the gate electrode 26 in the central portion 14 is positioned below the upper end 26b of the gate electrode 26 in the outer peripheral portion 16. In this step, etching is performed so that the upper ends 26a and 26b of the gate electrode 26 do not reach below the lower end of the source region 30. After that, the resist 60 is removed.

Next, as shown in FIG. 9, the semiconductor substrate 12x is heat-treated in an atmosphere containing oxygen. As a result, the surface of the gate electrode 26 is oxidized, and the semiconductor region at the upper end of the trench 22 is oxidized. As a result, the oxide film 27 is formed on the surface of the gate electrode 26, and the thickness of the gate insulating film 24 at the upper end of the trench 22 is increased. On the side surface of the trench 22, the oxidation reaction proceeds faster toward the upper side. Therefore, a portion 24a whose thickness increases from the lower side to the upper side is formed at the upper end portion of the gate insulating film 24. The portion 24a is formed on both the central portion 14 and the outer peripheral portion 16. Further, by this heat treatment, the nitrogen that has terminated the crystal defect 80 is eliminated. Therefore, the crystal defect 80 occurs again in the semiconductor region. The upper end of the gate electrode 26 is located below the outer peripheral portion 16 in the central portion 14. That is, in the central portion 14, the recess depth of the upper portion of the gate electrode 26 is deep. Therefore, the oxidation reaction by the heat treatment proceeds to a position deeper in the central portion 14 than in the outer peripheral portion 16. Therefore, in the central portion 14, nitrogen is separated to a position deeper than the outer peripheral portion 16, and a crystal defect 80 is formed.

After that, the interlayer insulating film 28 and the upper electrode 70 are formed by a conventionally known method. Further, if necessary, the semiconductor substrate 12x is thinned from the lower surface, and then the drain region 35 and the lower electrode 72 are formed. As a result, the switching element 10 of the present embodiment shown in FIGS. 1 and 2 is completed.

Next, the operation of the switching element 10 will be described. When the switching element 10 is used, the switching element 10, the load (for example, a motor), and the power supply are connected in series. A power supply voltage is applied to the series circuit of the switching element 10 and the load. The power supply voltage is applied in a direction in which the lower electrode 72 side of the switching element 10 has a higher voltage than the upper electrode 70 side. When a voltage equal to or higher than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the range in contact with the gate insulating film 24, and the switching element 10 is turned on. When the voltage applied to the gate electrode 26 is lowered below the gate threshold value, the channel disappears and the switching element 10 is turned off.

As described above, in the switching element 10 of the present embodiment, the upper end 26a of the gate electrode 26 in the central portion 14 is located below the upper end 26b of the gate electrode 26 in the outer peripheral portion 16. Therefore, when a voltage is applied to the gate electrode 26, an electric field is less likely to be applied to the upper end portion of the body region 32 in the range in contact with the gate insulating film 24 than the outer peripheral portion 16 in the central portion 14. Therefore, the gate threshold value in the central portion 14 is higher than that in the outer peripheral portion 16. As a result, the current density in the central portion 14 is lower than that in the outer peripheral portion 16.

Further, as described above, in the central portion 14, the crystal defect 80 is formed deeper than the outer peripheral portion 16. The crystal defect 80 is mainly generated in the region where the channel is formed when the switching element 10 is turned on (the range in contact with the gate insulating film 24). Crystal defects 80 affect the mobility of carriers within the channel. Since the crystal defect 80 is formed in the central portion 14 to a position deeper than the outer peripheral portion 16, the channel resistance is higher in the central portion 14 than in the outer peripheral portion 16. Therefore, the current density in the central portion 14 is lower than that in the outer peripheral portion 16.

As described above, when the switching element 10 is on, the current density in the central portion 14 is lower than that in the outer peripheral portion 16. Therefore, the amount of heat generated in the central portion 14 is smaller than that in the outer peripheral portion 16. As a result, the temperature rise of the central portion 14 of the semiconductor substrate 12 in which heat is difficult to escape is suppressed, and the temperature difference between the central portion 14 and the outer peripheral portion 16 becomes smaller than before. Therefore, the temperature distribution of the semiconductor substrate 12 can be made more uniform than before.

The n-type is an example of the "first conductive type", and the p-type is an example of the "second conductive type".

Although the n-type MOSFET has been described in the above-described embodiment, the technique disclosed in the present specification may be applied to the p-type MOSFET. In this case, the p-type is an example of the "first conductive type", and the n-type is an example of the "second conductive type".

Further, in the above-described embodiment, the gate insulating film 24 has a portion 24a whose thickness increases from the lower side to the upper side. However, the thickness of the gate insulating film 24 may be substantially constant over the entire inner surface of the trench 22.

The technical elements disclosed herein are described below. In the configuration of one example disclosed herein, the gate insulating film may have a portion at the upper end of the trench whose thickness increases from the lower side to the upper side.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in this specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

10: Switching element 12: Semiconductor substrate 12a: Upper surface 12b: Lower surface 14: Central portion 16: Outer peripheral portion 22: Trench 24: Gate insulating film 24a: Part 24b: Part 26: Gate electrode 26a: Upper end 26b: Upper end 28: Intermediate insulation Film 30: Source region 32: Body region 32a: Contact region 32b: Main body region 34: Drift region 35: Drain region 70: Upper electrode 72: Lower electrode

Claims (3)

It is a trench gate type switching element.
A semiconductor substrate having a central portion and an outer peripheral portion arranged around the central portion,
A trench provided on the upper surface of the semiconductor substrate and distributed across the central portion and the outer peripheral portion, and
The gate insulating film covering the inner surface of the trench and
A gate electrode arranged in the trench and insulated from the semiconductor substrate by the gate insulating film,
With
Each of the central portion and the outer peripheral portion
The first conductive type source region in contact with the gate insulating film and
A second conductive body region in contact with the gate insulating film below the source region,
The first conductive type drift region, which is in contact with the gate insulating film under the body region,
Have and
In each of the central portion and the outer peripheral portion, the gate electrode extends from a position above the lower end of the source region to a position below the upper end of the drift region.
The upper end of the gate electrode in the central portion is located below the upper end of the gate electrode in the outer peripheral portion.
Trench gate type switching element. The trench gate type switching element according to claim 1, wherein the gate insulating film has a portion at the upper end of the trench whose thickness increases from the lower side to the upper side. A method for manufacturing trench gate type switching elements.
A step of forming a trench distributed over the central portion and the outer peripheral portion on the upper surface of a semiconductor substrate having a central portion and an outer peripheral portion arranged around the central portion.
A step of forming a gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film in the trench.
A first conductive type source region in contact with the gate insulating film and a second conductive type body region in contact with the gate insulating film below the source region, respectively, in the central portion and the outer peripheral portion. And a step of forming a structure having a first conductive type drift region in contact with the gate insulating film on the lower side of the body region.
A step of heating the semiconductor substrate in an oxygen-containing atmosphere after forming the gate insulating film and the gate electrode.
Have,
In the step of forming the gate insulating film and the gate electrode, the gate electrode is formed so that the upper surface of the gate electrode is located below the upper surface of the semiconductor substrate.
In the step of forming the gate insulating film and the gate electrode, the gate electrode is formed so that the gate electrode extends from a position above the lower end of the source region to a position below the upper end of the drift region. And
In the step of forming the gate insulating film and the gate electrode, the gate electrode is formed so that the upper end of the gate electrode in the central portion is located below the upper end of the gate electrode in the outer peripheral portion. ,
Production method.

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