JP2020161524A - Manufacturing method of insulated circuit board and its insulated circuit board - Google Patents

Manufacturing method of insulated circuit board and its insulated circuit board Download PDF

Info

Publication number
JP2020161524A
JP2020161524A JP2019056280A JP2019056280A JP2020161524A JP 2020161524 A JP2020161524 A JP 2020161524A JP 2019056280 A JP2019056280 A JP 2019056280A JP 2019056280 A JP2019056280 A JP 2019056280A JP 2020161524 A JP2020161524 A JP 2020161524A
Authority
JP
Japan
Prior art keywords
copper
layer
cleaning
chloride
copper layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019056280A
Other languages
Japanese (ja)
Other versions
JP7334438B2 (en
Inventor
仁人 西川
Masato Nishikawa
仁人 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP2019056280A priority Critical patent/JP7334438B2/en
Publication of JP2020161524A publication Critical patent/JP2020161524A/en
Application granted granted Critical
Publication of JP7334438B2 publication Critical patent/JP7334438B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Ceramic Products (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

To provide an insulated circuit board which removes wax stains and has good solder wettability and the like.SOLUTION: A manufacturing method of an insulated circuit board includes a joining step of joining a ceramic substrate and a copper plate made of copper or a copper alloy via a brazing material to form a copper layer on the surface of the ceramic substrate, a primary cleaning step of cleaning the surface of the copper layer with an aqueous solution containing iron chloride or copper chloride after the joining step, a secondary cleaning step of cleaning the surface of the copper layer with an aqueous solution containing one or more of chlorides other than iron chloride and copper chloride, ammonia, cyanide, and thiosulfate after the primary cleaning step, and a tertiary cleaning step of performing the cleaning with an aqueous solution containing any one or more of sulfuric acid, persulfate, and a mixed solution of sulfuric acid and hydrogen peroxide after the secondary cleaning step.SELECTED DRAWING: Figure 1

Description

本発明は、大電流、高電圧を制御するパワーモジュール等に用いられる絶縁回路基板の製造方法及びその絶縁回路基板に関する。 The present invention relates to a method for manufacturing an insulated circuit board used for a power module or the like that controls a large current or a high voltage, and the insulated circuit board thereof.

従来のパワーモジュール等に用いられる絶縁回路基板は、例えば、AlN(窒化アルミニウム)、Al(アルミナ)、Si(窒化ケイ素)などからなるセラミックス基板と、このセラミックス基板の一方の面に形成された回路層と、セラミックス基板の他方の面に形成された放熱層と、を備えている。また、これらセラミックス基板とこれら回路層又は放熱層となる金属板との接合には一般にろう材が用いられる。金属板が銅又は銅合金板である場合、ろう材には活性金属を含むものが用いられる。 The insulating circuit substrate used for the conventional power module or the like is, for example, a ceramic substrate made of AlN (aluminum nitride), Al 2 O 3 (alumina), Si 3 N 4 (silicon nitride), or one of the ceramic substrates. It includes a circuit layer formed on a surface and a heat radiating layer formed on the other surface of the ceramic substrate. Further, a brazing material is generally used for joining these ceramic substrates to these circuit layers or metal plates serving as heat dissipation layers. When the metal plate is copper or a copper alloy plate, a brazing material containing an active metal is used.

特許文献1に記載の回路基板では、セラミックス基板の一方の面に銅からなる回路層(銅回路)が形成され、セラミックス基板の他方の面に銅からなる放熱層(放熱銅板)が形成されている。この場合、これら回路層や放熱層の銅層を形成する方法として、セラミック基板と銅板を接合した後に銅板の周囲をエッチングする方法、回路層等の形状に打ち抜かれた銅板をセラミック基板に接合する方法が挙げられている。また、その接合には、Ag−Cu−Ti系のろう材を用いた活性金属ろう付け法が記載されている。 In the circuit board described in Patent Document 1, a circuit layer made of copper (copper circuit) is formed on one surface of the ceramic substrate, and a heat radiating layer made of copper (heat radiating copper plate) is formed on the other surface of the ceramic substrate. There is. In this case, as a method of forming the copper layer of these circuit layers and heat dissipation layers, a method of etching the periphery of the copper plate after joining the ceramic substrate and the copper plate, and a method of joining the copper plate punched into the shape of the circuit layer or the like to the ceramic substrate. The method is listed. Further, for the joining, an active metal brazing method using an Ag-Cu-Ti-based brazing material is described.

特開平8−139420号公報Japanese Unexamined Patent Publication No. 8-139420

ところで、エッチングすることなく、あらかじめ、所望の形状に成形した回路層等用の銅板をセラミックス基板に接合して銅層が接合された回路基板を作製する場合、接合時に銅板からはみ出したろう材が銅板の側面を伝って表面に這い上がる現象が生じ、銅層の表面にろう染みが発生することが問題になっている。銅層が回路層である場合、その表面にろう染みが生じると、回路層表面にめっきする場合にめっき膜の密着性が損なわれ、はんだ濡れ性、ボンディングワイヤや封止樹脂の密着性が阻害されるおそれがある。
このため、接合後に回路層の表面を過硫酸や塩化鉄水溶液等で洗浄することが行われるが、ろう染みを十分に除去することは難しい。
By the way, in the case of producing a circuit board in which a copper plate for a circuit layer or the like molded into a desired shape is bonded to a ceramic substrate in advance without etching, the brazing material protruding from the copper plate at the time of bonding is a copper plate. A phenomenon occurs in which the copper layer crawls up to the surface along the side surface of the copper layer, causing wax stains on the surface of the copper layer. When the copper layer is a circuit layer, if wax stain occurs on the surface, the adhesion of the plating film is impaired when plating on the surface of the circuit layer, and the adhesiveness of the solder wettability and the adhesion of the bonding wire and the sealing resin are impaired. May be done.
For this reason, the surface of the circuit layer is washed with persulfuric acid, an aqueous iron chloride solution, or the like after bonding, but it is difficult to sufficiently remove the wax stain.

本発明は、このような事情に鑑みてなされたもので、ろう染みを除去してはんだ濡れ性等の良好な絶縁回路基板を提供することを目的とする。 The present invention has been made in view of such circumstances, and an object of the present invention is to remove wax stains and provide an insulated circuit board having good solder wettability and the like.

本発明の絶縁回路基板の製造方法は、セラミックス基板と銅又は銅合金からなる銅板とをろう材を介して接合してセラミックス基板の表面に銅層を形成する接合工程と、接合工程後に前記銅層の表面を塩化鉄又は塩化銅を含む水溶液によって洗浄する一次洗浄工程と、該一次洗浄工程後に前記銅層の表面を、塩化鉄及び塩化銅以外の塩化物、アンモニア、シアン化物、チオ硫酸塩のいずれか一つ以上を含む水溶液で洗浄する二次洗浄工程と、前記二次洗浄工程の後に、硫酸、過硫酸塩、硫酸と過酸化水素の混合液のいずれか一つ以上を含む水溶液で洗浄する三次洗浄工程とを有する。 The method for manufacturing an insulated circuit substrate of the present invention includes a joining step of joining a ceramic substrate and a copper plate made of copper or a copper alloy via a brazing material to form a copper layer on the surface of the ceramic substrate, and the copper after the joining step. A primary cleaning step of cleaning the surface of the layer with an aqueous solution containing iron chloride or copper chloride, and after the primary cleaning step, the surface of the copper layer is cleaned with chlorides other than iron chloride and copper chloride, ammonia, cyanide, and thiosulfate. A secondary cleaning step of washing with an aqueous solution containing any one or more of the above, and after the secondary cleaning step, an aqueous solution containing any one or more of a mixed solution of sulfuric acid, persulfate, and sulfuric acid and hydrogen peroxide. It has a tertiary cleaning step of cleaning.

ろう材を用いた接合後、銅のエッチング液として広く用いられている塩化鉄又は塩化銅を含む水溶液によって洗浄することにより、ろう染みを除去することができる。ところが、この一次洗浄だけでは、塩化鉄や塩化銅により銅が腐食する際に、腐食の過程で生成する塩化銅や一次洗浄に利用した塩化銅が銅層の表面に残存し易い。この塩化銅が残存していると、高温環境下等において表面に変色が生じ易い。この塩化銅は水に溶けにくいため、単に水洗浄しただけでは除去しきれない。そこで、二次洗浄工程により、塩化鉄及び塩化銅以外の塩化物、アンモニア、シアン化物、チオ硫酸塩のいずれか一つ以上を含む水溶液で洗浄する。これら塩化物等に含まれる塩化物イオン等により塩化銅を錯体化し、溶けやすくする。
そして、この二次洗浄で塩化銅を洗浄した後、表面を硫酸、過硫酸塩、硫酸と過酸化水素の混合液のいずれか一つ以上を含む水溶液で洗浄することにより、銅層を平滑な表面に形成することができる。
After joining with a brazing material, the wax stain can be removed by washing with an aqueous solution containing iron chloride or copper chloride, which is widely used as an etching solution for copper. However, with only this primary cleaning, when copper is corroded by iron chloride or copper chloride, copper chloride generated in the process of corrosion and copper chloride used for the primary cleaning tend to remain on the surface of the copper layer. If this copper chloride remains, discoloration is likely to occur on the surface in a high temperature environment or the like. Since this copper chloride is difficult to dissolve in water, it cannot be completely removed by simply washing with water. Therefore, it is washed with an aqueous solution containing any one or more of chlorides other than iron chloride and copper chloride, ammonia, cyanide, and thiosulfate by a secondary washing step. Copper chloride is complexed with chloride ions and the like contained in these chlorides and the like to make it easier to dissolve.
Then, after the copper chloride is washed by this secondary washing, the surface is washed with an aqueous solution containing any one or more of sulfuric acid, persulfate, and a mixed solution of sulfuric acid and hydrogen peroxide to smooth the copper layer. It can be formed on the surface.

本発明の絶縁回路基板は、セラミックス基板の表面に銅層がろう付けされてなる絶縁回路基板であって、前記銅層の表面に形成されたろう染みは前記銅層の端部からの幅が50μm以下であり、前記銅層の表面の塩素/銅濃度比が0.45以下である。 The insulating circuit board of the present invention is an insulating circuit board in which a copper layer is brazed to the surface of a ceramics substrate, and the wax stain formed on the surface of the copper layer has a width of 50 μm from the end of the copper layer. The chlorine / copper concentration ratio on the surface of the copper layer is 0.45 or less.

銅層の表面のろう染みが50μm以下の幅であり、かつ、銅層の表面の塩素/銅濃度比が0.45以下であることから、腐食による表面の変色も抑制できる。したがって、この銅層表面にめっき膜を形成する場合のめっき膜の密着性、半導体素子をはんだ付けする場合のはんだ濡れ性が優れており、ボンディングワイヤや樹脂等の密着性も良好になる。
なお、銅層がろう付け後のエッチングによりパターン化される場合は、周縁部が除去されるので、ろう染みの問題は発生しない。銅層の厚さが大きくなると、エッチングに時間がかかり不経済であるため、回路層の場合は予め回路パターンに形成した銅板を接合する方が経済的である。このように銅層をエッチングしない場合として、銅層の厚さが0.1mm以上の場合に本発明を用いると効果的であり、0.5mm以上の場合にさらに効果的である。
Since the wax stain on the surface of the copper layer has a width of 50 μm or less and the chlorine / copper concentration ratio on the surface of the copper layer is 0.45 or less, discoloration of the surface due to corrosion can be suppressed. Therefore, the adhesion of the plating film when forming the plating film on the surface of the copper layer and the solder wettability when soldering the semiconductor element are excellent, and the adhesion of the bonding wire, the resin, etc. is also good.
When the copper layer is patterned by etching after brazing, the peripheral portion is removed, so that the problem of brazing stain does not occur. If the thickness of the copper layer is large, etching takes time and it is uneconomical. Therefore, in the case of a circuit layer, it is more economical to join copper plates formed in a circuit pattern in advance. When the copper layer is not etched in this way, it is effective to use the present invention when the thickness of the copper layer is 0.1 mm or more, and it is more effective when the thickness of the copper layer is 0.5 mm or more.

本発明によれば、ろう染みを除去して、めっき膜の密着性、はんだ濡れ性等の良好な絶縁回路基板を提供することができる。 According to the present invention, it is possible to provide an insulated circuit board having good adhesion of a plating film, solder wettability, etc. by removing wax stains.

本発明の絶縁回路基板の製造方法の一実施形態を示す工程図である。It is a process drawing which shows one Embodiment of the manufacturing method of the insulated circuit board of this invention. 一実施形態の絶縁回路基板の縦断面図である。It is a vertical sectional view of the insulation circuit board of one Embodiment. 図2の絶縁回路基板の製造途中の状態を示す縦断面図である。It is a vertical cross-sectional view which shows the state in the manufacturing process of the insulation circuit board of FIG.

以下、本発明の絶縁回路基板及びその製造方法の実施形態について説明する。
本実施形態の絶縁回路基板は電源回路に用いられるパワーモジュール用基板である。このパワーモジュール用基板10は、図2に示すように、セラミックス基板11と、そのセラミックス基板11の一方の面に形成された回路層12と、セラミックス基板11の他方の面に形成された放熱層13と、を有している。
Hereinafter, embodiments of the insulated circuit board of the present invention and the method for manufacturing the same will be described.
The insulated circuit board of this embodiment is a power module board used in a power supply circuit. As shown in FIG. 2, the power module substrate 10 includes a ceramic substrate 11, a circuit layer 12 formed on one surface of the ceramic substrate 11, and a heat dissipation layer formed on the other surface of the ceramic substrate 11. It has 13 and.

セラミックス基板11は、回路層12と放熱層13との間の電気的接続を防止するものであって、窒化アルミニウム(AlN),窒化ケイ素(Si),酸化アルミニウム(Al)等を用いることができるが、そのうち、窒化ケイ素が高強度であるため、好適である。このセラミックス基板11の厚さは0.2mm以上1.5mm以下の範囲内に設定される。 Ceramic substrate 11 is for preventing an electrical connection between the circuit layer 12 and the heat dissipation layer 13, aluminum nitride (AlN), silicon nitride (Si 3 N 4), aluminum oxide (Al 2 O 3) Etc. can be used, but silicon nitride is preferable because of its high strength. The thickness of the ceramic substrate 11 is set within the range of 0.2 mm or more and 1.5 mm or less.

回路層12は、電気特性に優れる銅又は銅合金から構成される。また、放熱層13も銅又は銅合金から構成される。これら回路層12及び放熱層13としては、例えば、純度99.96質量%以上の無酸素銅の銅板がセラミックス基板11に例えば活性金属ろう材にてろう付け接合されることにより形成される。この回路層12及び放熱層13の厚さは0.1mm以上5mm以下の範囲内に設定される。 The circuit layer 12 is made of copper or a copper alloy having excellent electrical characteristics. The heat dissipation layer 13 is also made of copper or a copper alloy. The circuit layer 12 and the heat radiating layer 13 are formed, for example, by brazing and joining an oxygen-free copper plate having a purity of 99.96% by mass or more to the ceramic substrate 11 with, for example, an active metal brazing material. The thickness of the circuit layer 12 and the heat radiating layer 13 is set within the range of 0.1 mm or more and 5 mm or less.

ここで、回路層12及び放熱層13のろう染みは、回路層12及び放熱層13の端部からの幅が50μm以下とされている。ろう染みの幅が50μm以下とされているので、例えば、回路層12にNiめっきなどのめっきが施された場合において、めっき膜の密着性が損なわれることがない。また、はんだ濡れ性が低下することなく、また、ボンディングワイヤや封止樹脂の密着性が阻害されることがない。さらに、例えば、放熱層13とヒートシンクがはんだ付けされる場合においても、ろう染みの幅が50μm以下とされているので、はんだの濡れ性が低下せず、はんだ接合性が低下しない。 Here, the wax stains on the circuit layer 12 and the heat radiating layer 13 have a width of 50 μm or less from the ends of the circuit layer 12 and the heat radiating layer 13. Since the width of the wax stain is 50 μm or less, for example, when the circuit layer 12 is plated with Ni plating or the like, the adhesion of the plating film is not impaired. Further, the solder wettability is not deteriorated, and the adhesion of the bonding wire and the sealing resin is not impaired. Further, for example, even when the heat radiating layer 13 and the heat sink are soldered, the width of the wax stain is 50 μm or less, so that the wettability of the solder does not decrease and the solder bondability does not decrease.

さらに、回路層12及び放熱層13の表面の塩素/銅濃度比が0.45以下に設定される。この塩素/銅濃度比は、例えば走査型電子顕微鏡(SEM:Scanning Electron Microscope)を用いたエネルギー分散型X線分光法(EDX:Energy Dispersive X-ray Spectroscop)により、回路層12又は放熱層13の銅層(以下、回路層及び放熱層を特に区別しない場合は銅層と称す)表面から放出される特性X線を元素分析して測定する。この塩素/銅濃度比は、銅層の表面に残存する塩化銅に起因しており、0.45を超えると、残存する塩化銅が多くなり、高温環境下等において変色が生じ易くなる。 Further, the chlorine / copper concentration ratio on the surfaces of the circuit layer 12 and the heat dissipation layer 13 is set to 0.45 or less. This chlorine / copper concentration ratio is determined by, for example, energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray Spectroscopy) using a scanning electron microscope (SEM) in the circuit layer 12 or the heat dissipation layer 13. Characteristic X-rays emitted from the surface of the copper layer (hereinafter referred to as the copper layer when the circuit layer and the heat radiation layer are not particularly distinguished) are measured by elemental analysis. This chlorine / copper concentration ratio is due to the copper chloride remaining on the surface of the copper layer, and if it exceeds 0.45, the amount of copper chloride remaining increases, and discoloration is likely to occur in a high temperature environment or the like.

このように構成されるパワーモジュール用基板10の製造方法について説明する。
このパワーモジュール用基板10は、図1に示すように、銅板等作製工程、接合工程、1次洗浄工程、2次洗浄工程、3次洗浄工程の順に製造される。以下、工程順に説明する。
A method of manufacturing the power module substrate 10 configured in this way will be described.
As shown in FIG. 1, the power module substrate 10 is manufactured in the order of a copper plate or the like manufacturing step, a joining step, a primary cleaning step, a secondary cleaning step, and a tertiary cleaning step. Hereinafter, the steps will be described in order.

(銅板等作製工程)
回路層12及び放熱層13を形成するための銅板12´,13´をプレス加工等によって打抜き形成する。この場合、回路層12となる銅板12´は、回路層12としての所定のパターン形状を有している。
また、これら回路層12及び放熱層13が形成されるセラミックス基板11を用意する。または、複数のセラミックス基板11に分割可能なスクライブラインを形成したセラミックス板を用意する。この複数のセラミックス基板11に分割可能なセラミックス板を用いる場合、最終的には、回路層12及び放熱層13を有する個々のセラミックス基板11に分割されるが、後述の接合工程及び各洗浄工程は単独のセラミックス基板11に対するものと同様であるので、以下では、セラミックス基板11に回路層12及び放熱層13を形成するものとして説明する。
(Copper plate manufacturing process)
Copper plates 12'and 13'for forming the circuit layer 12 and the heat dissipation layer 13 are punched and formed by press working or the like. In this case, the copper plate 12'which becomes the circuit layer 12 has a predetermined pattern shape as the circuit layer 12.
Further, a ceramic substrate 11 on which the circuit layer 12 and the heat radiating layer 13 are formed is prepared. Alternatively, a ceramic plate having a scribe line that can be divided into a plurality of ceramic substrates 11 is prepared. When a ceramic plate that can be divided into the plurality of ceramic substrates 11 is used, it is finally divided into individual ceramic substrates 11 having a circuit layer 12 and a heat dissipation layer 13, but the joining step and each cleaning step described later are performed. Since it is the same as that for a single ceramic substrate 11, it will be described below assuming that the circuit layer 12 and the heat dissipation layer 13 are formed on the ceramic substrate 11.

(接合工程)
図3に示すように、セラミックス基板11の両面にろう材21,22を介して銅板12´,13´を配置し、これらを積層する。ろう材21,22としては、Ag−Ti又はAg−Cu−Tiからなるろう材が用いられる。このろう材21,22は、箔の形態で供給されるが、スクリーン印刷法等によってセラミックス基板11にろう材のペーストを塗布することによって形成してもよい。
この場合、各ろう材21,22とも、接合する銅板12´,13´の外形と同じか、それよりわずかに大きい外形に形成されることが好ましい。これらろう材21,22の厚さは10μm以上300μm以下とされる。
(Joining process)
As shown in FIG. 3, copper plates 12'and 13' are arranged on both sides of the ceramic substrate 11 via brazing materials 21 and 22, and these are laminated. As the brazing materials 21 and 22, a brazing material made of Ag-Ti or Ag-Cu-Ti is used. The brazing materials 21 and 22 are supplied in the form of foil, but may be formed by applying a brazing material paste to the ceramic substrate 11 by a screen printing method or the like.
In this case, it is preferable that each of the brazing members 21 and 22 is formed to have an outer shape that is the same as or slightly larger than the outer shape of the copper plates 12'and 13'to be joined. The thickness of these brazing materials 21 and 22 is 10 μm or more and 300 μm or less.

これらろう材21,22を介して積層したセラミックス基板11と銅板12´,13´との積層体を加圧状態で加熱炉内に設置し、真空雰囲気下で接合温度に加熱した後冷却することにより、セラミックス基板11の一方の面に回路層12、他方の面に放熱層13を形成する。この場合の接合条件としては、例えば0.1MPa以上3.5MPa以下の加圧力で積層体を加圧し、10−6Pa以上10−3Pa以下の真空雰囲気下で、例えば790℃以上850℃以下の接合温度で、1分〜60分の加熱とする。 A laminate of the ceramic substrate 11 and the copper plates 12'and 13'laminated via the brazing materials 21 and 22 is installed in a heating furnace in a pressurized state, heated to a bonding temperature in a vacuum atmosphere, and then cooled. As a result, the circuit layer 12 is formed on one surface of the ceramic substrate 11 and the heat dissipation layer 13 is formed on the other surface. In this case, the joining conditions include, for example, pressurizing the laminate with a pressing force of 0.1 MPa or more and 3.5 MPa or less, and in a vacuum atmosphere of 10-6 Pa or more and 10-3 Pa or less, for example, 790 ° C. or more and 850 ° C. or less. The bonding temperature is 1 to 60 minutes.

このようにして製造されたパワーモジュール用基板10は、セラミックス基板11と回路層12及び放熱層13との間がろう付けによって接合されている。
前述したろう染みは、パワーモジュール用基板11と銅板12´,13´との接合時に、溶融状態のろう材がセラミックス基板11と銅板12´,13´との間からはみ出して銅板12´,13´の側面を伝って這い上がることにより回路層12及び放熱層13の表面に形成され、後述の洗浄工程によっても大部分が除去される。
In the power module substrate 10 manufactured in this manner, the ceramic substrate 11 and the circuit layer 12 and the heat radiating layer 13 are joined by brazing.
The wax stain described above is caused by the molten brazing material protruding from between the ceramic substrate 11 and the copper plates 12'and 13'when the power module substrate 11 and the copper plates 12'and 13'are joined. It is formed on the surfaces of the circuit layer 12 and the heat radiating layer 13 by crawling up along the side surface of ′, and most of it is removed by the cleaning step described later.

(1次洗浄工程)
接合工程後のパワーモジュール用基板10の銅層(回路層12及び放熱層13)表面を1次洗浄液で洗浄する。
1次洗浄液としては、塩化鉄又は塩化銅の水溶液が用いられる。塩化鉄としては、塩化鉄(III)(FeCl)を用いることが好ましい。塩化銅としては塩化銅(II)(CuCl)を用いることが好ましい。
また、容量比率等が限定されるものではないが、塩化鉄水溶液としては、例えば30質量%以上45質量%以下のFeCl水溶液、塩化銅水溶液としては、例えば15質量%以上25質量%以下のCuClと3質量%以上15質量%以下のHClとの混合水溶液が用いられる。
この1次洗浄液を30℃以上60℃以下の温度に保持して、パワーモジュール用基板10を0.5分以上10分以下の時間浸漬する。
この1次洗浄により、銅層の表面が洗浄され、回路層12及び放熱層13の表面に形成されていたろう染みは、その全部または大部分が除去される。なお、回路層12及び放熱層13の側面には、固化したろう材が存在しているが、固化したろう材は厚く形成されているため、1次洗浄工程後もその一部が残存している場合もあるが、影響はない。
(Primary cleaning process)
The surface of the copper layer (circuit layer 12 and heat dissipation layer 13) of the power module substrate 10 after the joining step is cleaned with the primary cleaning liquid.
As the primary cleaning liquid, an aqueous solution of iron chloride or copper chloride is used. As the iron chloride, it is preferable to use iron (III) chloride (FeCl 3 ). It is preferable to use copper (II) chloride (CuCl 2 ) as the copper chloride.
Further, although not capacity ratio and the like is limited, as the aqueous solution of iron chloride, for example, 30 wt% to 45 wt% of FeCl 3 aqueous solution, the aqueous solution of copper chloride, for example, the following 15 wt% to 25 wt% A mixed aqueous solution of CuCl 2 and 3% by mass or more and 15% by mass or less of HCl is used.
The primary cleaning liquid is maintained at a temperature of 30 ° C. or higher and 60 ° C. or lower, and the power module substrate 10 is immersed for 0.5 minutes or longer and 10 minutes or shorter.
By this primary cleaning, the surface of the copper layer is cleaned, and all or most of the wax stains formed on the surfaces of the circuit layer 12 and the heat radiating layer 13 are removed. Although solidified brazing material is present on the side surfaces of the circuit layer 12 and the heat radiating layer 13, a part of the solidified brazing material remains even after the primary cleaning step because the solidified brazing material is formed thick. It may be, but it has no effect.

(2次洗浄工程)
1次洗浄工程後に、銅層の表面を2次洗浄液で洗浄する。
2次洗浄液としては、塩化鉄及び塩化銅以外の塩化物、アンモニア、シアン化物、チオ硫酸塩のいずれか一つ以上を含む水溶液が用いられる。
塩化鉄及び塩化銅以外の塩化物としては、金属元素の塩化物や塩酸を用いることができる。金属元素の塩化物としては、例えば、Li、Na、K、Be、Mg、Ca、Sr、Ba、Alの塩化物を用いることができる。
シアン化物としては、シアン化ナトリウム、シアン化カリウム、シアン化カルシウム、シアン化マグネシウム等があげられる。
チオ硫酸塩としては、チオ硫酸ナトリウム、チオ硫酸カリウム、チオ硫酸アンモニウム等があげられる。
なお、容量比率等が限定されるものではないが、例えば1質量%以上35質量%以下の塩酸、1質量%以上30質量%以下の塩化カリウム水溶液、1質量%以上30質量%以下のアンモニア水溶液等が用いられる。
この2次洗浄液を15℃以上40℃以下の温度に保持して、パワーモジュール用基板10を0.5分以上10分以下の時間浸漬する。
1次洗浄後に、その洗浄液である塩化鉄又は塩化銅により、銅層表面の銅が酸化される過程で発生した塩化銅、特に塩化銅(I)が銅層の表面に残存する場合があり、この塩化銅は水に溶けにくい。このため、2次洗浄により、銅層表面に残存した塩化銅を錯体化し、溶けやすくする。
(Secondary cleaning process)
After the primary cleaning step, the surface of the copper layer is cleaned with a secondary cleaning solution.
As the secondary cleaning solution, an aqueous solution containing any one or more of chlorides other than iron chloride and copper chloride, ammonia, cyanide, and thiosulfate is used.
As the chloride other than iron chloride and copper chloride, chloride of a metal element or hydrochloric acid can be used. As the chloride of the metal element, for example, chlorides of Li, Na, K, Be, Mg, Ca, Sr, Ba and Al can be used.
Examples of the cyanide include sodium cyanide, potassium cyanide, calcium cyanide, magnesium cyanide and the like.
Examples of the thiosulfate include sodium thiosulfate, potassium thiosulfate, ammonium thiosulfate and the like.
Although the volume ratio is not limited, for example, hydrochloric acid of 1% by mass or more and 35% by mass or less, an aqueous solution of potassium chloride of 1% by mass or more and 30% by mass or less, and an aqueous solution of ammonia of 1% by mass or more and 30% by mass or less. Etc. are used.
The secondary cleaning liquid is maintained at a temperature of 15 ° C. or higher and 40 ° C. or lower, and the power module substrate 10 is immersed for 0.5 minutes or longer and 10 minutes or shorter.
After the primary cleaning, copper chloride, especially copper (I) chloride, generated in the process of oxidizing the copper on the surface of the copper layer by the cleaning liquid, iron chloride or copper chloride, may remain on the surface of the copper layer. This copper chloride is difficult to dissolve in water. Therefore, by the secondary cleaning, the copper chloride remaining on the surface of the copper layer is complexed and easily dissolved.

(3次洗浄工程)
2次洗浄後に、銅層の表面を3次洗浄液で洗浄する。
3次洗浄液としては、硫酸、過硫酸塩、硫酸と過酸化水素の混合液のいずれか一つ以上を含む水溶液が用いられる。過硫酸塩としては過硫酸ナトリウム、過硫酸カリウム、過硫酸アンモニウム等が挙げられる。容量比率等が限定されるものではないが、3質量%以上30質量%以下の硫酸水溶液、3質量%以上30質量%以下の過硫酸塩水溶液、1質量%以上15質量%以下の過酸化水素水と3質量%以上20質量%以下の硫酸との混合水溶液が用いられる。
この3次洗浄液を15℃以上40℃以下の温度に保持して、パワーモジュール用基板10を0.5分以上10分以下の時間浸漬する。
この3次洗浄工程により、銅層(回路層12及び放熱層13)が平滑な表面に形成される。
(3rd cleaning process)
After the secondary cleaning, the surface of the copper layer is cleaned with a tertiary cleaning solution.
As the tertiary cleaning solution, an aqueous solution containing any one or more of sulfuric acid, persulfate, and a mixed solution of sulfuric acid and hydrogen peroxide is used. Examples of the persulfate include sodium persulfate, potassium persulfate, ammonium persulfate and the like. The volume ratio is not limited, but a sulfuric acid aqueous solution of 3% by mass or more and 30% by mass or less, a persulfate aqueous solution of 3% by mass or more and 30% by mass or less, and a hydrogen peroxide of 1% by mass or more and 15% by mass or less. A mixed aqueous solution of water and sulfuric acid of 3% by mass or more and 20% by mass or less is used.
The tertiary cleaning liquid is maintained at a temperature of 15 ° C. or higher and 40 ° C. or lower, and the power module substrate 10 is immersed for 0.5 minutes or longer and 10 minutes or shorter.
By this tertiary cleaning step, a copper layer (circuit layer 12 and heat radiating layer 13) is formed on a smooth surface.

なお、各洗浄工程の後には洗浄液を洗い落とすため、パワーモジュール用基板10を水洗する。
このようにして3次洗浄まで終了したパワーモジュール用基板10は、回路層12及び放熱層13とも表面にろう染みがなく、ろう染みの除去に用いた洗浄液に起因する塩化物も残存していないため、表面にめっき膜を形成する場合のめっき膜の密着性に優れたものとなる。また、はんだ濡れ性、ボンディングワイヤや封止樹脂の密着性も良好となる。
After each cleaning step, the power module substrate 10 is washed with water in order to wash off the cleaning liquid.
In the power module substrate 10 which has been completed up to the third cleaning in this way, neither the circuit layer 12 nor the heat radiation layer 13 has a wax stain on the surface, and no chloride due to the cleaning liquid used for removing the wax stain remains. Therefore, the adhesion of the plating film is excellent when the plating film is formed on the surface. In addition, the solder wettability and the adhesion of the bonding wire and the sealing resin are also improved.

本発明は、上記実施形態の構成のものに限定されるものではなく、細部構成においては、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
実施形態ではセラミックス基板の両面に銅層が形成されているものとしたが、少なくとも回路層としての銅層が形成されていればよい。
また、各洗浄液にパワーモジュール用基板を浸漬するものとしたが、洗浄液を銅層にスプレー等で供給する場合も含むものとする。
実施形態ではパワーモジュール用基板として説明したが、パワーモジュール用基板以外の絶縁回路基板に適用可能である。
The present invention is not limited to the configuration of the above embodiment, and various changes can be made to the detailed configuration without departing from the spirit of the present invention.
In the embodiment, it is assumed that copper layers are formed on both sides of the ceramic substrate, but at least a copper layer as a circuit layer may be formed.
Further, although the power module substrate is immersed in each cleaning liquid, it also includes the case where the cleaning liquid is supplied to the copper layer by spraying or the like.
Although described as a power module board in the embodiment, it can be applied to an insulated circuit board other than the power module board.

Siからなるセラミックス基板(40mm×40mm×0.32mmt)の一方の面に、純度99.99質量%以上の無酸素銅(OFC)からなる銅板(37mm×37mm×0.3mmt)をAg−Tiろう材箔(37mm×37mm×0.05mmt)を介して積層し、0.6MPaの加圧力で加圧状態に保持し、真空雰囲気下、加熱温度820℃で30分間保持し、セラミックス基板の上に銅層を形成した。 A copper plate (37 mm × 37 mm × 0.3 mmt) made of oxygen-free copper (OFC) having a purity of 99.99% by mass or more is placed on one surface of a ceramic substrate (40 mm × 40 mm × 0.32 mmt) made of Si 3 N 4. Laminated via Ag-Ti brazing foil (37 mm x 37 mm x 0.05 mmt), held in a pressurized state with a pressing force of 0.6 MPa, held in a vacuum atmosphere at a heating temperature of 820 ° C. for 30 minutes, and ceramics. A copper layer was formed on the substrate.

得られた接合体について、1次洗浄工程、2次洗浄工程、3次洗浄工程を順に行った。各洗浄工程で用いた洗浄液は表1に示す通りである。
表中、1次洗浄工程及び3次洗浄工程の洗浄液は以下の通りとした。
「塩化鉄」:42質量%FeCl水溶液
「塩化銅」:21質量%CuClと9質量%HClとの混合水溶液
「硫酸+過酸化水素」:15質量%硫酸と2質量%の過酸化水素との混合水溶液
「硫酸」:10質量%の硫酸水溶液
「過硫酸ナトリウム」:15質量%過硫酸ナトリウム水溶液
また、2次洗浄工程には、表1の各欄に記載の薬液とした。各洗浄の後には接合体を純水で洗浄した。
この洗浄工程においては、1次洗浄を42℃の温度で2分、2次洗浄を常温(25℃)で1分、3次洗浄を常温(25℃)で1分施した。表1中「−」は、その工程の洗浄を行わなかったことを示す。
The obtained bonded body was subjected to a primary cleaning step, a secondary cleaning step, and a tertiary cleaning step in order. The cleaning liquids used in each cleaning step are as shown in Table 1.
In the table, the cleaning liquids for the primary cleaning step and the tertiary cleaning step are as follows.
"Iron chloride": 42 mass% FeCl 3 aqueous solution "Copper chloride": A mixed aqueous solution of 21 mass% CuCl 2 and 9 mass% HCl "Sulfuric acid + hydrogen peroxide": 15 mass% sulfuric acid and 2 mass% hydrogen peroxide Aqueous solution of "sulfuric acid": 10% by mass of sulfuric acid "Sodium persulfate": 15% by mass of aqueous sodium persulfate In addition, the chemical solution described in each column of Table 1 was used in the secondary washing step. After each wash, the conjugate was washed with pure water.
In this cleaning step, the primary cleaning was performed at a temperature of 42 ° C. for 2 minutes, the secondary cleaning was performed at room temperature (25 ° C.) for 1 minute, and the tertiary cleaning was performed at room temperature (25 ° C.) for 1 minute. “-” In Table 1 indicates that the process was not washed.

Figure 2020161524
Figure 2020161524

得られた接合体の銅層の表面について、残存塩素濃度を測定するとともに、ろう染み、変色の程度を評価した。
銅層表面の塩素及び銅の濃度の測定は、走査型電子顕微鏡(SEM)を用いたエネルギー分散型X線分光法(EDX)により、銅層表面から放出される特性X線を元素分析して測定した。銅層の表面の任意の15か所について、CuとClの定量値(at%)の比(Cl/Cu)を測定し、その平均を求めた。各条件ごとに15枚の接合体の銅層についてそれぞれ測定し、その平均値を求め、その値を表面の塩素/銅濃度比とした。
The residual chlorine concentration was measured on the surface of the copper layer of the obtained bonded body, and the degree of wax stain and discoloration was evaluated.
The concentration of chlorine and copper on the surface of the copper layer is measured by elemental analysis of the characteristic X-rays emitted from the surface of the copper layer by energy dispersive X-ray spectroscopy (EDX) using a scanning electron microscope (SEM). It was measured. The ratio (Cl / Cu) of the quantitative values (at%) of Cu and Cl was measured at any 15 locations on the surface of the copper layer, and the average was calculated. Each of the 15 copper layers of the bonded body was measured under each condition, the average value was calculated, and the value was taken as the surface chlorine / copper concentration ratio.

ろう染みの幅Wは以下の通り、測定した。
銅層表面を上から目視し、黒色となっている領域(黒色部)をろう染みとみなし、銅層の端部から、黒色部と黒色部以外の領域との境までの距離を各辺について測定した。最も距離の大きかった箇所をろう染みの幅Wとし、各条件ごとに15枚の接合体について測定し平均値を求めた。その幅が50μm以下の場合に「A」、50μmを超えていた場合に「B」と評価した。
変色については、接合体を温度60℃、湿度30%の恒温恒湿環境下に100時間放置し、銅層表面に銅層よりも濃い茶色の領域が観察されるか、または、白色のムラが観測された場合を「B」、それ以外の場合を「A」と評価した。
これらの結果を表2に示す。
The width W of the wax stain was measured as follows.
The surface of the copper layer is visually observed from above, and the black area (black part) is regarded as a wax stain, and the distance from the end of the copper layer to the boundary between the black part and the area other than the black part is measured for each side. It was measured. The place where the distance was the longest was defined as the width W of the wax stain, and 15 joints were measured under each condition and the average value was calculated. When the width was 50 μm or less, it was evaluated as “A”, and when it exceeded 50 μm, it was evaluated as “B”.
Regarding discoloration, the bonded body was left in a constant temperature and humidity environment at a temperature of 60 ° C. and a humidity of 30% for 100 hours, and a dark brown region darker than the copper layer was observed on the surface of the copper layer, or white unevenness was observed. The observed case was evaluated as "B", and the other cases were evaluated as "A".
These results are shown in Table 2.

Figure 2020161524
Figure 2020161524

表2に示されるように、1次洗浄、2次洗浄、3次洗浄を順に施した実施例では、銅層表面の塩素/銅濃度比が0.45以下で、ろう染みもなく、変色も生じなかった。
これに対して、比較例1は2次洗浄を施さなかったため、銅層表面の塩素/銅濃度比が0.45を超えており、変色が生じた。比較例2は1次洗浄を施さなかったため、ろう染みが生じた。
As shown in Table 2, in the examples in which the primary cleaning, the secondary cleaning, and the tertiary cleaning were performed in order, the chlorine / copper concentration ratio on the copper layer surface was 0.45 or less, there was no wax stain, and there was no discoloration. It did not occur.
On the other hand, in Comparative Example 1, since the secondary cleaning was not performed, the chlorine / copper concentration ratio on the surface of the copper layer exceeded 0.45, and discoloration occurred. In Comparative Example 2, since the primary cleaning was not performed, wax stain occurred.

10 パワーモジュール用基板(絶縁回路基板)
11 セラミックス基板
12 回路層(銅層)
13 放熱層(銅層)
12´,13´ 銅板
21,22 ろう材層
10 Power module board (insulated circuit board)
11 Ceramic substrate 12 Circuit layer (copper layer)
13 Heat dissipation layer (copper layer)
12', 13' Copper plate 21 and 22 Wax layer

Claims (2)

セラミックス基板と銅又は銅合金からなる銅板とをろう材を介して接合してセラミックス基板の表面に銅層を形成する接合工程と、接合工程後に前記銅層の表面を塩化鉄又は塩化銅を含む水溶液によって洗浄する一次洗浄工程と、該一次洗浄工程後に前記銅層の表面を、塩化鉄及び塩化銅以外の塩化物、アンモニア、シアン化物、チオ硫酸塩のいずれか一つ以上を含む水溶液で洗浄する二次洗浄工程と、前記二次洗浄工程の後に、硫酸、過硫酸塩、硫酸と過酸化水素の混合液のいずれか一つ以上を含む水溶液で洗浄する三次洗浄工程を有することを特徴とする絶縁回路基板の製造方法。 A joining step of joining a ceramic substrate and a copper plate made of copper or a copper alloy via a brazing material to form a copper layer on the surface of the ceramic substrate, and a joining step in which the surface of the copper layer contains iron chloride or copper chloride after the joining step. A primary cleaning step of cleaning with an aqueous solution, and after the primary cleaning step, the surface of the copper layer is washed with an aqueous solution containing one or more of chlorides other than iron chloride and copper chloride, ammonia, cyanide, and thiosulfate. It is characterized by having a secondary cleaning step for cleaning, and after the secondary cleaning step, a tertiary cleaning step for cleaning with an aqueous solution containing any one or more of a mixed solution of sulfuric acid, persulfate, and sulfuric acid and hydrogen peroxide. Manufacturing method of insulated circuit board. セラミックス基板の表面に銅層がろう付けされてなる絶縁回路基板であって、前記銅層の表面に形成されたろう染みは前記銅層の端部からの幅が50μm以下であり、前記銅層の表面の塩素/銅濃度比が0.45以下であることを特徴とする絶縁回路基板。 An insulating circuit board in which a copper layer is brazed to the surface of a ceramics substrate, and the wax stain formed on the surface of the copper layer has a width of 50 μm or less from the end of the copper layer, and the copper layer has a width of 50 μm or less. An insulated circuit board having a surface chlorine / copper concentration ratio of 0.45 or less.
JP2019056280A 2019-03-25 2019-03-25 Insulated circuit board manufacturing method and its insulated circuit board Active JP7334438B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019056280A JP7334438B2 (en) 2019-03-25 2019-03-25 Insulated circuit board manufacturing method and its insulated circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019056280A JP7334438B2 (en) 2019-03-25 2019-03-25 Insulated circuit board manufacturing method and its insulated circuit board

Publications (2)

Publication Number Publication Date
JP2020161524A true JP2020161524A (en) 2020-10-01
JP7334438B2 JP7334438B2 (en) 2023-08-29

Family

ID=72639794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019056280A Active JP7334438B2 (en) 2019-03-25 2019-03-25 Insulated circuit board manufacturing method and its insulated circuit board

Country Status (1)

Country Link
JP (1) JP7334438B2 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736467B2 (en) * 1991-07-05 1995-04-19 電気化学工業株式会社 Ceramic circuit board manufacturing method
JPH10303532A (en) * 1997-04-25 1998-11-13 Sharp Corp Manufacture of printed wiring board
JP2004172182A (en) * 2002-11-18 2004-06-17 Denki Kagaku Kogyo Kk Circuit board and its manufacturing method
JP2008181939A (en) * 2007-01-23 2008-08-07 Mitsubishi Materials Corp Production process of substrate for power module and substrate for power module and power module
JP2013055264A (en) * 2011-09-05 2013-03-21 Toshiba Corp Manufacturing method of ceramic copper circuit board
JP2016517914A (en) * 2013-03-27 2016-06-20 アトーテヒ ドイッチュラント ゲゼルシャフト ミット ベシュレンクテル ハフツング Electroless copper plating solution
JP2018145047A (en) * 2017-03-03 2018-09-20 Dowaメタルテック株式会社 Method for producing metal/ceramic circuit board
WO2019054294A1 (en) * 2017-09-12 2019-03-21 株式会社 東芝 Method for manufacturing ceramic circuit board

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736467B2 (en) * 1991-07-05 1995-04-19 電気化学工業株式会社 Ceramic circuit board manufacturing method
JPH10303532A (en) * 1997-04-25 1998-11-13 Sharp Corp Manufacture of printed wiring board
JP2004172182A (en) * 2002-11-18 2004-06-17 Denki Kagaku Kogyo Kk Circuit board and its manufacturing method
JP2008181939A (en) * 2007-01-23 2008-08-07 Mitsubishi Materials Corp Production process of substrate for power module and substrate for power module and power module
JP2013055264A (en) * 2011-09-05 2013-03-21 Toshiba Corp Manufacturing method of ceramic copper circuit board
JP2016517914A (en) * 2013-03-27 2016-06-20 アトーテヒ ドイッチュラント ゲゼルシャフト ミット ベシュレンクテル ハフツング Electroless copper plating solution
JP2018145047A (en) * 2017-03-03 2018-09-20 Dowaメタルテック株式会社 Method for producing metal/ceramic circuit board
WO2019054294A1 (en) * 2017-09-12 2019-03-21 株式会社 東芝 Method for manufacturing ceramic circuit board

Also Published As

Publication number Publication date
JP7334438B2 (en) 2023-08-29

Similar Documents

Publication Publication Date Title
JP6799479B2 (en) Manufacturing method of metal-ceramic circuit board
JP6742073B2 (en) Ceramics circuit board
JP4811756B2 (en) Method for manufacturing metal-ceramic bonding circuit board
JPWO2018221493A1 (en) Ceramic circuit board and module using the same
JP6687109B2 (en) Substrate for power module
JP4710798B2 (en) Power module substrate, power module substrate manufacturing method, and power module
JP5741971B2 (en) Method for manufacturing metal-ceramic bonding circuit board
JP4037425B2 (en) Ceramic circuit board and power control component using the same.
US9872380B2 (en) Ceramic circuit board and method for producing same
JP3449458B2 (en) Circuit board
JP4930833B2 (en) Ceramic circuit board and manufacturing method thereof
JP2003060111A (en) Method for manufacturing ceramic circuit board
JP6904094B2 (en) Manufacturing method of insulated circuit board
JPWO2016013651A1 (en) Brazing material and ceramic substrate using the same
JP6750422B2 (en) Method for manufacturing insulated circuit board, insulated circuit board, power module, LED module, and thermoelectric module
JP7334438B2 (en) Insulated circuit board manufacturing method and its insulated circuit board
JP7543805B2 (en) Manufacturing method for insulating circuit board
JP2022052848A (en) Method of manufacturing insulating circuit board
JP5643959B2 (en) Method for manufacturing metal-ceramic bonding circuit board
JP6477386B2 (en) Manufacturing method of power module substrate with plating
JP2007173577A (en) Ceramic circuit board
WO2020218193A1 (en) Ceramic circuit substrate and electronic component module
JP6386310B2 (en) Pretreatment method for plating Al-Cu joint
JP6621353B2 (en) Heat resistant ceramic circuit board
JP3827605B2 (en) Circuit board and method for improving solder wettability of circuit board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210930

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220823

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220830

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221026

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230124

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230221

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20230516

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230622

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20230630

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230718

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230731

R150 Certificate of patent or registration of utility model

Ref document number: 7334438

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150