JP2020123612A - Manufacturing method of semiconductor device and manufacturing apparatus of the semiconductor device - Google Patents

Abstract

To provide a memory device having high reliability to achieve a high capacity memory device in a low cost.SOLUTION: A transistor (which is also called as a first transistor) as a semiconductor in which a channel is formed in one part of a substrate is formed. Sequentially, a functional layer containing the transistor to which an oxide semiconductor is applied, and a capacity element, or the like, and a first barrier layer are alternately repeatedly formed by a predetermined time to form a lamination body in which the plurality of functional layer and the plurality of first barrier layers are alternately laminated. Sequentially, one part of the lamination body is etched so that the lamination body is divided into a plurality of areas to form a plurality of lamination blocks. After that, a second barrier layer covering each lamination block and an insulator layer embedding a gap between the lamination blocks on the second barrier layer are formed. Sequentially, in a region which is not overlapped with each lamination block, a second plug electrode embedded into the insulator layer and the battier layer is formed.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a method for manufacturing a semiconductor device. One embodiment of the present invention relates to a semiconductor device manufacturing apparatus.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the present invention disclosed in this specification and the like includes a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input/output device, and a driving method thereof. , Or their manufacturing method can be given as an example. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

DRAM, which is a memory device, is required to be low in cost, and in order to further reduce the cost, research and development for increasing the capacity are being actively conducted. For example, although cost reduction can be achieved to some extent by changing the layout of the memory cell and miniaturizing the element, there is a limit to the size reduction of the memory cell and the miniaturization of the element.

As a device for the layout of the memory cell, a structure in which transistors each including silicon as a semiconductor layer are three-dimensionally stacked to reduce the size of the memory cell and an oxide semiconductor (OS) is used as a semiconductor layer. There is disclosed a structure in which a size of a memory cell is reduced by stacking transistors (hereinafter, OS transistors) (Patent Document 1 and Patent Document 2).

JP-A-11-40772 JP, 2013-145875, A

One object of one embodiment of the present invention is to realize a large-capacity memory device at low cost. Another object is to provide a highly reliable memory device. Another object is to provide a new memory device.

Note that the description of these problems does not prevent the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. Note that problems other than these can be extracted from the description in the specification, drawings, claims, and the like.

According to one embodiment of the present invention, a step of preparing a substrate, a step of forming a first transistor in which a part of the substrate serves as a channel formation region, a functional layer, and a first barrier layer on the first transistor. And n are alternately formed n times (n is an integer of 2 or more and 200 or less) to form a laminated body in which n functional layers and first barrier layers are laminated alternately, and a plurality of laminated bodies are formed. A step of partially etching the laminated body to form a plurality of laminated blocks so as to be divided into areas, a second barrier layer that covers upper surfaces and side surfaces of the plurality of laminated blocks, and a second barrier layer. And a step of forming an insulating layer located between the laminated blocks, and forming a plug electrode embedded in the opening reaching the substrate in a part of the insulating layer and the second barrier layer in a region not overlapping the laminated block. The method of manufacturing a semiconductor device, comprising: Here, the functional layer is formed so as to include the second transistor and the capacitor, and the second transistor is formed so as to include the metal oxide in the channel formation region.

In the above, it is preferable that one of the source and the drain of the second transistor and one of the pair of electrodes of the capacitor be electrically connected to each other.

According to another embodiment of the present invention, a step of preparing a substrate, a step of forming a first transistor in which a part of the substrate serves as a channel formation region, a functional layer over the first transistor, and a first layer A step of alternately forming a barrier layer and n times (n is an integer of 2 or more and 200 or less) to form a laminated body in which n functional layers and first barrier layers are laminated alternately; A step of partially etching the laminated body to form a plurality of laminated blocks so as to be divided into a plurality of areas; a second barrier layer that covers upper surfaces and side surfaces of the plurality of laminated blocks; and a second barrier layer. A step of forming an insulating layer which covers and is located between the laminated blocks, and a plug electrode which is embedded in an opening reaching the substrate in a part of the insulating layer and the second barrier layer in a region which does not overlap the laminated block. And a step of forming a semiconductor device. Here, the functional layer is formed so as to include a second transistor, a third transistor, and a capacitor, and the second transistor and the third transistor are formed so as to include a metal oxide in a channel formation region. To be done.

In the above, it is preferable that one of the source and the drain of the second transistor and the gate of the third transistor be formed so as to be electrically connected to each other.

Further, in the above, it is preferable that the plurality of second transistors which overlap in the thickness direction be formed so that the other of the source and the drain is electrically connected to each other.

Further, another aspect of the present invention is a substrate loading unit, a first manufacturing line, a second manufacturing line, a third manufacturing line, a substrate unloading unit, a first transfer path, and 2 is a manufacturing device of a semiconductor device. The substrate loading unit is a unit that temporarily stores the loaded substrate. The first manufacturing line has a function of forming a first transistor in which a part of the substrate serves as a channel formation region. The second manufacturing line has a function of forming a functional layer and a first barrier layer in this order. The third manufacturing line has a function of etching a part of the laminated body to form a plurality of laminated blocks so as to divide the plurality of laminated bodies into a plurality of areas, and covers the upper surface and the side surface of the plurality of laminated blocks. The function of forming the second barrier layer and the insulating layer that covers the second barrier layer and is located between the stacked blocks and one of the insulating layer and the second barrier layer in a region that does not overlap with the stacked block. A function of forming a plug electrode embedded in the opening reaching the substrate. The board unloading section is a section for temporarily storing the board for which the process has been completed. The first transfer path has a function of transferring the substrate from the second manufacturing line to the third manufacturing line. Further, the second transfer path has a function of transferring the substrate, which has been processed in the second manufacturing line, to the second manufacturing line.

According to one embodiment of the present invention, a large-capacity memory device can be realized at low cost. Alternatively, a highly reliable memory device can be provided. Alternatively, a new memory device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have to have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, and the like.

(A) A configuration example of a manufacturing apparatus. (B) The flowchart which concerns on the manufacturing method of a semiconductor device. 6A to 6E are views illustrating a method for manufacturing a semiconductor device. 6A to 6C are views illustrating a method for manufacturing a semiconductor device. Configuration example of a semiconductor device. (A) (B) Structural example of a semiconductor device. Configuration example of a semiconductor device. FIG. 3A is a top view of the memory device and FIG. FIG. 3A is a top view of the memory device and FIG. FIG. 3 is a top view of a memory device. FIG. 3 is a cross-sectional view of a memory device. FIG. 3 is a cross-sectional view of a memory device. FIG. 3 is a cross-sectional view of a memory device. FIG. 3 is a cross-sectional view of a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. FIG. 7A is a top view and FIG. 9B is a cross-sectional view illustrating a method for manufacturing a memory device. (A) The figure explaining classification of the crystal structure of IGZO, (B) The figure explaining the XRD spectrum of quartz glass, (C) The figure explaining the XRD spectrum of crystalline IGZO. 3A and 3B are block diagrams illustrating a configuration example of a storage device. 6A to 6H are circuit diagrams illustrating a structural example of a memory device. 7A and 7B are circuit diagrams illustrating a configuration example of a memory device. (A) A block diagram of a semiconductor device. (B) A schematic view of a semiconductor device. FIG. 3 is a diagram showing various storage devices layer by layer. 7A and 7B are diagrams illustrating an example of an electronic component. 6A to 6E are schematic views of a storage device. 4A to 4C are block diagrams illustrating a structural example of a semiconductor device. 4A is a block diagram illustrating a structural example of a semiconductor device, and FIG. (C) A timing chart showing an operation example of the semiconductor device. FIG. 3 is a block diagram showing a configuration example of a semiconductor device. (A) A circuit diagram showing a configuration example of a semiconductor device. (B) A timing chart showing an operation example of the semiconductor device. FIG. 3 is a block diagram illustrating a semiconductor device. FIG. 3 is a circuit diagram showing a semiconductor device. (A) The schematic diagram which shows the example of (B) electronic component. 6A to 6F are diagrams illustrating electronic devices.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different modes, and that the modes and details can be variously changed without departing from the spirit and the scope thereof. .. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Note that, in the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and repeated description thereof is omitted. Further, when referring to the same function, the hatch patterns may be the same and may not be given a reference numeral in particular.

Note that in each drawing described in this specification, the size of each component, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to that scale.

Note that the ordinal numbers such as “first” and “second” in this specification and the like are added to avoid confusion among components, and are not numerically limited.

A transistor is a kind of semiconductor element, and can realize amplification of current or voltage, switching operation for controlling conduction or non-conduction, or the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

Further, the functions of the “source” and the “drain” may be switched when a transistor having a different polarity is used or when the direction of current flow is changed in circuit operation. Therefore, in this specification, the terms “source” and “drain” can be interchanged.

In this specification and the like, one of a source and a drain of a transistor is referred to as a “first electrode” and the other of the source and the drain is also referred to as a “second electrode”. Note that the gate is also referred to as a “gate” or a “gate electrode”.

In addition, in this specification and the like, the term “electrically connected” includes the case of being connected through “an object having some electrical action”. Here, the “object having some kind of electrical action” is not particularly limited as long as it can transfer an electric signal between the connection targets. For example, “things having some kind of electrical action” include electrodes and wirings, switching elements such as transistors, resistance elements, coils, capacitance elements, and elements having various other functions.

In the following, expressions such as “up” and “down” are basically used in combination with the orientation of the drawings. However, for the purpose of facilitating the description, etc., the orientation of “upper” or “lower” in the specification may not match with that in the drawing. As an example, when describing the stacking order (or formation order) of a laminated body or the like, the surface (formation surface, support surface, adhesive surface, flat surface, etc.) on the side where the laminated body is provided in the drawing is Even if it is located above the laminated body, the direction thereof may be expressed as a downward direction, and the opposite direction may be expressed as an upward direction.

Note that in this specification and the like, the channel length direction of a transistor refers to one of directions parallel to a straight line connecting a source region and a drain region with the shortest distance. That is, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is on. Further, the channel width direction means a direction orthogonal to the channel length direction. Note that depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be defined as one.

In addition, in this specification and the like, the term “film” and the term “layer” can be interchanged with each other. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film".

(Embodiment 1)
In this embodiment, a method for manufacturing a semiconductor device of one embodiment of the present invention and a device for manufacturing a semiconductor device will be described.

[Overview]
A semiconductor device that can be manufactured according to one embodiment of the present invention is a stacked device having a three-dimensional structure in which a plurality of circuits is stacked and provided over a semiconductor substrate of single crystal silicon or the like. For example, a memory device in which a plurality of memory cell arrays are stacked on a silicon single crystal substrate can be manufactured.

It is preferable to form a transistor in which a part of the substrate is used as a semiconductor layer in which a channel is formed in the semiconductor substrate. As a result, the semiconductor substrate can be provided with the sense amplifier and the driver circuit electrically connected to the memory cell array. Since the driving frequency of the transistor formed over the semiconductor substrate can be extremely high, the memory device can be driven at high speed.

On the other hand, in a plurality of memory cell arrays stacked over a semiconductor substrate, a transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed is preferably used. A transistor to which an oxide semiconductor is applied has a feature that leakage current in an off state (also referred to as off current) is extremely low; thus, charge can be held in a capacitor connected to the transistor for a long time.

In addition, a semiconductor device of one embodiment of the present invention includes a memory cell including a transistor and a capacitor over a semiconductor substrate, or a layer including a memory cell array including a plurality of memory cells (also referred to as a functional layer), a first barrier layer, and Have a structure in which they are alternately laminated. The number of stacked functional layers including memory cells can be, for example, 2 layers or more and 256 layers or less, preferably 2 layers or more and 200 layers or less, more preferably 2 layers or more and 128 layers or less. The number of layers is preferably 4, 5, 8, 10, 10, 12, 16, 16, 24, 32, 64, 100, 128, or 256 layers.

The first barrier layer has a function of preventing diffusion of water, hydrogen, or oxygen. By providing the barrier layer between the two functional layers, the reliability of the transistor provided in each layer can be improved.

Further, the laminated body in which the functional layer and the barrier layer are laminated is preferably divided into a plurality of blocks (also referred to as laminated blocks) in plan view (when viewed from the side where the substrate is formed). The plurality of blocks are preferably arranged one-dimensionally on the substrate or arranged in a two-dimensional matrix.

One block has a plurality of memory cells (or memory cell arrays) stacked in the thickness direction. Each memory cell array may be arranged in a block, and may be electrically connected to a sense amplifier, a drive circuit, or the like provided on the substrate by a plug electrode that connects the memory cells. As a result, the semiconductor device can write and read data for each block.

Further, the second barrier layer can be provided in contact with the top surface and the side surface of each block. Like the first barrier layer, the second barrier layer has a function of preventing diffusion of water, hydrogen, or oxygen. As a result, the functional layer included in each block can have a structure in which not only the upper surface and the side surface but also the four side surfaces are surrounded by the barrier layer, so that a highly reliable semiconductor device can be realized.

Further, an insulating layer is provided on the second barrier layer so as to fill the spaces between the plurality of blocks. Further, it is preferable to provide a plug electrode for electrically connecting the connection electrode on the insulating layer and the substrate in the region where the block is not provided.

A method for manufacturing a semiconductor device of one embodiment of the present invention will be described. First, a substrate is prepared. Next, a transistor (also referred to as a first transistor) or the like including a part of the substrate as a semiconductor in which a channel is formed is formed. Subsequently, the formation of a functional layer including a transistor to which an oxide semiconductor is applied, a capacitor, and the like, and the formation of a first barrier layer are alternately repeated a predetermined number of times, so that a plurality of functional layers are formed. A laminated body in which a plurality of first barrier layers are alternately laminated is formed. Then, a part of the stacked body is etched so that the stacked body is divided into a plurality of areas to form a plurality of stacked blocks. After that, a second barrier layer that covers each stacked block and an insulating layer that fills a gap between the stacked blocks are formed over the second barrier layer. Subsequently, a second plug electrode embedded in the insulating layer and the second barrier layer is formed between the stacked blocks.

According to the manufacturing method described above, the number of stacked layers can be freely set by making the number of times of repeating the step of forming the functional layer and the first barrier layer different. Further, since the functional layer and the first barrier layer can be laminated by repeating the same process, the same manufacturing line can be repeatedly used. As a result, even in the case of a laminated device, it is not necessary to provide as many manufacturing lines as the number of laminated layers, and the production facility (manufacturing apparatus) can be simplified, so that the manufacturing cost of the semiconductor device can be significantly reduced. it can.

Hereinafter, more specific examples will be described with reference to the drawings.

[Example of configuration of manufacturing equipment]
FIG. 1A shows a block diagram of the manufacturing apparatus 10. The manufacturing apparatus 10 includes a substrate loading unit LL1, a first manufacturing line 11, a second manufacturing line 12, a third manufacturing line 13, and a substrate unloading unit LL2. The manufacturing apparatus 10 also includes a transport path 21, a transport path 22, a transport path 23 a, a transport path 23 b, and a transport path 24, which are the transport paths for the substrate. The manufacturing apparatus 10 can load a substrate from the substrate loading unit LL1 and unload a completed substrate from each manufacturing line from the substrate unloading unit LL2. The manufacturing apparatus 10 can also be called a production facility including a plurality of devices.

The substrate carry-in section LL1 is a portion into which the substrate is carried in. The substrate loading unit LL1 can temporarily store the loaded substrate. The substrate loading unit LL1 can be configured to include, for example, a load lock chamber.

The transfer path 21 has a mechanism for transferring a substrate from the substrate loading unit LL1 to the first manufacturing line 11.

The first manufacturing line 11 includes a device for forming a first transistor in which at least a part of the substrate serves as a channel formation region. In addition to the first transistor, wirings, capacitors, plug electrodes, etc. may be formed on the substrate carried out through the first manufacturing line 11. For example, when a silicon wafer is used as the substrate, an n-type transistor using silicon as a semiconductor layer, a p-type transistor, or both can be formed in the first manufacturing line 11.

The transport path 22 has a mechanism for transporting the substrate from the first manufacturing line 11 to the second manufacturing line 12.

The second manufacturing line 12 includes a device for sequentially forming the functional layer and the first barrier layer.

The functional layer includes at least a second transistor in which an oxide semiconductor is applied to a semiconductor layer in which a channel is formed and a capacitor. Further, the functional layer may further include electrodes, wirings, plug electrodes, insulating layers, and the like.

The first barrier layer is formed so as to cover the upper surface of the functional layer. The first barrier layer includes an insulating layer in which water, hydrogen, or oxygen does not easily diffuse. As the first barrier layer, an insulating film containing aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like is preferably used. In particular, since silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, it can be preferably used as a sealing material. Further, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide are preferable because they sometimes have a function of trapping and fixing hydrogen. Further, it is preferable that the first barrier layer has a structure in which two or more layers of the above-described insulating films are stacked because the barrier property is improved.

The transfer path 23 a has a mechanism that transfers the substrate carried out from the second manufacturing line 12 to the second manufacturing line 12 again. By providing the transport path 23a, the functional layer and the first barrier layer can be repeatedly formed by the second manufacturing line 12, and a laminated body in which these are laminated alternately can be formed.

The transport path 23b has a mechanism for transporting the substrate carried out from the second manufacturing line 12 to the third manufacturing line 13.

The third manufacturing line 13 includes devices related to the following steps. In the third manufacturing line 13, first, a part of the laminated body is etched so that the laminated body formed in the second manufacturing line 12 is divided into a plurality of areas to form a plurality of laminated blocks. Subsequently, a second barrier layer that covers the top surface and side surfaces of the plurality of stacked blocks and an insulating layer that covers the second barrier layer and fills the space between the stacked blocks are formed. Then, in a portion where the stacked block is not provided (for example, a region located between the stacked blocks), an opening is formed in the insulating layer and the second barrier layer and electrically connected to a wiring or the like formed over the substrate. A plug electrode is formed.

In addition, the third manufacturing line 13 may include a device that forms, on the insulating layer, a connection terminal that is electrically connected to the plug electrode formed above.

The transfer path 24 has a mechanism that transfers the substrate carried out from the third manufacturing line 13 to the substrate carrying-out section LL2.

The substrate unloading unit LL2 is a portion into which the substrate is loaded. The substrate unloading unit LL2 can temporarily store the substrate for which the process has been completed. The substrate unloading unit LL2 can be configured to include, for example, a load lock chamber.

Here, the first manufacturing line 11, the second manufacturing line 12, and the third manufacturing line 13 included in the manufacturing apparatus 10 can include various devices necessary for a manufacturing process of a target semiconductor device. .. Typically, a structure including a film forming device, a photolithography device, an etching device, a cleaning device, an ion doping device, a heat treatment device, a laser device, and the like can be employed. Moreover, it is preferable that the first manufacturing line 11, the second manufacturing line 12, and the third manufacturing line 13 include so-called in-line devices in which various devices are arranged in the order of the manufacturing process.

[Example of manufacturing method of semiconductor device]
Hereinafter, an example of a method of manufacturing a semiconductor device using the manufacturing apparatus 10 will be described with reference to the drawings.

FIG. 1B is a flowchart of a method for manufacturing a semiconductor device using the manufacturing apparatus 10. 2A to 2E and FIGS. 3A to 3C are schematic perspective views for explaining the method for manufacturing the semiconductor device.

[Substrate loading (step S1)]
First, the substrate 30 is loaded into the substrate loading unit LL1 of the manufacturing apparatus 10. The loaded substrate 30 is temporarily stored in the substrate loading unit LL1 and then sent to the first manufacturing line 11 via the transport path 21.

Here, a case where a silicon wafer is used as the substrate 30 will be described as an example.

[Si-FET forming step (step S2)]
In the first manufacturing line 11, a transistor (first transistor, also referred to as Si-FET (Field Effect Transistor)) in which silicon is applied to a semiconductor layer is formed. In addition to this, by forming wirings, electrodes, capacitors, and the like, various circuits including the first transistor can be formed over the substrate 30. For example, when manufacturing a memory device, examples of the circuit include a driver circuit which controls writing and reading operations, a sense amplifier circuit, and the like.

A known Si-LSI manufacturing process can be applied to the manufacturing method of the first transistor. For example, a planar type transistor, a Fin type transistor, a trench type transistor, or the like can be manufactured. In addition, the first manufacturing line 11 can manufacture an n-type transistor, a p-type transistor, or both. By forming a circuit using both an n-type transistor and a p-type transistor, the functionality and performance of the circuit can be improved.

FIG. 2A illustrates an example in which the circuit 31 including the sense amplifier 32, the wiring 33, and the connection portion 34 are formed over the substrate 30. The circuit 31 functions as a read circuit which reads data of the memory cell 41 which is formed later. In addition, a row driver circuit, a column driver circuit, an arithmetic circuit, a memory circuit and the like (not shown) may be formed on the substrate 30. The connection portion 34 is a portion to which a plug 56 formed later is connected. The wiring 33 is a wiring electrically connected to the circuit 31 and has a function of supplying a signal or a potential supplied to a terminal 57 formed later to the circuit 31, for example.

Subsequently, in the first manufacturing line 11, the barrier layer 39 that covers the circuit 31 and the like is formed (FIG. 2B). The barrier layer 39 has a function of preventing water or hydrogen from diffusing on the side of the functional layer 40 to be formed later. Further, it may have a function of suppressing diffusion of a metal element (typically, copper or the like) contained in wirings or electrodes provided on the substrate 30. The barrier layer 39 preferably has a structure including one or more of the above-described insulating films. The barrier layer 39 can be formed by a method similar to that of the barrier layer 51 described later.

The substrate 30 for which the process in the first manufacturing line 11 has been completed is sent to the second manufacturing line 12 via the transport path 22.

[OS-FET, capacitance forming step (step S3)]
In the second manufacturing line 12, the functional layer 40 is formed on the barrier layer 39 (FIG. 2C).

FIG. 2C shows an example in which the functional layer 40 has a plurality of memory cells 41. The memory cell 41 has a transistor 42 and a capacitor 43. The transistor 42 is a transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed (also referred to as a second transistor or an OS (Oxide Semiconductor)-FET). The memory cell 41 can store data by holding charge in the capacitor 43 through the transistor 42.

The transistor 42 is electrically connected to the circuit 31 provided on the substrate 30 through the plug 44 that functions as a bit line. FIG. 2C shows an example in which two memory cells share one bit line (plug 44). This is preferable since the memory cells can be arranged at a higher density. The plug 44 is formed so as to penetrate the barrier layer 39.

In the second manufacturing line 12, the transistor 42, the capacitor 43, and the plug 44 can be formed. In addition to this, the memory cell 41 can be formed by forming wirings, electrodes, and the like. A circuit may be formed in addition to the memory cell 41.

[Barrier Layer Forming Step (Step S4)]
Subsequently, in the second manufacturing line 12, the barrier layer 51 is formed on the functional layer 40 (FIG. 2D).

The barrier layer 51 can be formed as a single layer or a stack of the above-described insulating films. The barrier layer 51 can be formed by a film forming method such as a CVD method, an ALD method, or a sputtering method.

For the insulating film used for the barrier layer 51, it is preferable to reduce the hydrogen concentration in the film by appropriately setting the film forming conditions. In general, a film formed by a CVD method or an ALD method has higher coverage than a film formed by a sputtering method. On the other hand, the compound gas used for the CVD method or the ALD method often contains hydrogen, and the film formed by the CVD method or the ALD method has a higher hydrogen content than the film formed by the sputtering method. Many.

Therefore, for example, a film with a reduced hydrogen concentration in the film (specifically, a film formed by a sputtering method) is preferably used as a film which is close to the functional layer 40. Further, as a film that suppresses diffusion of impurities, a film having high coverage (specifically, a film formed by using a CVD method or an ALD method) is sandwiched between a pair of films whose hydrogen concentration is reduced. Good to do. Further, a film having a function of capturing and fixing hydrogen and having a reduced hydrogen concentration may be provided in contact with the film having high coverage.

By providing the barrier layer 51, diffusion of water, hydrogen, and oxygen between the two functional layers 40 can be prevented. It can be said that the barrier layer 51 also functions as a separation layer that separates the two functional layers 40.

[Branching (step S5)]
Here, when the number of repetitions of the process in the second manufacturing line 12 reaches the predetermined number (n times), the process proceeds to step S6. On the other hand, when the number of repetitions is less than n, the process proceeds to step S3. Here, first, the latter will be described.

The substrate 30 whose process has been completed in the second manufacturing line 12 is sent again to the second manufacturing line 12 via the transfer path 23a.

After that, the functional layer 40 and the barrier layer 51 are laminated and formed on the barrier layer 51 through the same steps as above in the second manufacturing line 12.

FIG. 2E shows a schematic perspective view after the process in the second manufacturing line 12 is repeated a plurality of times. Here, as an example, a state in which six functional layers 40 and six barrier layers 51 are alternately stacked is shown.

Here, a plug 45 that is electrically connected to the plug 44 is provided between the two functional layers 40. The plug 45 is formed in the same process as the plug 44. The configuration in which the plurality of plugs 45 and the plugs 44 are connected functions as a bit line.

[Blocking Step (Step S6)]
The substrate on which the process in the second manufacturing line 12 has been completed a predetermined number of times (n times) is sent to the third manufacturing line 13 via the transfer path 23b.

In the third manufacturing line 13, a part of the laminated body is etched so that the laminated body in which the functional layers 40 and the barrier layers 51 are alternately laminated is divided into a plurality of areas to form a plurality of laminated blocks 60. Formed (FIG. 3A). The etching can be performed so that the upper surface of the barrier layer 39 is exposed. The etching is preferably performed by an anisotropic dry etching method.

One laminated block 60 has a configuration in which island-shaped functional layers 40a and island-shaped barrier layers 51a are alternately laminated. It is preferable that the plurality of laminated blocks 60 be formed so as to be arranged one-dimensionally or arranged two-dimensionally in a matrix.

[Block sealing step (step S7)]
Then, in the manufacturing line 13, the barrier layer 52 is formed so as to cover the upper surface and the side surface of the laminated block 60 and the upper surface of the barrier layer 39. The barrier layer 52 can be formed under the same conditions as the barrier layer 51. By forming the barrier layer 52 and the barrier layer 51 under the same conditions, it is possible to use the same film forming gas and the like, so that the manufacturing cost can be reduced.

After forming the barrier layer 52, the insulating layer 55 is formed so as to fill the space between the laminated blocks 60. The insulating layer 55 may be provided so as to cover the upper surface of the barrier layer 52 located on the laminated block 60. Further, after the insulating layer 55 is formed, it is preferable to perform a process of planarizing the upper surface (planarizing process). As the flattening treatment, a CMP (Chemical Mechanical Polishing) method can be typically used.

By forming the barrier layer 52, the side surface of each functional layer 40a included in the laminated block 60 can be protected, and diffusion of impurities such as water and hydrogen from the insulating layer 55 to the side surface can be suppressed. Therefore, a highly reliable semiconductor device can be realized. In addition, since a film having a high hydrogen content can be used for the insulating layer 55, the range of choices for the method of forming the insulating layer 55 and the material can be expanded. As a result, the insulating layer 55 can be formed under the condition that the film formation rate is increased, and the secondary effect of reducing the manufacturing cost can be obtained.

[Plug Electrode Forming Step (Step S8)]
Then, in the third manufacturing line 13, in the region where the laminated block 60 is not provided, an opening reaching the connection portion 34 of the substrate 30 is formed in the insulating layer 55, the barrier layer 52, and the barrier layer 39. Then, a conductive layer is formed so as to fill the opening, whereby the plug 56 which is electrically connected to the connection portion 34 can be formed (FIG. 3C).

In FIG. 3C, a terminal 57 provided on the insulating layer 55 and electrically connected to the plug 56 is clearly shown. The terminal 57 functions as an external connection terminal and can be electrically connected to an electrode included in an IC package or the like by a wire bonding method or the like.

Although the insulating layer 55 covers the barrier layer 52 in the region overlapping with the stacked block 60 in FIG. 3C, the upper surface of the barrier layer 52 is exposed by the above planarization treatment. It may be. At this time, an insulating layer may be further provided so as to cover the upper surface of the barrier layer 52 and the upper surface of the insulating layer 55.

Through the above steps, a semiconductor device having a laminated structure can be manufactured using the manufacturing apparatus 10.

[Configuration Example of Semiconductor Device]
Hereinafter, a configuration example of a semiconductor device that can be manufactured using the manufacturing apparatus 10 will be described. The semiconductor device illustrated below can be used as a memory device (memory device).

[Structure example 1]
FIG. 4 is a schematic diagram showing an exploded view of the laminated structure of the semiconductor device 50. Note that some of the constituent elements (barrier layer 52, etc.) are not shown in FIG.

In one laminated block 60, n functional layers 40a are laminated on the substrate 30. FIG. 4 illustrates the functional layer 40a_1, the functional layer 40a_2, and the uppermost functional layer 40a_n from the substrate 30 side. A barrier layer 51a is provided between the two functional layers 40a. A barrier layer 39 is provided between the substrate 30 and the functional layer 40a_1.

One functional layer 40a has one or more memory cells 41. The memory cell 41 has a transistor 42 and a capacitor 43. One of the source and the drain of the transistor 42 is electrically connected to the circuit 31 through the plug 44 (or the plug 44 and the plug 45) whose source or drain functions as a bit line, and the other is electrically connected to one electrode of the capacitor 43. It is connected.

Writing data to the memory cell 41 is performed by turning on the transistor 42 and charging or discharging the capacitor 43 through the transistor 42 in accordance with the potential of the bit line. Data is held by turning off the transistor 42. Data is read by reading the change in the potential of the bit line when the transistor 42 is turned on by the sense amplifier of the circuit 31. Therefore, the semiconductor device 50 functions as a destructive read storage device.

Further, FIG. 4 shows a configuration in which two memory cells share one bit line. As a result, the area occupied by the memory cells can be reduced, and a larger-capacity storage device can be obtained.

Next, an example of the structure of the laminated block 60 will be described with reference to FIGS. 5A and 5B are schematic diagrams showing the configuration of the plurality of laminated blocks 60.

As shown in FIG. 5A, one laminated block 60 is provided with a plurality of functional layers 40a laminated. The functional layer 40a has a memory cell array 65 to which a plurality of memory cells 41 are electrically connected.

The memory cell array 65 has a plurality of bit lines BL, a plurality of word lines WL, and a plurality of wirings CL. The memory cell array 65 has a configuration in which a plurality of pairs of memory cells 41 sharing the bit line BL are arranged in the word line WL direction.

The configuration illustrated in FIG. 5A is an example in which one memory cell array 65 is provided in one functional layer 40a. Here, if one memory cell array 65 has m memory cells 41 in the word line WL direction, and n functional layers 40a are stacked on the stacked block 60, one stacked block 60 is formed. Is provided with 2×m×n memory cells 41.

The configuration illustrated in FIG. 5B is an example in which a plurality of memory cell arrays 65 is provided in one functional layer 40a. With such a configuration, the amount of data per stacked block 60 can be increased, so that a larger-capacity storage device can be realized.

[Structure example 2]
FIG. 6 is a schematic diagram showing an exploded view of the laminated structure of the semiconductor device 50a. The semiconductor device 50a has a memory cell configuration different from that of the semiconductor device 50 illustrated in FIG.

The memory cell 41a has a transistor 46 in addition to the transistor 42 and the capacitor 43. Here, an example is shown in which a pair of memory cells 41a that share the plug 44 (and the plug 45) that functions as a bit line are provided in one functional layer 40a. A plug 47a (or a plug 47b) that functions as a read wiring is electrically connected to the memory cell 41a. The plug 47a and the plug 47b are electrically connected to the plurality of stacked memory cells 41a and the circuit 31.

One of the source and the drain of the transistor 42 is electrically connected to the circuit 31 through the plug 44 (or the plug 44 and the plug 45) whose source or drain functions as a bit line, and the other is electrically connected to one electrode of the capacitor 43. It is connected. The other of the source and the drain of the transistor 42 is electrically connected to one electrode of the capacitor 43 and the gate of the transistor 46. One of a source and a drain of the transistor 46 is electrically connected to the circuit 31 through the plug 47a (or the plug 47b).

The memory cell 41a can hold data by holding a potential at a node to which the gate of the transistor 46 is connected. Further, since the on state of the transistor 46 changes in accordance with the potential (that is, the data potential) to which the gate of the transistor 46 is connected, data can be read by detecting the current flowing in the transistor 46 with the circuit 31. .. That is, the semiconductor device 50a having the memory cell 41a functions as a nondestructive read type memory device.

The transistor 42 and the transistor 46 can be manufactured through the same process. Therefore, the semiconductor device 50 and the semiconductor device 50a illustrated above can be separately manufactured using the manufacturing apparatus 10 of one embodiment of the present invention. Note that the transistor 42 and the transistor 46 can be manufactured by different steps.

In the structure illustrated in FIGS. 4 and 6, a transistor including an oxide semiconductor for a semiconductor layer in which a channel is formed is used as the transistor 42, so that the potential written in the capacitor 43 is held for a long time. can do. Further, since the leak current in the off state of the transistor 42 is extremely small, the data potential during the holding period hardly changes. Therefore, it is possible to realize a storage device capable of writing and reading not only binary data but also multivalued data of three or more values or analog data.

Here, in FIG. 4 and FIG. 6, an example in which the functional layers 40a having the same circuit configuration are laminated is shown, but the functional layers 40a having different circuit configurations may be laminated. For example, in the above manufacturing method, by changing only the photomask used in the exposure apparatus included in the second manufacturing line 12, the functional layers 40 having different layout patterns can be created separately. Further, at this time, since steps other than the photomask can be shared, a new apparatus is not required, and one second manufacturing line 12 can be formed without changing processing conditions in each apparatus other than the exposure apparatus. It can be used repeatedly. Further, since semiconductor devices of various kinds can be manufactured only by switching the photomask, it is possible to produce a large number of kinds of products at a low cost using the same equipment.

By the above method, it is possible to stack two or more kinds of functional layers 40 in a desired order. For example, a semiconductor device in which the functional layer 40a including the memory cell 41 illustrated in FIG. 4 and the functional layer 40 including the memory cell 41a illustrated in FIG. 6 are stacked can be manufactured. Further, for example, a functional layer having a selector circuit, a buffer circuit, a sense amplifier circuit, or the like is stacked on the substrate 30, a functional layer 40 having a memory cell 41a is stacked thereon, and the memory cell 41 is further stacked thereon. It is also possible to manufacture a semiconductor device in which a plurality of the functional layers 40 included therein are stacked.

The above is the description of the configuration example of the semiconductor device that can be manufactured using the manufacturing apparatus 10.

According to one embodiment of the present invention, a large-capacity storage device can be manufactured with high yield at low cost. According to one embodiment of the present invention, memory devices having different memory capacities can be easily manufactured by differentiating the number of times of repeating the step of forming the functional layer and the first barrier layer. Therefore, it is not necessary to provide a manufacturing line for each product, and it is possible to manufacture a wide variety of storage devices at low cost.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 2)
Hereinafter, a configuration example of the semiconductor device that can be manufactured by the manufacturing method and the manufacturing apparatus illustrated in the first embodiment will be described. Here, in particular, a memory device will be described as an example of a semiconductor device.

The memory cell illustrated below corresponds to the memory cell provided in the functional layer, which is illustrated in Embodiment 1. Further, the memory cell layers exemplified below correspond to the functional layers exemplified in the first embodiment.

<Example of memory cell configuration>
7A and 7B illustrate a structure of the memory cell 860 included in the memory device according to one embodiment of the present invention. FIG. 7A is a top view of the memory cell 860 and its periphery. 7B is a cross-sectional view of the memory cell 860, and FIG. 7B corresponds to a portion indicated by dashed-dotted line A1-A2 in FIG. 7A. In FIG. 7B, a cross section in the channel length direction of the transistor 600 and a cross section in the channel width direction of the transistor 700 are shown. Note that in the top view of FIG. 7A, some elements are omitted for clarity of the drawing. Note that the X direction, the Y direction, and the Z direction shown in FIG. 7A are directions orthogonal to or intersecting with each other. Here, it is preferable that the X direction and the Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially vertical to the substrate surface.

The memory cell 860 described in this embodiment includes the transistor 600, the transistor 700, and the capacitor 655. The memory cell 860 corresponds to the memory cell 41a described in the above embodiment, and the transistor 600, the transistor 700, and the capacitor 655 respectively correspond to the transistor 42, the transistor 46, and the capacitor described in the above embodiment. Corresponds to 43. Therefore, one of the source and the drain of the transistor 600, the gate of the transistor 700, and one of the electrodes of the capacitor 655 are electrically connected to each other.

As illustrated in FIGS. 7A and 7B, in the memory cell 860, the transistor 600 and the transistor 700 are provided over the insulator 614 and the insulator 680 is provided over part of the transistor 600 and the transistor 700. The insulator 682 is provided over the transistor 600, the transistor 700, and the insulator 680, the insulator 685 is provided over the insulator 682, the capacitor 655 is provided over the insulator 685, and the capacitor 655 is provided. An insulator 688 is disposed on the above. The insulator 614, the insulator 680, the insulator 682, the insulator 685, and the insulator 688 function as an interlayer film.

Here, the transistor 600 includes an insulator 616 over an insulator 614, a conductor 605 (a conductor 605a, and a conductor 605b) arranged so as to be embedded in the insulator 616, over the insulator 616, and a conductor. Insulator 622 over body 605, insulator 624 over insulator 622, oxide 630a over insulator 624, oxide 630b over oxide 630a, oxide 643a over oxide 630b, and oxide. 643b, the conductor 642a over the oxide 643a, the conductor 642b over the oxide 643b, part of the insulator 624, the side surface of the oxide 630a, the side surface of the oxide 630b, the side surface of the oxide 643a, the conductor An insulator 672 in contact with the side surface of the conductor 642a, the top surface of the conductor 642a, the side surface of the oxide 643b, the side surface of the conductor 642b, and the top surface of the conductor 642b; the insulator 673 over the insulator 672; Oxide 630c, the insulator 650 over the oxide 630c, and the conductor 660 (the conductor 660a and the conductor 660b) which is located over the insulator 650 and overlaps with the oxide 630c. The oxide 630c is in contact with the side surface of the oxide 643a, the side surface of the oxide 643b, the side surface of the conductor 642a, and the side surface of the conductor 642b, respectively. Here, as shown in FIG. 7B, the top surface of the conductor 660 is arranged to be substantially aligned with the top surface of the insulator 650, the top surface of the oxide 630c, and the top surface of the insulator 680. The insulator 682 is in contact with the top surfaces of the conductor 660, the insulator 650, the oxide 630c, and the insulator 680, respectively.

Note that in the following, the oxide 630a, the oxide 630b, and the oxide 630c may be collectively referred to as the oxide 630. The oxide 643a and the oxide 643b may be collectively referred to as the oxide 643. In addition, the conductor 642a and the conductor 642b may be collectively referred to as a conductor 642.

In the transistor 600, the conductor 660 functions as a gate, and the conductors 642a and 642b function as a source and a drain, respectively. Further, the conductor 605 functions as a back gate. The transistor 600 is formed in a self-aligned manner so that the conductor 660 functioning as a gate fills the opening formed by the insulator 680 or the like. As described above, in the memory device according to this embodiment, the conductor 660 can be reliably arranged in the region between the conductors 642a and 642b without alignment.

In addition, the transistor 700 includes the insulator 616 over the insulator 614, the conductor 705 (the conductor 705a, and the conductor 705b) arranged so as to be embedded in the insulator 616, the insulator 616, and the conductor 705. Insulator 622 over 705, insulator 624 over insulator 622, oxide 730a over insulator 624, oxide 730b over oxide 730a, oxide 743a and oxide 743b over oxide 730b. And a conductor 742a over the oxide 743a, a conductor 742b over the oxide 743b, a part of the insulator 624, a side surface of the oxide 730a, a side surface of the oxide 730b, a side surface of the oxide 743a, and a conductor 742a. Of the conductor 742a, the top surface of the conductor 742a, the side surface of the oxide 743b, the side surface of the conductor 742b, and the top surface of the conductor 742b, an insulator 672 over the insulator 672, and an insulator 673 over the oxide 730b. The oxide 730c, the insulator 750 over the oxide 730c, and the conductor 760 (the conductor 760a and the conductor 760b) which is located over the insulator 750 and overlaps with the oxide 730c are included. The oxide 730c is in contact with the side surface of the oxide 743a, the side surface of the oxide 743b, the side surface of the conductor 742a, and the side surface of the conductor 742b, respectively. Here, as shown in FIG. 7B, the top surface of the conductor 760 is provided to be substantially aligned with the top surface of the insulator 750, the top surface of the oxide 730c, and the top surface of the insulator 680. The insulator 682 is in contact with the top surfaces of the conductor 760, the insulator 750, the oxide 730c, and the insulator 680, respectively.

In the following, the oxide 730a, the oxide 730b, and the oxide 730c may be collectively referred to as the oxide 730. In addition, the oxide 743a and the oxide 743b may be collectively referred to as an oxide 743. Further, the conductor 742a and the conductor 742b may be collectively referred to as a conductor 742.

In the transistor 700, the conductor 760 functions as a gate, and the conductors 742a and 742b function as a source and a drain, respectively. In addition, the conductor 705 functions as a back gate. The transistor 700 is formed in a self-aligned manner so that the conductor 760 functioning as a gate fills an opening formed by the insulator 680 or the like. As described above, in the memory device according to this embodiment, the conductor 760 can be reliably arranged in the region between the conductors 742a and 742b without alignment.

Here, the transistor 700 is formed in the same layer as the transistor 600 and has a similar structure. Therefore, although a cross section in the channel length direction of the transistor 700 is not illustrated, the transistor 700 has a structure similar to the cross section in the channel length direction of the transistor 600 illustrated in FIG. That is, the oxide 743 and the conductor 742 which are not illustrated in the cross-sectional view also have the same structure as the oxide 643 and the conductor 642 illustrated in FIG. 7B. Note that although a cross section in the channel width direction of the transistor 600 is not illustrated, the transistor 600 has a structure similar to that of the transistor 700 in the channel width direction illustrated in FIG. 7B.

Therefore, the oxide 730 has a structure similar to that of the oxide 630, and the description of the oxide 630 can be referred to. The conductor 705 has a structure similar to that of the conductor 605, and the description of the conductor 605 can be referred to. The oxide 743 has a structure similar to that of the oxide 643, and the description of the oxide 643 can be referred to. The conductor 742 has a structure similar to that of the conductor 642, and the description of the conductor 642 can be referred to. The insulator 750 has a structure similar to that of the insulator 650, and the description of the insulator 650 can be referred to. The conductor 760 has a structure similar to that of the conductor 660, and the description of the conductor 660 can be referred to. In the following, for the structure of the transistor 700 as described above, the description of the structure of the transistor 600 can be referred to unless otherwise specified.

Here, in the transistor 600 and the transistor 700, the oxide 630 and the oxide 730 including a region where a channel is formed (hereinafter also referred to as a channel formation region) is formed in a metal oxide (hereinafter, an oxide) which functions as an oxide semiconductor. It is also preferable to use).

For example, as the metal oxide which functions as an oxide semiconductor, it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a large energy gap, leakage current (off current) in the non-conduction state of the transistor 600 can be extremely reduced.

As an oxide semiconductor, for example, an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium). , One kind or a plurality of kinds selected from hafnium, tantalum, tungsten, magnesium, and the like are preferably used. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. Alternatively, an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used as the oxide semiconductor.

The transistor 600 and the transistor 700 each including an oxide semiconductor for a channel formation region have extremely low leakage current (off-state current) in a non-conduction state, so that a semiconductor device with low power consumption can be provided. Further, the off-state current of the transistors 600 and 700 hardly increases even in a high temperature environment. Specifically, the off-current hardly increases even at an ambient temperature of room temperature or higher and 200° C. or lower. Therefore, the operation is stable even in a high temperature environment, and a highly reliable storage device can be realized.

Since the off-state current of the transistor 600 is extremely small, the capacitance value of the capacitor 655 can be set small. As a result, the area occupied by the memory cell 860 can be reduced, and the storage device can be integrated.

As shown in FIG. 7A, the conductor 742a, the conductor 660, the conductor 605, and the conductor 705 preferably extend in the Y direction. The conductor 742a functions as a selection line. In addition, the conductor 660 functions as a word line. The conductor 605 and the conductor 705 each function as a wiring for controlling the back gate potential of the transistor 600 or the transistor 700.

The capacitor 655 includes a conductor 646a over the insulator 685, an insulator 686 that covers the conductor 646a, and a conductor 656 which overlaps at least part of the conductor 656 and is provided over the insulator 686. Have. Here, the conductor 646a functions as one electrode of the capacitor 655 and the conductor 646b functions as the other electrode of the capacitor 655. The insulator 686 functions as a dielectric of the capacitor 655.

The conductor 656 preferably extends in the Y direction and functions as a capacitor line.

In addition, openings are formed in the insulator 622, the insulator 624, the insulator 672, the insulator 673, the insulator 680, the insulator 682, and the insulator 685, and the conductor 640 serving as a plug (the conductor 640a, The conductor 640b, the conductor 640c, and the conductor 640d) are provided so as to be embedded in the opening. The conductor 640 is provided so as to be exposed on the upper surface of the insulator 685.

The conductor 640a has a lower surface in contact with the conductor 642a and an upper surface in contact with the conductor 646a. The conductor 640c has a lower surface in contact with the conductor 760 and an upper surface in contact with the conductor 646a. In this manner, one of the source and the drain of the transistor 600, the gate of the transistor 700, and one of the electrodes of the capacitor 655 are electrically connected.

The conductor 640b is provided in contact with the side surface of the conductor 642b. The conductor 615 and the conductor 607 are provided below the conductor 640b, and the conductor 646b and the conductor 657 are provided above the conductor 640b. The conductor 607 is provided in the opening formed in the insulator 614. Here, the conductor 615 is formed in the same layer as the conductor 605 and has a similar structure. The conductor 646b is formed in the same layer as the conductor 646a and has a similar structure. The conductor 657 is provided in the opening formed in the insulator 686 and the insulator 688.

The conductor 640b is electrically connected to the conductor 640b of the memory cell 860 in the lower layer by the conductor 607 and the conductor 615. The conductor 640b is electrically connected to the conductor 640b of the memory cell 860 in the upper layer by the conductor 646b and the conductor 657. As described above, the conductor 607, the conductor 615, the conductor 640b, the conductor 646b, and the conductor 657 extend in the Z direction and function as bit lines.

Although not shown in the cross-sectional view, the conductor 640d is provided in contact with the side surface of the conductor 742b. A conductor 715 is provided below the conductor 640d. A conductor having a structure similar to that of the conductor 607, the conductor 646b, and the conductor 657 is provided, and the conductor 640d is electrically connected to the upper and lower conductors 640d. Thus, the conductor 715, the conductor 640d, and the like extend in the Z direction and function as a bit line different from the above.

As illustrated in FIG. 7B, by forming the transistor 600 and the transistor 700 in the same layer, the transistor 600 and the transistor 700 can be formed in the same step, so that a process for manufacturing a memory device can be shortened and production can be performed. It is possible to improve the sex.

Note that in the memory cell 860, the transistor 600, the transistor 700, and the capacitor 655 are provided so that the channel length direction of the transistor 600 and the channel length direction of the transistor 700 are parallel to each other. Is not limited to this. The memory cell 860 illustrated in FIG. 7 and the like is an example of a structure of a memory device, and a transistor, a capacitor, or the like having an appropriate structure may be arranged as appropriate depending on a circuit structure or a driving method.

[Detailed configuration of memory cell]
Hereinafter, a detailed structure of the memory cell 860 according to one embodiment of the present invention will be described. In the following, for components of the transistor 700, the description of components of the transistor 600 can be referred to.

As illustrated in FIG. 7, the oxide 630 is provided over the oxide 630a over the insulator 624, the oxide 630b over the oxide 630a, and the oxide 630b, and at least part of the oxide 630 is over the oxide 630b. And an oxide 630c in contact with the oxide 630c. Here, the side surface of the oxide 630c is preferably provided in contact with the oxide 643a, the oxide 643b, the conductor 642a, the conductor 642b, the insulator 672, the insulator 673, and the insulator 680.

That is, the oxide 630 includes the oxide 630a, the oxide 630b over the oxide 630a, and the oxide 630c over the oxide 630b. By including the oxide 630a below the oxide 630b, diffusion of impurities from the structure formed below the oxide 630a into the oxide 630b can be suppressed. In addition, by having the oxide 630c over the oxide 630b, diffusion of impurities from the structure formed above the oxide 630c into the oxide 630b can be suppressed.

Although the transistor 600 has a structure in which three layers of the oxide 630a, the oxide 630b, and the oxide 630c are stacked in the channel formation region and the vicinity thereof, the present invention is not limited to this. .. For example, a single layer of the oxide 630b, a two-layer structure of the oxide 630b and the oxide 630a, a two-layer structure of the oxide 630b and the oxide 630c, or a stacked structure of four or more layers may be provided. For example, the oxide 630c may have a two-layer structure and a stacked structure of four layers may be provided.

Further, the oxide 630 preferably has a stacked-layer structure of oxides in which the atomic ratio of each metal atom is different. Specifically, in the metal oxide used for the oxide 630a, the atomic number ratio of the element M in the constituent elements is higher than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 630b. It is preferable. In the metal oxide used for the oxide 630a, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 630b. In the metal oxide used for the oxide 630b, the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 630a. For the oxide 630c, a metal oxide that can be used for the oxide 630a or the oxide 630b can be used. Note that in the metal oxide used for the oxide 630c, the atomic ratio of In to the element M may be higher than that in the metal oxide used for the oxide 630b.

Specifically, as the oxide 630a, In:Ga:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof, or 1:1:0.5 [atomic ratio] or a composition in the vicinity thereof. The above metal oxide may be used.

As the oxide 630b, a metal oxide having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or in the vicinity thereof, or 1:1:1 [atomic ratio] or a composition in the vicinity thereof is used. You can use it. In addition, as the oxide 630b, In:Ga:Zn=5:1:3 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=10:1:3 [atomic ratio] or a composition in the vicinity thereof is used. You may use the metal oxide of a composition. As the oxide 630b, an In—Zn oxide (for example, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=5:1 [atomic ratio] or a composition in the vicinity thereof is used. Alternatively, In:Zn=10:1 [atomic ratio] or a composition in the vicinity thereof may be used. Alternatively, an In oxide may be used as the oxide 630b.

Further, as the oxide 630c, In:Ga:Zn=1:3:4 [atomic ratio or composition in the vicinity thereof], Ga:Zn=2:1 [atomic ratio] or composition in the vicinity thereof, or Ga: Zn=2:5 [atomic ratio] or a metal oxide having a composition in the vicinity thereof may be used. Alternatively, a material that can be used for the oxide 630b may be applied to the oxide 630c and the oxide 630c may be provided as a single layer or a stacked layer. For example, as a specific example of the case where the oxide 630c has a stacked structure, In:Ga:Zn=4:2:3 [atomic ratio] or a composition in the vicinity thereof and In:Ga:Zn=1:3: 4 [atomic ratio] or a laminated structure with a composition near it, Ga:Zn=2:1 [atomic ratio] or a composition near it, and In:Ga:Zn=4:2:3 [atomic ratio] ] Or a laminated structure with a composition in the vicinity thereof, Ga:Zn=2:5 [atomic ratio] or a composition in the vicinity thereof, and In:Ga:Zn=4:2:3 [atomic ratio] or a vicinity thereof Examples thereof include a laminated structure with a composition, a laminated structure with gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio] or a composition in the vicinity thereof.

Further, as the oxides 630b and 630c, increasing the proportion of indium in the film is preferable because the on-state current, field-effect mobility, or the like of the transistor can be increased. Further, the above-mentioned composition in the vicinity includes a range of ±30% of a desired atomic number ratio.

In addition, the oxide 630b may have crystallinity. For example, it is preferable to use a CAAC-OS (c-axis aligned crystal oxide semiconductor) described later. An oxide having crystallinity such as CAAC-OS has a dense structure with few impurities and defects (such as oxygen vacancies) and high crystallinity. Therefore, extraction of oxygen from the oxide 630b by the source electrode or the drain electrode can be suppressed. Further, even if heat treatment is performed, oxygen can be prevented from being extracted from the oxide 630b, so that the transistor 600 is stable against a high temperature (so-called thermal budget) in a manufacturing process.

Further, the oxide 630c is preferably provided in the opening provided in the interlayer film including the insulator 680. Therefore, the insulator 650 and the conductor 660 have a region overlapping with the stacked-layer structure of the oxide 630b and the oxide 630a with the oxide 630c interposed therebetween. With such a structure, the oxide 630c and the insulator 650 can be formed by continuous film formation; therefore, the interface between the oxide 630 and the insulator 650 can be kept clean. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 600 can obtain high on-state current and high frequency characteristics.

An oxide semiconductor having a low carrier concentration is preferably used for the oxide 630 (eg, the oxide 630b). In the case of reducing the carrier concentration of the oxide semiconductor, the concentration of impurities in the oxide semiconductor may be lowered and the density of defect states may be lowered. In this specification and the like, low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

In particular, hydrogen contained in the oxide semiconductor reacts with oxygen which is bonded to a metal atom to be water, which might cause oxygen deficiency (also referred to as V 2 _{O 3} ) in the oxide semiconductor. Furthermore, defects containing hydrogen to an oxygen vacancy (hereinafter may be referred to as V O _H.) Functions as a donor, sometimes electrons serving as carriers are generated. In addition, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including an oxide semiconductor which contains a large amount of hydrogen is likely to have normally-on characteristics. Further, hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field; therefore, when a large amount of hydrogen is contained in the oxide semiconductor, reliability of the transistor might be deteriorated.

V _OH can function as a donor of an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Therefore, the oxide semiconductor may be evaluated not by the donor concentration but by the carrier concentration. Therefore, in this specification and the like, the carrier concentration which is assumed to be a state where no electric field is applied may be used as a parameter of the oxide semiconductor, instead of the donor concentration. That is, the “carrier concentration” described in this specification and the like can be called the “donor concentration” in some cases.

From the above, the case of using an oxide semiconductor in the oxide 630, reduced as much as possible V _{O H} in the oxide 630, it is preferable that the highly purified intrinsic or substantially highly purified intrinsic. Thus, the V O _H to obtain a sufficiently reduced oxide semiconductor, the moisture in the oxide semiconductor, to remove impurities such as hydrogen (dehydration, may be described as dehydrogenation.) Then, it is important to supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxygenation treatment). The V O _H oxide semiconductor impurity is sufficiently reduced such by using a channel formation region of the transistor, it is possible to have stable electrical characteristics.

For example, the hydrogen concentration of the oxide 630b obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 ²⁰ atoms/cm ³ , and preferably less than 1×10 ¹⁹ atoms/cm ³ . It can be preferably less than 5×10 ¹⁸ atoms/cm ³ , and more preferably less than 1×10 ¹⁸ atoms/cm ³ . By using the oxide 630 in which impurities such as hydrogen are sufficiently reduced in the channel formation region of the transistor 600, normally-off characteristics can be obtained, stable electrical characteristics can be obtained, and reliability can be improved. it can.

In the case where an oxide semiconductor is used for the oxide 630, the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is preferably 1×10 ¹⁸ cm ⁻³ or lower, and 1×10 ¹⁷ cm ^−3. Is more preferably less than 1×10 ¹⁶ cm ⁻³ , further preferably less than 1×10 ¹³ cm ⁻³ , further preferably less than 1×10 ¹² cm ^−3. More preferable. Note that there is no particular limitation on the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region, but it can be set to, for example, 1×10 ⁻⁹ cm ⁻³ .

Therefore, as the insulator 614, the insulator 622, the insulator 672, the insulator 673, and the insulator 682, a material that suppresses diffusion of impurities (hereinafter also referred to as a barrier material against impurities) is used and impurities such as hydrogen are used. To reduce diffusion into oxide 630. Note that in this specification and the like, the barrier property refers to a function of suppressing diffusion of a corresponding substance (also referred to as low permeability). Alternatively, the corresponding substance has a function of capturing and fixing (also referred to as gettering). In this specification and the like, an insulating film having a barrier property may be referred to as a barrier insulating film.

For example, as a material having a function of suppressing diffusion of hydrogen and oxygen, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like can be given. In particular, since silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, it is preferably used as a sealing material.

Further, for example, as a material having a function of capturing and fixing hydrogen, there is a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide.

For example, as the insulator 614, aluminum oxide, hafnium oxide, or the like is preferably used. Thus, impurities such as water or hydrogen can be suppressed from diffusing from the substrate side to the transistor 600 side. Alternatively, oxygen contained in the insulator 624 and the like can be suppressed from diffusing to the substrate side.

The conductor 605 is arranged so as to overlap with the oxide 630 and the conductor 660. Further, the conductor 605 is preferably provided by being embedded in the insulator 616.

In the case where the conductor 605 functions as a gate electrode, the potential applied to the conductor 605 is changed independently without being linked with the potential applied to the conductor 660, so that the threshold voltage (Vth ) Can be controlled. In particular, by applying a negative potential to the conductor 605, Vth of the transistor 600 can be further increased and off-state current can be reduced. Therefore, applying a negative potential to the conductor 605 can reduce the drain current when the potential applied to the conductor 660 is 0 V, as compared to the case where no potential is applied.

Note that the conductor 605 is preferably larger than a region of the oxide 630 which does not overlap with the conductors 642a and 642b as illustrated in FIG. In particular, as shown in FIG. 7C, the conductor 605 preferably extends in a region outside the end portion of the oxide 630 which intersects with the channel width direction. That is, it is preferable that the conductor 605 and the conductor 660 overlap with each other with the insulator provided outside the side surface of the oxide 630 in the channel width direction. Alternatively, by providing the conductor 605 large, local charging (called charge-up) may be alleviated in a treatment using plasma in a manufacturing process after the formation of the conductor 605. However, one embodiment of the present invention is not limited to this. The conductor 605 may overlap with at least the oxide 630 located between the conductor 642a and the conductor 642b.

Further, with respect to the bottom surface of the insulator 624, the height of the bottom surface of the conductor 660 in a region where the oxide 630a and the oxide 630b do not overlap with the conductor 660 is lower than the height of the bottom surface of the oxide 630b. Are preferably arranged in

As shown in the figure, the conductor 660 functioning as a gate has a structure in which the side surface and the top surface of the oxide 630b in the channel formation region are covered with the oxide 630c and the insulator 650 so that an electric field generated from the conductor 660 is generated. Can easily act on the entire channel formation region generated in the oxide 630b. Therefore, the on-state current of the transistor 600 can be increased and the frequency characteristics can be improved. In this specification, a structure of a transistor in which a channel formation region is electrically surrounded by an electric field of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.

Further, the conductor 605a is preferably a conductor which suppresses permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Further, the conductor 605b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Although the conductor 605 is illustrated as having two layers, it may have a multilayer structure of three or more layers.

Further, the insulator 616, the insulator 680, the insulator 685, and the insulator 688 preferably have lower dielectric constants than the insulator 614. By using a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 616, the insulator 680, the insulator 685, and the insulator 688, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and Nitrogen-added silicon oxide, silicon oxide having holes, or the like may be used as appropriate.

Further, the insulator 616, the insulator 680, the insulator 685, and the insulator 688 are formed by a CVD method or an ALD method using a compound gas which does not contain hydrogen atoms or has a small hydrogen atom content. Good.

In forming the insulating film, a gas having molecules containing silicon atoms is mainly used as a film forming gas. In order to reduce hydrogen contained in the insulating film, the number of hydrogen atoms contained in the molecule containing the silicon atom is preferably small, and the molecule containing the silicon atom is more preferably free of hydrogen atom. Of course, the film-forming gas other than the gas having a molecule containing a silicon atom preferably contains a small number of hydrogen atoms and more preferably does not contain a hydrogen atom.

When the molecule containing a silicon atom as described above is represented by Si _x —R _y , for example, as the functional group R, an isocyanate group (—N═C═O), a cyanate group (—O—C≡N), a cyano group, etc. (-C≡N), diazo group _{(= N} 2), azido group _(-N 3), it is possible to use at least one nitroso group (-NO), and a nitro group (-NO _2). For example, 1≦x≦3 and 1≦y≦8 may be satisfied. As such a molecule containing a silicon atom, for example, tetraisocyanate silane, tetracyanate silane, tetracyanosilane, hexaisocyanate silane, octaisocyanate silane, etc. can be used. Here, a molecule in which the same type of functional group is bonded to a silicon atom has been exemplified, but the present embodiment is not limited to this. You may make it the structure which a different kind of functional group couple|bonds with a silicon atom.

Alternatively, for example, halogen (Cl, Br, I, or F) may be used as the functional group R. For example, 1≦x≦2 and 1≦y≦6. As such a molecule containing a silicon atom, for example, tetrachlorosilane (SiCl ₄ ) or hexachlorodisilane (Si ₂ Cl ₆ ) can be used. Although an example in which chlorine is used as the functional group is shown, halogen other than chlorine, such as bromine, iodine, or fluorine, may be used as the functional group. Further, a structure in which different kinds of halogens are bonded to silicon atoms may be adopted.

The insulator 622 and the insulator 624 have a function as a gate insulator.

Here, it is preferable that the insulator 624 which is in contact with the oxide 630 release oxygen by heating. In the present specification, oxygen released by heating may be referred to as excess oxygen. For example, the insulator 624 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate. By providing the insulator containing oxygen in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced and the reliability of the transistor 600 can be improved.

As the insulator 624, specifically, an oxide material from which part of oxygen is released by heating is preferably used. The oxide that desorbs oxygen by heating means that the desorption amount of oxygen molecules is 1.0×10 ¹⁸ molecules/cm ³ or more, preferably by thermal desorption gas analysis (TDS (Thermal Desorption Spectroscopy) analysis). Is an oxide film of 1.0×10 ¹⁹ molecules/cm ³ or more, more preferably 2.0×10 ¹⁹ molecules/cm ³ or more, or 3.0×10 ²⁰ molecules/cm ³ or more. The surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

The insulator 622 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 600 from the substrate side. For example, the insulator 622 preferably has lower hydrogen permeability than the insulator 624. By surrounding the insulator 624 and the oxide 630 with the insulator 622 and the insulator 683, impurities such as water or hydrogen can be prevented from entering the transistor 600 from the outside.

Further, the insulator 622 preferably has a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (it is difficult for oxygen to permeate). For example, the insulator 622 preferably has lower oxygen permeability than the insulator 624. It is preferable that the insulator 622 have a function of suppressing diffusion of oxygen and impurities because oxygen in the oxide 630 can be prevented from diffusing below the insulator 622. In addition, the conductor 605 can be prevented from reacting with the insulator 624 and oxygen contained in the oxide 630.

As the insulator 622, an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 622 is formed using such a material, the insulator 622 suppresses release of oxygen from the oxide 630 and mixture of impurities such as hydrogen from the peripheral portion of the transistor 600 into the oxide 630. Functions as a layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator and used.

The insulator 622 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba,Sr)TiO ₃ (BST). An insulator including a so-called high-k material may be used in a single layer or a stacked layer. As transistors are miniaturized and highly integrated, thinning of the gate insulator may cause problems such as leakage current. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

Note that the insulator 622 and the insulator 624 may have a stacked structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

Further, the oxide 643 (the oxide 643a and the oxide 643b) may be provided between the oxide 630b and the conductor 642 (the conductor 642a and the conductor 642b) which functions as a source electrode or a drain electrode. .. Since the conductor 642 and the oxide 630 are not in contact with each other, the conductor 642 can suppress absorption of oxygen in the oxide 630. That is, by preventing the conductor 642 from being oxidized, it is possible to suppress a decrease in the conductivity of the conductor 642. Therefore, the oxide 643 preferably has a function of suppressing oxidation of the conductor 642.

Therefore, the oxide 643 preferably has a function of suppressing permeation of oxygen. By disposing the oxide 643 having a function of suppressing permeation of oxygen between the conductor 642 functioning as a source electrode or a drain electrode and the oxide 630b, electric power between the conductor 642 and the oxide 630b is reduced. It is preferable because the resistance is reduced. With such a structure, electric characteristics of the transistor 600 and reliability of the transistor 600 can be improved.

A metal oxide containing the element M may be used as the oxide 643. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. The oxide 643 preferably has a higher concentration of the element M than the oxide 630b. Alternatively, gallium oxide may be used as the oxide 643. Alternatively, as the oxide 643, a metal oxide such as an In-M-Zn oxide may be used. Specifically, in the metal oxide used for the oxide 643, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 630b. The film thickness of the oxide 643 is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. Further, the oxide 643 preferably has crystallinity. When the oxide 643 has crystallinity, release of oxygen in the oxide 630 can be favorably suppressed. For example, if the oxide 643 has a crystal structure such as a hexagonal crystal, release of oxygen in the oxide 630 can be suppressed in some cases.

Note that the oxide 643 does not necessarily have to be provided. In that case, when the conductor 642 (the conductor 642a and the conductor 642b) is in contact with the oxide 630, oxygen in the oxide 630 may diffuse into the conductor 642 and the conductor 642 may be oxidized. Oxidation of the conductor 642 is likely to reduce the conductivity of the conductor 642. Note that diffusion of oxygen in the oxide 630 into the conductor 642 can be restated as absorption of oxygen in the oxide 630 by the conductor 642.

Further, oxygen in the oxide 630 diffuses into the conductor 642 (the conductor 642a and the conductor 642b), so that the conductor 642a and the oxide 630b are separated from each other and the conductor 642b and the oxide 630b are separated from each other. Different layers may be formed between them. Since the different layer contains more oxygen than the conductor 642, it is estimated that the different layer has an insulating property. At this time, the three-layer structure of the conductor 642, the different layer, and the oxide 630b can be regarded as a three-layer structure including a metal-insulator-semiconductor and a MIS (Metal-Insulator-Semiconductor) structure. It may be referred to as a diode junction structure mainly including the MIS structure.

Note that the different layer is not limited to being formed between the conductor 642 and the oxide 630b; for example, when the different layer is formed between the conductor 642 and the oxide 630c, or It may be formed between the body 642 and the oxide 630b and between the conductor 642 and the oxide 630c.

The conductor 642 (the conductor 642a and the conductor 642b) which functions as a source electrode and a drain electrode is provided over the oxide 643. The thickness of the conductor 642 may be, for example, 1 nm to 50 nm inclusive, preferably 2 nm to 25 nm inclusive.

As the conductor 642, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. It is preferable. Further, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. A conductive material or a material that maintains conductivity even when absorbing oxygen is preferable.

The insulator 672 is provided in contact with the top surface of the conductor 642 and preferably functions as a barrier insulating film. Further, an insulator 673 which functions as a barrier insulating film is preferably provided over the insulator 672. With such a structure, absorption of excess oxygen in the insulator 680 by the conductor 642 can be suppressed. Further, by suppressing the oxidation of the conductor 642, an increase in contact resistance between the transistor 600 and the wiring can be suppressed. Therefore, the transistor 600 can have favorable electrical characteristics and reliability.

Therefore, the insulator 672 and the insulator 673 preferably have a function of suppressing diffusion of oxygen. For example, the insulator 672 preferably has a function of suppressing diffusion of oxygen as compared with the insulator 680. As the insulator 672, for example, an insulator containing one or both oxides of aluminum and hafnium may be formed. As the insulator 673, for example, silicon nitride, silicon nitride oxide, or the like may be used.

Further, impurities such as water or hydrogen can be suppressed from diffusing from the insulator 680 or the like which is provided with the insulator 672 and the insulator 673 to the transistor 600 side. As described above, the transistor 600 is preferably surrounded by the insulator 672 and the insulator 673 which have a function of suppressing diffusion of impurities such as water or hydrogen and oxygen.

The insulator 650 functions as a gate insulator. The insulator 650 is preferably arranged in contact with the top surface of the oxide 630c. As the insulator 650, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having holes is used. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

Like the insulator 624, the insulator 650 is preferably formed using an insulator from which oxygen is released by heating. By providing an insulator from which oxygen is released by heating as the insulator 650 in contact with the top surface of the oxide 630c, oxygen can be effectively supplied to the channel formation region of the oxide 630b. Further, similarly to the insulator 624, the concentration of impurities such as water or hydrogen in the insulator 650 is preferably reduced. The thickness of the insulator 650 is preferably 1 nm or more and 20 nm or less.

Further, a metal oxide may be provided between the insulator 650 and the conductor 660. The metal oxide preferably suppresses oxygen diffusion from the insulator 650 to the conductor 660. By providing the metal oxide which suppresses diffusion of oxygen, diffusion of oxygen from the insulator 650 to the conductor 660 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 630 can be suppressed. In addition, oxidation of the conductor 660 due to oxygen in the insulator 650 can be suppressed.

In addition, the metal oxide may have a function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 650, the metal oxide is preferably a high-k material having a high relative dielectric constant. When the gate insulator has a stacked structure of the insulator 650 and the metal oxide, a stacked structure which is stable to heat and has a high relative dielectric constant can be obtained. Therefore, the gate potential applied during the operation of the transistor can be reduced while maintaining the physical film thickness of the gate insulator. Further, the equivalent oxide film thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like may be used. it can. In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (a hafnium aluminate), which is an insulator containing an oxide of one or both of aluminum and hafnium.

Alternatively, the metal oxide may have a function as a part of the gate. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate. Alternatively, a conductive material containing the above metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

The bottom surface and the side surface of the conductor 660 are arranged in contact with the insulator 650. Although the conductor 660 has a two-layer structure in FIG. 7, it may have a single-layer structure or a stacked structure of three or more layers.

The conductor 660a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N ₂ O, NO, NO _2, etc.), and copper atoms. It is preferable to use materials. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules).

In addition, since the conductor 660a has a function of suppressing diffusion of oxygen, oxygen contained in the insulator 650 can prevent the conductor 660b from being oxidized and decreasing in conductivity. As a conductive material having a function of suppressing diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

The conductor 660b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Since the conductor 660 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductor 660b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above conductive material.

For the insulator 680, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having holes is used. It is preferable to use. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies is preferable because a region containing oxygen which is released by heating can be easily formed. The insulator 680 may have a structure in which the above materials are stacked, for example, a stacked structure of silicon oxide formed by a sputtering method and silicon oxynitride formed thereover by a CVD method. do it. In addition, silicon nitride may be stacked further thereon.

Here, the insulator 680 preferably contains excess oxygen. For example, the insulator 680 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate. By providing the insulator 680 including excess oxygen in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced and the reliability of the transistor 600 can be improved. In order to make the insulator 680 contain excess oxygen, for example, the insulator 682 may be formed by a sputtering method in an atmosphere containing oxygen. By forming the insulator 682 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulator 680 while forming the film.

It is preferable that the concentration of impurities such as water or hydrogen in the insulator 680 be reduced. Further, the upper surface of the insulator 680 may be flattened.

The insulator 682 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the insulator 680 from above. Further, the insulator 682 preferably functions as a barrier insulating film which suppresses permeation of oxygen. As the insulator 682, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used. For example, aluminum oxide having a high barrier property against oxygen may be used as the insulator 682.

As shown in FIG. 7B, the insulator 682 has a structure in direct contact with the oxide 630c. With such a structure, diffusion of oxygen contained in the insulator 680 into the conductor 660 can be suppressed. Therefore, oxygen contained in the insulator 680 can be efficiently supplied to the oxide 630a and the oxide 630b through the oxide 630c, so that oxygen vacancies in the oxide 630a and the oxide 630b are reduced. The electrical characteristics and reliability of the transistor 600 can be improved.

Further, an insulator 685 which functions as an interlayer film is preferably provided over the insulator 682. Like the insulator 624 and the like, the insulator 685 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

The conductor 640 is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Further, the conductor 640 may have a stacked structure. Although the conductor 640 is circular in a top view in FIG. 7A, the invention is not limited to this. For example, the conductor 640 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle in which the corners are rounded in a top view.

When the conductor 640 has a stacked structure, it is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. The conductive material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen may be used as a single layer or a stacked layer. By using the conductive material, impurities such as water or hydrogen that diffuse from the insulator 680 or the like can be further reduced from entering the oxide 630 through the conductor 640. In addition, oxygen added to the insulator 680 can be prevented from being absorbed by the conductor 640.

Further, the conductor 646a is arranged in contact with the top surfaces of the conductor 640a and the conductor 640c, and the conductor 646b is arranged in contact with the top surface of the conductor 640b. The conductors 646a and 646b are preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Further, the conductors 646a and 646b may have a stacked structure, for example, a stack of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in the opening provided in the insulator.

An insulator 686 is provided so as to cover the insulator 685, the conductor 646a, and the conductor 646b. The insulator 686 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or oxide. Zirconium or the like may be used, and it can be provided in a laminated or single layer.

For example, the insulator 686 may have a stacked-layer structure of a material having high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material. With this structure, the capacitor 655 has an insulator with a high dielectric constant (high-k), whereby sufficient capacity can be secured, and an insulator with a large dielectric strength improves the dielectric strength, Electrostatic breakdown of the element 655 can be suppressed.

Note that as an insulator of a high dielectric constant (high-k) material (a material having a high relative dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, is used. , An oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. Alternatively, the insulator 686 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr)TiO ₃ (BST). The insulator including the high-k material may be used in a single layer or a stacked layer. For example, in the case of stacking the insulator 686, a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide is sequentially formed, zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are formed. It may be formed in order and a four-layer stack or the like may be used. As the insulator 686, a compound containing hafnium and zirconium may be used. As semiconductor devices become finer and more highly integrated, problems such as leakage current of transistors and capacitors may occur due to thinning of gate insulators and dielectrics used for capacitors. By using a high-k material for the gate insulator and the insulator functioning as a dielectric used for the capacitor, the gate potential during operation of the transistor can be reduced and the capacitance of the capacitor can be secured while maintaining the physical film thickness. It will be possible.

On the other hand, as a material having a high dielectric strength (a material having a low relative dielectric constant), silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen are used. Examples thereof include added silicon oxide, silicon oxide having holes, or resin.

A conductor 656 is arranged so as to overlap with at least part of the conductor 646a with the insulator 686 interposed therebetween. As the conductor 656, a conductor that can be used for the conductor 646 may be used.

Further, an insulator 688 which functions as an interlayer film is preferably provided over the insulator 686 and the conductor 646b. Like the insulator 624 and the like, the insulator 688 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

<<Modification of Memory Cell>>
A modified example of the memory cell will be described below with reference to FIG. FIG. 8A is a top view of the periphery of the memory cell 860. 8B is a cross-sectional view of the memory cell 860, and FIG. 8B corresponds to a portion indicated by dashed-dotted line A1-A2 in FIG. 8A. In FIG. 8B, a cross section in the channel length direction of the transistor 600 and a cross section in the channel width direction of the transistor 700 are shown. Note that in the top view of FIG. 8A, some elements are omitted for clarity of the drawing. Note that the X direction, the Y direction, and the Z direction shown in FIG. 8A are directions orthogonal to or intersecting with each other. Here, it is preferable that the X direction and the Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially vertical to the substrate surface.

The memory cell 860 illustrated in FIG. 8 is different from the memory cell 860 illustrated in FIG. 7 in that a transistor 690 and a transistor 790 are used instead of the transistor 600 and the transistor 700. Here, the transistor 790 is formed in the same layer as the transistor 690 and has a similar structure. In the following, for the components of the transistor 790, the description of the components of the transistor 690 can be referred to.

The transistor 690 has a U-shape so that the oxide 630c extends along the openings formed in the insulator 680, the insulator 672, the insulator 673, the conductor 642 (the conductor 642a and the conductor 642b), and the oxide 630b. The transistor 600 is different from the transistor 600 in that it is formed in a U-shape.

For example, when the channel length of a transistor is miniaturized (typically 5 nm or more and less than 60 nm, preferably 10 nm or more and 30 nm or less), the transistor 600 having the above structure can increase the effective L length. .. As an example, when the distance between the conductor 642a and the conductor 642b is 20 nm, the effective L length is 40 nm or more and 60 nm or less, and the distance between the conductor 642a and the conductor 642b, that is, the minimum processing dimension. It is possible to make the length about 2 times or more and about 3 times or less. Therefore, the memory cell 860 illustrated in FIG. 8 has a structure including the transistor 690, the transistor 790, and the capacitor 655 which are excellent in miniaturization.

<< metal oxide >>
As the oxide 630, a metal oxide which functions as an oxide semiconductor is preferably used. The metal oxide applicable to the oxide 630 according to the present invention will be described below.

The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that gallium, yttrium, tin, and the like are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.

Here, the case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered. Note that the element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium. However, as the element M, it may be acceptable to combine a plurality of the aforementioned elements.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, the metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Structure of metal oxide]
Hereinafter, the configurations of a CAC-OS (Clu-Aligned Composite Oxide Semiconductor) and a CAAC-OS (c-axis Aligned Crystal Oxide Semiconductor) that are metal oxides that can be used for an OS transistor will be described.

The CAC-OS or the CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a function as a semiconductor in the whole material. Note that when CAC-OS or CAC-metal oxide is used for an active layer of a transistor, a conductive function is a function of flowing electrons (or holes) serving as carriers, and an insulating function is an electron serving as carriers. It is a function that does not flow. By causing the conductive function and the insulating function to act in a complementary manner, a switching function (a function of turning on/off) can be imparted to the CAC-OS or the CAC-metal oxide. By separating the respective functions in the CAC-OS or the CAC-metal oxide, both functions can be maximized.

Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed as the periphery is blurred and connected in a cloud shape.

Further, in the CAC-OS or the CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

Moreover, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, the CAC-OS or the CAC-metal oxide is composed of a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In the case of the structure, when the carrier flows, the carrier mainly flows in the component having the narrow gap. Further, the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used in the channel formation region of the transistor, a high current driving force, that is, a high on-current and a high field-effect mobility can be obtained when the transistor is on.

That is, the CAC-OS or the CAC-metal oxide may be referred to as a matrix composite material or a metal matrix composite material.

<Structure of metal oxide>
The oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystal oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide). OS: amorphous-like oxide semiconductor (OS) and amorphous oxide semiconductors.

Further, when attention is paid to the crystal structure, the oxide semiconductor may be classified differently from the above. Here, classification of crystal structures in an oxide semiconductor will be described with reference to FIG. 25A is a diagram illustrating classification of crystal structures of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

As shown in FIG. 25A, IGZO is roughly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Moreover, CAAC (c-axis aligned crystal line), nc (nano crystal line), and CAC (Cloud-Aligned Composite) are contained in Crystalline. Moreover, single crystal and poly crystal are included in Crystal.

The structure in the thick frame shown in FIG. 25(A) is a structure belonging to the New crystalline phase. The structure is in the boundary region between Amorphous and Crystal. That is, it can be said that the energy-unstable Amorphous and Crystalline are completely different structures.

Note that the crystal structure of the film or the substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) image. Here, XRD spectra of quartz glass and IGZO having a crystal structure classified as crystalline (also referred to as crystalline IGZO) are shown in FIGS. 25B and 25C. Further, FIG. 25B is a quartz glass and FIG. 25C is an XRD spectrum of crystalline IGZO. Note that the crystalline IGZO illustrated in FIG. 25C has a composition of In:Ga:Zn=4:2:3 [atomic ratio]. Further, the crystalline IGZO shown in FIG. 25C has a thickness of 500 nm.

As shown by the arrow in FIG. 25B, the peak of the XRD spectrum of the silica glass is almost symmetrical. On the other hand, as shown by the arrow in FIG. 25C, crystalline IGZO has an asymmetric peak in the XRD spectrum. The asymmetric peak in the XRD spectrum is evidence of the presence of crystals. In other words, unless the peak of the XRD spectrum is symmetrical, it cannot be said to be Amorphous.

The CAAC-OS has a crystal structure having c-axis orientation and a plurality of nanocrystals connected in the ab plane direction and having strain. Note that the strain refers to a portion where the orientation of the lattice arrangement is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in the region where a plurality of nanocrystals are connected.

The nanocrystal is basically a hexagon, but is not limited to a regular hexagon, and may be a non-regular hexagon. In addition, the strain may have a lattice arrangement such as a pentagon and a heptagon. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it is understood that the distortion of the lattice arrangement suppresses the formation of crystal grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the bond distance between atoms changes due to substitution with a metal element, or the like. It is thought to be because. A crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. The crystal grain boundaries serve as recombination centers, and carriers are likely to be trapped to cause a decrease in on-state current of the transistor or a decrease in field-effect mobility. Therefore, the CAAC-OS in which clear crystal grain boundaries are not confirmed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming the CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are preferable because they can suppress generation of crystal grain boundaries more than In oxide.

Further, the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M,Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M of the (M,Zn) layer is replaced with indium, it can be expressed as an (In,M,Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can be expressed as an (In,M) layer.

CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, in the CAAC-OS, a clear crystal grain boundary cannot be confirmed; therefore, it can be said that a decrease in electron mobility due to the crystal grain boundary does not easily occur. In addition, the crystallinity of an oxide semiconductor might be lowered due to entry of impurities, generation of defects, or the like; therefore, the CAAC-OS can be referred to as an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the oxide semiconductor including the CAAC-OS has stable physical properties. Therefore, the oxide semiconductor including the CAAC-OS is highly heat resistant and highly reliable. Further, the CAAC-OS is stable even at a high temperature (so-called thermal budget) in the manufacturing process. Therefore, when the CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be increased.

The nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Moreover, in the nc-OS, no regularity is found in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the crystallinity of the a-like OS is lower than that of the nc-OS and the CAAC-OS.

Oxide semiconductors have various structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

<Transistor having oxide semiconductor>
Next, the case where the above oxide semiconductor is used for a transistor is described.

By using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

In addition, an oxide semiconductor having a low carrier concentration is preferably used for the transistor. In the case of reducing the carrier concentration of the oxide semiconductor film, the concentration of impurities in the oxide semiconductor film may be lowered and the density of defect states may be lowered. In this specification and the like, low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and thus has a low density of trap states in some cases.

In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear and may behave like fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density might have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

<Impurity>
Here, the influence of each impurity in the oxide semiconductor will be described.

When the oxide semiconductor contains silicon or carbon which is one of Group 14 elements, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS) are 2) It is set to be not more than ×10 ¹⁸ atoms/cm ³ , preferably not more than 2×10 ¹⁷ atoms/cm ³ .

Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level might be formed and a carrier might be generated. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

Further, in the oxide semiconductor, when nitrogen is contained, electrons which are carriers are generated, carrier concentration is increased, and n-type is easily generated. As a result, a transistor including an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Therefore, in the oxide semiconductor, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 ¹⁹ atoms/cm ^{3 in} SIMS, preferably 5×10 ^18. Atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and further preferably 5×10 ¹⁷ atoms/cm ³ or less.

Further, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, which might cause oxygen deficiency. When hydrogen enters the oxygen vacancies, electrons which are carriers may be generated. Further, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , and more preferably 5×10 ¹⁸ atoms/cm 3. ^{It is} less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced in a channel formation region of a transistor, stable electric characteristics can be given.

<<Other semiconductor materials>>
Semiconductor materials that can be used for the oxide 630 are not limited to the above metal oxides. As the oxide 630, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, a layered substance functioning as a semiconductor (also referred to as an atomic layer substance, a two-dimensional material, or the like) is preferably used as a semiconductor material. In particular, it is preferable to use a layered substance that functions as a semiconductor for the semiconductor material.

Here, in the present specification and the like, the layered substance is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by a covalent bond or an ionic bond are stacked via a bond weaker than the covalent bond or the ionic bond, such as Van der Waals force. The layered material has high electric conductivity in the unit layer, that is, two-dimensional electric conductivity. By using a material which functions as a semiconductor and has high two-dimensional electrical conductivity for the channel formation region, a transistor with high on-state current can be provided.

Layered materials include graphene, silicene, chalcogenides, and the like. A chalcogenide is a compound containing chalcogen. Chalcogen is a general term for elements belonging to Group 16 and includes oxygen, sulfur, selenium, tellurium, polonium, and livermolium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

As the oxide 630, for example, a transition metal chalcogenide which functions as a semiconductor is preferably used. Specific examples of the transition metal chalcogenide applicable as the oxide 630 include molybdenum sulfide (typically MoS ₂ ), molybdenum selenide (typically MoSe ₂ ), molybdenum tellurium (typically MoTe ₂ ). , Tungsten sulfide (typically WS ₂ ), tungsten selenide (typically WSe ₂ ), tungsten tellurium (typically WTe ₂ ), hafnium sulfide (typically HfS ₂ ), hafnium selenide ( representative HFSE ₂₎ the sulfide zirconium (typically _ZrS 2 is), the selenide zirconium (typically ZrSe _2), and the like.

<Configuration example of memory cell layout>
Next, an example of the arrangement of the above-described memory cell 860 will be described with reference to FIGS. 9 and 10. 9 and 10 show a memory cell block in which 2×2×2 memory cells 860 are arranged. FIG. 9 is a top view of the memory cell block. 10 is a cross-sectional view of the memory cell block, and FIG. 10 corresponds to a portion shown by a dashed line B1-B2 in FIG. In FIG. 10, a cross section in the channel length direction of the transistor 600 and a cross section in the channel width direction of the transistor 700 are shown. In the top view of FIG. 9, some elements are omitted for the sake of clarity. The X direction, the Y direction, and the Z direction shown in FIG. 9 are directions orthogonal to or intersecting with each other. Here, it is preferable that the X direction and the Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially vertical to the substrate surface.

In the memory cell block shown in FIGS. 9 and 4, memory cell 860_2 is arranged adjacent to memory cell 860_1 in the X direction. Further, the memory cell 860_1 and the memory cell 860_2 are arranged adjacent to the memory cell 860_1 in the Y direction. Further, the memory cell 860_1 and the memory cell 860_2 are arranged adjacent to each other in the Z direction, and the memory cell 860_5 and the memory cell 860_6 are arranged.

As shown in FIGS. 9 and 10, in the memory cell 860_1 and the memory cell 860_2, respective constituent elements can be arranged in line symmetry. At this time, the side surface of the conductor 640b is preferably in contact with the conductor 642b of the memory cell 860_1 and the conductor 642b of the memory cell 860_2. That is, the conductor 607, the conductor 615, the conductor 640b, the conductor 646b, and the conductor 657 which function as a bit line are formed as one of the source and the drain of the transistor 600 of the memory cell 860_1 and the transistor 600 of the memory cell 860_2. It is preferable to be electrically connected to one of the source and the drain. As described above, by sharing the wirings connected to the memory cells 860_1 and 860_2, the area occupied by the memory cells can be further reduced.

In addition, as illustrated in FIG. 10, the conductor 607, the conductor 615, the conductor 640b, the conductor 646b, and the conductor 657 which function as bit lines are arranged in the upper layer, and the memory cell 860_5 and the memory cell 860_6 are provided. The transistor 600 is also electrically connected. Note that as illustrated in FIG. 10, the conductor 657 of the memory cell 860_1 and the memory cell 860_2 corresponds to the conductor 607 of the memory cell 860_5 and the memory cell 860_6. In this way, the bit line can be extended in the Z direction. Although not shown in the sectional view, the bit line including the conductor 640d and the like can be similarly extended in the Z direction.

Further, as shown in FIG. 9, the conductor 660 of the memory cell 860_1 is provided so as to extend to the memory cell 860_3. In this way, the word line can be extended in the Y direction. Further, as shown in FIG. 9, the conductor 742a of the memory cell 860_1 is provided so as to extend to the memory cell 860_3. In this way, the selection line can be extended in the Y direction. Note that the selection line may be shared by the memory cells 860 adjacent in the X direction. Further, as shown in FIG. 9, the conductor 605 of the memory cell 860_1 is provided so as to extend to the memory cell 860_3. In this way, the wiring can be extended in the Y direction. Further, as illustrated in FIG. 9, the conductor 705 of the memory cell 860_1 is provided so as to extend to the memory cell 860_3. In this way, the wiring can be extended in the Y direction.

Note that although the structure in which the oxide 630c is extended to overlap with the conductor 660 in FIG. 9 is not limited to this, the memory device described in this embodiment is limited to this. For example, the oxide 630c may be patterned for each memory cell 860, and the oxide 630c may be provided separately for each transistor 600. In the case where the oxide 630c has a two-layer stacked structure, for example, either the upper layer or the lower layer of the oxide 630c may be provided separately for each transistor 600.

Note that although an example in which the memory cell includes two transistors, the transistor 600 and the transistor 700, is shown here, the present invention is not limited to this. For example, when the memory cell has one transistor and one capacitor as shown in FIGS. 4 and 5, the transistor 700 in FIG. 11 should not be provided as shown in FIG. You can The structure shown in FIG. 11 can be manufactured by the same manufacturing method as the structure shown in FIG.

<Structure example of storage device>
Next, an example of a memory device in which the above memory cells 860 are stacked will be described with reference to FIG. FIG. 12 is a cross-sectional view of a memory device in which a plurality of memory cell layers 870 including memory cells 860 are stacked over a silicon layer 871. The memory device shown in FIG. 12 corresponds to the semiconductor device 50a shown in FIG. 6, the silicon layer 871 corresponds to the substrate 30, and the memory cell layer 870 corresponds to the functional layer 40a.

First, the silicon layer 871 will be described. A plurality of transistors 800 are provided in the silicon layer 871.

The transistor 800 is provided over the substrate 811, and includes a conductor 816 which functions as a gate, an insulator 815 which functions as a gate insulator, a semiconductor region 813 which is a part of the substrate 811, and a low region which functions as a source region or a drain region. It has a resistance region 814a and a low resistance region 814b. The transistor 800 may be either a p-channel type or an n-channel type.

Here, in the transistor 800 illustrated in FIG. 12, a semiconductor region 813 (a part of the substrate 811) in which a channel is formed has a convex shape. In addition, the conductor 816 is provided so as to cover the side surface and the upper surface of the semiconductor region 813 with the insulator 815 interposed therebetween. Note that the conductor 816 may be formed using a material whose work function is adjusted. Such a transistor 800 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator which functions as a mask for forming the protrusion may be provided in contact with the top of the protrusion. Further, although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI substrate may be processed to form a semiconductor film having a convex shape.

Note that the transistor 800 illustrated in FIGS. 12A and 12B is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

Further, a wiring layer provided with an interlayer film, a wiring, a plug and the like may be provided between each structure. Further, a plurality of wiring layers can be provided according to the design. Here, the conductor having a function as a plug or a wiring may have a plurality of structures collectively given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, part of the conductor may function as a wiring, and part of the conductor may function as a plug.

For example, an insulator 820, an insulator 822, an insulator 824, and an insulator 826 are sequentially stacked over the transistor 800 as interlayer films. Further, in the insulator 820, the insulator 822, the insulator 824, and the insulator 826, a conductor 828 which functions as a plug or a wiring, a conductor 830, and the like are embedded.

Further, the insulator functioning as an interlayer film may function as a flattening film that covers the uneven shape below the insulator. For example, the upper surface of the insulator 822 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method or the like in order to enhance planarity.

A wiring layer may be provided over the insulator 826 and the conductor 830. For example, in FIG. 12, an insulator 850, an insulator 852, and an insulator 854 are sequentially stacked and provided. A conductor 856 is formed over the insulator 850, the insulator 852, and the insulator 854. The conductor 856 functions as a plug or a wiring.

As an insulator that can be used as the interlayer film, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like can be given.

For example, by using a material having a low relative dielectric constant for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material should be selected according to the function of the insulator.

For example, the insulator 820, the insulator 822, the insulator 826, the insulator 852, the insulator 854, and the like preferably include insulators having a low relative dielectric constant. For example, the insulator may include silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having holes, or a resin. preferable. Alternatively, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having holes. And a laminated structure of a resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining with a resin, a laminated structure having thermal stability and a low relative dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like.

In addition, a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 824, the insulator 850, and the like, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used.

Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. The insulator containing lanthanum, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or as a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium. It is possible to use a material containing at least one metal element selected from ruthenium and ruthenium. Alternatively, a semiconductor having high electric conductivity, which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

For example, as the conductor 828, the conductor 830, the conductor 856, and the like, a single layer of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials can be used. Alternatively, they can be stacked and used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

The insulator 611 and the insulator 612 are provided over the silicon layer 871, and the memory cell layers 870_1 to 870_n (n is a natural number of 2 or more) are stacked over the insulator 611 and the insulator 612. .. The value of n is not particularly limited, but is 2 or more and 200 or less, preferably 2 or more and 100 or less, and more preferably 2 or more and 10 or less. For example, 1≦n≦10, preferably 1≦n≦50, and more preferably 1≦n≦100. )

In each memory cell layer 870, memory cells 860 and various wirings are arranged in a matrix, as in FIG. Further, as shown in FIG. 10, the memory cell layers 870 adjacent to each other in the stacking direction are electrically connected by wiring such as bit lines.

Further, as shown in FIG. 12, in the lowermost memory cell layer 870_1, the conductor 607 is arranged so as to be embedded in the insulator 611 and the insulator 612. The conductor 607 is in contact with the conductor 857 provided in the same layer as the conductor 856. In this way, the bit line connected to the memory cell 860 is connected to the read/write circuit through the conductor 857.

Further, the memory cell layers 870_1 to 870_n preferably have a structure in which the insulator 611, the insulator 612, the insulator 687, the insulator 683, and the insulator 684 are sealed. Here, the insulator 611 is provided over the silicon layer 871 and the insulator 612 is provided over the insulator 611. The memory cell layers 870_1 to 870_n are provided over the insulator 612, and the insulator 612 is also formed in the same pattern as the memory cell layers 870_1 to 870_n in a top view. The insulator 687 is provided in contact with the top surface of the insulator 611, the side surface of the insulator 612, and the side surfaces of the memory cell layers 870_1 to 870_n. That is, the insulator 687 is formed in a sidewall shape with respect to the memory cell layers 870_1 to 870_n. The insulator 683 is provided so as to cover the insulator 611, the insulator 687, and the memory cell layers 870_1 to 870_n. Further, an insulator 684 is arranged so as to cover the insulator 683.

As with the insulator 682, the insulator 611, the insulator 612, the insulator 687, the insulator 683, and the insulator 684 are preferably formed using a barrier material.

Here, each memory cell layer 870 is sealed with an insulator 614, an insulator 687, and an insulator 682. The same material is preferably used for the insulator 614, the insulator 687, and the insulator 682. The insulators 614, 687, and 682 are preferably formed under the same conditions. When the insulator 614, the insulator 687, and the insulator 682 having the same film quality are in contact with each other, a sealed structure with high airtightness can be obtained.

Further, for the insulator 614, the insulator 687, and the insulator 682, it is preferable to use a material having a function of capturing and fixing hydrogen. Specifically, a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide can be used.

The insulator 614, the insulator 687, and the insulator 682 which form the sealing structure are provided in contact with the insulator 680. Therefore, by capturing and fixing hydrogen which is mixed in the insulator 680, the hydrogen concentration of the oxide semiconductor included in the memory cell 860 can be reduced.

Further, the insulator 614, the insulator 687, and the insulator 682 which are structures for sealing the memory cell layer 870 are further covered with the insulator 611, the insulator 612, and the insulator 683. For example, as illustrated in FIG. 12, the insulator 611 and the insulator 683 are in contact with each other outside the memory cell layers 870_1 to 870_n, so that a second sealing structure is formed.

Here, for the insulator 611, the insulator 612, and the insulator 683, it is preferable to use a material having a function of suppressing diffusion of hydrogen and oxygen. In particular, since silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, it is preferably used as a sealing material.

Further, an insulator 684 having high coverage is preferably provided above the insulator 683 which covers the transistor 600. Note that the insulator 684 is preferably formed using the same material as the insulator 612 and the insulator 683.

For example, the insulator 612 and the insulator 683 can be formed by a sputtering method, so that the sealing structure can be provided with a film having a relatively low hydrogen concentration in the film.

On the other hand, the film formed by the sputtering method has relatively low coverage. Therefore, by forming the insulator 611 and the insulator 684 by a CVD method or the like having high coverage, the airtightness can be further improved.

Therefore, the insulator 612 and the insulator 683 preferably have lower hydrogen concentration than the insulator 611 and the insulator 684.

As described above, by sealing the memory cell layers 870_1 to 870_n with the barrier insulating film, hydrogen diffused into the oxide semiconductor included in each memory cell 860 can be reduced. Therefore, a highly reliable storage device can be provided.

Note that preferably, the insulator 611, the insulator 612, the insulator 614, the insulator 682, the insulator 687, the insulator 683, and the insulator 684 may be formed using a material having a barrier property against oxygen. Since the sealing structure has a barrier property against oxygen, outflow of excess oxygen in the insulator 680 can be suppressed and the oxygen can be efficiently supplied to the transistor 600.

In addition, the insulator 674 is preferably provided so as to fill the memory cell layers 870_1 to 870_n, the insulator 684, and the like. As the insulator 674, an insulator that can be used for the insulator 680 may be used. As shown in FIG. 12, it is preferable that the heights of the upper surfaces of the insulator 674 and the insulator 684 are substantially the same.

Alternatively, as illustrated in FIG. 12, an opening may be provided in the insulator 674, the insulator 684, the insulator 683, and the insulator 611, and the conductor 876 may be provided in the opening. The lower surface of the conductor 876 is in contact with the conductor 856. A conductor 878 which functions as a wiring may be provided in contact with the top surface of the conductor 876. Further, an insulator 689 which functions as an interlayer film is preferably provided to cover the memory cell layer 870_n, the insulator 674, and the conductor 878. With such a structure, the wiring of the upper layer (the conductor 878) and the circuit of the silicon layer 871 can be electrically connected without the memory cell layer 870.

Note that FIG. 12 illustrates a structure in which the memory cell layers 870_1 to 870_n are collectively sealed with the insulator 611, the insulator 612, the insulator 687, the insulator 683, and the insulator 684. The storage device according to the embodiment is not limited to this. For example, as shown in FIG. 13, each memory cell layer 870 may be sealed with an insulator 611, an insulator 612, an insulator 687, an insulator 683, and an insulator 684. Here, the insulator 612 and the insulator 611 are arranged below the insulator 614.

The insulator 687 is provided in contact with side surfaces of the insulator 680, the insulator 673, the insulator 672, the insulator 624, the insulator 622, the insulator 616, and the insulator 614. An insulator 683 is provided so as to cover the insulator 680 and the insulator 687, and the insulator 684 is provided over the insulator 683. In that case, the capacitor 655 and the insulator 688 which are provided above the insulator 682 may be provided over the insulator 684.

<Method of manufacturing memory cell>
Next, a manufacturing method of the memory cell 860 included in the memory device illustrated in FIG. 7 is described with reference to FIGS. In the following, the description of the components of the transistor 600, the manufacturing method thereof, and the like can be referred to for the components of the transistor 700, the manufacturing method thereof, and the like.

14A to 24B, (A) of each drawing shows a top view of the memory cell 860. Further, (B) in each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2 in (A), and is a cross-sectional view in the channel length direction of the transistor 600 and a channel width direction of the transistor 700. A sectional view is shown. In addition, in the top view of (A) of each drawing, some elements are omitted for clarity of the drawing. Further, the X direction, the Y direction, and the Z direction shown in FIG. 7A are directions orthogonal to or intersecting with each other. Here, it is preferable that the X direction and the Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially vertical to the substrate surface.

First, the insulator 614 is formed. The insulator 614 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or a pulsed laser deposition (PLD) method. (Atomic Layer Deposition) method or the like.

The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, an optical CVD method that uses light, and the like. Further, it can be classified into a metal CVD method and an organometallic CVD method depending on the raw material gas used. Further, depending on the pressure at the time of film formation, atmospheric pressure CVD (APCVD: Atmospheric Pressure CVD) method for forming a film under atmospheric pressure, and low pressure CVD (LPCVD: Low Pressure CVD) method for forming a film under a reduced pressure lower than atmospheric pressure. , Can be divided into

The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, the thermal CVD method is a film forming method which can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in a semiconductor device might be charged up by receiving electric charge from plasma. At this time, the accumulated charges may damage wirings, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, plasma damage does not occur during film formation, so that a film with few defects can be obtained.

Further, as the ALD method, a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactant is performed only with thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant, and the like can be used.

The ALD method utilizes the self-controllability that is the property of atoms, and it is possible to deposit atoms one by one, so it is possible to form extremely thin films, to form films with a high aspect ratio, pinholes, etc. It is possible to form a film with few defects, to form a film with excellent coverage, and to form a film at a low temperature. In the PEALD method, the use of plasma may be preferable because it enables film formation at a lower temperature. Note that some precursors used in the ALD method include impurities such as carbon. Therefore, the film formed by the ALD method may contain a large amount of impurities such as carbon as compared with the film formed by another film formation method. Note that the amount of impurities can be quantified by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, the film forming method is not easily affected by the shape of the object to be processed and has good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for coating the surface of the opening having a high aspect ratio. However, since the ALD method has a relatively low film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gas. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the raw material gas while forming the film. When film formation is performed while changing the flow rate of the source gas, the time required for transfer and pressure adjustment is shorter than the case where film formation is performed using multiple film formation chambers. can do. Therefore, it may be possible to improve the productivity of the semiconductor device.

In this embodiment, as the insulator 614, aluminum oxide is deposited by a sputtering method.

Although the transistor 600 is formed over the insulator 614 in a subsequent step, a film in the vicinity of the transistor 600 preferably has relatively low hydrogen concentration, and a film having relatively high hydrogen concentration is remote from the transistor 600. It is preferable to arrange them.

Next, an opening is formed in the insulator 614 and the conductor 607 is formed so as to be embedded in the opening. Regarding the formation of the conductor 607, the method for forming the conductor 605 described later can be referred to. Although not illustrated, a conductor which overlaps with the conductor 715 can be formed in parallel with the conductor 607 in a later step.

Next, the insulator 616 is formed over the insulator 614 and the conductor 607. The insulator 616 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 616. In addition, the insulator 616 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 616 can be reduced.

Next, an opening reaching the insulator 614 is formed in the insulator 616. The openings include, for example, grooves and slits. In addition, the area where the opening is formed may be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. Further, as the insulator 614, it is preferable to select an insulator which functions as an etching stopper film when the insulator 616 is etched to form a groove. For example, when a silicon oxide film or a silicon oxynitride film is used for the insulator 616 which forms the groove, the insulator 614 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

After forming the opening, a conductive film to be the conductor 605a is formed. The conductive film preferably contains a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum tungsten alloy can be used. The conductive film to be the conductor 605a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, the conductive film to be the conductor 605a has a multilayer structure. First, tantalum nitride is formed into a film by a sputtering method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride in the lower layer of the conductor 605b, even if a metal such as copper that easily diffuses is used as a conductive film to be the conductor 605b described later, the metal diffuses out of the conductor 605a. Can be prevented.

Next, a conductive film to be the conductor 605b is formed. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a low-resistance conductive material such as copper is formed as the conductive film to be the conductor 605b.

Next, CMP treatment (Chemical Mechanical Polishing) is performed to remove a part of the conductive film to be the conductor 605a and the conductive film to be the conductor 605b, so that the insulator 616 is exposed. As a result, the conductors 605a and 605b remain only in the openings. Accordingly, the conductor 605 whose top surface is flat can be formed. Note that part of the insulator 616 may be removed by the CMP treatment (see FIG. 14).

Here, the conductor 615, the conductor 705, and the conductor 715 can be formed in parallel with the conductor 605. As shown in FIG. 14A, the conductor 605 and the conductor 705 may be formed to extend in the Y direction. The conductor 615 is formed so as to overlap with at least part of the conductor 607. Although not shown, the conductor 715 is formed similarly to the conductor 615.

Although the conductor 605 is formed so as to be embedded in the opening of the insulator 616 in the above, the present embodiment is not limited to this. For example, the conductor 605 is formed over the insulator 614, the insulator 616 is formed over the conductor 605, and the insulator 616 is subjected to CMP treatment, whereby part of the insulator 616 is removed and the conductor 605 is removed. The surface of 605 may be exposed.

Next, the insulator 622 is formed over the insulator 616, the conductor 605, the conductor 615, the conductor 705, and the conductor 715. The insulator 622 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

As the insulator 622, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. As the insulator containing one or both oxides of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. An insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 622 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 600 are prevented from diffusing into the transistor 600 through the insulator 622. The generation of oxygen vacancies in the oxide 630 can be suppressed.

Next, the insulator 624 is formed over the insulator 622. The insulator 624 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 624. Further, the insulator 624 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 624 can be reduced. Since the insulator 624 becomes the insulator 624 which is in contact with the oxide 630a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250 °C to 650 °C inclusive, preferably 300 °C to 500 °C inclusive, and more preferably 320 °C to 450 °C inclusive. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere and then in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to supplement desorbed oxygen. Good.

In this embodiment mode, after a treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400° C. for 1 hour is continuously performed in an oxygen atmosphere. By the heat treatment, impurities such as water and hydrogen contained in the insulator 624 can be removed.

The heat treatment may be performed after the insulator 622 is formed. The heat treatment conditions described above can be used for the heat treatment.

Here, in order to form an excess oxygen region in the insulator 624, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves, for example. Alternatively, a power source for applying a high frequency wave such as RF may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently introduced into the insulator 624. it can. Alternatively, plasma treatment containing an inert gas may be performed using this apparatus, and then plasma treatment containing oxygen may be performed to supplement desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 624 can be removed by appropriately selecting the conditions of the plasma treatment. In that case, heat treatment may not be performed.

Here, aluminum oxide may be formed over the insulator 624 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 624. By performing the CMP, the surface of the insulator 624 can be planarized and the surface of the insulator 624 can be smoothed. By arranging the aluminum oxide on the insulator 624 and performing CMP, the end point of CMP can be easily detected. Further, although part of the insulator 624 is polished by CMP and the thickness of the insulator 624 may be reduced, the thickness may be adjusted when the insulator 624 is formed. By planarizing and smoothing the surface of the insulator 624, deterioration in coverage of an oxide film to be formed later can be prevented in some cases and reduction in yield of semiconductor devices can be prevented. In addition, oxygen can be added to the insulator 624 by depositing aluminum oxide over the insulator 624 by a sputtering method, which is preferable.

Next, an oxide film 630A and an oxide film 630B are sequentially formed over the insulator 624 (see FIG. 14). The oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without exposing it to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 630A and the oxide film 630B, and the vicinity of the interface between the oxide film 630A and the oxide film 630B can be prevented. Can be kept clean.

The oxide film 630A and the oxide film 630B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 630A and the oxide film 630B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. When the above oxide film is formed by the sputtering method, the above In-M-Zn oxide target can be used.

In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 624 when the oxide film 630A is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 630A may be 70% or higher, preferably 80% or higher, more preferably 100%.

In the case where the oxide film 630B is formed by a sputtering method, when the proportion of oxygen contained in the sputtering gas is 1% to 30% inclusive, preferably 5% to 20% inclusive, an oxygen-deficient oxide semiconductor is obtained. It is formed. A transistor including an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by forming the film while heating the substrate. However, one embodiment of the present invention is not limited to this. In the case where the oxide film 630B is formed by a sputtering method, if the proportion of oxygen contained in the sputtering gas is greater than 30% and 100% or less, preferably 70% or more and 100% or less, the oxygen-excess oxide semiconductor is formed. Is formed. A transistor including an oxygen-excess oxide semiconductor in a channel formation region has relatively high reliability.

In this embodiment, as the oxide film 630A, In:Ga:Zn=1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]) or 1:3 by a sputtering method. : 4 [atomic ratio] is used to form a film. Further, the oxide film 630B is formed by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] or 1:1:1 [atomic ratio]. Note that each oxide film may be formed in accordance with characteristics required for the oxide 630 by appropriately selecting film formation conditions and atomic ratio.

Next, heat treatment may be performed. For the heat treatment, the heat treatment conditions described above can be used. By the heat treatment, impurities such as water and hydrogen in the oxide films 630A and 630B can be removed. In this embodiment mode, after a treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400° C. for 1 hour is continuously performed in an oxygen atmosphere.

Next, an oxide film 643A is formed over the oxide film 630B (see FIG. 14). The oxide film 643A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 643A preferably has an atomic ratio of Ga to In larger than that of Ga in the oxide film 630B. In this embodiment, the oxide film 643A is formed by a sputtering method using a target of In:Ga:Zn=1:3:4 [atomic ratio].

Next, a conductive film 642A is formed over the oxide film 643A (see FIG. 14). The conductive film 642A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the oxide film 630A, the oxide film 630B, the oxide film 643A, and the conductive film 642A are processed into an island shape by a lithography method to form the oxide 630a, the oxide 630b, the oxide layer 643B, and the conductor layer. 642B is formed (see FIG. 15). Here, the oxide 630a, the oxide 630b, the oxide layer 643B, and the conductor layer 642B are formed so that at least part of them overlaps with the conductor 605. In addition, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing. Note that in this step, the thickness of a region of the insulator 624 which does not overlap with the oxide 630a may be thin.

Further, at the same time as the formation of the oxide 630a, the oxide 630b, the oxide layer 643B, and the conductor layer 642B, the oxide 730a, the oxide 730b, the oxide layer 743B, and the conductor layer 742B are formed (see FIG. 15). ). Here, the oxide 730a, the oxide 730b, the oxide layer 743B, and the conductor layer 742B are formed so that at least part of them overlaps with the conductor 705. Further, as shown in FIG. 15A, part of the conductor layer 742B may be formed to extend in the Y direction.

In the lithography method, first, the resist is exposed through a mask. Next, the exposed region is removed or left with a developing solution to form a resist mask. Next, the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, an electron beam or an ion beam may be used instead of the above-mentioned light. If an electron beam or an ion beam is used, no mask is needed. Note that the resist mask can be removed by performing dry etching treatment such as ashing, performing wet etching treatment, performing wet etching treatment after dry etching treatment, or performing dry etching treatment after wet etching treatment.

A hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film serving as a hard mask material is formed over the conductive film 642A, a resist mask is formed thereover, and the hard mask material is etched to form a hard mask having a desired shape. can do. Etching of the conductive film 642A or the like may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. After etching the conductive film 642A or the like, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.

As the dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having the parallel plate type electrodes may have a configuration in which a high frequency power source is applied to one of the parallel plate type electrodes. Alternatively, a plurality of different high frequency power supplies may be applied to one of the parallel plate electrodes. Alternatively, a high frequency power source having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a configuration may be adopted in which high frequency power supplies having different frequencies are applied to the parallel plate electrodes. Alternatively, a dry etching device having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

Further, the side surfaces of the oxide 630a, the oxide 630b, the oxide layer 643B, and the conductor layer 642B are preferably substantially perpendicular to the top surface of the insulator 622. Since the side surfaces of the oxide 630a, the oxide 630b, the oxide layer 643B, and the conductor layer 642B are substantially perpendicular to the top surface of the insulator 622, the area of the transistor 600 can be reduced when the plurality of transistors 600 are provided. Higher density is possible. However, the invention is not limited to this, and the angle formed between the side surfaces of the oxide 630a, the oxide 630b, the oxide layer 643B, and the conductor layer 642B and the top surface of the insulator 622 may be a low angle. Note that the side surfaces of the oxide 730a, the oxide 730b, the oxide layer 743B, and the conductor layer 742B are processed similarly to the side surfaces of the oxide 630a, the oxide 630b, the oxide layer 643B, and the conductor layer 642B. ..

Next, the insulator 672 is formed over the insulator 624, the oxide 630a, the oxide 630b, the oxide layer 643B, the conductor layer 642B, the oxide 730a, the oxide 730b, the oxide layer 743B, and the conductor layer 742B. A film is formed (see FIG. 16). The insulator 672 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the insulator 672, aluminum oxide is formed by a sputtering method. Oxygen can be injected into the insulator 624 by forming aluminum oxide by a sputtering method.

Next, the insulator 673 is formed over the insulator 672. The insulator 673 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is formed as the insulator 673 by a sputtering method (see FIG. 16).

Next, an insulating film to be the insulator 680 is formed. The insulating film to be the insulator 680 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulator 680, a silicon oxide film may be formed by a sputtering method and a silicon oxide film may be formed thereover by a PEALD method or a thermal ALD method. Further, the insulating film to be the insulator 680 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 680 can be reduced.

Next, the insulator 680 is subjected to CMP treatment to form the insulator 680 whose top surface is flat (see FIG. 17). Note that similarly to the insulator 624, aluminum oxide may be formed over the insulator 680 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 680.

Next, part of the insulator 680, part of the insulator 673, part of the insulator 672, part of the conductor layer 642B, and part of the oxide layer 643B are processed to reach the oxide 630b. An opening is formed (see FIG. 18). The opening is preferably formed so as to overlap with the conductor 605. The conductor 642a, the conductor 642b, the oxide 643a, and the oxide 643b are formed by forming the opening. As shown in FIG. 19, the opening may be formed to extend in the Y direction so that the conductor 660 can be formed to extend in the Y direction in a step described later.

At the same time, another part of the insulator 680, another part of the insulator 673, another part of the insulator 672, a part of the conductor layer 742B, and a part of the oxide layer 743B are processed. Forming an opening reaching the oxide 730b (see FIG. 18). The opening is preferably formed so as to overlap with the conductor 705. By forming the opening, the conductor 742a, the conductor 742b, the oxide 743a, and the oxide 743b are formed.

The etching of part of the insulator 680, part of the insulator 673, part of the insulator 672, part of the oxide layer 643B, and part of the conductor layer 642B is performed by a dry etching method or a wet etching method. Can be used. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions. For example, part of the insulator 680 is processed by dry etching, part of the insulator 673 is processed by wet etching, the insulator 672 is processed by dry etching, and the oxide layer 643B and the conductor layer are processed. A part of 642B may be processed by a dry etching method. Note that the above processing is the same for the conductor layer 742B and the oxide layer 743B.

Impurities resulting from the etching gas or the like may be attached or diffused to the surface or inside of the oxide 630a, the oxide 630b, the oxide 730a, and the oxide 730b by performing the above-described treatment such as dry etching. .. Examples of impurities include fluorine and chlorine.

Cleaning is performed to remove the above impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in appropriate combination.

As the wet cleaning, cleaning treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.

The thickness of a region of the oxide 630b which does not overlap with the oxide 643a and the oxide 643b overlaps with the oxide 643a and the oxide 643b by a process such as dry etching or the above-described cleaning treatment. It may be thinner than the film thickness of the region (see FIG. 18). Similarly, the oxide 743a of the oxide 730b and a region of the oxide 730b which does not overlap with the oxide 743b may have a smaller thickness than the oxide 743a and a region of the oxide 730b which overlaps with the oxide 743b. ..

A heat treatment may be performed after the etching or the cleaning. The heat treatment may be performed at 100 °C to 450 °C inclusive, more preferably 350 °C to 400 °C inclusive, for example. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas in an amount of 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide 630a, the oxide 630b, the oxide 730a, and the oxide 730b to reduce oxygen vacancy V _O. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment is performed in an oxygen atmosphere, the heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the air.

Next, an oxide film 630C is formed (see FIG. 19). A heat treatment may be performed before the oxide film 630C is formed, and the heat treatment is preferably performed under reduced pressure and the oxide film 630C is continuously formed without being exposed to the air. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surfaces of the oxide 630b and the oxide 730b are removed, and further, the oxide 630a, the oxide 630b, the oxide 730a, and the oxide 730b are removed. The water concentration and hydrogen concentration can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower, and more preferably 150° C. or higher and 350° C. or lower. In this embodiment mode, heat treatment is performed at a temperature of 200° C. under reduced pressure.

Here, the oxide film 630C includes at least part of the upper surface of the oxide 630b, part of the side surface of the oxide 643, part of the side surface of the conductor 642, part of the upper surface of the oxide 730b, and side surface of the oxide 743. Is preferably provided so as to be in contact with part of the side surface of the conductor 742, part of the side surface of the insulator 672, part of the side surface of the insulator 673, and part of the side surface of the insulator 680. Since the conductor 642 is surrounded by the oxide 643, the insulator 672, the insulator 673, and the oxide film 630C, reduction in conductivity due to oxidation of the conductor 642 in subsequent steps can be suppressed. Similarly, the conductor 742 is also surrounded by the oxide 743, the insulator 672, the insulator 673, and the oxide film 630C, so that a decrease in conductivity due to oxidation of the conductor 742 can be suppressed in subsequent steps. it can.

The oxide film 630C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the oxide film 630C, the atomic ratio of Ga to In is preferably higher than the atomic ratio of Ga to In of the oxide film 630B. In this embodiment, the oxide film 630C is formed by a sputtering method using a target of In:Ga:Zn=1:3:4 [atomic ratio]. Note that as the oxide film 630C, a film in which the atomic ratio of In to Ga is higher than that of In in the oxide film 630B to Ga may be used. In this case, as the oxide film 630C, a target of In:Ga:Zn=5:1:3 [atomic ratio] or In:Ga:Zn=10:1:3 [atomic ratio] is used by a sputtering method. A film may be formed.

Note that the oxide film 630C may be a stacked layer. For example, a film is formed by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio], and In:Ga:Zn=1:3:4 [atoms] are continuously formed. A film ratio may be used for the target formation.

At the time of forming the oxide film 630C, part of oxygen contained in the sputtering gas may be supplied to the oxide 730a, the oxide 730b, the oxide 630a, and the oxide 630b. Alternatively, part of oxygen contained in the sputtering gas may be supplied to the insulator 680 when the oxide film 630C is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 630C may be 70% or higher, preferably 80% or higher, more preferably 100%.

Next, heat treatment may be performed. Further, the heat treatment may be performed under reduced pressure, and the insulating film 650A may be continuously formed without being exposed to the air. By performing the heat treatment, moisture and hydrogen adsorbed on the surface of the oxide film 630C or the like is removed, and the oxide 630a, the oxide 630b, the oxide 730a, the oxide 730b, and the oxide film 630C are removed. It is possible to reduce the water concentration and the hydrogen concentration of. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment mode, the temperature of the heat treatment is 200° C.

Next, an insulating film 650A is formed on the oxide film 630C (see FIG. 19). The insulating film 650A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In addition, the insulating film 650A is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulating film 650A can be reduced. Since the insulating film 650A serves as the insulator 650 which is in contact with the oxide 630c and the insulator 750 which is in contact with the oxide 730c in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

Next, microwaves or high frequencies such as RF may be applied. Irradiated microwaves or high frequencies such as RF penetrate into the insulator 680, the oxide 630b, the oxide 630a, the oxide 730b, and the oxide 730a, and remove hydrogen in these. In particular, in the oxide 630a, the oxide 630b, the oxide 730b, and the oxide 730a, a reaction in which a VoH bond is broken occurs and dehydrogenation occurs. Part of the hydrogen generated at this time may be removed from the oxide 630, the oxide 730, and the insulator 680. Further, part of hydrogen may be gettered to the conductor 642 or the conductor 742 in some cases. Thus, by irradiation with microwaves or high frequencies such as RF, the hydrogen concentration in the insulator 680, the oxide 630b, the oxide 630a, the oxide 730b, and the oxide 730a can be reduced.

Alternatively, oxygen radicals may be formed by converting oxygen gas into plasma by microwaves or high frequencies such as RF. That is, plasma treatment may be performed in an atmosphere in which the insulator 680, the oxide 630b, the oxide 630a, the oxide 730b, and the oxide 730a contain oxygen. Hereinafter, such a process may be referred to as an oxygen plasma process. The formed oxygen radicals can supply oxygen to the insulator 680, the oxide 630b, the oxide 630a, the oxide 730b, and the oxide 730a. In the case where plasma treatment is performed on the insulator 680, the oxide 630b, the oxide 630a, the oxide 730b, and the oxide 730a in an atmosphere containing oxygen, the oxide 630 and the oxide 730 are irradiated with microwaves or high-frequency waves such as RF. The structure may be such that is difficult to be irradiated with.

For the oxygen plasma treatment, it is preferable to use a microwave treatment apparatus having a power source for generating high-density plasma using microwaves, for example. Further, the microwave processing apparatus may have a power source for applying RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated. By applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the insulator 680, the oxide 630, and the oxide 730. The oxygen plasma treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, still more preferably 400 Pa or higher. The oxygen flow rate ratio (O ₂ /O ₂ +Ar) is 50% or less, preferably 10% or more and 30% or less. Further, the processing temperature may be about 400° C., for example. Further, after the oxygen plasma treatment is performed, the heat treatment may be continuously performed without being exposed to the outside air.

Next, the conductive film 660A (the conductive film 660Aa and the conductive film 660Ab) is formed (see FIG. 20). The conductive film 660Aa and the conductive film 660Ab can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use the CVD method. In this embodiment mode, the conductive film 660Aa is formed by an ALD method and the conductive film 660Ab is formed by a CVD method.

Next, the oxide film 630C, the insulating film 650A, the conductive film 660Aa, and the conductive film 660Ab are polished by CMP treatment until the insulator 680 is exposed, so that the oxide 630c, the insulator 650, and the conductor 660 (the conductor 660a Then, the conductor 660b), the oxide 730c, the insulator 750, and the conductor 760 (the conductor 660a and the conductor 660b) are formed (see FIG. 21). In this manner, the transistor 600 and the transistor 700 can be formed in the same step. Thus, the manufacturing process of the memory device according to this embodiment can be shortened and productivity can be improved.

Next, heat treatment may be performed. In this embodiment mode, the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere. By the heat treatment, moisture concentration and hydrogen concentration in the insulator 650, the insulator 750, and the insulator 680 can be reduced. Note that after the above heat treatment, the insulator 682 may be continuously formed without being exposed to the air.

Next, the insulator 682 is formed over the conductor 660, the oxide 630c, the insulator 650, the conductor 760, the oxide 730c, the insulator 750, and the insulator 680 (see FIG. 22). ). The insulator 682 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 682, for example, aluminum oxide is preferably formed by a sputtering method. By forming the insulator 682 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulator 680 while forming the film. At this time, it is preferable to form the insulator 682 while heating the substrate. By forming the insulator 682 in contact with the top surfaces of the conductor 660 and the conductor 760, oxygen contained in the insulator 680 is absorbed by the conductor 660 and the conductor 760 in the heat treatment performed later. Is preferable because it can be suppressed.

Next, heat treatment may be performed. In this embodiment mode, the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere. By the heat treatment, oxygen added by forming the insulator 682 can be diffused into the insulator 680 and further supplied to the oxide 630a and the oxide 630b through the oxide 630c. In this manner, by performing oxygenation treatment on the oxide 630, oxygen vacancies in the oxide 630 (oxide 630b) are repaired by oxygen.

Further, hydrogen remaining in the oxide 630 may diffuse to the insulator 682 through the insulator 680 and be captured or fixed to the insulator 682. That is, it is possible to suppress hydrogen that remained in the oxide 630 that recombine V _{O H} is formed by oxygen vacancies. Note that the heat treatment is not limited to after the insulator 682 is formed, and may be performed in a later step.

Next, the insulator 685 is formed over the insulator 682 (see FIG. 23). The insulator 685 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, for the insulator 622, the insulator 624, the insulator 672, the insulator 673, the insulator 680, the insulator 682, and the insulator 685, and for the conductor 642a, the conductor 615, the conductor 760, and the conductor 715. An opening is formed (see FIG. 23). The opening may be formed by using a lithography method. Note that although the shape of the opening is circular in a top view in FIG. 23A, the shape is not limited to this. For example, the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners in a top view.

Alternatively, as illustrated in FIG. 23A, the opening reaching the conductor 615 may be formed by removing part of the oxide 630a, the oxide 630b, the oxide 643b, and the conductor 642b. Similarly, the opening reaching the conductor 715 may be formed by removing part of the oxide 730a, the oxide 730b, the oxide 743b, and the conductor 742b.

Next, a conductive film to be the conductors 640a to 640d is formed. The conductive films to be the conductors 640a to 640d preferably have a stacked-layer structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen. For example, a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used. The conductive films to be the conductors 640a to 640d can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Next, by CMP treatment, part of the conductive film to be the conductors 640a to 640d is removed and the upper surface of the insulator 685 is exposed. As a result, the conductors 640a to 640d whose top surfaces are flat can be formed by leaving the conductive film only in the openings (see FIG. 23). Note that part of the upper surface of the insulator 685 may be removed by the CMP treatment.

Next, a conductive film to be the conductor 646a and the conductor 646b is formed. The conductive films to be the conductors 646a and 646b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive films to be the conductors 646a and 646b are processed by a lithography method to form the conductors 646a in contact with the top surfaces of the conductors 640a and 640c and the conductor 646b in contact with the top surfaces of the conductors 640b. (See Figure 24). At this time, part of the insulator 685 in a region where the conductor 646a and the conductor 646b do not overlap with the insulator 685 may be removed. Here, although not shown, a conductor having a structure similar to that of the conductor 646b and in contact with the top surface of the conductor 640d is also formed.

Next, the insulator 686 is formed over the conductor 646 and the insulator 684 (see FIG. 24). The insulator 686 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 686 preferably covers at least the conductor 646a.

Next, a conductive film to be the conductor 656 is formed over the insulator 686. The conductive film to be the conductor 656 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film to be the conductor 656 is processed by a lithography method to form the conductor 656 which overlaps with at least part of the conductor 646a (see FIG. 24). In this way, the capacitor 655 can be formed.

Next, the insulator 688 is formed over the conductor 656 and the insulator 686 (see FIG. 7). The insulator 688 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulator 688, silicon oxynitride may be formed by a CVD method, for example.

Next, an opening reaching the conductor 646b is formed in the insulator 686 and the insulator 688, and a conductor 657 is formed so as to be embedded in the opening (see FIG. 7). The conductor 657 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As shown in FIG. 7, the conductor 607, the conductor 615, the conductor 640b, the conductor 646b, and the conductor 657 function as wirings extending in the z direction. In addition, at the same time as the conductor 657, a conductor electrically connected to the conductor 640d is formed. It functions as a wiring including the conductor, the conductor 715, the conductor 640d, and the like and extending in the z direction.

Through the above steps, the semiconductor device including the transistor 600, the transistor 700, and the capacitor 655 illustrated in FIG. 7 can be manufactured. As shown in FIGS. 14 to 24, by using the method for manufacturing a memory cell described in this embodiment, a memory cell 860 and a memory device in which a plurality of memory cells 860 are stacked can be manufactured.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 3)
In this embodiment, a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied with reference to FIGS. A storage device (hereinafter, sometimes referred to as an OS memory device) that is installed will be described. An OS memory device is a storage device including at least a capacitor and an OS transistor that controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

<Structure example of storage device>
FIG. 26A shows an example of the structure of the OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 has, for example, a column decoder, a precharge circuit, a sense amplifier, a writing circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the wiring is a wiring connected to a memory cell included in the memory cell array 1470 and will be described later in detail. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 has a row decoder, a word line driver circuit, and the like, for example, and can select a row to be accessed.

A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are externally supplied to the memory device 1400 as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the memory device 1400. The address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.

The control logic circuit 1460 processes an external input signal (CE, WE, RE) to generate a control signal for the row decoder and the column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as necessary.

The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the structure of the memory cells MC, the number of memory cells MC in one column, and the like. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in one row, and the like.

Note that although FIG. 26A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed in the same plane, this embodiment is not limited to this. For example, as shown in FIG. 26B, a memory cell array 1470 may be provided so as to overlap part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.

FIG. 27 shows a configuration example of a memory cell applicable to the above memory cell MC.

[DOSRAM]
27A to 27C each show a circuit configuration example of a DRAM memory cell. In this specification and the like, a DRAM including a 1-OS transistor 1-capacitive element memory cell may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 1471 illustrated in FIG. 27A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a front gate) and a back gate.

The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected. Are connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.

The wiring BIL functions as a bit line and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable to apply a low-level potential to the wiring CAL at the time of writing and reading data. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, in the memory cell MC, like the memory cell 1472 illustrated in FIG. 27B, the back gate of the transistor M1 may be connected to the wiring WOL instead of the wiring BGL. Alternatively, for example, the memory cell MC may be a memory cell including a transistor having a single-gate structure, that is, a transistor M1 having no back gate, like the memory cell 1473 illustrated in FIG.

By using an OS transistor as the transistor M1, the leak current of the transistor M1 can be made extremely low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-level data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

Further, in the DOSRAM, if the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced and the storage capacity of the memory cell can be reduced.

Here, FIG. 28A illustrates an example of a memory device 1400 in which a memory cell array 1470 is provided over the peripheral circuit 1411 and a plurality of memory cells 1471 is provided in the memory cell array 1470.

In the memory cell array 1470, the plurality of memory cells 1471 are arranged in matrix, and the wiring WOL, the wiring BGL, and the like are also extended in the row direction or the column direction in the memory cell array 1470. The wiring BIL is connected to a column circuit 1430 provided in the peripheral circuit 1411, and the memory cell array 1470 is electrically connected to a sense amplifier or the like through the wiring BIL.

The memory cell array 1470 includes an OS transistor, and as shown in FIG. 27, the upper surface, the side surface, and the lower surface of the memory cell array 1470 are preferably sealed with a plurality of insulators.

Alternatively, as illustrated in FIG. 28B, a structure in which a plurality of memory cell arrays 1470_1 to 1470_n are stacked may be employed. The structure of each memory cell array 1470 is almost the same as the structure shown in FIG. 27A, but the column circuit 1430 and the memory cell 1471 of each memory cell array 1470 are connected by the wiring BIL. Further, the wiring BIL may be formed by penetrating the memory cell arrays 1470_1 to 1470_n with a plurality of or a single conductor as illustrated in FIG.

[NOSRAM]
27D to 27H each show a circuit configuration example of a gain cell type memory cell having two transistors and one capacitor. A memory cell 1474 illustrated in FIG. 27D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a front gate (may be simply referred to as a gate) and a back gate. In this specification and the like, a memory device including a gain cell type memory cell in which an OS transistor is used as the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

A first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2. Are connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable to apply a low-level potential to the wiring CAL during data writing, during data retention, and during data reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

The memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, in the memory cell MC, like the memory cell 1475 illustrated in FIG. 27E, the back gate of the transistor M2 may be connected to the wiring WOL instead of the wiring BGL. Alternatively, for example, the memory cell MC may be a memory cell including a transistor having a single-gate structure, that is, a transistor M2 having no back gate, like the memory cell 1476 illustrated in FIG. Alternatively, for example, the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL as in the memory cell 1477 illustrated in FIG.

By using an OS transistor as the transistor M2, the leak current of the transistor M2 can be made extremely low. Thus, the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-level data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

Note that the transistor M3 may be a transistor including silicon in a channel formation region (hereinafter, also referred to as Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a read transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be stacked over the transistor M3, so that the area occupied by the memory cell can be reduced and the memory device can be highly integrated.

Further, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.

In addition, FIG. 27H illustrates an example of a gain cell type memory cell including three transistors and one capacitor. A memory cell 1478 illustrated in FIG. 27H includes transistors M4 to M6 and a capacitor CC. The capacitive element CC is provided as appropriate. The memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring which gives a low-level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.

The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.

The transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-type transistors.

By using an OS transistor as the transistor M4, the leak current of the transistor M4 can be made extremely low.

Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to the above. The arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 4)
In this embodiment mode, an example of a chip 1200 in which a semiconductor device of the present invention is mounted is shown with reference to FIGS. A plurality of circuits (systems) are mounted on the chip 1200. The technique of integrating a plurality of circuits (systems) on one chip in this way may be referred to as a system on chip (SoC).

As shown in FIG. 29A, a chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more. Interface 1215, one or more network circuits 1216, and the like.

Bumps (not shown) are provided on the chip 1200, and are connected to a first surface of a printed circuit board (Printed Circuit Board: PCB) 1201 as shown in FIG. 29B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the mother board 1203.

The motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in any of the above embodiments can be used as the DRAM 1221. Further, for example, the NOSRAM described in the above embodiment can be used as the flash memory 1222.

The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. As the memory, the above-mentioned NOSRAM or DOSRAM can be used. Further, the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention or a product-sum operation circuit, image processing and product-sum operation can be performed with low power consumption.

Since the CPU 1211 and the GPU 1212 are provided in the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories included in the CPU 1211 and the GPU 1212, Further, after the calculation in the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.

The analog calculation unit 1213 includes one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog-calculation unit 1213 may be provided with the product-sum calculation circuit.

The memory controller 1214 has a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.

The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used.

The network circuit 1216 has a network circuit such as a LAN (Local Area Network). In addition, a circuit for network security may be included.

The above circuit (system) can be formed in the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

The PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be called a GPU module 1204.

Since the GPU module 1204 has the chip 1200 using the SoC technology, its size can be reduced. Moreover, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, portable (carry-out) game machines, and the like. In addition, a product-sum operation circuit using the GPU 1212 allows deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), self-encoders, deep Boltzmann machines (DBM), deep belief networks ( Since it is possible to execute operations such as DBN), the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.

Generally, in a semiconductor device such as a computer, various storage devices (memory) are used according to the application. FIG. 30 shows various storage devices layer by layer. A storage device located in the upper layer is required to have a high access speed, and a storage device located in the lower layer is required to have a large storage capacity and a high recording density. In FIG. 30, a memory, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a 3D NAND memory, which are mixedly mounted as a register in an arithmetic processing device such as a CPU, are shown in order from the top layer.

A memory that is mixedly mounted as a register in an arithmetic processing device such as a CPU is used for temporary storage of arithmetic results, and thus is frequently accessed from the arithmetic processing device. Therefore, an operation speed faster than the storage capacity is required. The register also has a function of holding setting information of the arithmetic processing unit.

The SRAM is used for a cache, for example. The cache has a function of copying a part of the information held in the main memory and holding it. By copying frequently used data in the cache, the access speed to the data can be increased.

The DRAM is used as, for example, a main memory. The main memory has a function of holding a program or data read from the storage. The recording density of DRAM is about 0.1 to 0.3 Gbit/mm ² .

The 3D NAND memory is used for storage, for example. The storage has a function of holding data that needs to be stored for a long time, various programs used in the arithmetic processing device, and the like. Therefore, the storage is required to have a storage capacity larger than the operating speed and a high recording density. The storage density of the storage device used for storage is approximately 0.6 to 6.0 Gbit/mm ² .

The storage device of one embodiment of the present invention has high operation speed and can hold data for a long time. The storage device of one embodiment of the present invention can be preferably used as a storage device located in a boundary area 901 including both a hierarchy where a cache is located and a hierarchy where a main memory is located. Further, the storage device of one embodiment of the present invention can be favorably used as a storage device located in the boundary area 902 including both the hierarchy where the main memory is located and the hierarchy where the storage is located.

The storage device of one embodiment of the present invention can be favorably used as a storage device used for servers, notebook PCs, smartphones, game machines, image sensors, IoT (Internet of Things), healthcare, and the like.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 5)
This embodiment shows an example of an electronic component and an electronic device in which the storage device of one embodiment of the present invention is incorporated.

<Electronic parts>
First, an example of an electronic component in which a memory device is incorporated will be described with reference to FIGS.

FIG. 31A shows a perspective view of the electronic component 500 and a substrate (mounting substrate 504) on which the electronic component 500 is mounted. The electronic component 500 illustrated in FIG. 31A includes a memory device 550 in a mold 511.

In FIG. 31A, a part of the electronic component 500 is omitted to show the inside. The electronic component 500 has a land 512 outside the mold 511. The land 512 is electrically connected to the electrode pad 513, and the electrode pad 513 is electrically connected to the memory device 550 by the wire 514. The electronic component 500 is mounted on the printed board 502, for example. The mounting board 504 is completed by combining a plurality of such electronic components and electrically connecting them to each other on the printed board 502.

The memory device 550 includes a substrate 551 and a memory circuit layer 552 in which a functional layer having a plurality of memory cells is stacked over the substrate 551.

FIG. 31B shows a perspective view of the electronic component 530. The electronic component 530 is an example of SiP (System in package) or MCM (Multi Chip Module). In the electronic component 530, an interposer 531 is provided on a package board 532 (printed board), and a semiconductor device 535 and a plurality of storage devices 550 are provided on the interposer 531.

In the electronic component 530, an example in which the storage device 550 is used as a wide band memory (HBM: High Bandwidth Memory) is shown. Further, as the semiconductor device 535, an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.

As the package substrate 532, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 531, a silicon interposer, a resin interposer, or the like can be used.

The interposer 531 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or a multilayer. In addition, the interposer 531 has a function of electrically connecting an integrated circuit provided over the interposer 531 to an electrode provided over the package substrate 532. From these things, an interposer may be called a "redistribution board" or an "intermediate board." In addition, a through electrode may be provided in the interposer 531 and the integrated circuit and the package substrate 532 may be electrically connected using the through electrode. Further, in the silicon interposer, TSV (Through Silicon Via) can be used as the through electrode.

It is preferable to use a silicon interposer as the interposer 531. Since the silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.

In the HBM, it is necessary to connect many wirings in order to realize a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted is required to have fine and high-density wiring. Therefore, it is preferable to use the silicon interposer as the interposer for mounting the HBM.

Further, in SiP or MCM using a silicon interposer, the reliability is less likely to decrease due to the difference in expansion coefficient between the integrated circuit and the interposer. Further, since the silicon interposer has a high surface flatness, a defective connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use the silicon interposer.

Further, a heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 530. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 531 be uniform. For example, in the electronic component 530 described in this embodiment, it is preferable that the memory device 550 and the semiconductor device 535 have the same height.

An electrode 533 may be provided on the bottom of the package substrate 532 to mount the electronic component 530 on another substrate. FIG. 31B shows an example in which the electrode 533 is formed of a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 532, BGA (Ball Grid Array) mounting can be realized. Alternatively, the electrode 533 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 532, PGA (Pin Grid Array) mounting can be realized.

The electronic component 530 can be mounted on another board using various mounting methods other than BGA and PGA. For example, a method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad-on-lead) method is used. be able to.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 6)
In this embodiment, an application example of a memory device including the semiconductor device described in any of the above embodiments will be described. The semiconductor device described in any of the above embodiments is, for example, a storage device of various electronic devices (eg, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, and the like). Applicable to Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, an SSD (solid state drive), and the like. FIG. 32 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device described in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.

FIG. 32A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 or the like of the substrate 1104.

32B is a schematic diagram of the external appearance of the SD card, and FIG. 32C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back surface side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided over the substrate 1113. As a result, the data in the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 of the substrate 1113 or the like.

FIG. 32D is a schematic diagram of the external appearance of the SSD, and FIG. 32E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the memory chip 1154, the memory chip 1155, and the controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 of the substrate 1153 or the like.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 7)
In this embodiment, an FPGA (field programmable gate array) will be described as an example of a semiconductor device to which an OS transistor and a capacitor are applied, which is one embodiment of the present invention, with reference to FIGS. .. In the FPGA of this embodiment, the OS memory is applied to the configuration memory and the register. Here, such an FPGA is referred to as an "OS-FPGA".

<<OS-FPGA>>
FIG. 33A shows a configuration example of the OS-FPGA. The OS-FPGA 3110 illustrated in FIG. 33A is capable of NOFF (normally off) computing that executes context switching with a multi-context structure and fine-grain power gating for each PLE. The OS-FPGA 3110 has a controller (Controller) 3111, a word driver (Word driver) 3112, a data driver (Data driver) 3113, and a programmable area (Programmable area) 3115.

The programmable area 3115 has two input/output blocks (IOB) 3117 and a core 3119. The IOB 3117 has a plurality of programmable input/output circuits. The core 3119 has a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130. The LAB 3120 has a plurality of PLEs 3121. FIG. 33B shows an example in which the LAB 3120 is composed of five PLEs 3121. As shown in FIG. 33C, the SAB 3130 has a plurality of switch blocks (SB) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and the LAB 3120 in four (up, down, left and right) directions via the SAB 3130.

The SB 3131 will be described with reference to FIGS. 34A to 34C. Data SB, datab, signals context[1:0], and word[1:0] are input to the SB3131 illustrated in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship. The number of contexts of the OS-FPGA 3110 is 2, and the signal context[1:0] is a context selection signal. The signal word[1:0] is a word line selection signal, and the wirings to which the signal word[1:0] is input are word lines.

The SB 3131 has PRSs (Programmable Routing Switches) 3133[0] and 3133[1]. The PRSs 3133[0] and 3133[1] have a configuration memory (CM) capable of storing complementary data. Note that when PRS3133[0] and PRS3133[1] are not distinguished, they are referred to as PRS3133. The same applies to other elements.

FIG. 34B shows a circuit configuration example of the PRS3133[0]. The PRS3133[0] and PRS3133[1] have the same circuit configuration. The PRS3133[0] and PRS3133[1] are different in the input context selection signal and word line selection signal. The signal context[0] and the signal word[0] are input to the PRS3133[0], and the signals context[1] and word[1] are input to the PRS3133[1]. For example, in SB3131, the signal context[0] becomes “H”, and thus PRS3133[0] becomes active.

The PRS3133[0] has a CM3135 and a Si transistor M31. The Si transistor M31 is a pass transistor controlled by the CM3135. The CM 3135 has memory circuits 3137 and 3137B. The memory circuits 3137 and 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitor C31 and OS transistors MO31 and MO32. The memory circuit 3137B includes a capacitor CB31 and OS transistors MOB31 and MOB32.

When the semiconductor device described in any of the above embodiments is used for the SAB3130, the transistors described in any of the above embodiments can be used as the OS transistors MO31 and MOB31. As a result, the off currents of the OS transistors MO31 and MOB31 can be reduced, so that the configuration data can be retained for a long time. Further, since the area occupied by a pair of the transistor and the capacitive element in top view can be reduced, the semiconductor device according to this embodiment can be highly integrated.

The OS transistors MO31, MO32, MOB31, MOB32 have back gates, and these back gates are electrically connected to power supply lines that supply fixed voltages.

The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. The nodes N32 and NB32 are charge holding nodes of the CM3135. The OS transistor MO32 controls the conduction state between the node N31 and the signal line for the signal context[0]. The OS transistor MOB32 controls the conduction state between the node N31 and the low potential power supply line VSS.

The data held by the memory circuits 3137 and 3137B have a complementary relationship. Therefore, one of the OS transistor MO32 and MOB32 becomes conductive.

An operation example of the PRS3133[0] will be described with reference to FIG. The configuration data is already written in the PRS3133[0], the node N32 of the PRS3133[0] is "H", and the node NB32 is "L".

PRS3133[0] is inactive while the signal context[0] is "L". During this period, even if the input terminal of the PRS3133[0] is changed to "H", the gate of the Si transistor M31 is maintained at "L" and the output terminal of the PRS3133[0] is also maintained at "L".

The PRS3133[0] is active while the signal context[0] is “H”. When the signal context[0] transitions to “H”, the gate of the Si transistor M31 transitions to “H” according to the configuration data stored in the CM 3135.

When the input terminal transitions to “H” while PRS3133 [0] is active, the gate voltage of the Si transistor M31 rises due to boosting because the OS transistor MO32 of the memory circuit 3137 is a source follower. To do. As a result, the OS transistor MO32 of the memory circuit 3137 loses its drivability, and the gate of the Si transistor M31 becomes floating.

In the PRS3133 having a multi-context function, the CM 3135 also has a multiplexer function.

FIG. 35 shows a configuration example of the PLE3121. The PLE 3121 has an LUT (look-up table) block (LUT block) 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block 3123 is configured to select internal data according to the input inA-inD and output it. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.

The PLE 3121 is electrically connected to the power supply line for the voltage VDD via the power switch 3127. ON/OFF of the power switch 3127 is set by the configuration data stored in the CM 3128. By providing the power switch 3127 in each PLE3121, fine grain power gating is possible. With the fine-grain power gating function, the PLE 3121 that is not used after the context switching can be power-gated, so that the standby power can be effectively reduced.

To implement NOFF computing, register block 3124 is composed of non-volatile registers. The non-volatile register in the PLE3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.

The register block 3124 has an OS-FF 3140[1] 3140[2]. The signals user_res, load, and store are input to the OS-FFs 3140[1] and 3140[2]. The clock signal CLK1 is input to the OS-FF 3140[1], and the clock signal CLK2 is input to the OS-FF 3140[2]. FIG. 36A shows a configuration example of the OS-FF 3140.

The OS-FF 3140 has an FF 3141 and a shadow register 3142. The FF 3141 has nodes CK, R, D, Q and QB. A clock signal is input to the node CK. The signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node and node Q is a data output node. The logics of the node Q and the node QB are complementary to each other.

The shadow register 3142 functions as a backup circuit for the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes the backed up data to the nodes Q and QB according to the signal load.

The shadow register 3142 has inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B. The memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitor C36 and OS transistors MO35 and MO36. The memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. The nodes N36 and NB36 are gates of the OS transistor MO36 and OS transistor MOB36, respectively, and are charge retention nodes. The nodes N37 and NB37 are the gates of the Si transistors M37 and MB37.

When the semiconductor device described in any of the above embodiments is used for the LAB 3120, the transistors described in any of the above embodiments can be used as the OS transistors MO35 and MOB35. As a result, the off currents of the OS transistors MO35 and MOB35 can be reduced, so that the OS-FF can hold the backed up data for a long period of time. Further, since the area occupied by a pair of the transistor and the capacitive element in top view can be reduced, the semiconductor device according to this embodiment can be highly integrated.

The OS transistors MO35, MO36, MOB35, MOB36 have back gates, and these back gates are electrically connected to power supply lines that supply a fixed voltage.

An example of an operation method of the OS-FF 3140 will be described with reference to FIG.

(Backup)
When the “H” signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data in the FF 3141. The node N36 becomes "L" when the data of the node Q is written, and the node NB36 becomes "H" when the data of the node QB is written. Then, power gating is executed and the power switch 3127 is turned off. Although the data in the nodes Q and QB of the FF 3141 is lost, the shadow register 3142 retains the backed up data even when the power is off.

(Recovery)
The power switch 3127 is turned on to supply power to the PLE3121. After that, when the "H" signal load is input to the OS-FF 3140, the shadow register 3142 writes the backed up data back to the FF 3141. Since the node N36 is "L", the node N37 is maintained at "L" and the node NB36 is "H", so that the node NB37 is "H". Therefore, the node Q becomes "H" and the node QB becomes "L". That is, the OS-FF 3140 returns to the state at the time of backup operation.

By combining the fine grain power gating and the backup/recovery operation of the OS-FF 3140, the power consumption of the OS-FPGA 3110 can be effectively reduced.

An error that can occur in the memory circuit is a soft error due to the incidence of radiation. A soft error is a secondary universe that occurs when α-rays emitted from the materials that make up memory and packages, and the primary cosmic rays that enter the atmosphere from the universe react with the atomic nuclei in the atmosphere. This is a phenomenon in which malfunction occurs such as inversion of data held in a memory due to irradiation of a transistor with linear neutrons or the like to generate electron-hole pairs. An OS memory using an OS transistor has high soft error resistance. Therefore, by mounting an OS memory, a highly reliable OS-FPGA 3110 can be provided.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 8)
In this embodiment, an example of a CPU including a semiconductor device according to one embodiment of the present invention, such as the above memory device, will be described.

<CPU configuration>
A semiconductor device 6400 shown in FIG. 37 includes a CPU core 6401, a power management unit 6421, and a peripheral circuit 6422. The power management unit 6421 has a power controller (Power Controller) 6402 and a power switch (Power Switch) 6403. The peripheral circuit 6422 includes a cache 6404 having a cache memory, a bus interface (BUS I/F) 6405, and a debug interface (Debug I/F) 6406. The CPU core 6401 includes a data bus 6423, a control unit (Control Unit) 6407, a PC (program counter) 6408, a pipeline register (Pipeline Register) 6409, a pipeline register (Pipeline Register) 6410, and an ALU (Arithmetic Logic Unit) 6411. And a register file (Register File) 6412. Data is exchanged between the CPU core 6401 and the peripheral circuit 6422 such as the cache 6404 via the data bus 6423.

The semiconductor device described in the above embodiment can be applied to many logic circuits including the power controller 6402 and the control device 6407. Accordingly, the semiconductor device 6400 capable of reducing power consumption can be provided. Further, the semiconductor device 6400 capable of improving the operation speed can be provided. Further, a semiconductor device 6400 capable of reducing fluctuations in power supply voltage can be provided.

In addition, it is preferably applied to the p-channel Si transistor, the transistor including the oxide semiconductor described in any of the above embodiments in a channel formation region, and the semiconductor device 6400. Accordingly, a small semiconductor device 6400 can be provided. Further, a semiconductor device 6400 capable of reducing power consumption can be provided. Further, the semiconductor device 6400 capable of improving the operation speed can be provided. In particular, by using only p-channel type Si transistors, the manufacturing cost of the semiconductor device can be kept low.

The control device 6407 controls the operations of the PC 6408, the pipeline register 6409, the pipeline register 6410, the ALU 6411, the register file 6412, the cache 6404, the bus interface 6405, the debug interface 6406, and the power controller 6402, thereby inputting. It has a function of decoding and executing an instruction included in a program such as a generated application.

The ALU 6411 has a function of performing various arithmetic processes such as four arithmetic operations and logical operations.

The cache 6404 has a function of temporarily storing frequently used data. The PC 6408 is a register having a function of storing an address of an instruction to be executed next. Although not shown in FIG. 37, the cache 6404 is provided with a cache controller that controls the operation of the cache memory.

The pipeline register 6409 is a register having a function of temporarily storing instruction data.

The register file 6412 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing of the ALU 6411, or the like.

The pipeline register 6410 is a register having a function of temporarily storing data used for arithmetic processing of the ALU 6411, data obtained as a result of arithmetic processing of the ALU 6411, and the like.

The bus interface 6405 has a function as a data path between the semiconductor device 6400 and various devices outside the semiconductor device 6400. The debug interface 6406 has a function as a signal path for inputting a command for controlling debugging to the semiconductor device 6400.

The power switch 6403 has a function of controlling supply of power supply voltage to various circuits of the semiconductor device 6400 other than the power controller 6402. The various circuits described above belong to several power domains, and the various circuits belonging to the same power domain are controlled by the power switch 6403 to be supplied with the power supply voltage. Further, the power controller 6402 has a function of controlling the operation of the power switch 6403.

The semiconductor device 6400 having the above structure can perform power gating. The flow of the power gating operation will be described with an example.

First, the CPU core 6401 sets the timing of stopping the supply of the power supply voltage in the register of the power controller 6402. Next, the CPU core 6401 sends an instruction to start power gating to the power controller 6402. Next, the various registers and the cache 6404 included in the semiconductor device 6400 start saving data. Next, the power switch 6403 stops the supply of the power supply voltage to various circuits other than the power controller 6402 included in the semiconductor device 6400. Next, an interrupt signal is input to the power controller 6402, so that supply of power supply voltage to various circuits included in the semiconductor device 6400 is started. Note that a counter may be provided in the power controller 6402 and the timing at which the supply of the power supply voltage is started may be determined using the counter regardless of the input of the interrupt signal. Next, the various registers and the cache 6404 start data recovery. Execution of the instructions in controller 6407 is then resumed.

Such power gating can be performed in the entire processor or in one or a plurality of logic circuits included in the processor. Further, the power supply can be stopped even in a short time. Therefore, it is possible to reduce the power consumption with a finer granularity spatially or temporally.

When power gating is performed, it is preferable that information held by the CPU core 6401 and the peripheral circuit 6422 can be saved in a short time. By doing so, the power can be turned on and off in a short period of time, and the effect of power saving becomes large.

In order to save the information held by the CPU core 6401 and the peripheral circuit 6422 in a short period of time, it is preferable that the flip-flop circuit can save data in the circuit (referred to as a flip-flop circuit that can be backed up). Further, it is preferable that the SRAM circuit can save data in the circuit (referred to as a back-upable SRAM circuit). The flip-flop circuit or SRAM circuit that can be backed up preferably includes a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region. As a result, since the transistor has a low off-state current, the flip-flop circuit or the SRAM circuit that can be backed up can hold data for a long time without power supply. Further, since the transistor has a high switching speed, a flip-flop circuit or an SRAM circuit that can be backed up may be able to save and restore data in a short period of time.

An example of a flip-flop circuit that can be backed up will be described with reference to FIG.

A semiconductor device 6500 illustrated in FIG. 38 is an example of a flip-flop circuit that can be backed up. The semiconductor device 6500 includes a first memory circuit 6501, a second memory circuit 6502, a third memory circuit 6503, and a reading circuit 6504. The potential difference between the potential V1 and the potential V2 is supplied to the semiconductor device 6500 as a power supply voltage. One of the potential V1 and the potential V2 has a high level, and the other has a low level. Hereinafter, an example of the structure of the semiconductor device 6500 will be described by taking the case where the potential V1 is low level and the potential V2 is high level as an example.

The first memory circuit 6501 has a function of holding the data when the signal D including data is input during a period in which the power supply voltage is supplied to the semiconductor device 6500. Then, during the period in which the power supply voltage is supplied to the semiconductor device 6500, the first memory circuit 6501 outputs the signal Q including the held data. On the other hand, the first memory circuit 6501 cannot hold data while the semiconductor device 6500 is not supplied with power supply voltage. That is, the first memory circuit 6501 can be referred to as a volatile memory circuit.

The second memory circuit 6502 has a function of reading and storing (or saving) the data held in the first memory circuit 6501. The third memory circuit 6503 has a function of reading and storing (or saving) the data held in the second memory circuit 6502. The reading circuit 6504 has a function of reading data held in the second memory circuit 6502 or the third memory circuit 6503 and storing (or restoring) the data in the first memory circuit 6501.

In particular, the third memory circuit 6503 has a function of reading and storing (or saving) the data held in the second memory circuit 6502 even when the semiconductor device 6500 is not supplied with power supply voltage. ..

As shown in FIG. 38, the second memory circuit 6502 includes a transistor 6512 and a capacitor 6519. The third memory circuit 6503 includes a transistor 6513, a transistor 6515, and a capacitor 6520. The reading circuit 6504 includes a transistor 6510, a transistor 6518, a transistor 6509, and a transistor 6517.

The transistor 6512 has a function of charging and discharging the capacitor 6519 with charge corresponding to data stored in the first memory circuit 6501. It is preferable that the transistor 6512 be able to charge and discharge the charge corresponding to the data held in the first memory circuit 6501 with respect to the capacitor 6519 at high speed. Specifically, the transistor 6512 preferably contains crystalline silicon (preferably polycrystalline silicon, more preferably single crystal silicon) in the channel formation region.

The conductive state or the non-conductive state of the transistor 6513 is selected in accordance with the charge held in the capacitor 6519. The transistor 6515 has a function of charging and discharging the capacitor 6520 with electric charge according to the potential of the wiring 6544 when the transistor 6513 is on. The off-state current of the transistor 6515 is preferably extremely low. Specifically, the transistor 6515 preferably contains an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region.

Specifically, the connection relation of each element is described. One of a source and a drain of the transistor 6512 is connected to the first memory circuit 6501. The other of the source and the drain of the transistor 6512 is connected to one electrode of the capacitor 6519, the gate of the transistor 6513, and the gate of the transistor 6518. The other electrode of the capacitor 6519 is connected to the wiring 6542. One of a source and a drain of the transistor 6513 is connected to the wiring 6544. The other of the source and the drain of the transistor 6513 is connected to one of the source and the drain of the transistor 6515. The other of the source and the drain of the transistor 6515 is connected to one electrode of the capacitor 6520 and the gate of the transistor 6510. The other electrode of the capacitor 6520 is connected to the wiring 6543. One of a source and a drain of the transistor 6510 is connected to the wiring 6541. The other of the source and the drain of the transistor 6510 is connected to one of the source and the drain of the transistor 6518. The other of the source and the drain of the transistor 6518 is connected to one of the source and the drain of the transistor 6509. The other of the source and the drain of the transistor 6509 is connected to one of the source and the drain of the transistor 6517 and the first memory circuit 6501. The other of the source and the drain of the transistor 6517 is connected to the wiring 6540. Although the gate of the transistor 6509 is connected to the gate of the transistor 6517 in FIG. 38, the gate of the transistor 6509 does not necessarily have to be connected to the gate of the transistor 6517.

The transistor illustrated in the above embodiment can be applied to the transistor 6515. Since the off-state current of the transistor 6515 is small, the semiconductor device 6500 can hold data without power supply for a long time. Since the switching characteristic of the transistor 6515 is favorable, the semiconductor device 6500 can perform high-speed backup and recovery.

(Embodiment 9)
This embodiment shows an example of an electronic component and an electronic device in which the memory device described in the above embodiment is incorporated.

<Electronic parts>
First, an example of an electronic component in which the memory device described in any of the above embodiments is incorporated will be described with reference to FIGS.

An electronic component 7000 shown in FIG. 39A is an IC chip and has leads and a circuit portion. The electronic component 7000 is mounted on the printed circuit board 7002, for example. A plurality of such IC chips are combined and electrically connected to each other on the printed board 7002 to complete a board (mounting board 7004) on which electronic components are mounted.

The circuit portion of the electronic component 7000 is formed by stacking a substrate 7031, a layer 7032, and a layer 7033.

As the substrate 7031, a material that can be used for the substrate described in any of the above embodiments may be used. When a semiconductor substrate such as silicon is used as the substrate 7031, an integrated circuit may be formed over the substrate 7031 and the layer 7032 having an OS transistor may be formed thereover.

The layer 7032 includes the OS transistor described in any of the above embodiments. For example, a control circuit such as a CPU can be provided in the layer 7032.

Layer 7033 has memory. As the memory, for example, a memory using an OS transistor such as NOSRAM or DOSRAM (registered trademark) (hereinafter referred to as an OS memory) can be used. Further, the memory device described in any of the above embodiments can be used as the NOSRAM.

Since the OS memory can be stacked and provided on another semiconductor element, the electronic component 7000 can be downsized. Further, the OS memory consumes less power when rewriting data, and thus the power consumption of the electronic component 7000 can be reduced.

The OS memory may be provided in the layer 7032 instead of the layer 7033. By doing so, the manufacturing process of the IC chip can be shortened.

In addition to the OS memory, the layer 7033 may be provided with ReRAM (Resistive Random Access Memory), MRAM (Magnetoresistive Random Access Memory), PRAM (Phase change RAM), FeRAM (FerRAM), or the like.

In FIG. 39A, QFP (Quad Flat Package) is applied to the package of the electronic component 7000, but the form of the package is not limited to this.

FIG. 39B is a schematic diagram of the electronic component 7400. The electronic component 7400 is a camera module and incorporates an image sensor chip 7451. The electronic component 7400 includes a package substrate 7411 that fixes the image sensor chip 7451, a lens cover 7421, a lens 7435, and the like. Further, an IC chip 7490 having functions such as a driver circuit and a signal converter circuit of an imaging device is provided between the package substrate 7411 and the image sensor chip 7451 and has a structure as a SiP (System in package). There is. The land 7441 is electrically connected to the electrode pad 7461, and the electrode pad 7461 is electrically connected to the image sensor chip 7451 or the IC chip 7490 by the wire 7471. In FIG. 39B, part of the lens cover 7421 and the lens 7435 are omitted in order to show the inside of the electronic component 7400.

The circuit portion of the image sensor chip 7451 is formed by stacking a substrate 7031, a layer 7032, a layer 7033, and a layer 7034.

For details of the substrate 7031, the layer 7032, and the layer 7033, the above description of the electronic component 7000 may be referred to.

The layer 7034 has a light receiving element. As the light receiving element, for example, a pn junction type photodiode having a selenium-based material as a photoelectric conversion layer can be used. A photoelectric conversion element using a selenium-based material has a high external quantum efficiency with respect to visible light and can realize a highly sensitive optical sensor.

The selenium-based material can be used as a p-type semiconductor. Examples of the selenium-based material include crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium and selenium (CIS), or a compound of copper, indium, gallium and selenium (CIGS). Can be used.

The n-type semiconductor of the pn junction photodiode is preferably formed of a material having a wide band gap and a property of transmitting visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used.

As the light-receiving element included in the layer 7034, a pn junction photodiode including a p-type silicon semiconductor and an n-type silicon semiconductor may be used. Further, it may be a pin junction type photodiode in which an i-type silicon semiconductor layer is provided between a p-type silicon semiconductor and an n-type silicon semiconductor.

The photodiode using silicon can be formed using single crystal silicon. At this time, it is preferable that the layer 7033 and the layer 7034 be electrically connected to each other by a bonding step. Further, the photodiode using silicon can also be formed using a thin film of amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 10)
In this embodiment, specific examples of electronic devices which can be applied to the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

More specifically, the semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip. FIG. 40 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU or a chip according to one embodiment of the present invention.

<Electronic devices and systems>
The GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic device include a television device, a desktop or notebook personal computer, a monitor for a computer, a digital signage (digital signboard), and a relatively large game machine such as a pachinko machine. In addition to electronic devices including screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be given. By providing the electronic device with the integrated circuit or the chip of one embodiment of the present invention, artificial intelligence can be mounted on the electronic device.

The electronic device of one embodiment of the present invention may include an antenna. By receiving the signal with the antenna, images, information, and the like can be displayed on the display portion. When the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, (Including the function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).

The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), wireless communication It can have a function, a function of reading a program or data recorded in a recording medium, and the like. FIG. 40 shows examples of electronic devices.

[mobile phone]
In FIG. 40A, a mobile phone (smartphone) which is a kind of information terminal is illustrated. The information terminal 5500 includes a housing 5510 and a display portion 5511. A touch panel is provided in the display portion 5511 and a button is provided in the housing 5510 as an input interface.

The information terminal 5500 can execute an application utilizing artificial intelligence by applying the chip of one embodiment of the present invention. As an application using artificial intelligence, for example, an application for recognizing a conversation and displaying the content of the conversation on the display unit 5511, a character input by a user on a touch panel included in the display unit 5511, a figure, etc. are recognized, An application displayed on the display portion 5511, an application for biometric authentication such as a fingerprint or a voiceprint, and the like can be given.

[Information terminal 1]
FIG. 40B shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

The desktop information terminal 5300 can execute an application utilizing artificial intelligence by applying the chip of one embodiment of the present invention, similarly to the above-described information terminal 5500. Examples of applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the desktop information terminal 5300, new artificial intelligence can be developed.

Note that, in the above description, although the smartphone and the desktop information terminal are illustrated as examples of the electronic device in FIGS. 40A and 40B, respectively, an information terminal other than the smartphone and the desktop information terminal may be applied. it can. Examples of the information terminal other than the smartphone and the desktop information terminal include a PDA (Personal Digital Assistant), a notebook information terminal, a workstation, and the like.

[Space applications]
The semiconductor device of one embodiment of the present invention can be applied to a device for space application. For example, FIG. 40C illustrates an artificial satellite 5800. The artificial satellite 5800 has a body 5801 and a solar panel 5802. The semiconductor device of one embodiment of the present invention can be used in the body 5801 of the artificial satellite 5800. Note that the semiconductor device of one embodiment of the present invention can be driven even in a situation where power supplied from the solar panel 5802 is low (e.g., a situation where the sun does not hit the solar panel) because of low power consumption. Further, in outer space, in a region exposed to sunlight, an electronic device, a semiconductor device, or the like provided in the body 5801 may be exposed to a high temperature environment of 200° C. or higher. The semiconductor device of one embodiment of the present invention has high reliability even in a high temperature environment, and thus can be preferably used.

[game machine]
FIG. 40D illustrates a portable game machine 5200 which is an example of a game machine. The portable game machine has a housing 5201, a display portion 5202, buttons 5203, and the like.

By applying the GPU or the chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. Further, low power consumption can reduce heat generation from the circuit, and thus can reduce the influence of heat generation on the circuit itself, peripheral circuits, and modules.

Further, by applying the GPU or the chip of one embodiment of the present invention to the mobile game machine 5200, the mobile game machine 5200 having artificial intelligence can be realized.

Originally, expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena occurring in the game are determined by the program included in the game. However, by applying artificial intelligence to the portable game machine 5200, It enables expressions that are not limited to game programs. For example, it is possible to express that the content that the player asks, the progress of the game, the time, and the behavior of the person who appears in the game changes.

Further, when a plurality of players play a necessary game on the portable game machine 5200, an artificial intelligence can configure a game player in an anthropomorphic manner. You can play games.

Although a portable game machine is illustrated as an example of a game machine in FIG. 40D, a game machine to which the GPU or the chip of one embodiment of the present invention is applied is not limited thereto. As a game machine to which the GPU or chip of one embodiment of the present invention is applied, for example, a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), or a sports facility is installed. There are pitching machines for batting practice.

[Mobile]
The GPU or the chip of one embodiment of the present invention can be applied to an automobile that is a moving object and around a driver's seat of the automobile.

FIG. 40E1 illustrates an automobile 5700 which is an example of a moving object, and FIG. 40E2 is a diagram illustrating a windshield and its surroundings in the interior of the automobile. FIG. 40E2 illustrates the display panel 5701, the display panel 5702, and the display panel 5703 attached to the dashboard, and the display panel 5704 attached to the pillar.

The display panels 5701 to 5703 can provide various kinds of information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioning setting, and the like. Further, the display items and layout displayed on the display panel can be appropriately changed according to the preference of the user, and the designability can be improved. The display panels 5701 to 5703 can also be used as a lighting device.

By projecting an image from an imaging device (not shown) provided in the automobile 5700 on the display panel 5704, the field of view (blind spot) blocked by the pillars can be complemented. That is, by displaying an image from an imaging device provided outside the automobile 5700, a blind spot can be compensated and safety can be improved. Further, by displaying an image that complements the invisible portion, it is possible to confirm the safety more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

Since the GPU or the chip of one embodiment of the present invention can be applied as a component of artificial intelligence, the chip can be used for an automatic driving system of the automobile 5700, for example. In addition, the chip can be used in a system that performs road guidance, risk prediction, and the like. Information such as road guidance and risk prediction may be displayed on the display panels 5701 to 5704.

In the above description, an automobile is described as an example of the moving body, but the moving body is not limited to the automobile. For example, as the moving object, a train, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), or the like can be given, and the chip of one embodiment of the present invention is applied to these moving objects. Thus, a system using artificial intelligence can be added.

[Broadcast system]
The GPU or chip of one embodiment of the present invention can be applied to a broadcasting system.

FIG. 40(F) schematically shows data transmission in the broadcasting system. Specifically, FIG. 40F illustrates a path in which a radio wave (broadcast signal) transmitted from the broadcasting station 5680 reaches a television receiver (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.

In FIG. 40F, the antenna 5650 is a UHF (Ultra High Frequency) antenna, but a BS 110° CS antenna, a CS antenna, or the like can be used as the antenna 5650.

The radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. At each home, the terrestrial TV broadcast can be viewed on the TV 5600 by receiving the radio wave 5675B through the antenna 5650. Note that the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 40F, but may be satellite broadcasting using an artificial satellite, data broadcasting using an optical line, or the like.

The broadcasting system described above may be a broadcasting system using artificial intelligence by applying the chip of one embodiment of the present invention. When the broadcast data is transmitted from the broadcasting station 5680 to the TV 5600 in each home, the broadcast data is compressed by the encoder, and when the antenna 5650 receives the broadcast data, the decoder of the receiving device included in the TV 5600 decodes the broadcast data. Restore is performed. By using artificial intelligence, it is possible to recognize a display pattern included in a display image in motion compensation prediction, which is one of the encoder compression methods. It is also possible to perform intra-frame prediction using artificial intelligence. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on the TV 5600 having a high resolution, an image interpolation process such as up-conversion can be performed when the broadcast data is restored by the decoder.

The above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data increases.

Further, as an application of artificial intelligence on the TV 5600 side, for example, the TV 5600 may be provided with a recording device having artificial intelligence. With such a configuration, the program can be automatically recorded by allowing the recording device to learn the user's preference by artificial intelligence.

The electronic device described in this embodiment, a function of the electronic device, an application example of artificial intelligence, effects thereof, and the like can be combined as appropriate with description of other electronic devices.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

10: Manufacturing apparatus, 11: First manufacturing line, 12: Second manufacturing line, 13: Third manufacturing line, 21, 22, 23a, 23b, 24: Conveyance route, 30: Substrate, 31: Circuit, 32: sense amplifier, 33: wiring, 34: connection part, 39: barrier layer, 40, 40a, 40a_n, 40a_1, 40a_2: functional layer, 41, 41a: memory cell, 42, 46: transistor, 43: capacitance, 44 , 45, 47a, 47b: plug, 50, 50a: semiconductor device, 51, 51a, 52: barrier layer, 55: insulating layer, 56: plug, 57: terminal, 60: laminated block, 65: memory cell array

Claims (6)

A step of preparing a substrate,
Forming a first transistor in which a part of the substrate serves as a channel formation region;
A functional layer and a first barrier layer are alternately formed n times (n is an integer of 2 or more and 200 or less) on the first transistor, and the functional layer and the first barrier layer are alternately formed. Forming a laminated body in which n pieces are laminated in
A step of forming a plurality of laminated blocks by partially etching the laminated body so as to divide the laminated body into a plurality of areas;
Forming a second barrier layer that covers upper and side surfaces of the plurality of laminated blocks; and an insulating layer that covers the second barrier layer and is located between the laminated blocks,
Forming a plug electrode embedded in an opening reaching the substrate in a part of the insulating layer and the second barrier layer in a region that does not overlap with the stacked block,
The functional layer includes a second transistor and a capacitor,
The second transistor includes a metal oxide in a channel formation region,
Method of manufacturing semiconductor device. In claim 1,
One of a source and a drain of the second transistor and one of a pair of electrodes of the capacitor are electrically connected.
Method of manufacturing semiconductor device. A step of preparing a substrate,
Forming a first transistor in which a part of the substrate serves as a channel formation region;
A functional layer and a first barrier layer are alternately formed n times (n is an integer of 2 or more and 200 or less) on the first transistor, and the functional layer and the first barrier layer are alternately formed. Forming a laminated body in which n pieces are laminated in
A step of forming a plurality of laminated blocks by partially etching the laminated body so as to divide the laminated body into a plurality of areas;
Forming a second barrier layer that covers upper and side surfaces of the plurality of laminated blocks; and an insulating layer that covers the second barrier layer and is located between the laminated blocks,
Forming a plug electrode embedded in an opening reaching the substrate in a part of the insulating layer and the second barrier layer in a region that does not overlap with the stacked block,
The functional layer includes a second transistor, a third transistor, and a capacitor,
The second transistor and the third transistor include a metal oxide in a channel formation region,
Method of manufacturing semiconductor device. In claim 3,
One of a source and a drain of the second transistor and a gate of the third transistor are electrically connected.
Method of manufacturing semiconductor device. In any one of Claim 1 thru|or Claim 4,
The plurality of second transistors overlapping in the thickness direction are formed such that the other of the source and the drain is electrically connected to each other.
Method of manufacturing semiconductor device. A semiconductor device having a substrate loading section, a first manufacturing line, a second manufacturing line, a third manufacturing line, a substrate unloading section, a first transfer path, and a second transfer path. Manufacturing equipment of
The substrate carry-in unit is a portion for temporarily storing the carried-in substrate,
The first manufacturing line has a function of forming a first transistor in which a part of the substrate serves as a channel formation region,
The second manufacturing line has a function of forming a functional layer and a first barrier layer in this order,
The third manufacturing line has a function of etching a part of the laminated body to form a plurality of laminated blocks so as to divide the plurality of laminated bodies into a plurality of areas, and a top surface of the plurality of laminated blocks. A function of forming a second barrier layer that covers a side surface and an insulating layer that covers the second barrier layer and is located between the stacked blocks, and the insulating layer and the insulating layer in a region that does not overlap with the stacked block. A function of forming a plug electrode embedded in an opening reaching the substrate in a part of the second barrier layer,
The substrate unloading unit is a part for temporarily storing the substrate for which the process has been completed,
The first transfer path has a function of transferring the substrate from the second manufacturing line to the third manufacturing line,
The second transport path has a function of transporting the substrate, which has been processed in the second manufacturing line, to the second manufacturing line.
Semiconductor device manufacturing equipment.