JP2019050355A - Light-emitting thyristor, light-emitting thyristor array, exposure head, and image forming apparatus - Google Patents

Abstract

To improve luminous efficiency while maintaining thyristor characteristics.SOLUTION: A light-emitting thyristor L has a lamination structure 200 having first to fourth semiconductor layers 110 to 140, and the third semiconductor layer 130 has at least a fifth semiconductor layer 131 in contact with the second semiconductor layer 120 and a sixth semiconductor layer 132 in this order from a semiconductor substrate 100 side. The sixth semiconductor layer 132 is a layer having the smallest band gap among the layers constituting the laminated structure 200, and a difference in band gap ΔEg between the fifth semiconductor layer 131 and sixth semiconductor layer 132 is 0.05 eV or more and less than 0.15 eV.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a light emitting thyristor, a light emitting thyristor array, an exposure head, and an image forming apparatus.

  One of the electrophotographic printers is a printer using an exposure head when exposing a photosensitive drum to form a latent image. The exposure head includes a light emitting element array in which semiconductor light emitting elements such as light emitting diodes (LEDs) are arranged in the longitudinal direction of the photosensitive drum, a rod lens array for focusing light emitted from the light emitting element array on the photosensitive drum. It consists of Printers using an exposure head have attracted attention because they have advantages such as being easy to miniaturize as compared with printers using a laser scanning method in which a laser beam is deflected and scanned by a polygon mirror.

  A self-scanning light emitting thyristor array is one of the light emitting element arrays. The self-scanning light emitting thyristor array has a structure in which a shift thyristor in which thyristors are one-dimensionally arranged as switch elements and a light emitting thyristor in which the thyristors are one-dimensionally arranged as light emitting elements are integrated on the same substrate.

  Patent Document 1 describes that the light emission efficiency is improved by introducing a quantum well structure into a thyristor structure in a light emitting thyristor.

JP, 2013-65591, A

  As described in Patent Document 1, a layer having a smaller band gap (hereinafter, referred to as a “small Eg layer”) than a surrounding layer such as a quantum well structure is also used in a light emitting thyristor as in the case of a light emitting element such as an LED. By introducing it, the light emission efficiency can be improved.

  However, as a result of intensive studies by the present inventors, it was found that the introduction of the small Eg layer to the light-emitting thyristor also affects the on-characteristics and the off-characteristics which are characteristics peculiar to the thyristor. These characteristics do not have to be considered in a two-terminal light emitting element such as an LED. Further, it was found that depending on the structure of the small Eg layer and the position of the small Eg layer in the thyristor structure, the on characteristics and the off characteristics (hereinafter collectively referred to as "thyristor characteristics") may be adversely affected.

  Then, in view of the above-mentioned subject, it aims at providing the light emitting thyristor which raised luminous efficiency, maintaining thyristor characteristics in the present invention.

  A light emitting thyristor according to one aspect of the present invention comprises a first semiconductor layer of the first conductivity type and a second conductivity type different from the first conductivity type on a semiconductor substrate of a first conductivity type. A light emitting thyristor having a laminated structure in which a second semiconductor layer, a third semiconductor layer of at least a part of the first conductivity type, and a fourth semiconductor layer of the second conductivity type are arranged in this order. The third semiconductor layer is composed of a plurality of semiconductor layers, and the fifth semiconductor layer of the first conductivity type in contact with the second semiconductor layer from the semiconductor substrate side; And a sixth semiconductor layer containing a first conductivity type or i-type in this order, and the sixth semiconductor layer is the layer having the smallest band gap among the layers constituting the laminated structure. The band gap of the fifth semiconductor layer and the band gap of the sixth semiconductor layer The difference ΔEg between bandgap is characterized by at least 0.05 eV 0.15 eV or less.

  According to the light emitting thyristor as one aspect of the present invention, the luminous efficiency can be improved while maintaining the thyristor characteristic.

It is a figure showing typically the structure of the light emitting thyristor concerning an embodiment. It is a figure which shows typically the structure of the simulation model of the light emitting thyristor which has a small Eg layer. It is a figure which shows the result of the simulation regarding the light emission thyristor of general structure which does not have a small Eg layer. It is a band figure when distance d is 50 nm and 200 nm. FIG. 2 is a view schematically showing a structure of a light emitting thyristor of Example 1; FIG. 7 is a view schematically showing a structure of a light emitting thyristor of Example 2; FIG. 7 is a view schematically showing a structure of a light emitting thyristor of Example 3; FIG. 16 is a view schematically showing a structure of a light emitting thyristor of Example 4; It is a figure which shows typically the structure of the printed circuit board which arranged the light emitting element array chip group of Example 8. FIG. FIG. 18 is a view for explaining the arrangement of an exposure head according to an eighth embodiment; FIG. 18 is a diagram for describing a configuration of an image forming apparatus of an eighth embodiment. FIG. 18 is a view schematically showing a structure of a light emitting thyristor of Example 5. FIG. 18 is a view schematically showing a structure of a light emitting thyristor of Example 7; It is a figure showing typically the structure of the simulation model of concentration distribution in a light emitting thyristor. It is a graph which shows the simulation result of carrier concentration distribution. It is a graph which shows the I-V curve of the light emitting thyristor of Example 6 and Comparative Example 3. It is a graph which shows the simulation result of the ratio of the luminescence amount in a small Eg layer to the luminescence amount in the whole gate layer. FIG. 18 schematically shows a structure of a light emitting thyristor of Example 6. It is a graph which shows the IV curve of the light-emitting thyristor of Example 3 and Comparative Example 1. It is a graph which shows the I-V curve of the light emitting thyristor of the comparative example 2. FIG.

  Hereinafter, embodiments of the present invention will be described in detail. The present invention is not limited to the following embodiments, and appropriate modifications may be made to the following embodiments based on the ordinary knowledge of those skilled in the art without departing from the spirit of the present invention. Those to which improvements and the like have been added are also included in the scope of the present invention.

[Structure of light emitting thyristor]
The light emitting thyristor L according to the present embodiment has a stacked structure 200 in which a plurality of semiconductor layers are stacked on a substrate 100 (on a semiconductor substrate), as shown in FIG.

  The substrate 100 is a semiconductor substrate of the first conductivity type. As the substrate 100, GaAs, InP, GaP or the like can be used.

  The stacked structure 200 is a thyristor in which a plurality of semiconductor layers of different conductivity types are alternately arranged. In the laminated structure 200, the first semiconductor layer 110, the second semiconductor layer 120, the third semiconductor layer 130, and the fourth semiconductor layer 140 are arranged in this order from the semiconductor substrate side (substrate 100 side). It is stacked. The first semiconductor layer 110 is a semiconductor layer of a first conductivity type, and the second semiconductor layer 120 and the fourth semiconductor layer 140 are a second conductivity type different from the first conductivity type. The third semiconductor layer 130 is a semiconductor layer of a conductive type different from the second conductive type. That is, the third semiconductor layer 130 at least includes a semiconductor layer of the first conductivity type. Alternatively, the third semiconductor layer 130 includes at least the semiconductor layer of the first conductivity type and the semiconductor layer of the third conductivity type different from the first and second conductivity types.

  It is preferable that each semiconductor layer which comprises the laminated structure 200 be comprised with a III-V group compound semiconductor. As the III-V compound semiconductor, it is preferable to use a GaAs-based material, an AlGaAs-based material, a GaP-based material, a GaAsP-based material, an InP-based material, an InAs-based material, an AlAs-based material, or an AlGaInP-based material. Among these, each of the semiconductor layers constituting the laminated structure 200 preferably contains a GaAs-based material or an AlGaAs-based material from the viewpoint of the light emission wavelength.

  As described above, the stacked structure 200 according to the present embodiment has a thyristor structure of a structure (pnpn structure or npnp structure) in which four semiconductor layers are stacked. When the first conductivity type is n-type, the second conductivity type is p-type, and the stacked structure 200 is an n-type semiconductor layer, a p-type semiconductor layer, an n-type semiconductor layer from the semiconductor substrate side (substrate 100 side) , And a thyristor having a p-type semiconductor layer in this order. When the first conductivity type is p-type, the second conductivity type is n-type, and the stacked structure 200 is a p-type semiconductor layer, an n-type semiconductor layer, a p-type semiconductor layer from the semiconductor substrate side (substrate 100 side) , A thyristor having an n-type semiconductor layer in this order. The first semiconductor layer 110 is an anode or a cathode of the thyristor, and the second semiconductor layer 120 is a gate (or a base) of the thyristor. The third semiconductor layer 130 is the gate (or base) of the thyristor, and the fourth semiconductor layer 140 is the cathode or anode of the thyristor.

  The light emitting thyristor L includes a drive electrode 101 disposed on the fourth semiconductor layer 140, a gate electrode 102 disposed on the third semiconductor layer 130, the drive electrode 101, the gate electrode 102, and the substrate 100. And a back electrode 103 disposed opposite to each other. In the present embodiment, the drive electrode 101 is a ring-shaped or frame-shaped electrode. Another layer such as a current diffusion layer may be interposed between the drive electrode 101 and the fourth semiconductor layer 140.

The third semiconductor layer 130 includes a plurality of semiconductor layers, and a fifth semiconductor layer 131 in contact with the second semiconductor layer 120 and a sixth semiconductor layer 132 from the semiconductor substrate side (the substrate 100 side). And at least in this order. The fifth semiconductor layer 131 is a semiconductor layer of the first conductivity type. The sixth semiconductor layer 132 is a semiconductor layer of the first conductivity type. Alternatively, the sixth semiconductor layer 132 is a semiconductor layer of a third conductivity type different from the first conductivity type and the second conductivity type. Here, the first conductivity type and the second conductivity type are either n-type or p-type, and the third conductivity type is i-type. The anode layer 140 is made of p-type Al _0.4 GaAs.

Note that in this specification, the i-type semiconductor layer refers to a non-doped (undoped) semiconductor layer. Non-doped (undoped) indicates that the dopant for controlling the conductivity type is not intentionally doped during the growth of the semiconductor layer. The dopant concentration in the i-type semiconductor layer is preferably 1 × 10 ¹⁶ cm ⁻³ or less. In addition, as a specific dopant element in each semiconductor layer, when each semiconductor layer is made of an AlGaAs-based material which is a III-V group semiconductor, Zn, Mg, which is a group II element, or a group IV element C, Si, Se which is a Group VI element, etc. are used.

  The sixth semiconductor layer 132 is a layer having the smallest band gap among the layers constituting the stacked structure 200, and is a layer (small Eg layer) having a smaller band gap than the surrounding (upper and lower) layers. By introducing the sixth semiconductor layer 132 which is a small Eg layer into the third semiconductor layer 130, carriers can be concentrated on the sixth semiconductor layer 132. As a result, the luminous efficiency of the light emitting thyristor L can be increased. It can be improved.

  The fifth semiconductor layer 131 is a layer adjacent to the second semiconductor layer 120. That is, the fifth semiconductor layer 131 forms a central pn junction among the three pn junctions of the light emitting thyristor L with the second semiconductor layer 120. The difference between the band gap of the third semiconductor layer 130 and the band gap of the sixth semiconductor layer 132 (band gap difference ΔEg) is 0.05 eV or more and less than 0.15 eV. The band gap difference ΔEg is preferably 0.05 eV or more and 0.1 eV or less. The reason will be described later. In the present embodiment, the band gap difference ΔEg is the difference between the band gap of the fifth semiconductor layer 131 and the band gap of the sixth semiconductor layer 132.

  When a drive voltage of the light emitting thyristor L is applied between the first semiconductor layer 110 and the fourth semiconductor layer 140 of the light emitting thyristor L in the off state, the second semiconductor layer 120 and the third semiconductor layer 130 A depletion layer occurs at the interface between This depletion layer occurs across the interface. In the present embodiment, when the conductivity type of the sixth semiconductor layer 132 is i-type, the distance d between the second semiconductor layer 120 and the sixth semiconductor layer 132 closest to the second semiconductor layer 120 is Is larger than the thickness of a portion of the depletion layer which can be formed in the third semiconductor layer 130. In other words, a depletion layer formed at the interface between the third semiconductor layer 130 having the sixth semiconductor layer 132 and the second semiconductor layer 120 which is another semiconductor layer adjacent to the third semiconductor layer 130. However, it can also be said that the sixth semiconductor layer 132 is not in contact. The reason will be described later.

  The light emitting thyristor L may further include a buffer layer (not shown) between the substrate 100 and the laminated structure 200. By providing the buffer layer, the crystal quality of the stacked structure 200 formed over the substrate 100 can be improved. The buffer layer is a semiconductor layer of the first conductivity type which is the same as the conductivity type of the substrate 100. As the buffer layer, a semiconductor of the same material system as that of the substrate 100 is preferably used. For example, if the substrate 100 is a GaAs substrate, GaAs or AlGaAs can be used.

  The light emitting thyristor L may have a current narrowing structure in which the current injected from the drive electrode 101 or the back surface electrode 103 narrows a region in which the current flows in the light emitting thyristor L. Thereby, the current flowing in the light emitting thyristor L can be concentrated in a desired region, and the light emission efficiency can be improved. The position of the current narrowing structure is not particularly limited as long as it is disposed between the drive electrode 101 and the back electrode 103. For example, it may be disposed in or between each semiconductor layer constituting the laminated structure 200, and may be disposed between the laminated structure 200 and the drive electrode 101, or between the back electrode 103 and the laminated structure 200. May be A conventionally known structure can be used as the current narrowing structure. For example, in a plan view seen from the stacking direction, the low resistance region and the low resistance region arranged around the low resistance region are more resistant than the low resistance region. And a high-resistance region can be used. The high resistance region can be formed, for example, by ion implantation or oxidation treatment from the side surface of the mesa.

  The light emitting thyristor L may further include a distributed Bragg reflector (not shown) between the substrate 100 and the laminated structure 200. The distributed Bragg reflector layer is also referred to as a distributed Bragg reflector (DBR) layer. The DBR layer is a layer that reflects the light emitted from the light emitting thyristor L to the surface side (the drive electrode 101 side) of the substrate 100. By providing the DBR layer, the light emission efficiency of the light emitting element can be improved. It is preferable that the DBR layer have high reflectance with respect to the wavelength of light emitted from the light emitting thyristor L.

  The DBR layer is preferably formed by alternately laminating two different types of semiconductor layers of the first conductivity type. For example, AlGaAs with a high concentration Al composition (for example, Al composition 0.8) and AlGaAs with a low concentration Al composition (for example, Al composition 0.1), etc. are used as two different types of semiconductor layers constituting the DBR layer. be able to.

  In the above embodiment, although the configuration in which the third semiconductor layer 130 has the small Eg layer 132 has been described, the present invention is not limited to this and either of two layers forming the central pn junction It is sufficient to have a small Eg layer in the layer of. That is, the second semiconductor layer 120 may have a small Eg layer. When the small Eg layer is provided in the second semiconductor layer 120, the second semiconductor layer 120 is formed of a plurality of semiconductor layers. Then, the second semiconductor layer 120 includes, from the opposite side of the substrate 100, a fifth semiconductor layer of a second conductivity type in contact with the third semiconductor layer, and a sixth semiconductor layer of a third conductivity type. At least in this order.

  As described above, the small Eg layer may be introduced into any of the second semiconductor layer 120 and the third semiconductor layer 130, but it is preferable to introduce the small Eg layer into the n-type semiconductor layer. Therefore, the third semiconductor layer 130 preferably has a small Eg layer when the conductivity type of the substrate 100 is n-type, and the second semiconductor layer 120 has a small Eg layer when the conductivity type of the substrate 100 is p-type. It is preferable to have

[Structure and position of small Eg layer]
As a result of intensive studies by the present inventors, when the small Eg layer is of the first conductivity type, the introduction of the small Eg layer into the light emitting thyristor affects the thyristor characteristics of the light emitting thyristor, that is, the on characteristics and the off characteristics. Found that there is one element that gives Also, when the small Eg layer is of the third conductivity type (i type), one more element is added to the factors that affect the on and off properties, and I found one thing.

  The first one is the band gap of the semiconductor layer (fifth semiconductor layer 131) forming the central pn junction among the layers constituting the semiconductor layer into which the small Eg layer is introduced, and the band gap of the small Eg layer. And the magnitude of the difference between the and (hereinafter referred to as "band gap difference .DELTA.Eg"). As shown below, as a result of studies by the present inventors, it was found that if the band gap difference ΔEg is 0.05 eV or more and less than 0.15 eV, it is possible to improve the luminous efficiency while maintaining the thyristor characteristics. .

  The second is that when the conductivity type of the small Eg layer is i-type, the pn junction in the center (the second pn junction counting from the substrate side) and the small Eg layer among the three pn junctions constituting the light emitting thyristor (Hereinafter referred to as “distance d”). In other words, it is the thickness of the layer located between the central pn junction and the small Eg layer. As shown below, as a result of studies by the present inventors, the distance d is larger than the thickness of the depletion layer formed in the layer located between the central pn junction and the small Eg layer when the drive voltage is applied. For example, it has been found that the luminous efficiency can be improved while maintaining the thyristor characteristics. Although the light emitting thyristor has three pn junctions, the pn junction referred to here also includes a pin junction.

[Simulation about structure and position of small Eg layer]
Hereinafter, the influence of the above two parameters (the band gap difference ΔEg and the distance d) on the thyristor characteristics and a preferable range for improving the light emission efficiency while maintaining the thyristor characteristics will be described with simulation results.

  First, the layer structure and calculation method of the simulation model of the light emitting thyristor used in this simulation will be described.

<Simulation model>
FIG. 2 is a view schematically showing a layer configuration of a simulation model of a light emitting thyristor having a small Eg layer used in the simulation. As shown in FIG. 2, the light-emitting thyristor used in the simulation has a structure in which a cathode layer 110, a p base layer 120, an n gate layer 130, an anode layer 140, and an overflow suppression layer 150 are stacked in this order on a GaAs substrate 100. Have. In this simulation, each of the cathode layer 110, the p base layer 120, the n gate layer 130, the anode layer 140, and the overflow suppression layer 150 is made of an AlGaAs-based material.

  The n gate layer 130 has a three-layer structure. The middle layer is a layer having a smaller Al composition than the upper and lower layers (the other two layers constituting the n gate layer), and is a layer having a small band gap, a small Eg layer 132. The n gate layer 130 has a spacer layer 131 and a spacer layer 133 so as to sandwich the small Eg layer 132. The spacer layer 131 and the spacer layer 133 are made of the same material and have the same band gap.

Next, details of each layer of the light emitting thyristor used in the simulation will be described. The cathode layer 110 was made of AlGaAs to a thickness of 600 nm. The p base layer 120 is made of Al _0.22 GaAs and has a thickness of 720 nm and a doping concentration of 3 × 10 ¹⁷ cm ⁻³ . The spacer layer 131 and the spacer layer 133 were Al _0.22 GaAs, and the doping concentration was 2 × 10 ¹⁷ cm ⁻³ . The total thickness of the three layers (the small Eg layer 132, the spacer layer 131 and the spacer layer 133) constituting the n gate layer 130 is 350 nm. The anode layer 140 is made of AlGaAs. The overflow suppression layer 150 is made of Al _0.8 GaAs with a thickness of 150 nm.

<Calculation method>
In this simulation, the simulation model was divided into small meshes in the stacking direction, and numerical analysis was performed on each mesh. Unlike the LED, LD (laser diode) and light emitting transistor, even when the same voltage is applied between the anode and the cathode, the light emitting thyristor takes two different states according to the history of the current injected to the gate. Therefore, in the simulation, these two states are reproduced and calculated.

Specifically, simulations were performed for the following two states. In the first state, first, a drive voltage _VAK , which is a voltage for causing the light emitting thyristor to emit light, is applied between the anode and the cathode while supplying a gate current Ig of 1 mA to the gate. Thereafter, the anode - gate current Ig while applying a driving voltage V _AK between the cathode was changed to 0mA to hold until a stable state. The first state is a state in which the "on condition" in a general light emitting thyristor is reproduced. The second state, the anode - gate current Ig injected into the light emission gate in a state where a driving voltage is not applied V _AK between the cathode and 0 mA, while the gate current Ig was 0 mA, anode - drive between the cathode voltage V _AK Is applied. The second state is a state in which the "off condition" in a general light emitting thyristor is reproduced.

<Simulation result>
Before the simulation results for the light emitting thyristor incorporating the small Eg layer, the simulation results for the light emitting thyristor of the general structure are shown. FIG. 3 is a diagram showing the results of simulation for a light emitting thyristor of a general structure without a small Eg layer. Here, as a light emitting thyristor having a general structure, a simulation was performed on a light emitting thyristor having a single-layer structure in which the n gate layer 130 of the light emitting thyristor shown in FIG. 2 does not have the small Eg layer 132. FIG. 3 shows the cathode current I _K when performing simulations by changing the drive voltage V _AK applied between the anode and the cathode in this light emitting thyristor configuration. In this simulation, the cross-sectional area of the portion through which the cathode current I _K flows (the area of the cross section perpendicular to the stacking direction) was 10 μm × 10 μm.

As shown in FIG. 3, in the light emitting thyristor having a general structure, in the first state (the state in which the “on condition” is reproduced), the driving voltage V _{AK is set} to 1.25 V or more between the anode and the cathode. The cathode current I _K continued to flow even after the gate current Ig was set to 0 mA. That is, the typical on-state V _AK -I _K characteristics could be confirmed. On the other hand, in the second state (the state in which the “off condition” is reproduced), the rise of the gate current Ig in the vicinity of the drive voltage V _AK 1.25 V between the anode and the cathode observed in the first state is observed. In addition, typical off-state V _AK -I _K characteristics could be confirmed. As described above, even when the driving voltage V _AK between the anode and the cathode is made the same, different results are obtained depending on whether the constant current is supplied to the gate or not (when 0 is kept from the beginning). I was able to confirm that I was doing.

  Here, the thyristor is a semiconductor element which can be switched on and off depending on whether or not a gate current is injected into the gate. Furthermore, as described above, the thyristor has a characteristic that once it is turned on and current flows between the anode and the cathode, the on state is maintained even if injection of the gate current is stopped. This property is referred to herein as the "on property". Once the thyristor is in the ON state, a reverse voltage is applied between the anode and the cathode for a certain period of time, or the current flowing between the anode and the cathode is maintained for a certain period of time with the current below the predetermined value (holding current). Can be turned off. The thyristor thus turned off has the characteristic that the off state is maintained if the voltage applied between the anode and the cathode is equal to or less than a predetermined value (break over voltage) unless the gate current is injected to the gate. Have. This property is referred to herein as the "off property". Further, in the present specification, the "on characteristics" and the "off characteristics" are collectively referred to as "thyristor characteristics".

  Next, simulation results regarding the light emitting thyristor having the small Eg layer 132 introduced as shown in FIG. 2 will be described.

(Influence of band gap difference ΔEg)
First, how the band gap difference ΔEg affects the thyristor characteristics will be described using simulation results.

Table 1 shows the cathode current I _K when simulation was performed while changing the band gap difference ΔEg. In Table 1, in the first state (the state where the gate current Ig is changed from 1 mA to 0 mA and held to the stable state), the case where the cathode current I _K did not decrease before and after the change of the gate current Ig is ○. The case where the cathode current I _K decreases is represented by x. In this simulation, in the simulation model of FIG. 2, a configuration in which the center in the thickness direction of the small Eg layer 132 and the center in the thickness direction of the n gate layer 130 are aligned is used as a simulation model. In other words, a configuration in which the spacer layer 131 and the spacer layer 133 disposed above and below the small Eg layer 132 have the same thickness was used as a simulation model. Here also, the anode - for each case the driving voltage V _AK between the cathode was the case with 2.5V, which was 2.0 V, a simulation was performed.

From Table 1, it was found that the on state can be maintained up to ΔEg = 0.105 eV in the case of V _AK = 2.0 V, and the on state can not be maintained if the band gap difference ΔEg is 0.15 eV or more. Further, it was found that the on state can be maintained up to ΔEg = 0.15 eV in the case of V _AK = 2.5 V, and the on state can not be maintained if the band gap difference ΔEg is 0.21 eV or more. In any of the cases shown in Table 1, the off state was maintained in the above-described second state (the state in which the “off state” was reproduced).

From this, when the small Eg layer is introduced to increase the light emission efficiency, the band gap difference ΔEg is preferably less than 0.15 eV, and more preferably less than 0.105 eV, in consideration of thyristor characteristics (particularly on characteristics). I understood it. It was found that when the band gap difference ΔEg is less than 0.15 eV, the on state can be maintained when the drive voltage V _AK is 2.0 V or more. When the drive voltage V _AK is 2.5 V or more, the band gap difference ΔEg is preferably less than 0.21 eV, and more preferably 0.15 eV or less.

In addition, although a quantum well structure with a small band gap (corresponding to the small Eg layer in the present specification) may be introduced to improve the light emission efficiency in LEDs, LDs, etc., in that case the band gap difference from the viewpoint of light emission efficiency. In many cases, ΔEg is 0.2 eV or more. Therefore, if the quantum well structure often used in LEDs and LDs is applied as it is to a light-emitting thyristor, the on-state characteristics may be adversely affected depending on the drive voltage V _AK and the material properties (such as the intra-band transition probability of carriers). I understand that. On the other hand, according to the present embodiment, when the band gap difference ΔEg is less than 0.15 eV as described above, the on state can be maintained even if the drive voltage V _AK is lowered to 2.0 V.

The simulation results in the case where the conductivity type of the small Eg layer is i-type have been described above. The same simulation was performed when the conductivity type of the small Eg layer 132 was the same as that of the surrounding spacer layers 131 and 133, and the result as to whether or not the on state was maintained was the same as described above. That is, it was found that the on state can be maintained up to ΔEg = 0.105 eV in the case of V _AK = 2.0 V, and the on state can not be maintained if the band gap difference ΔEg is 0.15 eV or more. Further, it was found that the on state can be maintained up to ΔEg = 0.15 eV in the case of V _AK = 2.5 V, and the on state can not be maintained if the band gap difference ΔEg is 0.21 eV or more. Thus, the conductivity type of the small Eg layer 132 is not limited to i-type, and may be p-type or n-type.

  The reason why the phenomenon that the on-state can not be maintained occurs when the small Eg layer is introduced to the light emitting thyristor when the band gap difference ΔEg is large is considered qualitatively as follows.

  A thyristor including a light emitting thyristor is turned on by carriers being accumulated in a gate layer or a base layer and so-called conductivity modulation occurring. By flowing gate current, carriers are injected into the gate layer or the base layer, carriers are accumulated and turned on, and current flows between the anode and the cathode. Thereafter, while current is flowing between the anode and the cathode, accumulation of carriers in the gate layer or the base layer is maintained, so that the on state is maintained even if the gate current is stopped.

  That is, in order to turn on the thyristor, a certain amount of carriers needs to be accumulated in the gate layer or the base layer. On the other hand, when the small Eg layer is introduced into the gate layer or the base layer, carriers are concentrated in the small Eg layer because the small Eg layer has a small band gap. In the case of an LED or LD, by introducing a well layer of a quantum well structure with a small band gap (corresponding to the small Eg layer in the present specification), carriers are concentrated on that portion, and as a result, the light emission efficiency is improved. It is known that it can. Also in the light emitting thyristor, the luminous efficiency can be improved by introducing a small Eg layer in the gate layer or the base layer and concentrating the carriers there. However, if carriers are concentrated too much in the small Eg layer, carriers in the surrounding gate layer or base layer will be reduced, so that a sufficient amount of carriers can not be stored, and conductivity modulation can not occur. As a result, when the small Eg layer is introduced into the light emitting thyristor, if the band gap difference ΔEg is large, the on state can not be maintained or the gate current does not turn on.

  On the other hand, even if the small Eg layer is introduced into the light emitting thyristor, the on state can be maintained if the band gap difference ΔEg is small to some extent. The reason is considered to be that the carrier has a distribution represented by Fermi-Dirac distribution in the energy direction. More specifically, the carrier distribution in the energy direction is expressed by multiplying the density of states gc (E) and gv (E) of the conduction band and the valence band by the Fermi-Dirac distribution f (E). Therefore, when the band gap difference ΔEg is small to a certain extent, a certain amount of carriers are also present at the energy positions of the conduction band lower end and the valence band upper end of the gate layer and the base layer according to the Fermi-Dirac distribution. become. There is a negative correlation between the amount of carriers present at energy positions below the conduction band lower end of the gate layer and the base layer and above the upper end of the valence band and the band gap difference ΔEg. And if the amount of carriers protruding outward from the quantum well structure of the small Eg layer is sufficiently large as described above, the necessary amount of carriers can be stored in the base layer or the gate layer, and as a result, the conductivity modulation is It will be possible to wake up.

  In the case of a bulk semiconductor, gc (E) and gv (E) can be expressed by Formulas (1) and (2), where the effective masses of electrons and holes are me and mh, respectively. In the case of a quantum well structure in which the shape of the bulk semiconductor and the shape of the state density are different, the carrier distribution can be similarly calculated by the expression according to the rectangular state density.

Further, the Fermi-Dirac distribution f (E) can be expressed by the equation (3) with the Fermi level E _F and the temperature T. In the case of not being in a thermal equilibrium state, for example, in a state in which a bias is applied between the anode and the cathode, the Fermi level E _F in Equation (3) is made to be a pseudo Fermi level of the conduction band and the valence band respectively. The carrier distribution of the conduction band and the valence band can be expressed.

  As described above, in the introduction of the small Eg layer to the light emitting thyristor, it is understood that there is a certain trade-off relationship between the light emission efficiency and the on-characteristic. Therefore, when introducing the small Eg layer into the light emitting thyristor, it is important to select the band gap difference ΔEg properly.

The upper limit of the band gap difference ΔEg is preferably set to a maximum value that can accumulate carriers sufficient to cause conductivity modulation when the drive voltage V _AK is applied. More specifically, as described above, when the drive voltage V _AK is 2.5 V or more, ΔEg is preferably less than 0.21 eV, and more preferably 0.15 eV or less. Further, when the drive voltage V _AK is 2.0 V or more, ΔEg is preferably less than 0.15 eV, and more preferably 0.105 eV or less.

  The lower limit value of the band gap difference ΔEg may be larger than 0 eV as long as it can be maintained on. However, from the viewpoint of light emission efficiency, it is preferable to confine a certain amount of carriers in the small Eg layer, so a value somewhat larger than 0 eV is preferable.

Table 2 shows the relationship between the ratio of the number of carriers present in the small Eg layer 132 to the number of carriers present in the entire p base layer 120 and the n gate layer 130, and the band gap difference ΔEg. From Table 2, it can be seen that carriers tend to be concentrated in the small Eg layer 132 as the band gap difference ΔEg increases. In particular, when the band gap difference ΔEg is compared with 0 eV and 0.05 eV, by making the band gap difference ΔEg 0.05 eV, concentration of twice or more carriers in the small Eg layer 132 can be achieved. it can. Therefore, from the viewpoint of concentrating the carriers to enhance the light emission efficiency, the band gap difference ΔEg is preferably 0.05 eV or more, and more preferably 0.1 eV or more. Further, depending on the value of the drive voltage V _AK , it is preferable that the value is 0.15 eV or more.

In summary, when the driving voltage V _AK is 2.5 V or more, ΔEg is preferably 0.05 eV or more and less than 0.21 eV, more preferably 0.05 eV or more and 0.15 eV or less, and 0. It is particularly preferable to be 1 eV or more and 0.15 eV or less. When the drive voltage V _AK is 2.0 V or more, ΔEg is preferably 0.05 eV or more and less than 0.15 eV, and more preferably 0.05 eV or more and 0.1 eV or less.

(Influence of distance d)
Next, in the case where the conductivity type of the small Eg layer is i-type, how the distance d affects the thyristor characteristics will be described using simulation results.

Table 3 shows the cathode current I _K when the simulation was performed while changing the distance d. In Table 3, in the second state (the state in which the above-mentioned "off condition" is reproduced), the case where the off state is maintained is ○, and the case where the off state can not be maintained is x. Further, Table 3 shows the value of the cathode current I _K in the first state (the state where the gate current Ig is changed from 1 mA to 0 mA and held to a stable state). In this simulation, in the simulation model of FIG. 1, ΔEg was set to 0.105 eV, and the thickness of the small Eg layer 132 was fixed at 150 nm. Then, the simulation was performed while changing the distance d between the pn interface formed between the p base layer 120 and the n gate layer 130 and the small Eg layer 132. In the simulation, the distance d corresponds to the thickness of the spacer layer 131.

  As a result of this simulation, as shown in Table 3, it was found that when the distance d is too small, the gate turns on (can not maintain the off state) even when current is not supplied to the gate. That is, the inventors found that the distance between the small Eg layer and the center pn junction greatly affects the thyristor characteristics when the small Eg layer is introduced to the light-emitting thyristor by this simulation. And in the structure of FIG. 2 used by this simulation, when distance d was 50 nm or less, it turned out that an OFF state can not be maintained.

  When the conductivity type of the small Eg layer is i-type, if the distance d is too small, the reason for turning on (if the current is not supplied to the gate) can not be maintained (can not maintain the off state) is considered as follows. .

  First, when a positive voltage (a voltage that causes the potential on the anode side to be higher than that on the cathode side) is applied between the anode and the cathode of the light emitting thyristor, the pn junction at the center among the three pn junctions constituting the light emitting thyristor It becomes reverse bias state. That is, most of the voltage is applied to the central pn junction and a depletion layer is generated near the central pn junction, which acts as a barrier layer to maintain the off state (state of blocking the current). Then, in the central pn junction, the flow of the reverse current for some reason causes the light emitting thyristor to shift to the on state.

  When the small Eg layer is disposed near the central pn junction, the end of the small Eg layer approaches the depletion layer formed by reverse biasing the pn junction, and in some cases the end of the small Eg layer Comes into the depletion layer. When the end of the small Eg layer enters the depletion layer, the band of the layer having a large band gap Eg in contact with the small Eg layer is bent, and the depletion layer does not function as a barrier layer. This will be described in more detail with reference to FIG.

FIG. 4 is a band diagram in the vicinity of the p base layer 120 and the n gate layer 130 in the second state described above (the state in which the “off condition” is reproduced) when the drive voltage V _AK is 2.0 V. Shows the calculation results of The upper end of the valence band and the lower end of the conduction band are shown in FIG. FIG. 4A is a band diagram when the distance d is 50 nm, and FIG. 4B is a band diagram when the distance d is 200 nm. As shown in Table 3, when the distance d is 50 nm, the off state can not be maintained, and when the distance d is 200 nm, the off state can be maintained.

  First, referring to FIG. 4B, it can be seen that a voltage is applied in the reverse direction between the p base layer 120 and the n gate layer 130. Then, as viewed from the interface between the p base layer 120 and the n gate layer 130, the small Eg layer 132 having a small band gap is present ahead of the spacer layer 131 having a thickness of 200 nm. The distance d is the same as the thickness of the spacer layer 131 shown in FIG. Then, looking at the valence band side, a step is formed at the interface between the spacer layer 131 and the small Eg layer 132, and the valence band is flat before and after this step. From this, it can be seen that the step functions as a barrier to holes and there is no acceleration due to the electric field before and after the barrier.

  On the other hand, as shown in FIG. 4A, the small Eg layer 132 approaches the depletion layer formed in the vicinity of the pn junction in the center, and the valence band of the spacer layer 131 has no flat portion. It can be seen that due to the influence of both the electric field of the layer and the small Eg layer 132, it has a downward convex shape. Therefore, it can be seen that the effect as a barrier to holes present in the small Eg layer 132 is reduced. In FIG. 4A, the distance d between the pn junction formed by the p base layer 120 and the n gate layer 130 and the small Eg layer 132 is 50 nm, but if this distance is further reduced, The height of the barrier due to the convex shape made is further reduced. Then, although the reverse bias is applied to the central pn junction, the current is more likely to flow.

In this way, the step of the valence band formed between the small Eg layer 132 and the layer (spacer layer 131) between the central pn junction and the small Eg layer 132 functions as a barrier. It can be seen that the distance d needs to be large to some extent. More specifically, of the depletion layer formed in the central pn junction when drive voltage _VAK is applied in the off state, the distance d is larger than the thickness of the portion formed in spacer layer 131. It is understood that it is necessary to do.

  Referring to FIG. 4B, in the depletion layer formed in the central pn junction, the thickness of the portion formed in the spacer layer 131 is the thickness of the portion where the valence band is sloped. Corresponding to about 60 nm. Therefore, in the configuration of FIG. 2, the distance d is preferably greater than 60 nm, and as shown in Table 3, is more preferably 70 nm or more.

Further, as shown in Table 3, when the distance d increases, the on current (cathode current I _K in the first state) decreases. Therefore, from the viewpoint of increasing the on current, the distance d is preferably smaller. In the configuration of FIG. 2, the distance d is preferably 200 nm or less. By setting the distance d to 200 nm or less, the reduction rate of the cathode current I _K from the cathode current I _K in the case of 70 nm which is the minimum value of the distance d which can maintain the off in the configuration of FIG. be able to. In the case where the distance d is 200 nm, the thickness of the n gate layer 130 is 350 nm in the configuration of FIG. 2, and the small Eg layer 132 is 150 nm in thickness. As a result, the spacer layer 131 and the small Eg layer 132 have a two-layer structure.

  Table 3 shows that if the distance d is too small, the off state can not be maintained. For this reason, it can be said that the off condition works better in the case where the distance d is 50 nm, that is, in the case where the spacer layer 131 is provided, as compared to the case where the distance d is 0 nm, ie, the spacer layer 131 is not provided. Therefore, in Table 3, when the distance d is 50 nm, the off state maintenance is "x", but it is more effective in the case where the distance d is 50 nm than in the case where the distance d is 0 nm. It can be said.

  Moreover, in the above-mentioned simulation, although the AlGaAs type | system | group material crystal-grown on the GaAs substrate was used as each semiconductor layer which comprises a light emission thyristor, limitation is not carried out to this. Each semiconductor layer which comprises a light emitting thyristor can be suitably selected according to the desired light emission wavelength as mentioned above. At that time, by designing the band gap difference ΔEg and the distance d based on the above-described design concept, it is possible to improve the luminous efficiency while maintaining the thyristor characteristics even with other material systems.

For example, when In _0.47 GaAs is used as the small Eg layer 132, the effective mass me of electrons and the effective mass mh of holes are both Al _0.14 GaAs (ΔEg = 0.1 eV in the configuration of FIG. 1). Compared to 2/3 to about half. Therefore, from Equation (1) and Equation (2), the carrier density at the energy position of the lower end of the conduction band and the upper end of the valence band of n gate layer 130 is approximately half. In that case, by changing the band gap difference ΔEg to about 0.08 eV from the equation (3), it is possible to realize the same carrier density as that of ΔEg = 0.1 eV in Al _0.14 GaAs, A level of thyristor characteristics can be realized. Further, also when the material system of each semiconductor layer constituting the light emitting thyristor is changed to another material system, or when the environmental temperature at which the light emitting thyristor operates is changed, the band gap difference ΔEg is appropriately selected similarly. It can be designed. Further, although the material of the single composition is used as the small Eg layer 132 in the above description, the small Eg layer 132 may be configured of a plurality of layers made of different materials.

  As described above, according to the configuration of the present embodiment, it is possible to provide a light emitting thyristor with improved light emission efficiency while maintaining the thyristor characteristic.

[Width and position of small Eg layer]
By satisfying the above conditions, the light amount can be further increased by bringing the position of the small Eg layer closer to the anode side. The reason is explained below.

  FIG. 17 is a graph showing simulation results of the ratio of the light emission amount in the small Eg layer to the light emission amount in the entire gate layer. FIG. 17 shows that as the thickness of the small Eg layer increases, the ratio of the light emission amount in the small Eg layer increases. In order to improve the amount of light emission while maintaining the thyristor characteristics, it is preferable to set the width of the small Eg layer to 50 nm or more and the ratio of the amount of light emission to 0.5 or more.

  FIG. 14 is a view showing a structure used for simulation of carrier concentration distribution in a light emitting thyristor. As shown in FIG. 14, the light emitting thyristor used in the simulation has a structure in which a cathode layer 110, a p base layer 120, an n gate layer 130, an anode layer 140, and an oxide confinement layer 190 are stacked. The substrate is omitted in this simulation.

Details of each layer of the light emitting thyristor used in this simulation will be described. The cathode layer 110 was made of Al _0.25 GaAs to a thickness of 580 nm. The p base layer 120 is made of Al _0.14 GaAs and has a thickness of 700 nm and a doping concentration of 2 × 10 ¹⁷ cm ⁻³ . The n gate layer 130 was Al _0.14 GaAs with a thickness of 340 nm and a doping concentration of 3 × 10 ¹⁷ cm ⁻³ . The anode layer 140 was made of Al _0.3 GaAs to a thickness of 420 nm. The oxidized constricting layer 190 is made of AlAs to a thickness of 130 nm.

  FIG. 15 is a graph showing simulation results of carrier concentration distribution. It can be seen from FIG. 15 that in the n gate layer 130, the carrier concentration is higher as it is closer to the anode layer 140 side. Therefore, by setting the central position of the small Eg layer closer to the anode layer 140 than the central position of the n gate layer 130, the carrier concentration in the small Eg layer becomes higher, and thus the light quantity can be further increased.

  As one example, when the thickness of the small Eg layer is 120 nm, the carrier concentration of holes when the central position of the small Eg layer is the same as the central position of the n gate layer 130 is normalized to 1. In this case, when the small Eg layer is in contact with the anode layer 140 (when the center position of the small Eg layer is shifted to the anode layer 140 by 110 nm), the carrier concentration of holes is 1.56. On the other hand, when the small Eg layer is in contact with the p base layer 120 (when the center position of the small Eg layer is shifted by 110 nm toward the p base layer 120), the carrier concentration of holes is 0.64.

  As described above, the small Eg layer provided in the n-type semiconductor layer is preferably disposed close to the anode layer 140 from the viewpoint of carrier concentration distribution. Further, the small Eg layer is more preferably disposed at a position where the end thereof contacts the anode layer 140.

  Since the anode layer 140 and the small Eg layer have different conductivity types, the diffusion of the dopant may be a problem depending on the doping type, the concentration, the temperature history during the process, and the like. In that case, it is preferable to provide a distance between the small Eg layer and the anode layer 140 to such an extent that the influence of dopant diffusion does not occur. For example, the distance between the small Eg layer and the anode layer 140 is preferably 5 nm or more.

  Hereinafter, examples of the present invention will be described in more detail while showing specific layer configurations and the like of light emitting elements.

Example 1
FIG. 5 is a device cross-sectional view of the light-emitting thyristor of the first embodiment. In the light emitting thyristor of this embodiment, a GaAs buffer layer 504, a cathode layer 510, a p base layer 520, an n gate layer 530, and an anode layer 540 are stacked in this order on an n-type GaAs substrate 500. An anode electrode 501 is formed on the anode layer 540. The anode electrode 501 is a ring electrode (frame-like electrode), and has a structure in which light emitted from the n gate layer 530 and the p base layer 520 is extracted from the opening. In addition, a gate electrode 502 is disposed on the n gate layer 530. The cathode electrode 503 is disposed on the back surface of the n-type GaAs substrate 500.

The cathode layer 510 is made of n-type Al _0.6 GaAs. The p base layer 520 is made of p-type Al _0.23 GaAs and has a thickness of 700 nm and a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ . The n gate layer 530 is composed of three layers, a spacer layer 531, a small Eg layer 532, and a spacer layer 533. The spacer layer 531 is made of n-type Al _0.23 GaAs, has a thickness of 100 nm, and a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ . The small Eg layer 532 is made of Al _0.14 GaAs and is 150 nm thick and non-doped (undoped). The spacer layer 533 is made of n-type Al _0.23 GaAs and has a thickness of 100 nm and a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ . The anode layer 540 is made of p-type Al _0.4 GaAs.

In the present embodiment, as described above, the small Eg layer is introduced into the third semiconductor layer, the spacer layer 531 corresponds to the fifth semiconductor layer, and the small Eg layer 532 corresponds to the sixth semiconductor layer. . In the present embodiment, the difference ΔEg between the band gap of the spacer layer 531 and the band gap of the small Eg layer 532 is 0.1 eV. Therefore, as described above, the light emitting thyristor of the present embodiment exhibits a good on characteristic even when the driving voltage V _AK is lowered to 2.0 V. In addition, since the small Eg layer is introduced in this embodiment, carriers can be concentrated on the small Eg layer, and the light emission efficiency can be improved. That is, according to the present embodiment, the luminous efficiency can be improved while maintaining the thyristor characteristics.

Further, in the present embodiment, an oxidized constricting layer 541 is disposed in the anode layer 540, which functions as a current constricting structure that confines carriers (electric current) injected from the anode electrode 501. The oxidized constricting layer 541 is formed by the same method as that of the oxidized constricting layer widely used in surface emitting lasers. Specifically, the oxide confinement layer 541 is formed by oxidizing the Al _0.98 GaAs layer from the side surface of the mesa with water vapor. Oxidation is performed from the side wall to a predetermined distance, and the central portion is not oxidized to leave a region through which current can pass, thus realizing a current confinement structure. In the present embodiment, although the oxidized constriction structure in which the Al _0.98 GaAs layer is partially oxidized is used as the current constriction structure, if a structure that can realize the current constriction, a configuration other than the oxidized constriction structure is used. May be By providing the current confinement structure in this manner, the light extraction efficiency can be improved.

(Example 2)
FIG. 6 is an element cross-sectional view of the light-emitting thyristor of the second embodiment. The light emitting thyristor of the present embodiment is provided with a multiple quantum well structure (MQW structure) 534 instead of the small Eg layer 532 of the light emitting thyristor of the first embodiment. The structure of the other parts is the same as that of the first embodiment, so the description will be omitted.

The MQW structure 534 has a structure in which barrier layers 5341 and quantum well layers 5342 are alternately stacked. In the present embodiment, the MQW structure 534 includes 15 layers of quantum well layers 5342 and 16 layers of barrier layers 5341. The barrier layer 5341 is made of Al _0.23 GaAs, is 6 nm thick, and is undoped. On the other hand, the quantum well layer 5342 is made of Al _0.06 GaAs, is 8 nm thick and is undoped.

  Thus, as the small Eg layer, a structure called a quantum well in which the thickness in the stacking direction is about the wavelength of electrons, or the thickness in the stacking direction and the size of the structure in the direction perpendicular to the stacking direction are the wavelength of electrons It is also possible to use a structure called a quantum dot, which is a degree. In such cases, the quantization results in one or more quantum levels in the valence band and the conductor. And, among the quantum levels generated in the valence band and the conductor, the energy difference between the ground levels having the smallest energy difference is different from the band gap in the bulk of the same material system. In this specification, when a quantum well structure or a quantum dot structure is used as the small Eg layer, the energy difference between ground levels having the smallest energy difference among the quantum orders is read as “band gap of the small Eg layer”. .

  The reason why the quantum well structure is used in this embodiment is to narrow the width of the emission spectrum. As in the case of LEDs and LDs, the state density can be made rectangular by making the structure of the light emitting layer from a bulk to a quantum well structure, and as a result, the width of the light emission spectrum can be reduced. Further, in the present embodiment, the number of quantum wells is set to 15 instead of 1 to 4 which is usually used in LD. The reason for this is that the carrier density stored in each of the quantum wells can be lowered, and the absolute value of the range in which the pseudo Fermi level of carriers fluctuates when the drive current changes can be reduced. To reduce the absolute value of the fluctuation range of the pseudo Fermi level of the carrier leads to the stabilization of the thyristor characteristics.

The emission wavelength of the ground level of the quantum well layer 5342 is 780 nm. Since the emission wavelength of the ground level is 780 nm, the energy difference (band gap) between the ground level of the conduction band and the valence band is 1.6 eV. Therefore, the difference ΔEg in the band gap between the quantum well layer 5342 and the spacer layers 531 and 533 is 0.1 eV. Therefore, as described above, the light emitting thyristor of the present embodiment exhibits a good on characteristic even when the driving voltage V _AK is lowered to 2.0 V. In addition, since the small Eg layer is introduced in this embodiment, carriers can be concentrated on the small Eg layer, and the light emission efficiency can be improved. That is, according to the present embodiment, the luminous efficiency can be improved while maintaining the thyristor characteristics.

(Example 3)
FIG. 7A is a cross-sectional view of the light-emitting thyristor of the third embodiment. In the light emitting thyristor of the second embodiment, a DBR layer 505 is further disposed between the cathode layer 510 and the GaAs buffer layer 504 in the light emitting thyristor of the second embodiment. The structure of the other parts is the same as that of the second embodiment, so the description will be omitted.

The DBR layer 505 has a layered structure in which a low refractive index layer 5051 made of Al _0.8 GaAs and a high refractive index layer 5052 made of Al _0.3 GaAs are alternately stacked. The optical thicknesses of the low refractive index layer 5051 and the high refractive index layer 5052 are both 1/4 of the light emission wavelength 780 nm of the light emitting thyristor. Here, the optical thickness of a film is a value obtained by multiplying the physical film thickness by the refractive index of the film. The optical film thickness is 1⁄4 of 780 nm in both cases, but since the refractive index is different between the low refractive index layer and the high refractive index layer, the actual film thickness is different between the two. The number of stacked layers is 21 for the low refractive index layer 5051 and 20 for the high refractive index layer 5052. The doping concentration of the DBR layer 505 is uniform and 2 × 10 ¹⁸ cm ⁻³ .

  The reason why the DBR layer 505 is introduced in this embodiment is to reflect the light emitted to the GaAs substrate 500 among the light emitted by the light emitting thyristor to the surface side and to increase the light quantity emitted from the surface. FIG. 7B shows the reflectance spectrum of the DBR layer 505 used in this example. In the DBR layer 505 of this embodiment, the maximum value of the reflectance is about 91% around the wavelength 780 nm which is the design wavelength of the light emitting thyristor, and the light quantity emitted from the top of the light emitting thyristor is the case where the DBR layer 505 is not provided. It will be 1.5 times or more. The wavelength at which the reflectance is half the peak value is 754 nm on the short wavelength side and 809 nm on the long wavelength side. If the wavelength between which the reflectance is half the peak value is defined as the high reflection band of the DBR layer 505, the width of the high reflection band in this embodiment is 55 nm. In this embodiment, as described above, since the DBR layer 505 is provided for the purpose of reflecting light emitted by the light emitting thyristor, the peak value of the light emission wavelength of the light emitting thyristor is within the high reflection band of the DBR layer 505 Is desirable.

  In this embodiment, carriers are concentrated in the quantum well layer 5342 and light is emitted by light emission recombination. Therefore, the peak of the light emission wavelength of the light emitting thyristor is the peak of the wavelength of light emitted by the light emission recombination in the quantum well layer 5342. In the quantum well layer, among the quantum levels generated in the quantum well, the transition between ground levels is the above emission wavelength, and in a bulk semiconductor, the wavelength close to the wavelength corresponding to the band gap of the semiconductor is the emission peak It becomes a wavelength.

  According to this embodiment, as in the first and second embodiments, it is possible to improve the luminous efficiency while maintaining the thyristor characteristics. In addition, since the DBR layer is further introduced in this embodiment, the light emission efficiency as a light emitting element can be further improved. In the present embodiment, the barrier layer 1201 and the quantum well layer 1202 constituting the MQW structure 534 may be doped.

A light emitting thyristor corresponding to Example 3 and a light emitting thyristor according to a comparative example were manufactured, and current-voltage characteristics (I-V curve) were measured. The I-V curve will be described. FIG. 19A is a graph showing an I-V curve of the light emitting thyristor corresponding to the third embodiment. The light-emitting thyristor for which the measurement of FIG. 19A is performed has substantially the same configuration as that of the third embodiment, but the following points are different. The thickness of the n gate layer 530 is 340 nm, and the barrier layer 5341 is made of Al _0.22 GaAs. The quantum well layer 5342 is made of Al _0.06 GaAs, ΔEg is 0.105 eV, and the distance d is 65 nm.

  First, measurement conditions of the IV curve will be described. The graph of FIG. 19 (a) shows the voltage and current obtained by applying a voltage between the anode and the cathode and measuring the current flowing between the anode and the cathode with the gate of the light emitting thyristor open (Open). Shows the relationship between Since the I-V curve of the light emitting thyristor has hysteresis, different characteristics can be obtained depending on the sweep direction of the voltage. Therefore, first, measure the forward path while gradually increasing the applied voltage between the anode and the cathode from 0 V (broken line arrow), and then gradually decrease the voltage after the light emitting thyristor shifts to the "on state". While measuring the return path (dotted-dotted arrow).

  As shown in FIG. 19A, in the measurement of the forward path, the “off state” is maintained from about 0 V to about 3 V. In the vicinity of 3 V, once the light emitting thyristor is shifted to the "on state", the "on state" is maintained in the range of at least 2.0 V and 2.5 V or less. In addition, when a current of 5.0 mA was flowing at room temperature, the amount of light output from the light emitting thyristor was 300 μW.

(Comparative Example 1, difference in I-V curve due to ΔEg)
As a comparative example 1 of the third embodiment, FIG. 19B shows an I-V curve of a light-emitting thyristor in which the value of ΔEg is the same as the structure showing the I-V curve in FIG. Specifically, the barrier layer 5341 of the light emitting thyristor in FIG. 19B is made of Al _0.30 GaAs, and ΔEg is 0.21 eV.

  As shown in FIG. 19B, in the forward path measurement, the “off state” is maintained from about 0 V to about 2.5 V. Thereafter, when the current flows and the light emitting thyristor shifts to the "on state", the voltage gradually decreases, and then the voltage turns to increase again. The rate of increase of the voltage relative to the current after the voltage starts to increase is larger than that of FIG. 19 (a). Further, in the I-V curve of Comparative Example 1, the forward path and the return path almost overlap, and hysteresis unique to the thyristor can not be seen.

Comparative Example 2 Difference in I-V Curve According to Distance d
As Comparative Example 2 of Example 3, the I-V curve of the light-emitting thyristor in which the value of d and the thickness of the n gate layer 530 are different from the structure showing the IV curve in FIG. And FIG. 20 (b). Specifically, in the present comparative example, an I-V curve corresponding to one in which the thickness of the n gate layer 530 in Example 3 is 0.8 times is shown in FIG. At this time, the distance d is 31 nm. An I-V curve corresponding to one in which the thickness of the n gate layer 530 in Example 3 is 1.2 times is shown in FIG. At this time, the distance d is 99 nm.

  In FIG. 20A, the forward path and the return path overlap. Further, in FIG. 20A, there is no “off state”, current starts to flow gradually from a low voltage, and thyristor characteristics are not shown. In this structure, the distance d is 31 nm, which is smaller than 50 nm. This is an area where the “off state” can not be maintained even in the simulation.

  On the other hand, in FIG. 20 (b), the forward path and the return path are different, and the "off state" is maintained from 0 V to 13 V or more. In addition, once the light emitting thyristor is shifted to the "on state", the "on state" is maintained even at a low voltage of about 2.0V. In the present structure, the distance d is 99 nm, which is larger than 50 nm. This is an area where the “off state” can be maintained also in the simulation.

(Example 4) (p substrate thyristor)
FIG. 8 is a device cross-sectional view of the light-emitting thyristor of the fourth embodiment. The light emitting thyristor of the present embodiment differs in that at least a p-type GaAs substrate is used as a semiconductor substrate, and the stacking order of layers, the type of conduction type of some layers, and the like differ from those of the third embodiment.

  The light-emitting thyristor of this embodiment is stacked on a p-type GaAs substrate 800 in the order of a p-type GaAs buffer layer 804, a DBR layer 805, an anode layer 810, an n base layer 820, ap gate layer 830 and a cathode layer 840. ing. The cathode electrode 801 is formed on the cathode layer 840. The cathode electrode 801 is a ring electrode (frame-like electrode), and has a structure in which light emitted from the p gate layer 830 and the n base layer 820 is extracted from the opening. In addition, a gate electrode 802 is disposed on the p gate layer 830. Further, on the back surface of the p-type GaAs substrate 800, an anode electrode 803 is disposed.

The DBR layer 805 is a stacked structure in which a low refractive index layer 8051 made of p-type Al _0.8 GaAs and a high refractive index layer 8052 made of p-type Al _0.3 GaAs are alternately stacked. It has a structure. The optical thickness of each of the low refractive index layer 8051 and the high refractive index layer 8052 is 1⁄4 of the light emission wavelength 780 nm of the light emitting thyristor. Note that since the refractive index differs between the low refractive index layer 8051 and the high refractive index layer 8052, the actual film thickness differs between the two. The number of stacked layers is 16 in the low refractive index layer 8051 and 15 in the high refractive index layer 8052. The doping concentration of the DBR layer 805 is uniform and 1 × 10 ¹⁸ cm ⁻³ .

  The reason for introducing the DBR layer 805 in the present embodiment is the same as the reason for introducing the DBR layer 505 in the third embodiment, the light emitted to the p-type GaAs substrate 800 among the light emitted by the light emitting thyristor It is for reflecting to the side and increasing the amount of light emitted from the surface.

The anode layer 810 is made of p-type Al _0.6 GaAs. The n base layer 820 has the same configuration as the n gate layer 530 of the second embodiment, and includes the spacer layer 821, the multiple quantum well (MQW) structure 824, and the spacer layer 823. Each of the spacer layer 821 and the spacer layer 823 is made of n-type Al _0.23 GaAs and has a thickness of 100 nm and a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ . The MQW structure 824 has the same structure as the MQW structure 534 of the second embodiment. The p gate layer 830 is made of p-type Al _0.23 GaAs and has a thickness of 700 nm and a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ .

  The reason why the p-type GaAs substrate 800 is used in this embodiment is to make the top layer (fourth semiconductor layer) of the semiconductor multilayer structure constituting the light emitting thyristor into an n-type semiconductor layer. In the present embodiment, this makes it possible for the n-type semiconductor layer to be present immediately below the upper electrode (cathode electrode 801) in the semiconductor layer configuration that constitutes the light emitting thyristor. In this way, the current injected from the upper electrode (cathode electrode 801) is directed in the lateral direction (from just under the electrode to the center of the element) in the n-type semiconductor layer (cathode layer 840) of the uppermost layer of the semiconductor multilayer structure. Can flow). In general, since the mobility of carriers is larger in the n-type semiconductor as compared with the p-type semiconductor, the resistance at the time of flowing the current in the lateral direction can be reduced. Thereby, the current can be sufficiently diffused in the fourth semiconductor layer laterally before the current reaches the second and third semiconductor layers constituting the central pn junction. As a result, the uniformity of light emission when viewed from the top of the light emitting thyristor can be improved.

  In the first to third embodiments, the n-type GaAs substrate 500 is used, but if the conductivity types of the semiconductor layers constituting the light-emitting thyristor described in each of the embodiments are reversed, the fourth embodiment is similar to the fourth embodiment. Can be transformed into a configuration in which the semiconductor layer is an n-type semiconductor layer. Here, "inverting the conductivity type" specifically means that the n-type GaAs substrate 500 is a p-type GaAs substrate, each n-type layer thereon is p-type, and each p-type layer is n-type. , Which means to replace each. By doing so, the top layer of the semiconductor multilayer structure can be made n-type, and the same effect as that of the fourth embodiment can be obtained.

  When an n-type substrate is used, the thyristor has a pnpn structure, so the fourth semiconductor layer, that is, the uppermost layer is p-type. In this case, although the effect when the above-described n-type semiconductor layer is used as the top layer can not be obtained, there is also a merit of using an n-type substrate instead. Specifically, from the viewpoint of the semiconductor industry as a whole, since the proportion of n-type substrates being used is higher than that of p-type substrates, it is easy to reduce the cost. Also, in terms of crystal quality such as defect density, an n-type substrate is easier to obtain a substrate of better quality than a p-type substrate. Therefore, when emphasizing these effects, a configuration using an n-type GaAs substrate is preferable. If the conductivity types of the respective semiconductor layers constituting the light emitting thyristor in the fourth embodiment are reversed, the fourth embodiment can be modified to a configuration using an n-type GaAs substrate.

  In the first to third embodiments, the small Eg layer is located in the gate layer through which the gate current flows. Therefore, even when only the gate current flows, light emission occurs due to the gate current. On the other hand, in Example 4, the small Eg layer is not located in the gate layer. Therefore, even when the gate current flows, the gate current flows from the p gate layer 830 to the cathode layer 840, and the gate current does not flow to the small Eg layer, so there is no light emission in the small Eg layer. Therefore, when it is preferable to emit light by the gate current, it is desirable to provide the small Eg layer in the gate layer as in the first to third embodiments. On the other hand, in the case where it is preferable not to emit light only by the gate current, it is desirable that no small Eg layer is provided in the gate layer as in the fourth embodiment.

  Although the MQW structure 824 is used as the small Eg layer in the n base layer 820 in this embodiment, the bulk type active layer used in the first embodiment may be used. Similarly, quantum dots or the like may be used as the small Eg layer. In that case, the effect of the present invention can be designed to be obtained by replacing the energy difference between the ground levels with the band gap difference ΔEg by the method described in the second embodiment. This is not limited to this embodiment, and the same applies to the other embodiments. Furthermore, in the present embodiment, the barrier layer 8241 and the quantum well layer 8242 which constitute the MQW structure 824 may be doped.

  Also in the present embodiment, as described with reference to FIGS. 14 and 15, the carrier concentration of the small Eg layer is made higher by setting the central position of the small Eg layer to the anode side than the central position of the gate layer. It is possible to realize an increase in the amount of light. Specifically, by arranging the MQW structure 824 which is the small Eg layer closer to the anode layer 810 than the center of the n base layer 820 in FIG. 8, the light quantity can be increased.

(Example 5)
FIG. 12 is a device sectional view of the light emitting thyristor of the present embodiment. In the light emitting thyristor of this embodiment, an MQW structure 1200 is provided instead of the multiple quantum well (MQW) structure 534 of the second embodiment. Hereinafter, the description of the parts having the same configuration as that of the second embodiment will be omitted, and only different parts will be described.

The MQW structure 1200 has a structure in which barrier layers 1201 and quantum well layers 1202 are alternately stacked. In the present embodiment, the MQW structure 1200 includes 25 layers of quantum well layers 1202 and 26 layers of barrier layers 1201. The barrier layer 1201 is made of Al _0.22 GaAs. The quantum well layer 1202 is made of Al _0.06 GaAs. The barrier layer 1201 and the quantum well layer 1202 are uniformly doped, and the carrier concentration of the barrier layer 1201 and the quantum well layer 1202 is 3 × 10 ¹⁷ cm ⁻³ .

The spacer layer 1203 is made of n-type Al _0.22 GaAs and has a thickness of 43 nm and a carrier concentration of 3 × 10 ¹⁷ cm ⁻³ . The spacer layer 1204 is made of n-type Al _0.23 GaAs and has a thickness of 39 nm and a carrier concentration of 3 × 10 ¹⁷ cm ⁻³ . In the present configuration, ΔEg is 0.105 eV.

  One of the differences from the second embodiment of the present embodiment is that the MQW structure 1200 is composed of the doped barrier layer 1201 and the quantum well layer 1202. Thus, the thyristor characteristics can be maintained even if the number of quantum well layers 1202 is increased to 25. By increasing the number of layers of the quantum well layer 1202 compared to the second embodiment, it is possible to further increase the light quantity and make the thyristor characteristics compatible.

  When the MQW structure 1200 is non-doped, it is required to set the distance d to 50 nm or more as described above. As a method to increase the light quantity while satisfying this condition, increasing the number of layers in the quantum well layer can be one option, but considering the travel distance of the carriers, it is not enough to make the n gate layer too thick Not desirable. Therefore, there is an upper limit to the number of quantum well layers, and there is a limit to the increase in light quantity. In this embodiment, by using the barrier layer 1201 and the quantum well layer 1202 which are doped in the MQW structure 1200, the restriction that the distance d is 50 nm or more can be eliminated. Therefore, by increasing the number of layers of the quantum well layer 1202 compared to the second embodiment, it is possible to further increase the light quantity.

  In addition, by increasing the number of layers of the quantum well layer 1202 as in the configuration of the present embodiment, it is possible to lower the carrier density per layer at the time of light emission, thereby providing a long-lived light emitting thyristor. .

(Example 6)
FIG. 18 is a device cross-sectional view of the light-emitting thyristor of this embodiment. In the light emitting thyristor of this embodiment, an MQW structure 1200 similar to that of the fifth embodiment is provided instead of the MQW structure 534 of the third embodiment. In other words, the light emitting thyristor of the present embodiment is obtained by adding the DBR layer 505 of the third embodiment to the light emitting thyristor of the fifth embodiment.

  According to the present embodiment, it is possible to improve the luminous efficiency while maintaining the thyristor characteristics for the same reason as the fifth embodiment. In addition, since the DBR layer 505 is further added in this embodiment, the light emission efficiency can be further improved.

  FIG. 16A is a graph showing an I-V curve of the light emitting thyristor of the present example. The measurement conditions of the IV curve are the same as those shown in Example 3. The solid line in the figure is an outward IV curve measured while gradually increasing the voltage applied between the anode and the cathode from 0V. The broken line in the figure is an IV curve of the return path measured while gradually reducing the applied voltage after the light emitting thyristor has shifted to the "on state".

  As shown in FIG. 16A, in the forward path measurement, the “off state” is maintained from 0 V to a high voltage of 15 V or more. Once in the "on state", the "on state" is maintained even at a low voltage of about 2.0V. In addition, when a current of 5.0 mA was flowing at room temperature, the amount of light output from the light emitting thyristor was 330 μW.

(Comparative example 3)
As Comparative Example 3 of Example 6, an I-V curve of a light-emitting thyristor in which the doping concentration of the MQW structure 1200 is different from that of this example is shown in FIG. In the present comparative example, the MQW structure 1200 is non-doped. In FIG. 16 (b), the forward path and the return path overlap. Further, in FIG. 16 (b), there is no "off state", current starts to flow gradually from low voltage, and thyristor characteristics are not shown. In this comparative example, since the MQW structure 1200 is non-doped and the number of quantum well layers 1202 is 25 layers, the distance d is 39 nm, which is smaller than 50 nm. This is an area where the “off state” can not be maintained even in the simulation.

  Also in the present embodiment, as in the fifth embodiment, the MQW structure 1200 is composed of the doped barrier layer 1201 and the quantum well layer 1202. As a result, the number of layers of the quantum well layer 1202 can be increased as compared with the case of non-doping, and it is possible to further increase the light quantity and make the thyristor characteristics compatible. In addition, since it is possible to lower the carrier density per layer at the time of light emission, a long-life light emitting thyristor is provided.

(Example 7)
FIG. 13 is a device cross-sectional view of the light-emitting thyristor of this embodiment. The light emitting thyristor of the present embodiment has a structure in which the position of the MQW 1334 is closer to the anode layer 540 as compared with the second embodiment.

Specifically, the spacer layer 533 is made of n-type Al _0.23 GaAs, its thickness is 50 nm, and its carrier concentration is 3 × 10 ¹⁷ cm ⁻³ . The spacer layer 531 is made of n-type Al _0.23 GaAs and has a thickness of 150 nm and a carrier concentration of 3 × 10 ¹⁷ cm ⁻³ .

  In this embodiment, the position of the MQW 1334 is closer to the side of the anode layer 540 where the carrier density is higher than that of the second embodiment. This makes it possible to provide a light-emitting thyristor with a further increased amount of light.

(Example 8)
The present embodiment is an electrophotographic system (image forming apparatus) using the light emitting thyristor of the fourth embodiment.

  FIG. 9 is a view schematically showing a printed circuit board 902 in which the light emitting element array chip group 901 is arranged. FIG. 9A is a view showing a surface (referred to as a “light emitting element array mounting surface”) on which the light emitting element array chip group 901 is mounted on the printed circuit board 902, and FIG. 9B is a light emitting element array. It is a figure which shows the surface (a "light emitting element array non-mounting surface") on the opposite side to a mounting surface.

  As shown in FIG. 9A, in the present embodiment, the light emitting element array chip group 901 includes 29 light emitting element array chips C1 to C29. The light emitting element array chip group 901 is mounted on the light emitting element array mounting surface of the print substrate 902, and the light emitting element array chips C1 to C29 are arranged on the print substrate 902 in a staggered manner.

  Each of the light emitting element array chips C1 to C29 has 516 light emitting points, and has 516 light emitting thyristors corresponding to the respective light emitting points. Each light emitting thyristor has the structure of the above-mentioned embodiment or each example. In each of the light emitting element array chips C1 to C29, the 516 light emitting thyristors are one-dimensionally arranged at a predetermined pitch in the longitudinal direction of the chips, and the adjacent light emitting thyristors are separated by the element separation groove. That is, the light emitting element array chips C1 to C29 can also be called a light emitting thyristor array in which a plurality of light emitting thyristors are one-dimensionally arranged. In this embodiment, the pitch between adjacent light emitting thyristors is 21.16 μm, which corresponds to a pitch of resolution of 1200 dpi. In addition, the distance from end to end of 516 light emitting points in the chip is about 10.9 mm (≒ 21.16 μm × 516).

  As shown in FIG. 9B, on the non-mounted surface of the light emitting element array, a driving unit 903a for driving the light emitting element array chips C1 to C15 and a driving unit 903b for driving the light emitting element array chips C16 to C29 are connectors. It is arranged on both sides of 905. The connector 905 is connected to a signal line for controlling the driving units 903a and 903b from an image controller unit (not shown), a power supply and a ground line, and is connected to the driving units 903a and 903b. Wirings for driving the light emitting element array chips are connected to the light emitting element array chips C1 to C15 and the light emitting element array chips C16 to C29 through the inner layer of the print substrate 902 from the driving units 903a and 903b.

  The light emitting element array chips C <b> 1 to C <b> 29 are arranged in two rows in a staggered manner, and each row is arranged along the longitudinal direction of the printed circuit board 902. FIG. 9C shows the state of the boundary between the light emitting element array chip C28 and the light emitting element array chip C29. Wire bonding pads P for inputting control signals are arranged at the end of each light emitting element array chip. The transfer unit T and the light emitting thyristor L are driven by the signal input from the wire bonding pad P. The pitch in the longitudinal direction of the printed circuit board 902 between the adjacent light emitting thyristors is also 21.16 μm, which corresponds to a resolution of 1200 dpi, even at the boundary between the chips. In addition, the pitch (S in FIG. 9C) of the print substrate 902 of the light emission points of the two rows of chips (S in FIG. 9C) is about 84 μm (4 pixels for 1200 dpi, 8 pixels for 2400 dpi) Is located in

  Since 29 light emitting element array chips each having 516 light emitting points are arranged on the printed board 902, the number of light emitting thyristors that can emit light is 14 in the entire light emitting element array chip group 901. , 964 pieces. Further, the width which can be exposed by the light emitting element array chip group 901 of this embodiment is about 316 mm (≒ 10.9 mm × 29), and an image corresponding to this width can be obtained by using the exposure head on which the light emitting element array chip group 901 is mounted. Can be formed.

Next, the exposure head 306 on which the light emitting element array chip group 901 is mounted will be described.
The exposure head 306 of this embodiment can be suitably used when exposing the photosensitive drum 302 and forming an electrostatic latent image on the photosensitive drum. However, the application of the exposure head 306 is not particularly limited, and can also be used, for example, as a light source of a line scanner.

  The exposure head 306 includes the above-described light emitting element array chip group 901, a printed board 902 on which the light emitting element array chip group 901 is mounted, and a rod lens array 403. The exposure head 306 also has a housing (support member) 404 for supporting the rod lens array 403 and the printed circuit board 902.

  The rod lens array 403 is an optical system that condenses the light from the light emitting element array chip group 901. The exposure head 306 condenses the light from each of the light emitting thyristors in the light emitting element array chip group 901 by the rod lens array 403. The light collected by the rod lens array 403 is irradiated to the photosensitive drum 302.

  10 (a) and 10 (b) show the arrangement of the photosensitive drum 302 and the exposure head 306 and how light from the exposure head 306 is imaged on the surface of the photosensitive drum 302. FIG. The exposure head 306 is disposed to face the photosensitive drum 302. Each of the exposure head 306 and the photosensitive drum 302 is used by being attached to the image forming apparatus by an attachment member (not shown).

  The exposure head 306 is assembled and adjusted alone in the factory, and focus adjustment and light amount adjustment of each spot are performed so that the light condensing position becomes an appropriate position when attached to the image forming apparatus. Is preferred. Here, the distance between the photosensitive drum 302 and the rod lens array 403 and the distance between the rod lens array 403 and the light emitting element array chip group 901 are arranged to be a predetermined distance. Thus, the light from the exposure head 306 is imaged on the photosensitive drum 302. Therefore, at the time of focus adjustment, adjustment of the attachment position of the rod lens array 403 is performed such that the distance between the rod lens array 403 and the light emitting element array chip group 901 becomes a desired value. Further, at the time of adjusting the light amount, the light emitting thyristors are sequentially caused to emit light, and the drive current of each light emitting element is adjusted so that the light condensed through the rod lens array 403 has a predetermined light amount.

  Next, an image forming apparatus using the exposure head 306 will be described with reference to FIG. FIG. 11 is a diagram for explaining the configuration of the image forming apparatus of the present embodiment.

  The image forming apparatus according to this embodiment is an electrophotographic image forming apparatus, and includes a scanner unit 700, an image forming unit 703, a fixing unit 704, a sheet feeding / conveying unit 705, and a control unit (not shown) for controlling them. Have.

  The scanner unit 700 illuminates a document to be read and optically reads an image of the document. Image data is created by converting the image read by the scanner unit 700 into an electrical signal.

  The image forming unit 703 includes a plurality of developing units that perform development using an electrophotographic process, and each developing unit includes a photosensitive drum 302, an exposure head 306, a charger 707, and a developing unit 708. The developing unit may be a process cartridge having a configuration used for developing a toner image. In this case, the process cartridge is preferably removable from the image forming apparatus main body.

  The photosensitive drum 302 is an image bearing member on which an electrostatic latent image is formed. The photosensitive drum 302 is rotationally driven and charged by the charger 707.

  The exposure head 306 irradiates the photosensitive drum 302 with light according to the image data to form an electrostatic latent image on the photosensitive drum 302. Specifically, the exposure head 306 condenses the light generated from the chip surface of the light emitting element array chip group 901 onto the photosensitive drum 302 by the rod lens array 403, and the electrostatic latent image corresponding to the image data is formed. The photosensitive drum 302 is formed.

  The developing device 708 supplies toner (developer) to the electrostatic latent image formed on the photosensitive drum 302 for development. The toner is stored in the storage unit. The storage unit for storing the toner is preferably included in the developing unit. The developed toner image (developer image) is transferred onto a recording medium such as paper conveyed on a transfer belt 711.

  The image forming apparatus of the present embodiment has four developing units (developing stations) that perform development using such a series of electrophotographic processes, and transfers a toner image from each developing unit to obtain a desired image. Form The four developing units respectively have toners of different colors, and sequentially execute the image forming operation of magenta, yellow and black after a predetermined time has elapsed from the start of image formation with cyan.

  The sheet feeding / conveying unit 705 feeds a sheet from a sheet feeding unit instructed in advance among the in-body sheet feeding units 709a and 709b, the external sheet feeding unit 709c, and the manual sheet feeding unit 709d, and the sheet is fed. The paper is conveyed to the registration roller 710.

  The registration roller 710 conveys the paper onto the transfer belt 711 so that the toner image formed in the image forming unit 703 described above is transferred onto the paper.

  An optical sensor 713 is disposed to face the surface of the transfer belt 711 on which the toner image is to be transferred, and a test chart printed on the transfer belt 711 is used to derive the amount of color shift between the developing units. Perform position detection. The color misregistration amount derived here is sent to an image controller unit (not shown) and used to correct the image position of each color. By this control, it is possible to transfer a full-color toner image without color misregistration onto paper.

  Fixing unit 704 incorporates a plurality of rollers and a heat source such as a halogen heater, and melts and fixes the toner on the sheet to which the toner image has been transferred from transfer belt 711 by heat and pressure. And discharge the sheet outside the image forming apparatus.

  An image formation control unit (not shown) is connected to an MFP control unit that controls the entire multifunction peripheral (MFP) including the image forming apparatus, and executes control according to an instruction from the MFP control unit. In addition, the image forming control unit instructs the entire image to operate smoothly and smoothly while managing the states of the scanner unit 700, the image forming unit 703, the fixing unit 704, and the sheet feeding / conveying unit 705 described above. Do.

  In such an image forming apparatus using an exposure head, the number of parts used is smaller than that of a laser scanning type image forming apparatus in which a laser beam is deflected and scanned by a polygon motor. Is easy to

100 Substrate 110 Cathode Layer (First Semiconductor Layer)
120p base layer (second semiconductor layer)
130 n gate layer (third semiconductor layer)
131 Spacer layer (fifth semiconductor layer)
132 Small Eg layer (sixth semiconductor layer)
140 anode layer (fourth semiconductor layer)

Claims (20)

At least a portion of a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, and a semiconductor substrate of a first conductivity type A light emitting thyristor having a laminated structure having a third semiconductor layer of the first conductivity type and a fourth semiconductor layer of the second conductivity type in this order,
The third semiconductor layer is composed of a plurality of semiconductor layers, and a fifth semiconductor layer of the first conductivity type in contact with the second semiconductor layer from the semiconductor substrate side, and the first semiconductor layer A sixth semiconductor layer containing a conductivity type or i-type in this order at least
The sixth semiconductor layer is a layer having the smallest band gap among the layers constituting the laminated structure,
A light emitting thyristor characterized in that a difference ΔEg between the band gap of the fifth semiconductor layer and the band gap of the sixth semiconductor layer is 0.05 eV or more and 0.15 eV or less.   The distance d between the second semiconductor layer and the sixth semiconductor layer is determined by driving the light emitting thyristor between the first semiconductor layer and the fourth semiconductor layer of the light emitting thyristor in the off state. In a state where a voltage is applied, the depletion layer formed at the interface between the second semiconductor layer and the third semiconductor layer is larger than the thickness of the portion formed in the third semiconductor layer A light emitting thyristor according to claim 1, characterized in that   The light emitting thyristor according to claim 1 or 2, wherein a driving voltage applied between the first semiconductor layer and the fourth semiconductor layer is 2.5 V or less.   The light emitting thyristor according to any one of claims 1 to 3, wherein a distance d between the second semiconductor layer and the sixth semiconductor layer is 70 nm or more.   The light emitting thyristor according to any one of claims 1 to 4, wherein a distance d between the second semiconductor layer and the sixth semiconductor layer is 200 nm or less.   The semiconductor device according to any one of claims 1 to 5, further comprising a seventh semiconductor layer of the first conductivity type between the sixth semiconductor layer and the fourth semiconductor layer. The light emitting thyristor as described in. The center of the said 6th semiconductor layer is distribute | arranged to the position nearer to the said 4th semiconductor layer rather than the center of the said 3rd semiconductor layer, It is characterized by the above-mentioned. A light emitting thyristor as described. A first semiconductor layer of the first conductivity type, and a second semiconductor layer of a second conductivity type at least a part of which is different from the first conductivity type on a semiconductor substrate of a first conductivity type; A light emitting thyristor having a laminated structure having a third semiconductor layer of the first conductivity type and a fourth semiconductor layer of the second conductivity type in this order,
The second semiconductor layer is composed of a plurality of semiconductor layers, and the fifth semiconductor layer of the second conductivity type is in contact with the third semiconductor layer from the opposite side of the semiconductor substrate; A sixth semiconductor layer containing two conductivity types or i-type in this order,
The sixth semiconductor layer is a layer having the smallest band gap among the layers constituting the laminated structure,
A light emitting thyristor characterized in that a difference ΔEg between the band gap of the fifth semiconductor layer and the band gap of the sixth semiconductor layer is 0.05 eV or more and 0.15 eV or less.   The distance d between the third semiconductor layer and the sixth semiconductor layer is determined by driving the light emitting thyristor between the first semiconductor layer and the fourth semiconductor layer of the light emitting thyristor in the off state. In a state where a voltage is applied, a depletion layer formed at an interface between the third semiconductor layer and the second semiconductor layer is larger than a thickness of a portion formed in the second semiconductor layer. The light emitting thyristor according to claim 8, characterized in that   The light emitting thyristor according to claim 8 or 9, wherein a drive voltage applied between the first semiconductor layer and the fourth semiconductor layer is 2.5 V or less.   The light emitting thyristor according to any one of claims 8 to 10, wherein a distance d between the third semiconductor layer and the sixth semiconductor layer is 70 nm or more.   The light emitting thyristor according to any one of claims 8 to 11, wherein a distance d between the third semiconductor layer and the sixth semiconductor layer is 200 nm or less.   The semiconductor device according to any one of claims 8 to 12, further comprising a seventh semiconductor layer of the second conductivity type between the sixth semiconductor layer and the first semiconductor layer. The light emitting thyristor as described in.   The center of the sixth semiconductor layer is disposed closer to the first semiconductor layer than the center of the second semiconductor layer. The light-emitting thyristor as described in a term.   The light emitting thyristor according to any one of claims 1 to 14, wherein the first conductivity type is n-type, and the second conductivity type is p-type.   The light emitting thyristor according to any one of claims 1 to 14, wherein the first conductivity type is p-type, and the second conductivity type is n-type.   The light emitting thyristor according to any one of claims 1 to 16, wherein the sixth semiconductor layer constitutes a well layer of a multiple quantum well structure.   The light emitting thyristor according to any one of claims 1 to 17, wherein the second semiconductor layer and the third semiconductor layer are made of an AlGaAs-based material. A plurality of light emitting thyristors according to any one of claims 1 to 18,
A light emitting thyristor array, wherein the plurality of light emitting thyristors are arranged in a one-dimensional manner. An image carrier,
Charging means for charging the surface of the image carrier;
An exposure head which exposes the surface of the image carrier charged by the charging unit and forms an electrostatic latent image on the surface of the image carrier;
Developing means for developing the electrostatic latent image formed by the exposure head;
An image forming apparatus comprising: transfer means for transferring an image developed by the developing means onto a recording medium;
An image forming apparatus comprising the light emitting thyristor array according to claim 19.

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