JP2018166276A - Charge redistribution AD converter and AD conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge redistribution AD converter having good linearity of conversion characteristics and reduced in input capacitance, without performing trimming and calibration operations of a capacitance value.SOLUTION: A charge redistribution AD converter and AD conversion method include: a plurality of sampling capacitors C1-C6 sampling an analog signal, each sampling capacitor having a first end connected to a common line and a second end to which the analog signal is input; a comparator 40 to compare an input voltage from the common line and a reference voltage; and a first capacitor 210 connected in series between the comparator and all sampling capacitors sampling the analog signal, on the common line.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a charge redistribution AD converter and an AD conversion method.

There are various architectures for ADC (analog-digital converter) that converts an analog signal into a digital signal, and they are properly used according to the specification application and requirements. In particular, the successive approximation ADC (SARADC) can be realized with a relatively simple circuit configuration, so it is highly compatible with the CMOS process and meets recent demands for miniaturization and low power consumption. Can be used widely (see, for example, Patent Document 1).
Japanese Patent Application Publication No. 2009-518964

  Such a charge redistribution AD converter that is a successive approximation ADC preferably has linearity with good conversion characteristics and low input capacitance. Therefore, it has been proposed to trim the capacitance value and calibrate the capacitance value by digital calculation in the AD converter manufacturing process. However, the trimming process increases the manufacturing cost. Further, if a logic circuit or the like is added in order to execute calibration, the chip cost is increased and the usage method is restricted.

  In the first aspect of the present invention, the first end is connected to the common line, the analog signal is input to the second end, the plurality of sampling capacitors for sampling the analog signal, the input voltage from the common line, and the reference voltage A charge redistribution type AD converter and AD conversion comprising: a comparator for comparing analog data signals; and a first capacitor connected in series between all sampling capacitors for sampling an analog signal and the comparator on a common line Provide a method.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

2 shows a configuration example of the charge redistribution AD converter 100. 2 shows a configuration example of a charge redistribution AD converter 200 according to the present embodiment. An example of the relationship of the thermal noise Vn with respect to the capacity | capacitance Cx of the charge redistribution type AD converter 200 which concerns on this embodiment is shown. An example of the relationship between the input capacitance Cinput and the capacitance Cx of the charge redistribution AD converter 200 according to the present embodiment is shown. A modification of the charge redistribution AD converter 200 according to the present embodiment is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration example of a charge redistribution AD converter 100. The charge redistribution AD converter 100 AD converts an input voltage using a plurality of sampling capacitors having different weights. The charge redistribution AD converter 100 includes a common line 10, a capacitor unit 20, a switching unit 30, a comparator 40, a reference voltage 50, a switching unit 60, an adjustment capacitor 70, a control unit 80, Is provided.

  The common line 10 connects between the capacitor unit 20 and the comparator 40, and transmits the input voltage from the capacitor unit 20 to the comparator 40. The charge redistribution AD converter 100 operates so that the voltage of the common line 10 and the reference voltage 50 are substantially matched.

The capacitor unit 20 includes a plurality of sampling capacitors, and FIG. 1 illustrates an example having a total of seven sampling capacitors from C0 to C6. Each of the plurality of sampling capacitors has, for example, a predetermined capacitance value 2 ⁿ times the predetermined first unit capacitance Cu (n is an integer of 0 or more). FIG. 1 shows that among seven sampling capacitors, C0 and C1 have a capacitance value Cu, C2 has a capacitance value 2Cu, C3 has a capacitance value 4Cu, C4 has a capacitance value 8Cu, C5 has a capacitance value 16Cu, and C6 has The example which has each capacitance value 32Cu is shown.

  Each of the plurality of sampling capacitors has a first end connected to the common line 10 and a second end connected to the positive reference voltage VRP, the negative reference voltage VRN, or an analog signal via the switching unit 30. . Here, the positive-side reference voltage VRP and the negative-side reference voltage VRN are voltages that serve as a reference for determining the input amplitude of the charge redistribution AD converter 100. In the configuration of this embodiment, VRP− VRN is the input amplitude.

  The capacitor unit 20 samples an analog signal input to the charge redistribution AD converter 100 in the sample mode. On the other hand, in the hold mode, either the positive reference voltage VRP or the negative reference voltage VRN is input to each of the second ends of the plurality of sampling capacitors, and the difference between the input signal and the reference voltage is input to the common line 10. A voltage corresponding to the voltage is output. This differential voltage is supplied as an input voltage to the comparator 40.

  The switching unit 30 switches the signal voltage supplied to the capacitor unit 20. The switching unit 30 includes a plurality of switch elements corresponding to the plurality of sampling capacitors of the capacitor unit 20. FIG. 1 shows an example in which the switching unit 30 has a total of seven switching elements SW0 to SW6 corresponding to the seven sampling capacitors of the capacitor unit 20.

  The plurality of switch elements may be CMOS switches. Each of the plurality of switch elements may supply either the input signal VI or the negative reference voltage VRN to the corresponding sampling capacitor according to the control signal to be input. As an example, the switching element SW0 supplies either the input signal VI or the negative reference voltage VRN to the corresponding sampling capacitor C0 according to the control signal.

  In addition, each of the plurality of switch elements may supply any one of the input signal VI, the positive reference voltage VRP, and the negative reference voltage VRN to the corresponding sampling capacitor in accordance with the input control signal. Good. As an example, each of the switching elements SW1 to SW6 causes the input signal VI, the positive reference voltage VRP, or the negative reference voltage VRN to be applied to the corresponding sampling capacitors C1 to C6, respectively, according to the control signal. Supply.

  The comparator 40 compares the input voltage from the common line 10 with the reference voltage 50. The comparator 40 may be a comparator. The reference voltage 50 is 0 V in this embodiment. The comparator 40 supplies the comparison result to the control unit 80.

  The switcher 60 switches whether or not the common line 10 and the reference voltage 50 are electrically connected. For example, the switcher 60 electrically connects the common line 10 and the reference voltage 50 in the sample mode. In this case, the switcher 60 electrically disconnects between the common line 10 and the reference voltage 50 in the hold mode.

  The adjustment capacitor 70 is connected between the common line 10 and the reference voltage 50. One end of the adjustment capacitor 70 on the side connected to the common line 10 may be connected between the capacitor unit 20 and the comparator 40 in the common line 10. Further, the other end of the adjustment capacitor 70 may be connected to the reference voltage 50. Note that the other end of the adjustment capacitor 70 may be connected to a reference voltage having a voltage value different from the reference voltage 50. The adjustment capacitor 70 may adjust the voltage level of the input voltage transmitted to the comparator 40 according to the operating range of the switch 60. The adjustment capacitor 70 may attenuate and adjust the input voltage transmitted to the switch 60 according to the capacitance value.

  The control unit 80 controls the switching unit 30 according to the comparison result of the comparator 40. The control unit 80 generates a control signal for controlling switching of the plurality of switch elements of the switching unit 30 and supplies the control signal to the corresponding switch elements. For example, in the sample mode, the control unit 80 supplies the control signals to the plurality of switch elements so as to supply the input signal VI to the plurality of sampling capacitors of the capacitor unit 20, respectively. In this case, the control unit 80 supplies a control signal corresponding to the comparison result of the comparator 40 to each of the plurality of switch elements in the hold mode.

  The charge redistribution AD converter 100 described above switches between the sample mode and the hold mode in synchronization with a clock signal or the like, and converts an input analog signal into a digital signal. For example, in the sample mode, the switch 60 electrically connects the common line 10 and the reference voltage 50, and each of the switching elements SW0 to SW6 supplies the input signal VI to the corresponding sampling capacitor. That is, each of the plurality of sampling capacitors C0 to C6 has one end connected to the reference voltage 50 and the other end connected to the input signal VI.

  When switching to the hold mode, the switch 60 electrically disconnects between the common line 10 and the reference voltage 50, so that each of the plurality of sampling capacitors C0 to C6 holds a charge corresponding to the input signal VI. become. In the example of FIG. 1, the sampling capacitors C0 and C1 are Cu · VI, C2 is 2Cu · VI, C3 is 4Cu · VI, C4 is 8Cu · VI, C5 is 16Cu · VI, and C6 is 32Cu. -The charge of VI is retained.

  Then, the control unit 80 connects the switching elements SW0 to SW6 to the positive reference voltage VRP in order from the switching element corresponding to the sampling capacitor having the larger weight (ie, capacitance value). For example, the controller 80 switches from SW0 to SW6, connects the positive reference voltage VRP to the other end of the sampling capacitor C6, and connects the negative reference voltage VRN to the other ends of the sampling capacitors C0 to C5. In this case, since the differential voltage VI−0.5 · (VRP−VRN) between the input voltage VI and the reference voltage is output to the common line 10, the comparator 40 outputs the differential voltage and the reference voltage 50 (main voltage). In the embodiment, 0V) is compared.

  When the difference voltage is positive, the comparison result of the comparator 40 is a result of the input voltage being larger, so the control unit 80 sets the most significant bit (MSB) to the comparison result (high potential) and sets SW6 to the positive side. And remain connected to the reference voltage VRP. When the differential voltage is negative, the comparison result of the comparator 40 is smaller than the input voltage. Therefore, the control unit 80 sets the MSB as the comparison result (low potential) and sets SW6 as the negative reference. Switch to voltage VRN. Then, the control unit 80 switches the switching element SW5 corresponding to the sampling capacitor C5 having the next highest weight, and connects the positive reference voltage VRP to the other end of the sampling capacitor C5. The control unit 80 may be configured with a logic circuit or the like.

  In this way, the charge redistribution AD converter 100 determines the bit value from the MSB according to the comparison result of the comparator 40 based on the binary search, and references each of the sampling capacitors C6 to C1 on the positive side. It is selected whether to connect to either the voltage VRP or the negative reference voltage VRN. That is, the control unit 80 controls the reference voltage connected to each sampling capacitor so that the differential voltage finally output to the common line 10 is substantially equal to the reference voltage 50. Then, each comparison result of the comparator 40 becomes digital data that is AD-converted from the MSB side in order.

In the example of FIG. 1, since the capacitor unit 20 has six types (n = 1, 2,..., 6) of capacitance values ²ⁿ times the first unit capacitance Cu, 6-bit charge redistribution AD conversion is performed. The device 100 is configured. Thus, the charge redistribution AD converter 100 can configure a multi-bit AD converter according to the plurality of sampling capacitors of the capacitor unit 20. Note that the size of the first unit capacitance Cu of the plurality of sampling capacitors used in the charge redistribution AD converter 100 is determined by, for example, the required accuracy of thermal noise or linearity, whichever is stricter. .

Here, the thermal noise generated by the switching operation of the switching unit 30 to the capacitor unit 20 is calculated as follows. Here, k is a Boltzmann constant, T is an absolute temperature, and Cs is a combined capacity of the capacitor unit 20. In the case of FIG. 1, Cs indicates a combined capacity from the capacity C0 to C6.

In addition, the linearity error becomes maximum before and after the code is switched from 31 to 32 in the case of the 6-bit charge redistribution AD converter 100 of FIG. Here, assuming that the mismatch error of the first unit capacity Cu is ε, the error ε _{31 → 32} in which the code is switched from 31 to 32 is calculated as follows. Note that it is known that ε depends on the manufacturing process of the capacitor portion 20, the area of the capacitor, and the like, and decreases in inverse proportion to the square root of the area.

In general, if the required accuracy of noise and linearity is approximately the same, the design that satisfies the linearity requirement is often stricter. In this case, the first unit capacitance Cu has a size that satisfies the linearity requirement. Set to In this case, the input capacitance Cinput as viewed from the input side of the charge redistribution AD converter 100 from the buffer or the like that drives the charge redistribution AD converter 100 is the capacitance connected to the input side in the sample mode. Combined capacity. Here, the combined capacity is calculated as follows.

  Since the charge redistribution AD converter 100 does not have an amplifier or the like that amplifies an input signal unlike the pipeline AD converter, the requirement of design accuracy for the capacitor unit 20 becomes severe. That is, an increase in the capacity of the capacitor unit 20 directly leads to an increase in the input capacity, which may cause problems due to an increase in the load on the preceding buffer and kickback noise.

  In order to solve such a problem, it has been proposed to perform the trimming of the capacitance value of the capacitance unit 20 in the manufacturing process, the calibration of the capacitance value by digital calculation, and the like. However, the trimming process may cause an increase in the manufacturing unit cost, and the addition of calibration logic may increase the chip cost and restrict the usage method.

  On the other hand, the charge redistribution AD converter according to the present embodiment value satisfies the linearity requirement specification and does not perform the capacitance value trimming and calibration operations, and reduces the input capacitance. I will provide a. Such an AD converter will be described next.

  FIG. 2 shows a configuration example of the charge redistribution AD converter 200 according to the present embodiment. In the charge redistribution AD converter 200 of the present embodiment, the same reference numerals are given to substantially the same operations as those of the charge redistribution AD converter 100 shown in FIG. The charge redistribution AD converter 200 further includes a first capacitor 210.

The first capacitor 210 is connected in series between the comparator 40 and all the sampling capacitors that sample the analog signal on the common line 10. The first capacitor 210 may be connected between the capacitor unit 20 and the adjustment capacitor 70. In this case, the adjustment capacitor 70 is connected between the portion between the first capacitor 210 and the comparator 40 on the common line 10 and the reference voltage 50. Here, assuming that the capacitance of the first capacitor 210 is Cx, the thermal noise Vn in the equation (1) is expressed as the following equation by the insertion of the first capacitor 210.

The error ε _{31 → 32 in the} equation (2) is similarly expressed as the following equation.

Further, the combined capacity Cinput of the equation (3) is expressed as the following equation.

  That is, the charge redistribution AD converter 200 according to the present embodiment has no change in linearity error as compared with the charge redistribution AD converter 100 shown in FIG. 1, but the thermal noise Vn and the input capacitance Cinput. It can be seen that changes according to the value of the capacitance Cx. The relationship between such a capacitance Cx, thermal noise Vn, and input capacitance Cinput is shown below.

  FIG. 3 shows an example of the relationship of the thermal noise Vn to the capacitance Cx of the charge redistribution AD converter 200 according to this embodiment. The horizontal axis in FIG. 3 indicates the capacitance Cx, and the vertical axis indicates the thermal noise Vn. FIG. 3 shows an example in which the combined capacitance Cs of the capacitor unit 20 is calculated as 10 pF, and the capacitance C7 of the adjustment capacitor 70 is calculated as 5 pF. As shown in FIG. 3, the thermal noise Vn deteriorates when the capacitance Cx is reduced. Therefore, when the thermal noise Vn is reduced, it is desirable to set the capacitance Cx to a larger value.

  FIG. 4 shows an example of the relationship between the input capacitance Cinput and the capacitance Cx of the charge redistribution AD converter 200 according to the present embodiment. The horizontal axis in FIG. 4 indicates the capacitance Cx, and the vertical axis indicates the input capacitance Cinput. FIG. 4 shows an example in which the combined capacitance Cs of the capacitance unit 20 is calculated as 10 pF and the capacitance C7 of the adjustment capacitor 70 is calculated as 5 pF, as in FIG. As shown in FIG. 4, when the capacitance Cx is increased, the input capacitance Cinput increases. Therefore, when the input capacitance Cinput is decreased, it is desirable to set the capacitance Cx to a smaller value.

  As described above, the charge redistribution AD converter 200 according to the present embodiment adjusts the thermal noise Vn and the input capacitance Cinput without changing the configuration of the capacitance unit 20 by inserting the first capacitor 210. can do. For example, the input capacitance Cinput is reduced without deteriorating the linearity error by reducing the capacitance Cx within a range in which the thermal noise Vn is allowed with respect to the first unit capacitance Cu determined from the linearity requirement or the like. be able to.

  From the example of FIG. 3, it can be seen that when the thermal noise Vn of 20.0 μVrms or less is allowed for the first unit capacitance Cu of 10 pF, the capacitance Cx can be reduced to about 10 pF. 4 that the input capacitance Cinput can be reduced to about 5 pF by setting the capacitance Cx to about 10 pF. That is, in the charge redistribution AD converter 200 according to the present embodiment, the thermal noise Vn is reduced to 20.0 μVrms by inserting the first capacitor 210 of about 10 pF into the capacitance unit 20 of the combined capacitance Cs of 10 pF. The input capacitance Cinput can be reduced to about 5 pF while maintaining the following.

  Since the first capacitor 210 is not involved in the linearity error ε at all, it is not necessary to consider matching with the plurality of sampling capacitors C0 to C6 of the capacitor unit 20. Therefore, the charge redistribution AD converter 200 can change the capacity of the first capacitor 210 according to the required specification.

  Further, the charge redistribution AD converter 200 according to the present embodiment can reduce the capacitance of the adjustment capacitor 70 by inserting the first capacitor 210. For example, when the adjustment amount is substantially the same as the adjustment amount (that is, the attenuation amount) of the adjustment capacitor 70 before the first capacitor 210 is inserted, the adjustment capacitor 70 may have a capacitance that is Cx / (Cs + Cx) times the size. Can be reduced to the same extent. Therefore, even if the first capacitor 210 is inserted, the total chip area of the charge redistribution AD converter 200 can be suppressed to the same level or slightly increased.

  As described above, the charge redistribution AD converter 200 according to the present embodiment can easily adjust the thermal noise Vn and the input capacitance Cinput by inserting the first capacitor 210. Therefore, the charge redistribution AD converter 200 satisfies the linearity requirement specification and reduces the input capacitance without performing the trimming and calibration operations of the capacitance value and preventing an increase in the chip area. can do.

  FIG. 5 shows a modification of the charge redistribution AD converter 200 according to the present embodiment. The charge redistribution AD converter 200 according to the modified example substantially uses the second unit capacitor Cu ′ having a capacity value larger than Cu when the first unit capacitor Cu is difficult to manufacture. The capacity unit 20 having the first unit capacity Cu can be configured. In this modification, the manufacturable second unit capacity Cu ′ is 8Cu.

  In this case, the sampling capacitors C4 to C6 of the capacitor unit 20 can be manufactured, but the sampling capacitors C0 to C3 cannot be manufactured. Therefore, the charge redistribution AD converter 200 of the present modification further includes a second capacitor 220 while making the sampling capacitors C0 to C3 have a capacitance value based on the second unit capacitance Cu ′ that can be manufactured.

  Here, the common line 10 is divided into a plurality of segments. One segment is connected to one or more sampling capacitors. That is, a part of the plurality of sampling capacitors may be connected to each of the plurality of segments obtained by dividing the common line 10. The capacity unit 20 may also be divided according to the common line. For example, one or more capacitors connected to one segment of the common line 10 may be one segment. FIG. 5 shows an example in which the capacity unit 20 is divided into a first segment 22 and a second segment 24.

  The first segment 22 includes sampling capacitors C0 to C3 having a capacitance value that is difficult to manufacture. That is, the first segment 22 has a plurality of sampling capacitors C0 to C3 using a second unit capacitance Cu ′ that can be manufactured. As an example, the capacitances of the plurality of sampling capacitors are C0 = C1 = Cu ′ = 8Cu, C2 = 2Cu ′ = 16Cu, and C3 = 4Cu ′ = 32Cu.

The second segment 24 includes sampling capacitors C4 to C6 having capacitance values that can be manufactured. As an example, the capacitances of the plurality of sampling capacitors are C4 = Cu ′ = 8Cu, C5 = 2Cu ′ = 16Cu, and C6 = 4Cu ′ = 32Cu. Thus, each of the plurality of sampling capacitors has a capacitance value ²ⁿ times the second unit capacitance Cu ′ having a capacitance value larger than that of the first unit capacitance Cu.

  The second capacitor 220 is connected in series between each of the plurality of segments on the common line 10. For example, the second capacitor 220 is connected in series between the first segment 22 and the second segment 24. The second capacitor 220 reduces the capacitance value of each of the plurality of sampling capacitors included in the first segment 22 by combining them. By adjusting the capacitance value of the second capacitor 220, the combined capacitance of each of the plurality of sampling capacitors included in the first segment 22 is set to a plurality of values using the first unit capacitance Cu smaller than the second unit capacitance Cu ′. The capacitance values of the sampling capacitors are substantially matched.

For example, assuming that the capacitance of the second capacitor 220 is Cc, the combined capacitances C0 ′ to C3 ′ of the plurality of sampling capacitors C0 to C3 of the first segment 22 are expressed by the following equations.

Here, as an example, by setting the capacitance Cc of the second capacitor 220 to 64 Cu / 7, the equation (7) is calculated as the following equation.

As described above, the capacitor unit 20 having the combination of the first segment 22 and the second capacitor 220 and the second segment 24 shown in the example of FIG. 5 is substantially the same as the capacitor unit 20 shown in the example of FIG. It turns out that it becomes a substantially identical structure. That is, the second capacitor 220 can have a combined capacitance with each of the sampling capacitors included in the first segment 22 to a capacitance value that is ²ⁿ times the first unit capacitance. Also in the charge redistribution AD converter 200 having such a configuration, by including the first capacitor 210, it is possible to adjust the thermal noise Vn and the input capacitance Cinput without changing the configuration of the capacitance unit 20.

  The various embodiments of the present invention described above may be described with reference to flowcharts and block diagrams. The blocks in the flowcharts and block diagrams may be expressed as (1) the stage of the process in which the operation is performed or (2) the “part” of the device responsible for performing the operation. Certain stages and “parts” are provided with dedicated circuitry, programmable circuitry supplied with computer readable instructions stored on a computer readable storage medium, and / or computer readable instructions stored on a computer readable storage medium. It may be implemented by a processor.

  Certain stages and “parts” are provided with dedicated circuitry, programmable circuitry supplied with computer readable instructions stored on a computer readable storage medium, and / or computer readable instructions stored on a computer readable storage medium. It may be implemented by a processor. Note that the dedicated circuit may include a digital and / or analog hardware circuit, and may include an integrated circuit (IC) and / or a discrete circuit. Programmable circuits may be logical products, logical sums, exclusive logical sums, negative logical products, negative logical sums, and other logical operations, such as field programmable gate arrays (FPGAs) and programmable logic arrays (PLA), for example. , Flip-flops, registers, and memory elements, including reconfigurable hardware circuitry.

  The computer readable storage medium may include any tangible device that can store instructions executed by a suitable device. Thereby, a computer readable storage medium having instructions stored on the tangible device comprises a product including instructions that can be executed to create a means for performing the operations specified in the flowchart or block diagram. become.

  Examples of computer readable storage media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, and the like. More specific examples of the computer-readable storage medium include a floppy disk, diskette, hard disk, random access memory (RAM), read only memory (ROM), and erasable programmable read only memory (EPROM or flash memory). Electrically erasable programmable read only memory (EEPROM), static random access memory (SRAM), compact disc read only memory (CD-ROM), digital versatile disc (DVD), Blu-ray (registered trademark) disc, memory stick Integrated circuit cards and the like may be included.

  Computer readable instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, and the like. Computer-readable instructions also include object-oriented programming languages such as Smalltalk, JAVA, C ++, etc., and conventional procedural programming languages such as the “C” programming language or similar programming languages, or It may include source code or object code written in any combination of multiple programming languages.

  The computer readable instructions may be a processor of a general purpose computer, special purpose computer, or other programmable data processing device, either locally or via a wide area network (WAN) such as a local area network (LAN), the Internet, etc. Or it may be provided in a programmable circuit. This allows a general purpose computer, special purpose computer, or other programmable data processing device processor, or programmable circuit to generate means for performing the operations specified in the flowchart or block diagram, Computer readable instructions can be executed. Note that examples of the processor include a computer processor, a processing unit, a microprocessor, a digital signal processor, a controller, a microcontroller, and the like.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 Common line, 20 Capacity | capacitance part, 22 1st segment, 24 2nd segment, 30 switching part, 40 comparator, 50 reference voltage, 60 switching part, 70 adjustment capacitor, 80 control part, 100 charge redistribution type AD converter , 200 charge redistribution AD converter, 210 first capacitor, 220 second capacitor

Claims (6)

A plurality of sampling capacitors, the first end of which is connected to the common line and the second end is input with an analog signal to sample the analog signal;
A comparator that compares an input voltage from the common line with a reference voltage;
A charge redistribution AD converter comprising: a first capacitor connected in series between all the sampling capacitors for sampling the analog signal and the comparator on the common line. A part of each of the plurality of sampling capacitors is connected to each of a plurality of segments obtained by dividing the common line,
The charge redistribution AD converter according to claim 1, further comprising a second capacitor connected in series between each of the plurality of segments on the common line. The charge redistribution AD converter according to claim 2, wherein each of the plurality of sampling capacitors has a capacitance value 2 ⁿ times a predetermined first unit capacitance. Each of the plurality of sampling capacitors has a capacitance value that is 2 ⁿ times the second unit capacitance, which has a capacitance value larger than the first unit capacitance.
The second capacitor is
Connected in series between a first segment to which a part of the plurality of sampling capacitors is connected and a second segment to which the rest of the plurality of sampling capacitors are connected;
The combined capacitance with each of the sampling capacitors connected to the first segment is a capacitance value ²ⁿ times the first unit capacitance,
The charge redistribution AD converter according to claim 3.   5. The charge redistribution AD converter according to claim 1, further comprising an adjustment capacitor having one end connected to a portion between the first capacitor and the comparator on the common line. 6. A plurality of sampling capacitors having a first end connected to the common line and an analog signal input to the second end sampling the analog signal;
Transmitting an input voltage based on the sampled analog signal through a first capacitor connected to all sampling capacitors for sampling the analog signal on the common line;
Comparing the input voltage from the common line with a reference voltage;
An AD conversion method.

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