JP2018133892A5 - - Google Patents
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- JP2018133892A5 JP2018133892A5 JP2017025164A JP2017025164A JP2018133892A5 JP 2018133892 A5 JP2018133892 A5 JP 2018133892A5 JP 2017025164 A JP2017025164 A JP 2017025164A JP 2017025164 A JP2017025164 A JP 2017025164A JP 2018133892 A5 JP2018133892 A5 JP 2018133892A5
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- gate
- voltage
- power semiconductor
- gate driving
- state
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- 239000004065 semiconductor Substances 0.000 claims 24
- 238000006243 chemical reaction Methods 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
Claims (12)
前記パワー半導体のゲートに印加する前記ゲート電圧を、前記オン指令を受けると第一の電圧に制御し、前記オフ指令を受けると第二の電圧に制御するゲート出力回路と、
前記オフ指令を検知することにより一定時間の信号を前記ゲート出力回路へ出力するタイマ回路と
を備え、
前記ゲート出力回路は、前記一定時間の信号を入力している間は前記ゲート電圧を前記第二の電圧よりも低い第三の電圧に制御する
ことを特徴とするゲート駆動装置。 A gate driving device that controls a gate voltage of a power semiconductor in response to a gate on command or a gate off command from a control logic unit,
The gate voltage applied to the gate of the power semiconductor is controlled to a first voltage when the on command is received, and is controlled to a second voltage when the off command is received;
A timer circuit that outputs a signal of a predetermined time to the gate output circuit by detecting the off command;
The gate output device, wherein the gate output circuit controls the gate voltage to a third voltage lower than the second voltage while the signal of the predetermined time is input.
前記ゲート電圧を監視して前記パワー半導体のオン／オフの状態を判定するオン／オフ状態判定回路と更に備え、
前記タイマ回路は、前記オフ指令に替えて前記オン／オフ状態判定回路が出力するオフ状態の判定を検知することにより前記一定時間の信号を前記ゲート出力回路へ出力する
ことを特徴とするゲート駆動装置。 The gate driving device according to claim 1,
An on / off state determination circuit for monitoring the gate voltage and determining an on / off state of the power semiconductor;
The timer circuit outputs a signal of the predetermined time to the gate output circuit by detecting a determination of an off state output from the on / off state determination circuit instead of the off command. apparatus.
前記パワー半導体が有する一対の主端子から一方の主端子の電圧を検出し、当該パワー半導体のオフ後に前記検出した電圧が変化するか否かを判定する主端子電圧判定回路を更に備え、
前記タイマ回路は、前記オン／オフ状態判定回路が出力するオフ状態の判定と前記主端子電圧判定回路が出力する前記検出した電圧が変化しないことの判定とを検知することにより、前記一定時間の信号を前記ゲート出力回路へ出力する
ことを特徴とするゲート駆動装置。 The gate driving device according to claim 2,
The power semiconductor to detect the voltage of one of the main terminals of a pair of main terminals having further comprising determining main terminal voltage judging circuit whether the detected voltage after the power semiconductor off changes,
The timer circuit, by detecting a determination that the detected voltage determines that the main terminal voltage judging circuit in the OFF state where the ON / OFF state judging circuit outputs the output does not change, the predetermined time A gate driving device characterized by outputting a signal to the gate output circuit.
前記パワー半導体が有する一対の主端子と一対の補助端子から一方の主端子と該一方の主端子側にある一方の補助端子間に発生する電圧を検出し、前記パワー半導体の主電流の変化の有無を判定する電流判定回路を更に備え、
前記タイマ回路は、前記オン／オフ状態判定回路が出力するオフ状態判定と前記電流判定回路が出力する前記主電流が変化しないことの判定とを検知することにより、前記一定時間の信号を前記ゲート出力回路へ出力する
ことを特徴とするゲート駆動装置。 The gate driving device according to claim 2,
A voltage generated between one main terminal and one auxiliary terminal on the one main terminal side is detected from a pair of main terminals and a pair of auxiliary terminals of the power semiconductor, and a change in the main current of the power semiconductor is detected. A current determination circuit for determining presence or absence;
The timer circuit detects the off state determination output from the on / off state determination circuit and the determination that the main current output from the current determination circuit does not change, and thereby outputs the signal for the predetermined time to the gate. A gate driving device that outputs to an output circuit.
当該ゲート駆動装置は、前記パワー半導体を上アームおよび下アームに備えて構成した電力変換装置を駆動し、
前記タイマ回路は、前記上アームおよび前記下アームが備える前記パワー半導体各々のオン／オフに伴うデッドタイムを一定にした状態で、前記一定時間の信号を前記ゲート出力回路へ出力するタイミングを調整する
ことを特徴とするゲート駆動装置。 The gate drive device according to any one of claims 1 to 4,
The gate driving device drives a power conversion device configured to include the power semiconductor in an upper arm and a lower arm,
The timer circuit, a dead time associated with prior Kipa Wah semiconductor respective on / off provided in the upper arm and the lower arm in a state of being fixed, the timing for outputting the signal of said predetermined time to said gate output circuit A gate driving device characterized by adjusting.
前記パワー半導体は、シリコンカーバイドで構成した半導体である
ことを特徴とするゲート駆動装置。 A gate driving device according to any one of claims 1 to 5,
The power semiconductors, a gate drive apparatus which is a semiconductor that is made of silicon car-by mode.
前記パワー半導体のゲートにオン指令が印加されると前記パワー半導体のゲート電圧を第一の電圧に制御し、
前記パワー半導体のゲートにオフ指令が印加されると前記ゲート電圧を第二の電圧に制御すると共に、当該オフ指令を検知すると一定時間の間は前記ゲート電圧を前記第二の電圧よりも低い第三の電圧に制御する
ことを特徴とするゲート駆動方法。 A gate driving method for controlling a gate voltage of a power semiconductor,
When an ON command is applied to the gate of the power semiconductor, the gate voltage of the power semiconductor is controlled to a first voltage,
When an off command is applied to the gate of the power semiconductor, the gate voltage is controlled to a second voltage, and when the off command is detected, the gate voltage is lower than the second voltage for a certain time. A gate driving method characterized by controlling to three voltages.
前記ゲート電圧を監視して前記パワー半導体のオン／オフの状態を判定し、
前記オフ指令を検知することに替えて前記オン／オフのオフ状態を判定した場合に、前記一定時間の間は前記ゲート電圧を前記第二の電圧よりも低い前記第三の電圧に制御する
ことを特徴とするゲート駆動方法。 The gate driving method according to claim 7, wherein
Monitoring the gate voltage to determine the on / off state of the power semiconductor;
When the on / off off state is determined instead of detecting the off command, the gate voltage is controlled to the third voltage lower than the second voltage for the predetermined time. A gate driving method characterized by the above.
前記パワー半導体が有する一対の主端子から一方の主端子の電圧を検出することで、当該パワー半導体のオフ後に前記検出した電圧が変化するか否かを判定し、
前記オフ状態を判定しかつ前記検出した電圧が変化しないことを判定することにより、前記一定時間の間は前記ゲート電圧を前記第二の電圧よりも低い前記第三の電圧に制御する
ことを特徴とするゲート駆動方法。 The gate driving method according to claim 8, wherein
Said power semiconductor to detect one of the voltage of the main terminal from the pair of main terminals has, determines whether voltage the detected after the power semiconductor off changes,
By determining that the determined off-state and voltage the detected does not change during said predetermined time controls said gate voltage to lower the third voltage than the second voltage The gate drive method.
前記パワー半導体が有する一対の主端子と一対の補助端子から一方の主端子と該一方の主端子側にある補助端子間に発生する電圧を検出することで、前記パワー半導体の主電流が変化するか否かを判定し、
前記オフ状態を判定しかつ前記主電流が変化しないことを判定することにより、前記一定時間の間は前記ゲート電圧を前記第二の電圧よりも低い前記第三の電圧に制御する
ことを特徴とするゲート駆動方法。 The gate driving method according to claim 8, wherein
The main current of the power semiconductor changes by detecting a voltage generated between one main terminal and the auxiliary terminal on the one main terminal side from a pair of main terminals and a pair of auxiliary terminals included in the power semiconductor. Whether or not
The gate voltage is controlled to the third voltage lower than the second voltage for the certain time by determining the off state and determining that the main current does not change. To drive the gate.
当該ゲート駆動方法により、前記パワー半導体を上アームおよび下アームに備えて構成した電力変換装置を駆動し、
前記上アームおよび前記下アームが備える前記パワー半導体各々のオン／オフに伴うデッドタイムを一定にした状態で、前記一定時間を設定するタイミングを調整する
ことを特徴とするゲート駆動方法。 A gate driving method according to any one of claims 7 to 10, wherein
By the gate driving method, driving a power conversion device configured to include the power semiconductor in an upper arm and a lower arm,
The dead time associated with prior Kipa Wah semiconductor respective on / off provided in the upper arm and the lower arm in a state of being fixed, the gate driving method characterized by adjusting the timing for setting the predetermined time.
前記パワー半導体として、シリコンカーバイドで構成した半導体を対象とする
ことを特徴とするゲート駆動方法。
The gate driving method according to any one of claims 7 to 11,
Wherein as the power semiconductor, a gate driving method characterized in that the target semiconductor constituted by silicon car-by mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017025164A JP6723175B2 (en) | 2017-02-14 | 2017-02-14 | Gate drive device and gate drive method for power semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017025164A JP6723175B2 (en) | 2017-02-14 | 2017-02-14 | Gate drive device and gate drive method for power semiconductor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018133892A JP2018133892A (en) | 2018-08-23 |
| JP2018133892A5 true JP2018133892A5 (en) | 2019-04-11 |
| JP6723175B2 JP6723175B2 (en) | 2020-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2017025164A Active JP6723175B2 (en) | 2017-02-14 | 2017-02-14 | Gate drive device and gate drive method for power semiconductor |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7118027B2 (en) | 2019-04-17 | 2022-08-15 | 三菱電機株式会社 | gate driver |
| CN110224690B (en) * | 2019-06-04 | 2021-05-28 | 西安交通大学 | SiC MOSFET series driving circuit |
| JP7384714B2 (en) * | 2020-03-11 | 2023-11-21 | 株式会社 日立パワーデバイス | Wiring circuits for semiconductor devices, methods for controlling wiring circuits for semiconductor devices, semiconductor devices, power conversion devices, and electrical systems for railway vehicles |
| US20230268819A1 (en) * | 2020-05-07 | 2023-08-24 | Kabushiki Kaisha Toyota Jidoshokki | Power conversion device |
| CN115913204B (en) * | 2023-03-08 | 2023-05-05 | 北京全路通信信号研究设计院集团有限公司 | Electronic switch and automatic control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408150A (en) * | 1992-06-04 | 1995-04-18 | Linear Technology Corporation | Circuit for driving two power mosfets in a half-bridge configuration |
| JP2005045590A (en) * | 2003-07-23 | 2005-02-17 | Mitsubishi Electric Corp | Semiconductor device |
| JP4380726B2 (en) * | 2007-04-25 | 2009-12-09 | 株式会社デンソー | Method for controlling vertical MOSFET in bridge circuit |
| JP6319045B2 (en) * | 2014-10-30 | 2018-05-09 | 株式会社デンソー | Semiconductor device drive circuit and semiconductor device drive system |
| JP2016167498A (en) * | 2015-03-09 | 2016-09-15 | 株式会社東芝 | Semiconductor device |
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