JP2018073878A - Board, and noise filter structure - Google Patents

Board, and noise filter structure Download PDF

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JP2018073878A
JP2018073878A JP2016208374A JP2016208374A JP2018073878A JP 2018073878 A JP2018073878 A JP 2018073878A JP 2016208374 A JP2016208374 A JP 2016208374A JP 2016208374 A JP2016208374 A JP 2016208374A JP 2018073878 A JP2018073878 A JP 2018073878A
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circuit
layer
circuit bodies
multilayer substrate
bodies
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鈴木 慎吾
Shingo Suzuki
慎吾 鈴木
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Yazaki Corp
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Yazaki Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a board capable of suppressing increase in size, and to provide a noise filter structure.SOLUTION: A board 1 to which a noise filter structure 100 is applied includes a multilayer board body 3 where multiple circuit bodies 33 constituting circuit systems different from each other are provided while being laminated via an isolating layer 32, and a magnetic substance 4 enclosing the outside of the multiple circuit bodies 33 collectively. With such an arrangement, the board 1 and the noise filter structure 100 can reduce noise of the multiple circuit bodies 33 collectively by the magnetic substance 4, and have an effect of suppressing increase in size while ensuring proper noise reduction performance.SELECTED DRAWING: Figure 1

Description

本発明は、基板、及び、ノイズフィルタ構造に関する。   The present invention relates to a substrate and a noise filter structure.

従来の基板に関連する技術として、例えば、特許文献1には、第1、第2の磁性体基板の間に積層体を設けて構成されたコイル部品が開示されている。積層体は、第1の絶縁層、1次コイル、コイル間絶縁層、2次コイル、第2の絶縁層等を積み重ねることによって形成される。そして、第1、第2の磁性体基板は、2つの磁性体層の間に低誘電率層を挟む構成とされる。この構成により、コイル部品は、各コイルの周囲に生じる電気力線の一部が低誘電率層の内部を通過し、各コイルの浮遊容量が低下する。   As a technique related to a conventional substrate, for example, Patent Document 1 discloses a coil component configured by providing a laminated body between first and second magnetic substrates. The laminate is formed by stacking a first insulating layer, a primary coil, an inter-coil insulating layer, a secondary coil, a second insulating layer, and the like. The first and second magnetic substrates are configured such that a low dielectric constant layer is sandwiched between two magnetic layers. With this configuration, in the coil component, part of the electric lines of force generated around each coil pass through the inside of the low dielectric constant layer, and the stray capacitance of each coil is reduced.

特開2010−062386号公報JP 2010-062386

ところで、従来の基板は、例えば、ノイズ低減用の部品が付加されたものがあるが、近年、ノイズの低減が要求される回路が相対的に増加することで基板全体が相対的に大型化する傾向にあり、この点で更なる改善の余地がある。   By the way, there is a conventional substrate to which, for example, a noise reduction component is added, but in recent years, the number of circuits that are required to reduce noise is relatively increased, so that the entire substrate becomes relatively large. There is room for further improvement in this regard.

本発明は、上記の事情に鑑みてなされたものであって、大型化を抑制することができる基板、及び、ノイズフィルタ構造を提供することを目的とする。   This invention is made | formed in view of said situation, Comprising: It aims at providing the board | substrate which can suppress an enlargement, and a noise filter structure.

上記目的を達成するために、本発明に係る基板は、相互に異なる回路系統を構成する複数の回路体が絶縁層を介して積層されて設けられる多層基板本体と、前記複数の回路体の外側を当該回路体の延在方向周りに一括で包囲する磁性体とを備えることを特徴とする。   In order to achieve the above object, a substrate according to the present invention includes a multilayer substrate body in which a plurality of circuit bodies constituting mutually different circuit systems are provided via an insulating layer, and an outer side of the plurality of circuit bodies. And a magnetic body that collectively surrounds the extending direction of the circuit body.

また、上記基板では、前記多層基板本体は、前記複数の回路体の積層方向に沿って貫通し前記磁性体が挿通される貫通孔を有するものとすることができる。   In the above substrate, the multilayer substrate body may have a through-hole penetrating along the stacking direction of the plurality of circuit bodies and through which the magnetic body is inserted.

また、上記基板では、前記磁性体は、複数の分割体を組み合わせることで前記複数の回路体の外側を当該回路体の延在方向周りに一括で包囲する環状に形成されるものとすることができる。   In the substrate, the magnetic body may be formed in an annular shape that collectively surrounds the outside of the plurality of circuit bodies around the extending direction of the circuit bodies by combining a plurality of divided bodies. it can.

また、上記基板では、前記複数の回路体は、電力伝送用の電源パターン、及び、接地用のGNDパターンを含むものとすることができる。   In the substrate, the plurality of circuit bodies may include a power transmission power pattern and a ground GND pattern.

また、上記基板では、前記複数の回路体は、さらに信号通信用の信号線を含むものとすることができる。   In the substrate, the plurality of circuit bodies may further include signal lines for signal communication.

上記目的を達成するために、本発明に係るノイズフィルタ構造は、相互に異なる回路系統を構成する複数の回路体が絶縁層を介して積層されて設けられる多層基板本体を前記複数の回路体の積層方向に沿って貫通して設けられる貫通孔と、前記貫通孔を介して前記多層基板本体に組み付けられ、前記複数の回路体の外側を当該回路体の延在方向周りに一括で包囲する磁性体とを備えることを特徴とする。   In order to achieve the above object, a noise filter structure according to the present invention includes a multilayer substrate body in which a plurality of circuit bodies constituting mutually different circuit systems are stacked via an insulating layer. A through hole provided penetrating along the stacking direction, and a magnet that is assembled to the multilayer substrate body via the through hole and collectively surrounds the outside of the plurality of circuit bodies around the extending direction of the circuit body And a body.

本発明に係る基板、及び、ノイズフィルタ構造は、多層基板本体に絶縁層を介して積層されて設けられ相互に異なる回路系統を構成する複数の回路体の外側を磁性体によって一括で包囲する。この構成により、基板、及び、ノイズフィルタ構造は、磁性体によって当該複数の回路体のノイズを一括で低減することができるので、大型化を抑制することができる、という効果を奏する。   The substrate and the noise filter structure according to the present invention are provided by laminating an insulating layer on a multilayer substrate body, and collectively surround the outside of a plurality of circuit bodies constituting different circuit systems with a magnetic material. With this configuration, the substrate and the noise filter structure can reduce the noise of the plurality of circuit bodies in a lump by the magnetic body, so that an increase in size can be suppressed.

図1は、実施形態に係る基板の概略構成を表す部分断面図である。FIG. 1 is a partial cross-sectional view illustrating a schematic configuration of a substrate according to the embodiment. 図2は、実施形態に係る基板の概略構成を表す部分断面図である。FIG. 2 is a partial cross-sectional view illustrating a schematic configuration of the substrate according to the embodiment. 図3は、実施形態に係る基板の概略構成を表す模式的な平面図である。FIG. 3 is a schematic plan view illustrating a schematic configuration of the substrate according to the embodiment. 図4は、実施形態に係る基板における層間容量について説明する模式図である。FIG. 4 is a schematic diagram for explaining the interlayer capacitance in the substrate according to the embodiment.

以下に、本発明に係る実施形態を図面に基づいて詳細に説明する。なお、この実施形態によりこの発明が限定されるものではない。また、下記実施形態における構成要素には、当業者が置換可能かつ容易なもの、あるいは実質的に同一のものが含まれる。なお、以下で説明する図1は、図3に示すA−A断面図に相当する。図2は、図3に示すB−B断面図に相当する。   Embodiments according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited by this embodiment. In addition, constituent elements in the following embodiments include those that can be easily replaced by those skilled in the art or those that are substantially the same. Note that FIG. 1 described below corresponds to the AA cross-sectional view shown in FIG. 3. FIG. 2 corresponds to the BB cross-sectional view shown in FIG.

[実施形態]
図1、図2、図3に示す基板1は、種々の電子部品2が実装され、例えば、自動車等の車両に搭載される種々の電子部品ユニットに適用されるものである。本実施形態の基板1は、種々の電子部品2が実装された多層基板本体3にノイズフィルタ構造100が適用されたノイズフィルタ付基板を構成する。以下、各図を参照して基板1の各構成について詳細に説明する。
[Embodiment]
A substrate 1 shown in FIGS. 1, 2, and 3 is mounted with various electronic components 2, and is applied to various electronic component units mounted on a vehicle such as an automobile, for example. The substrate 1 of this embodiment constitutes a noise filter-equipped substrate in which a noise filter structure 100 is applied to a multilayer substrate body 3 on which various electronic components 2 are mounted. Hereafter, each structure of the board | substrate 1 is demonstrated in detail with reference to each figure.

なお、以下の説明では、互いに交差する第1方向、第2方向、及び、第3方向のうち、第1方向を「積層方向X」といい、第2方向を「第1幅方向Y」といい、第3方向を「第2幅方向Z」という。ここでは、積層方向Xと第1幅方向Yと第2幅方向Zとは、相互に直交する。積層方向Xは、典型的には、多層基板本体3の各層が積層される方向に相当する。以下の説明で用いる各方向は、特に断りのない限り、各部が相互に組み付けられた状態での方向を表すものとする。   In the following description, among the first direction, the second direction, and the third direction intersecting with each other, the first direction is referred to as “lamination direction X”, and the second direction is referred to as “first width direction Y”. The third direction is called “second width direction Z”. Here, the stacking direction X, the first width direction Y, and the second width direction Z are orthogonal to each other. The stacking direction X typically corresponds to the direction in which the layers of the multilayer substrate body 3 are stacked. Each direction used in the following description represents a direction in a state where the respective parts are assembled to each other unless otherwise specified.

具体的には、基板1は、電子部品2と、多層基板本体3と、ノイズフィルタ構造100と備える。ノイズフィルタ構造100は、多層基板本体3に形成された貫通孔35と、磁性体4とを備える。   Specifically, the substrate 1 includes an electronic component 2, a multilayer substrate body 3, and a noise filter structure 100. The noise filter structure 100 includes a through hole 35 formed in the multilayer substrate body 3 and the magnetic body 4.

電子部品2は、多層基板本体3に実装され種々の機能を発揮する素子である。電子部品2は、例えば、ヒューズ、コンデンサ、リレー、抵抗、トランジスタ、トランス、コイル、IPS(Intelligent Power Switch)、ECU(Electronic Control Unit)・マイコン等を含む電子制御ユニット、各種センサ素子、LED(Light Emitting Diode)素子、スピーカ等であるがこれに限られない。電子部品2は、例えば、後述する磁性体4の第2幅方向Zの両側に設けられるフィルタ用のコンデンサ等を含んでいてもよい。   The electronic component 2 is an element that is mounted on the multilayer substrate body 3 and exhibits various functions. The electronic component 2 includes, for example, an electronic control unit including a fuse, a capacitor, a relay, a resistor, a transistor, a transformer, a coil, an IPS (Intelligent Power Switch), an ECU (Electronic Control Unit) and a microcomputer, various sensor elements, and an LED (Light Emitting Diode) element, speaker, etc., but is not limited to this. The electronic component 2 may include, for example, filter capacitors provided on both sides in the second width direction Z of the magnetic body 4 to be described later.

多層基板本体3は、種々の電子部品2が実装され、これらを電気的に接続する電子回路を構成するものである。多層基板本体3は、板厚方向が積層方向Xに沿う略矩形板状に形成され、第1幅方向Y、及び、第2幅方向Zに沿って延在して形成される。ここでは、多層基板本体3は、積層方向Xの両側の主面がそれぞれ実装面31を構成し、各実装面31に電子部品2が実装される。本実施形態の多層基板本体3は、いわゆるプリント回路基板(Printed Circuit Board)である。すなわち、多層基板本体3は、エポキシ樹脂、ガラスエポキシ樹脂、紙エポキシ樹脂やセラミック等の絶縁性の材料からなる絶縁層32に、銅等の導電性の材料によって配線パターン(プリントパターン)が印刷されることで当該配線パターンによって回路体33が構成される。多層基板本体3は、当該多層基板本体3を積層方向Xに沿って貫通して形成されるスルーホール等に電子部品2のリード線や端子が挿入されハンダ付け等によって回路体33に電気的に接続されることで各実装面31に当該電子部品2が実装される。回路体33は、複数の電子部品2を電気的に接続し、要求される機能に応じた回路系統を構成する。   The multilayer substrate main body 3 constitutes an electronic circuit on which various electronic components 2 are mounted and electrically connected to each other. The multilayer substrate body 3 is formed in a substantially rectangular plate shape whose plate thickness direction is along the stacking direction X, and is extended along the first width direction Y and the second width direction Z. Here, in the multilayer substrate body 3, the principal surfaces on both sides in the stacking direction X constitute the mounting surfaces 31, and the electronic component 2 is mounted on each mounting surface 31. The multilayer substrate body 3 of the present embodiment is a so-called printed circuit board. That is, the multilayer substrate body 3 has a wiring pattern (print pattern) printed on a conductive material such as copper on an insulating layer 32 made of an insulating material such as epoxy resin, glass epoxy resin, paper epoxy resin, or ceramic. Thus, the circuit body 33 is configured by the wiring pattern. The multilayer substrate body 3 is electrically connected to the circuit body 33 by soldering or the like by inserting lead wires and terminals of the electronic component 2 into through holes formed through the multilayer substrate body 3 along the stacking direction X. The electronic component 2 is mounted on each mounting surface 31 by being connected. The circuit body 33 electrically connects the plurality of electronic components 2 and configures a circuit system corresponding to the required function.

そして、本実施形態の多層基板本体3は、相互に異なる回路系統を構成する複数の回路体33が絶縁層32を介して積層されて設けられる。すなわち、多層基板本体3は、回路体33が印刷された絶縁層32を複数積層させることで、複数の絶縁層32と複数の回路体33とが交互に積層されて多層化されたいわゆる多層基板を構成する。ここでは、多層基板本体3は、5層分の絶縁層32に対して交互に回路体33による導体層が積層されることで、当該回路体33による導体層が6層分積層されている。すなわち、多層基板本体3は、5層分の絶縁層32の間にそれぞれ1層分の回路体33による導体層が介在すると共に、積層方向Xの両最表面にそれぞれ1層分の回路体33による導体層が設けられることで、当該回路体33による導体層が6層分積層されている。当該回路体33による導体層は、多層基板本体3において、積層方向Xの一方側から他方側に向かって第1層34A、第2層34B、第3層34C、第4層34D、第5層34E、第6層34Fの順に積層されて構成される。そして、第1層34A、第2層34B、第3層34C、第4層34D、第5層34E、及び、第6層34Fを構成する各回路体33は、それぞれ相互に異なる回路系統、すなわち、合計6つの独立した回路系統を構成する。   In the multilayer substrate body 3 of the present embodiment, a plurality of circuit bodies 33 constituting different circuit systems are stacked with an insulating layer 32 interposed therebetween. That is, the multilayer substrate main body 3 is a so-called multilayer substrate in which a plurality of insulating layers 32 on which circuit bodies 33 are printed are stacked so that a plurality of insulating layers 32 and a plurality of circuit bodies 33 are alternately stacked. Configure. Here, the multilayer substrate main body 3 is formed by alternately laminating conductor layers of the circuit bodies 33 on the five insulating layers 32, so that six conductor layers of the circuit bodies 33 are laminated. That is, the multilayer substrate main body 3 includes a conductor layer formed by one circuit body 33 between five insulating layers 32 and one circuit body 33 on each outermost surface in the stacking direction X. As a result, the conductor layers of the circuit body 33 are stacked for six layers. The conductor layers of the circuit body 33 are the first layer 34A, the second layer 34B, the third layer 34C, the fourth layer 34D, and the fifth layer in the multilayer substrate body 3 from one side to the other side in the stacking direction X. 34E and the sixth layer 34F are stacked in this order. The circuit bodies 33 constituting the first layer 34A, the second layer 34B, the third layer 34C, the fourth layer 34D, the fifth layer 34E, and the sixth layer 34F have different circuit systems, that is, A total of six independent circuit systems are configured.

ここでは、一例として、第1層34A、及び、第6層34Fは、回路系統としてそれぞれ独立した信号層を構成し、各回路体33がそれぞれ信号通信用の信号線33a、33fを構成する。信号線33a、33fは、基板1に接続される各種機器に各種信号を供給するための伝送路である。第2層34B、及び、第5層34Eは、回路系統としてそれぞれ独立した接地(GND)層を構成し、各回路体33がそれぞれ接地用のGNDパターン(GND線)33b、33eを構成する。GNDパターン33b、33eは、基板1に接続される各種機器のいわゆるアース(接地)をとるための伝送路である。第3層34C、及び、第4層34Dは、回路系統としてそれぞれ独立した電源層を構成し、各回路体33がそれぞれ電力伝送用の電源パターン(電源線)33c、33dを構成する。電源パターン33c、33dは、基板1に接続される各種機器に所定の電圧の電力を伝送するための伝送路である。つまりここでは、多層基板本体3は、積層方向Xの一方側から他方側に向かって第1層34Aによる信号層、第2層34Bによる接地層、第3層34Cによる電源層、第4層34Dによる電源層、第5層34Eによる接地層、第6層34Fによる信号層の順で積層されている。なお、電源パターン33cと電源パターン33dとは、それぞれ相互に異なる電圧の電力を伝送するための伝送路を構成してもよく、例えば、一方が12Vの電力を伝送する12V電源系を構成し、他方が48Vの電力を伝送する48V電源系を構成するようにしてもよい。またここでは、GNDパターン33bとGNDパターン33eとは、典型的には、大電流に対応すべく2系統設けられており、例えば、一方が12V電源系に対応し、他方が48V電源系に対応して構成されてもよい。また、信号線33aと信号線33fとは、例えば、比較的に多くの信号を伝送可能とするため2系統設けられている。なお、多層基板本体3は、図1、図2では、第1層34Aの回路体33が一方の実装面31に露出して設けられ、第6層34Fの回路体33が他方の実装面31に露出して設けられるものとして図示しているがこれに限らない。多層基板本体3は、第1層34Aの回路体33、又は、第6層34Fの回路体33の一方、あるいは、両方が絶縁層32による層内に内蔵されて設けられるような位置関係で各層が積層されていてもよい。   Here, as an example, the first layer 34A and the sixth layer 34F constitute independent signal layers as a circuit system, and the circuit bodies 33 constitute signal lines 33a and 33f for signal communication, respectively. The signal lines 33 a and 33 f are transmission paths for supplying various signals to various devices connected to the substrate 1. The second layer 34B and the fifth layer 34E constitute an independent ground (GND) layer as a circuit system, and the circuit bodies 33 constitute ground GND patterns (GND lines) 33b and 33e, respectively. The GND patterns 33b and 33e are transmission paths for so-called grounding (grounding) of various devices connected to the substrate 1. The third layer 34C and the fourth layer 34D constitute independent power supply layers as a circuit system, and the circuit bodies 33 constitute power transmission power supply patterns (power supply lines) 33c and 33d, respectively. The power supply patterns 33 c and 33 d are transmission paths for transmitting power of a predetermined voltage to various devices connected to the substrate 1. That is, here, the multilayer substrate body 3 includes a signal layer by the first layer 34A, a ground layer by the second layer 34B, a power supply layer by the third layer 34C, and a fourth layer 34D from one side to the other side in the stacking direction X. Are stacked in this order: a power source layer, a ground layer by the fifth layer 34E, and a signal layer by the sixth layer 34F. In addition, the power supply pattern 33c and the power supply pattern 33d may constitute transmission paths for transmitting power of mutually different voltages, for example, one of which constitutes a 12V power supply system that transmits 12V of power, The other may constitute a 48V power supply system that transmits 48V power. In addition, here, the GND pattern 33b and the GND pattern 33e are typically provided in two systems to cope with a large current. For example, one corresponds to a 12V power supply system and the other corresponds to a 48V power supply system. May be configured. The signal line 33a and the signal line 33f are, for example, provided in two systems so that a relatively large number of signals can be transmitted. 1 and 2, the multilayer substrate body 3 is provided with the circuit body 33 of the first layer 34A exposed on one mounting surface 31, and the circuit body 33 of the sixth layer 34F is provided on the other mounting surface 31. However, the present invention is not limited to this. The multilayer substrate body 3 is arranged in such a positional relationship that one or both of the circuit body 33 of the first layer 34A and the circuit body 33 of the sixth layer 34F are provided in the layer made of the insulating layer 32. May be laminated.

多層基板本体3は、上記のような層構成とされることで、ノイズが相対的に大きくなる傾向にある各電源層(第3層34C、第4層34D)を一対の接地層(第2層34B、第5層34E)によって挟み込むことができる。また、多層基板本体3は、上記のような層構成とされることで、電源層、接地層と比較して流れる電流が相対的に小さい信号層(第1層34A、第6層34F)を当該層構成における外側の層とすることができる。この結果、多層基板本体3は、この層構成により、大電流によるノイズの影響を最小限に抑制可能な構成とすることができる。   Since the multilayer substrate body 3 has the above-described layer structure, each power supply layer (the third layer 34C and the fourth layer 34D) that tends to have a relatively large noise is used as a pair of ground layers (second layer). Layer 34B, fifth layer 34E). In addition, the multilayer substrate body 3 has a layer structure as described above, so that a signal layer (first layer 34A, sixth layer 34F) in which a flowing current is relatively small compared to the power supply layer and the ground layer is provided. It can be an outer layer in the layer configuration. As a result, the multilayer substrate body 3 can be configured to be able to suppress the influence of noise due to a large current to a minimum by this layer configuration.

そして、本実施形態の多層基板本体3は、ノイズフィルタ構造100の一部を構成する貫通孔35を有する。貫通孔35は、多層基板本体3を複数の回路体33の積層方向Xに沿って貫通して設けられる中空部分である。貫通孔35は、後述する磁性体4が挿通され組み付けられる部分を構成する。ここでは、貫通孔35は、積層方向Xと直交する第1幅方向Yに対して間隔をあけて一対で形成される(以下、一対の貫通孔35を区別する場合には、一方を「貫通孔35A」といい、他方を「貫通孔35B」という場合がある。)。各貫通孔35は、積層方向Xと直交する方向の断面形状が略矩形状に形成される。一対の貫通孔35、すなわち、貫通孔35Aと貫通孔35Bとは、第1幅方向Yに対して、多層基板本体3におけるノイズ低減対象部位101を挟んで対向して位置する。ノイズ低減対象部位101とは、多層基板本体3において磁性体4によるノイズ低減の対象となる複数の回路体33を含む部位である。言い換えれば、多層基板本体3は、第1幅方向Yに対して貫通孔35Aと貫通孔35Bとに挟まれた部位が、磁性体4によるノイズ低減の対象となる複数の回路体33を含むノイズ低減対象部位101となる。多層基板本体3は、当該ノイズ低減対象部位101においても、上述したように信号線33a、33f、GNDパターン33b、33e、電源パターン33c、33dを構成する6層分の回路体33が積層されている。   The multilayer substrate body 3 of the present embodiment has a through hole 35 that constitutes a part of the noise filter structure 100. The through-hole 35 is a hollow portion provided through the multilayer substrate body 3 along the stacking direction X of the plurality of circuit bodies 33. The through hole 35 constitutes a portion into which a magnetic body 4 described later is inserted and assembled. Here, the through-holes 35 are formed in pairs with a gap in the first width direction Y orthogonal to the stacking direction X (hereinafter, when distinguishing between a pair of through-holes 35, It may be referred to as “hole 35A” and the other may be referred to as “through hole 35B”.) Each through-hole 35 has a substantially rectangular cross-sectional shape in a direction orthogonal to the stacking direction X. The pair of through holes 35, that is, the through hole 35 </ b> A and the through hole 35 </ b> B are positioned to face the first width direction Y across the noise reduction target portion 101 in the multilayer substrate body 3. The noise reduction target portion 101 is a portion including a plurality of circuit bodies 33 that are targets of noise reduction by the magnetic body 4 in the multilayer substrate body 3. In other words, the multilayer substrate main body 3 includes a plurality of circuit bodies 33 in which a portion sandwiched between the through hole 35A and the through hole 35B in the first width direction Y includes noise reduction targets by the magnetic body 4. It becomes the reduction target part 101. As described above, the multilayer substrate body 3 includes the circuit bodies 33 for six layers constituting the signal lines 33a and 33f, the GND patterns 33b and 33e, and the power supply patterns 33c and 33d as described above. Yes.

磁性体4は、複数の回路体33の外側を当該回路体33の延在方向周りに一括で包囲することで、各回路体33におけるノイズを低減するものである。回路体33の延在方向は、多層基板本体3のノイズ低減対象部位101において、回路体33が延在する方向(回路体33が延びる方向)に相当し、ここでは、一対の貫通孔35が対向する第1幅方向Yと直交する第2幅方向Zに相当する。磁性体4は、例えば、透磁率の高い磁性体であるフェライトによって構成される。ここでは、磁性体4は、多層基板本体3において一対の貫通孔35に挟まれた部位、すなわち、信号線33a、33f、GNDパターン33b、33e、電源パターン33c、33dを構成する6層分の回路体33が積層されているノイズ低減対象部位101の外側を一括で包囲する。本実施形態の磁性体4は、貫通孔35を介して多層基板本体3に組み付けられ、一対の貫通孔35によって挟まれたノイズ低減対象部位101に含まれる複数の回路体33の外側を第2幅方向Z周りに一括で包囲する。さらに言えば、磁性体4は、ノイズ低減対象部位101において、各回路体33の延在方向周りに当該各回路体33を囲み込むようにして当該複数の回路体33の外側を一括で包囲する。   The magnetic body 4 reduces noise in each circuit body 33 by collectively enclosing the outside of the plurality of circuit bodies 33 around the extending direction of the circuit body 33. The extending direction of the circuit body 33 corresponds to the direction in which the circuit body 33 extends (the direction in which the circuit body 33 extends) in the noise reduction target portion 101 of the multilayer substrate body 3. Here, the pair of through holes 35 are provided. This corresponds to the second width direction Z orthogonal to the opposing first width direction Y. The magnetic body 4 is made of, for example, ferrite that is a magnetic body with high magnetic permeability. Here, the magnetic body 4 is a portion sandwiched between the pair of through holes 35 in the multilayer substrate body 3, that is, the signal lines 33a and 33f, the GND patterns 33b and 33e, and the power supply patterns 33c and 33d. The outside of the noise reduction target part 101 on which the circuit bodies 33 are stacked is collectively surrounded. The magnetic body 4 of the present embodiment is assembled to the multilayer substrate body 3 through the through holes 35 and the second outside of the plurality of circuit bodies 33 included in the noise reduction target portion 101 sandwiched between the pair of through holes 35 is the second. Surrounds all around the width direction Z. Furthermore, the magnetic body 4 collectively surrounds the outside of the plurality of circuit bodies 33 so as to surround the circuit bodies 33 around the extending direction of the circuit bodies 33 in the noise reduction target portion 101.

より詳細には、磁性体4は、複数の分割体、ここでは、2つの分割体41、42を組み合わせることで、ノイズ低減対象部位101を構成する複数の回路体33の外側を当該回路体3の延在方向(第2幅方向Z)周りに一括で包囲する環状に形成される。分割体41は、第2幅方向Zと直交する方向の断面形状(図1参照)が略門型形状(言い換えれば、略コの字型形状)に形成される。具体的には、分割体41は、略矩形板状に形成される基部41a、及び、当該基部41aから立設された一対の脚部41bを含んで構成され、これらが一体で形成される。基部41aは、多層基板本体3の積層方向Xの一方側で実装面31と対向して位置する部分である。一対の脚部41bは、それぞれ基部41aの第1幅方向Yの両端部から積層方向Xに沿って突出するようにして立設される部分である。一対の脚部41bは、略矩形板状に形成され、それぞれ一対の貫通孔35に挿入され、当該一対の貫通孔35を積層方向Xに沿って貫通可能な位置、形状に形成される。分割体41は、一対の脚部41bがそれぞれ一対の貫通孔35に挿入され貫通するようにして多層基板本体3に組み付けられた状態で、上述したように基部41aが多層基板本体3の積層方向Xの一方側で実装面31と対向して位置する。分割体42は、分割体41の基部41aとほぼ同等の大きさの略矩形板状に形成され、分割体41の一対の脚部41bの先端部(基部41aとは反対側の端部)に組み付けられる。分割体42は、例えば、接着材や種々の接続機構等を介して一対の脚部41bの先端部に組み付けられる。分割体42は、一対の脚部41bの先端部に組み付けられた状態で、多層基板本体3の積層方向Xの他方側で実装面31と対向して位置する。つまり、磁性体4は、分割体41の基部41aと分割体42とが積層方向Xに対して多層基板本体3のノイズ低減対象部位101を挟んで対向して位置し、かつ、分割体41の一対の脚部41bが第1幅方向Yに対して当該ノイズ低減対象部位101を挟んで対向して位置する。この構成により、磁性体4は、ノイズ低減対象部位101を構成する複数の回路体33の外側を回路体3の延在方向(第2幅方向Z)周りに略矩形環状に一括で包囲する構成となる。言い換えれば、磁性体4は、ノイズ低減対象部位101を構成する複数の回路体33が分割体41と分割体42とによって環状に形成された当該磁性体4の内側を第2幅方向Zに沿って通過するような位置関係で、多層基板本体3に組み付けられる。さらに言えば、磁性体4は、環状の中心軸線が回路体33の延在方向(第2幅方向Z)に沿うような位置関係で、多層基板本体3に組み付けられる。この構成により、基板1は、各回路体33の通電時に当該磁性体4に磁束が発生し、電流エネルギが磁気エネルギへ変換されると共に、電磁誘導によって再び磁気エネルギから電流エネルギに戻ろうとしたときに、磁気損失が起き、各回路体33におけるノイズ電流の一部が抑制される。この結果、基板1は、当該磁性体4によって外周側を包囲された各回路体33のノイズが低減される。   More specifically, the magnetic body 4 is formed by combining a plurality of divided bodies, here two divided bodies 41 and 42, so that the outside of the plurality of circuit bodies 33 constituting the noise reduction target portion 101 is outside the circuit body 3. Are formed in an annular shape surrounding the entire extending direction (second width direction Z). In the divided body 41, a cross-sectional shape (see FIG. 1) in a direction orthogonal to the second width direction Z is formed in a substantially gate shape (in other words, a substantially U-shaped shape). Specifically, the divided body 41 includes a base portion 41a formed in a substantially rectangular plate shape and a pair of leg portions 41b erected from the base portion 41a, and these are integrally formed. The base 41 a is a portion that is positioned opposite to the mounting surface 31 on one side in the stacking direction X of the multilayer substrate body 3. The pair of leg portions 41b are portions that stand up so as to protrude along the stacking direction X from both end portions in the first width direction Y of the base portion 41a. The pair of leg portions 41 b are formed in a substantially rectangular plate shape, are respectively inserted into the pair of through holes 35, and are formed in positions and shapes that can penetrate the pair of through holes 35 along the stacking direction X. In the divided body 41, the base portion 41 a is stacked in the stacking direction of the multilayer substrate body 3 as described above in a state where the pair of leg portions 41 b are inserted into the pair of through holes 35 and assembled to the multilayer substrate body 3. It is located opposite to the mounting surface 31 on one side of X. The divided body 42 is formed in a substantially rectangular plate shape having substantially the same size as the base portion 41a of the divided body 41, and is formed at the tip end portions (end portions opposite to the base portion 41a) of the pair of leg portions 41b of the divided body 41. Assembled. The division body 42 is assembled | attached to the front-end | tip part of a pair of leg part 41b via an adhesive material, various connection mechanisms, etc., for example. The divided body 42 is positioned opposite to the mounting surface 31 on the other side in the stacking direction X of the multilayer substrate body 3 in a state assembled to the distal ends of the pair of leg portions 41b. That is, in the magnetic body 4, the base portion 41 a and the divided body 42 of the divided body 41 are positioned opposite to each other with respect to the stacking direction X with the noise reduction target portion 101 of the multilayer substrate body 3 interposed therebetween. The pair of leg portions 41b are positioned to face each other with the noise reduction target portion 101 in between in the first width direction Y. With this configuration, the magnetic body 4 collectively surrounds the outside of the plurality of circuit bodies 33 constituting the noise reduction target portion 101 around the extending direction (second width direction Z) of the circuit body 3 in a substantially rectangular ring shape. It becomes. In other words, the magnetic body 4 extends along the second width direction Z inside the magnetic body 4 in which the plurality of circuit bodies 33 constituting the noise reduction target portion 101 are formed in a ring shape by the divided body 41 and the divided body 42. The multilayer substrate body 3 is assembled in such a positional relationship as to pass through. Furthermore, the magnetic body 4 is assembled to the multilayer substrate body 3 in such a positional relationship that the annular central axis is along the extending direction of the circuit body 33 (second width direction Z). With this configuration, the substrate 1 generates a magnetic flux in the magnetic body 4 when each circuit body 33 is energized, and the current energy is converted to magnetic energy. At the same time, the magnetic energy is again changed from the magnetic energy to the current energy by electromagnetic induction. In addition, a magnetic loss occurs, and a part of the noise current in each circuit body 33 is suppressed. As a result, the noise of each circuit body 33 whose substrate 1 is surrounded by the magnetic body 4 is reduced.

以上で説明した基板1、ノイズフィルタ構造100は、多層基板本体3に絶縁層32を介して積層されて設けられ相互に異なる回路系統を構成する複数の回路体33の外側を磁性体4によって一括で包囲する。この構成により、基板1、ノイズフィルタ構造100は、磁性体4によって当該複数の回路体33のノイズを一括で低減することができるので、適正なノイズ低減性能を確保した上で、大型化を抑制することができる。例えば、基板1、ノイズフィルタ構造100は、多層基板本体3において異なる回路系統を構成する複数の回路体33に対してそれぞれノイズ低減用の部品を設けるような場合と比較して、構成部品点数の増加を抑制し、ノイズ低減用の部品の実装面積や重量等の増加を抑制することができ、製造コストを抑制することができる。特に、基板1、ノイズフィルタ構造100は、例えば、大電流化が図られ、また、ノイズの低減が要求される回路が相対的に増加した場合等であっても、本構成によれば大型化の抑制効果を顕著に発揮することができる。   The substrate 1 and the noise filter structure 100 described above are provided by laminating the outside of a plurality of circuit bodies 33 provided on the multilayer substrate body 3 through the insulating layer 32 and constituting different circuit systems by the magnetic body 4. Surround with. With this configuration, the substrate 1 and the noise filter structure 100 can collectively reduce the noise of the plurality of circuit bodies 33 by the magnetic body 4, so that an increase in size can be suppressed while ensuring appropriate noise reduction performance. can do. For example, the substrate 1 and the noise filter structure 100 have a smaller number of components compared to a case where noise reduction components are provided for a plurality of circuit bodies 33 constituting different circuit systems in the multilayer substrate body 3. The increase can be suppressed, the increase in the mounting area, weight, etc. of the noise reduction component can be suppressed, and the manufacturing cost can be suppressed. In particular, the substrate 1 and the noise filter structure 100 can be increased in size according to the present configuration even when, for example, a large current is achieved and the number of circuits requiring noise reduction is relatively increased. Can be remarkably exerted.

また、基板1、ノイズフィルタ構造100は、図4に例示するように、多層基板本体3において絶縁層32を介して複数の回路体33が積層された第1層34A、第2層34B、第3層34C、第4層34D、第5層34E、第6層34Fの各層間に発生する層間容量(浮遊容量、寄生容量)Cと磁性体4とを組み合わせることで、高周波ノイズ対策用のフィルタを構成することができる。例えば、図4に例示するように、基板1、ノイズフィルタ構造100は、接地層である第2層34Bと電源層である第3層34Cとの層間に発生する層間容量Cによって、第3層34Cの回路体33が構成する電源パターン33cにおける高周波ノイズを低減することができる。   Further, as illustrated in FIG. 4, the substrate 1 and the noise filter structure 100 include a first layer 34 </ b> A, a second layer 34 </ b> B, a second layer 34 </ b> B in which a plurality of circuit bodies 33 are stacked via an insulating layer 32 in the multilayer substrate body 3. A filter for countermeasures against high frequency noise by combining an interlayer capacitance (floating capacitance, parasitic capacitance) C generated between each of the third layer 34C, the fourth layer 34D, the fifth layer 34E, and the sixth layer 34F and the magnetic body 4 Can be configured. For example, as illustrated in FIG. 4, the substrate 1 and the noise filter structure 100 include a third layer due to an interlayer capacitance C generated between a second layer 34 </ b> B that is a ground layer and a third layer 34 </ b> C that is a power supply layer. High frequency noise in the power supply pattern 33c formed by the circuit body 33 of 34C can be reduced.

また、以上で説明した基板1、ノイズフィルタ構造100は、多層基板本体3に設けられた貫通孔35に磁性体4の一部を挿通することで、当該磁性体4を当該多層基板本体3に簡単に組み付けることができる。この構成により、基板1、ノイズフィルタ構造100は、例えば、組み付け作業性を向上することができるので、この点でも製造コストを抑制することができる。   In addition, the substrate 1 and the noise filter structure 100 described above are configured such that the magnetic body 4 is inserted into the multilayer substrate body 3 by inserting a part of the magnetic body 4 into the through hole 35 provided in the multilayer substrate body 3. Easy to assemble. With this configuration, since the substrate 1 and the noise filter structure 100 can improve, for example, the assembly workability, the manufacturing cost can also be suppressed in this respect.

また、以上で説明した基板1、ノイズフィルタ構造100は、磁性体4が複数の分割体41、42を組み合わせて環状に形成されることで、複数の回路体33においてノイズ低減対象部位101を構成する部分を、当該磁性体4によって回路体33の延在方向周りに全周に渡って環状に包囲することができる。この結果、基板1、ノイズフィルタ構造100は、複数の回路体33のノイズをより確実に一括で低減することができる。   In addition, the substrate 1 and the noise filter structure 100 described above constitute the noise reduction target portion 101 in the plurality of circuit bodies 33 by forming the magnetic body 4 in an annular shape by combining the plurality of divided bodies 41 and 42. The part to be encircled can be surrounded by the magnetic body 4 in an annular shape around the entire extending direction of the circuit body 33. As a result, the substrate 1 and the noise filter structure 100 can more reliably reduce the noise of the plurality of circuit bodies 33 collectively.

また、以上で説明した基板1、ノイズフィルタ構造100は、磁性体4によって包囲される複数の回路体33が信号線33a、33f、GNDパターン33b、33e、電源パターン33c、33dを含むので、磁性体4によってこれら信号線33a、33f、GNDパターン33b、33e、電源パターン33c、33dのノイズを一括で低減することができる。   Further, in the substrate 1 and the noise filter structure 100 described above, the plurality of circuit bodies 33 surrounded by the magnetic body 4 include the signal lines 33a and 33f, the GND patterns 33b and 33e, and the power supply patterns 33c and 33d. The body 4 can collectively reduce noise of the signal lines 33a and 33f, the GND patterns 33b and 33e, and the power supply patterns 33c and 33d.

なお、上述した本発明の実施形態に係る基板、及び、ノイズフィルタ構造は、上述した実施形態に限定されず、特許請求の範囲に記載された範囲で種々の変更が可能である。   In addition, the board | substrate and noise filter structure which concern on embodiment of this invention mentioned above are not limited to embodiment mentioned above, A various change is possible in the range described in the claim.

以上で説明した基板1は、例えば、自動車等の車両に搭載される種々の電子部品ユニットに適用されるものとして説明したがこれに限らず、車両以外に適用されてもよい。   Although the board | substrate 1 demonstrated above was demonstrated as what is applied to the various electronic component units mounted in vehicles, such as a motor vehicle, for example, it is not restricted to this, You may apply other than a vehicle.

以上で説明した多層基板本体3は、プリント回路基板であるものとして説明したがこれに限らず、いわゆる絶縁性の樹脂材の内部に導電性の金属材のバスバが内蔵されたインサートバスバ基板であってもよい。この場合、多層基板本体3は、例えば、導電性の金属材からなる回路体としてのバスバを絶縁性の樹脂材で被覆し、これを複数積層することで多層化されて構成される。また、多層基板本体3は、積層方向Xの両面がそれぞれ実装面31を構成するものとして説明したがこれに限らず、実装面31は、どちらか一方の面であってもよい。   The multilayer substrate body 3 described above has been described as a printed circuit board, but is not limited to this, and is an insert bus bar substrate in which a conductive metal bus bar is incorporated in a so-called insulating resin material. May be. In this case, the multilayer substrate body 3 is configured to be multilayered by, for example, covering a bus bar as a circuit body made of a conductive metal material with an insulating resin material and laminating a plurality thereof. Further, the multilayer substrate body 3 has been described on the assumption that both surfaces in the stacking direction X constitute the mounting surface 31, but the present invention is not limited to this, and the mounting surface 31 may be either one of the surfaces.

以上で説明した多層基板本体3は、一対の貫通孔35(貫通孔35A、35B)を有するものとして説明したがこれに限らない。多層基板本体3は、例えば、多層基板本体3におけるノイズ低減対象部位101の位置や大きさ等に応じて貫通孔35が1つであってもよいし、そもそも貫通孔35が設けられていなくてもよい。   The multilayer substrate body 3 described above has been described as having a pair of through holes 35 (through holes 35A and 35B), but is not limited thereto. The multilayer substrate body 3 may have, for example, one through hole 35 according to the position and size of the noise reduction target portion 101 in the multilayer substrate body 3, or the through hole 35 is not provided in the first place. Also good.

以上で説明した多層基板本体3は、第1層34Aによる信号層、第2層34Bによる接地層、第3層34Cによる電源層、第4層34Dによる電源層、第5層34Eによる接地層、第6層34Fによる信号層の順で積層されているものとして説明したが、積層数、積層順はこれに限らない。多層基板本体3は、相互に異なる回路系統を構成する複数の回路体33が絶縁層32を介して積層された構成であればよく、例えば、回路体33による導体層が2層分であってもよいし、7層分以上が積層されていてもよい。つまり、磁性体4によって包囲されノイズが低減される複数の回路体33は、信号線33a、33f、GNDパターン33b、33e、電源パターン33c、33dを含むものとして説明したがこれに限らず、独立した複数の回路系統を構成するものであればよい。また、図1、図2では、GNDパターン33b、33e、電源パターン33c、33dを構成する回路体33は、例えば、大電流に対応すべく相対的に厚い厚銅であるものとして図示しているがこれに限らず、厚銅でなくてもよい。例えば、多層基板本体3は、大電流向けでなければ、2層分の信号層、及び、それぞれ1層分の電源層、接地層の合計4層分が積層されたものであってもよい。   The multilayer substrate body 3 described above includes a signal layer by the first layer 34A, a ground layer by the second layer 34B, a power layer by the third layer 34C, a power layer by the fourth layer 34D, a ground layer by the fifth layer 34E, Although it has been described that the signal layers are stacked in the order of the sixth layer 34F, the number of layers and the order of stacking are not limited thereto. The multilayer substrate body 3 may have a configuration in which a plurality of circuit bodies 33 constituting different circuit systems are stacked via an insulating layer 32. For example, the conductor body of the circuit body 33 is equivalent to two layers. Alternatively, seven or more layers may be laminated. In other words, the plurality of circuit bodies 33 surrounded by the magnetic body 4 and reduced in noise are described as including the signal lines 33a and 33f, the GND patterns 33b and 33e, and the power supply patterns 33c and 33d. What constitutes a plurality of circuit systems may be used. In FIG. 1 and FIG. 2, the circuit body 33 constituting the GND patterns 33b and 33e and the power supply patterns 33c and 33d is illustrated as being relatively thick thick copper to cope with a large current, for example. However, the present invention is not limited to this and may not be heavy copper. For example, the multilayer substrate body 3 may be formed by stacking two signal layers and a total of four layers of one power source layer and one ground layer, respectively, unless they are for large currents.

以上で説明した磁性体4は、分割体41、42を組み合わせることで環状に形成されるものとして説明したがこれに限らず、3つ以上の分割体を組み合わせることで環状に形成されてもよい。また、磁性体4は、必ずしも環状に形成されていなくてもよく、積層された複数の回路体33のそれぞれにおいてノイズ低減が可能な程度に包囲する構成であれば、例えば、分割体41単体のように略門型形状(略コの字型形状)に形成されていてもよい。   Although the magnetic body 4 demonstrated above was demonstrated as what is formed in cyclic | annular form by combining the split bodies 41 and 42, it may not be restricted to this but may be formed in cyclic | annular form by combining three or more divided bodies. . In addition, the magnetic body 4 does not necessarily have to be formed in an annular shape. For example, the divided body 41 alone may be used as long as it is configured to surround each of the stacked circuit bodies 33 to the extent that noise can be reduced. Thus, it may be formed in a substantially gate shape (substantially U-shaped).

1 基板
3 多層基板本体
4 磁性体
32 絶縁層
33 回路体
33a、33f 信号線
33b、33e GNDパターン
33c、33d 電源パターン
35、35A、35B 貫通孔
41、42 分割体
100 ノイズフィルタ構造
X 積層方向
Y 第1幅方向
Z 第2幅方向
DESCRIPTION OF SYMBOLS 1 Board | substrate 3 Multilayer board | substrate body 4 Magnetic body 32 Insulating layer 33 Circuit body 33a, 33f Signal line 33b, 33e GND pattern 33c, 33d Power supply pattern 35, 35A, 35B Through-hole 41, 42 Divided body 100 Noise filter structure X Lamination direction Y First width direction Z Second width direction

Claims (6)

相互に異なる回路系統を構成する複数の回路体が絶縁層を介して積層されて設けられる多層基板本体と、
前記複数の回路体の外側を当該回路体の延在方向周りに一括で包囲する磁性体とを備えることを特徴とする、
基板。
A multilayer substrate body in which a plurality of circuit bodies constituting mutually different circuit systems are provided by being laminated via an insulating layer;
A magnetic body that collectively surrounds the outside of the plurality of circuit bodies around the extending direction of the circuit bodies,
substrate.
前記多層基板本体は、前記複数の回路体の積層方向に沿って貫通し前記磁性体が挿通される貫通孔を有する、
請求項1に記載の基板。
The multilayer substrate body has a through hole that penetrates along the stacking direction of the plurality of circuit bodies and through which the magnetic body is inserted.
The substrate according to claim 1.
前記磁性体は、複数の分割体を組み合わせることで前記複数の回路体の外側を当該回路体の延在方向周りに一括で包囲する環状に形成される、
請求項1又は請求項2に記載の基板。
The magnetic body is formed in an annular shape that collectively surrounds the outside of the plurality of circuit bodies around the extending direction of the circuit bodies by combining a plurality of divided bodies.
The substrate according to claim 1 or 2.
前記複数の回路体は、電力伝送用の電源パターン、及び、接地用のGNDパターンを含む、
請求項1乃至請求項3のいずれか1項に記載の基板。
The plurality of circuit bodies include a power transmission power pattern and a ground GND pattern.
The substrate according to any one of claims 1 to 3.
前記複数の回路体は、さらに信号通信用の信号線を含む、
請求項4に記載の基板。
The plurality of circuit bodies further include signal lines for signal communication.
The substrate according to claim 4.
相互に異なる回路系統を構成する複数の回路体が絶縁層を介して積層されて設けられる多層基板本体を前記複数の回路体の積層方向に沿って貫通して設けられる貫通孔と、
前記貫通孔を介して前記多層基板本体に組み付けられ、前記複数の回路体の外側を当該回路体の延在方向周りに一括で包囲する磁性体とを備えることを特徴とする、
ノイズフィルタ構造。
A plurality of circuit bodies constituting mutually different circuit systems are stacked through an insulating layer, and a through-hole provided through a multilayer substrate body provided along the stacking direction of the plurality of circuit bodies;
A magnetic body that is assembled to the multilayer substrate body through the through-holes and collectively surrounds the outside of the plurality of circuit bodies around the extending direction of the circuit bodies,
Noise filter structure.
JP2016208374A 2016-10-25 2016-10-25 Board, and noise filter structure Abandoned JP2018073878A (en)

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JP2020072140A (en) * 2018-10-30 2020-05-07 北川工業株式会社 Noise filter and electronic circuit board with noise filter

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JPH02186570A (en) * 1989-01-12 1990-07-20 Matsushita Electric Ind Co Ltd Unnecessary radiation processing device
JPH10321973A (en) * 1997-05-19 1998-12-04 Nec Corp Printed circuit board
JP2000183533A (en) * 1998-12-17 2000-06-30 Mitsubishi Electric Corp Low-emi multilayer circuit board and electric and electronic device
JP2000323844A (en) * 1999-05-11 2000-11-24 Nec Corp Multilayer printed circuit board
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Publication number Priority date Publication date Assignee Title
JPS6029230Y2 (en) * 1980-01-07 1985-09-04 東北金属工業株式会社 Noise filter for circuit board
JPH02186570A (en) * 1989-01-12 1990-07-20 Matsushita Electric Ind Co Ltd Unnecessary radiation processing device
JPH10321973A (en) * 1997-05-19 1998-12-04 Nec Corp Printed circuit board
JP2000183533A (en) * 1998-12-17 2000-06-30 Mitsubishi Electric Corp Low-emi multilayer circuit board and electric and electronic device
JP2000323844A (en) * 1999-05-11 2000-11-24 Nec Corp Multilayer printed circuit board
US20130162370A1 (en) * 2011-12-22 2013-06-27 Rixin Lai Systems and methods for providing an electric choke

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020072140A (en) * 2018-10-30 2020-05-07 北川工業株式会社 Noise filter and electronic circuit board with noise filter
JP7204183B2 (en) 2018-10-30 2023-01-16 北川工業株式会社 Noise filter and electronic circuit board with noise filter

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