JP2017185362A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of stably achieving complex and advanced performance operation without excessively increasing a control load of a CPU.SOLUTION: A performance control part 22' including a CPU for controlling a movable performance body and a light emitting body in a predetermined mode separately includes a first serial port S0 for outputting a serial signal to a driver DRi for driving and controlling a movable performance body AMU at fixed time, and a second serial port S1 for outputting a serial signal to the drive DRi for driving and controlling a light emitting body at fixed time. An operation period of the first serial port S0 is set shorter than an operation period of the second serial port S1.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process resulting from a gaming operation, and more particularly to a gaming machine that can perform a bold movable effect by a movable effector.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing.

  For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation.

  In addition, before the final result is confirmed, a notice effect is also performed in which a character appears or a movable effect body starts to rotate, and a jackpot state is invited. For example, the movable effect body is informed of the lottery result with a predetermined reliability by operating at the time of the effect operation that is likely to reach a big hit state (for example, Patent Documents 1 to 3).

JP 2009-000411 A JP 2008-259920 A JP 2008-245679 A

  However, there is a demand for a configuration in which various control operations as described above are desired to be advanced and enriched, but the control burden on the CPU is not increased unnecessarily. That is, in order to enrich the production operations, it is desirable that the number of production bodies such as lamps and production motors is larger. However, if a large number of production bodies are controlled at a uniform high speed, the control burden on the CPU becomes excessive. There is a fear.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine capable of stably realizing a complex and advanced performance operation without increasing the control burden of the CPU. .

  In order to achieve the above object, the present invention is a gaming machine provided with effect control means having a CPU for controlling a movable effector and a light emitter in a predetermined manner based on a control command received from another control means. The effect control means includes a first serial port for regularly outputting a first serial signal to a driver for driving and controlling the movable effect body, and a second for a driver for driving and controlling the flashing light emitter. A second serial port that outputs serial signals at regular intervals is provided separately, and the operation cycle of the first serial port is set shorter than the operation cycle of the second serial port.

  In the gaming machine of the present invention, the serial port outputs serial signals on a regular basis, so that even if the amount of data increases, the control burden on the CPU does not become excessive. In addition, since the first serial port and the second serial port are associated with the driver for driving and controlling the movable effector and the driver for driving and controlling the light emitter, a control operation corresponding to the individuality of each effector is possible. .

  In addition, since the operation cycle of the first serial port is set to be shorter than the operation cycle of the second serial port, each effector can be optimally controlled. That is, for example, when the movable effector is driven by a motor, the motor can be quickly and irregularly rotated. On the other hand, since the light emitter cannot be recognized by humans even if its lighting state is changed at an extremely high speed, it can be driven at an optimal timing slower than the motor in accordance with human visual perception.

  By the way, in the present invention, preferably, the output operation of the first and second serial signals is executed in synchronization with the clock signal corresponding to each serial signal, and each clock signal is output of the serial signal in each operation cycle. Once the operation is complete, it should be configured to maintain a steady level until the subsequent output operation. Further, if the driver for driving and controlling the movable effector and the driver for driving and controlling the light emitter are substantially the same configuration, the control contents of the CPU can be shared to some extent, and the memory consumption and control burden can be reduced. Can do.

  The serial port includes a transmission data register that temporarily stores data output in parallel by the CPU, a transmission shift register that serially outputs data received from the transmission data register in synchronization with a clock signal, and an operation content being executed by the CPU. It is preferable that the control register is configured to be capable of grasping.

  Further, the driver is provided with unique address information and has a built-in register capable of setting a driving state of a light-emitting body or a moving effect body, and the effect control means specifies the driver. A first means for outputting address information to be performed; a second means for outputting register information for specifying a predetermined register built in a predetermined driver specified by the address information output by the first means; and setting the predetermined register. And third means for outputting power setting information. Here, it is also preferable to output a start command indicating that transmission of a series of serial signals is started.

  The serial port includes a plurality of bytes of transmission buffer capable of temporarily storing parallel data output by the CPU, a transmission data register capable of sequentially receiving one byte of parallel data from the transmission buffer, and the transmission data register. A transmission shift register that serially outputs the received parallel data having a length of 1 byte in synchronization with the level change of the clock signal, and from the transmission buffer to the transmission data register at a necessary timing. It is also preferable that output control means for transferring parallel data is provided. In this case, if the output control means is realized by the internal circuit operation of the serial port not directly involved in the CPU, the control burden on the CPU is reduced. Further, it is preferable that the transmission buffer has a FIFO configuration.

  According to the above-described present invention, it is possible to stably realize a complex and advanced performance operation without increasing the control burden of the CPU.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. It is drawing explaining the circuit structure of a motor driver and a sensor board | substrate. It is drawing explaining the principal part and operation | movement content of the internal structure of the one-chip microcomputer of an effect control part. It is a time chart which shows the serial signal transmitted to a motor drive board | substrate. It is a flowchart explaining operation | movement of an effect control part. It is drawing which shows the structure and operation | movement content of an effect table. It is a flowchart which shows a part of FIG. 8 in detail. It is a flowchart which shows a part of FIG. 8 in detail. It is a flowchart which shows a part of FIG. 8 in detail. It is a flowchart explaining a motor output process. It is a flowchart explaining another motor output process. It is a flowchart explaining another motor output process, and drawing explaining a FIFO buffer. It is drawing explaining the circuit structure and operation | movement of a frame relay board | substrate. It is a flowchart explaining a serial signal acquisition process. The relationship between a frame side member, a board side member, and an effect control part is illustrated about a serial signal.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a speaker is disposed below the glass door 6.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A production button 11 is provided on the outer peripheral surface of the upper plate 8. The effect button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the effect button 11 without releasing the right hand from the firing handle 10. The effect button 11 does not function normally, but, for example, when the game state becomes a button chance state, the operation of the effect button can be accepted, and the player is notified that the operation is possible by turning on the built-in lamp. The The effect button 11 may be used for the purpose of causing a player to participate in the motor effect.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided in an annular shape on the surface of the game board 5, and a central opening HO extending toward the back side is provided in the approximate center. It has been. A display device DISP composed of a liquid crystal color display is arranged at the bottom of the central opening HO. In addition, a symbol starting port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged at appropriate positions in the game area.

  Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball. When it is detected that a game ball has won at the symbol start opening 15, a big hit lottery process is executed unless the holding upper limit value is exceeded, and it is determined whether or not the game state is advantageous to the player. Is done.

  In a space formed on the front surface of the display device DISP, a movable effect body AMU that executes a movable effect is disposed so as to be movable up and down. The movable effector AMU is configured to be held by the left and right elevating mechanisms ALVa and ALVb, and moves up and down at high speed along the guide shaft PL in response to the rotation of the effecting motors M1 and M2 that drive the elevating mechanisms ALVa and ALVb. The movable effect body AMU may move to a target position such as the lowermost part of the display device DISP at the time of the movable effect, and execute a movable effect corresponding to the rotation of the other effect motors M3 to M9. In the standby state (origin region) located at the top, it is hidden from the player. In addition, a plurality of small movable effect bodies (not shown) are also arranged around the game board 5, and a complex movable effect is realized by a large number of effect motors MOi.

  The effect motors of the present embodiment are divided into a first group of effect motors MOi arranged in the game frame that holds the game board 5 and a second group of effect motors Mx arranged in the game board 5. . The second group of production motors Mx is a board-side member GM2 (see FIG. 3) integrated with the game board 5, and executes a unique movable production corresponding to the game characteristics of the game machine. On the other hand, the first group of production motors MOi is a frame-side member GM1 (see FIG. 3) that is separable from the game board 5, and executes a somewhat regular movable production.

  Although not particularly limited, all the production motors Mx and MOi of the first group and the second group are configured by stepping motors, and each stepping motor is driven by a two-phase excitation method or a 1-2 phase excitation method. Yes. In this embodiment, the effect motors M1 and M2 for reciprocating the movable effector AMU in the vertical direction are unipolar types with a constant current direction, but it is also preferable to use a bipolar type to increase the rotational torque. .

  By the way, an LED display portion LP for specifying the number of lottery processes in the standby state is arranged on the upper part of the display device DISP. The LED display portion LP is composed of four LED lamps corresponding to the holding upper limit value of the embodiment.

  The display device DISP is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DISP has a special symbol display part Da to Dc in the center, a normal symbol display part 19 in the upper right part, and a reserved number display part NUM in the lower center part. The number-of-holds display unit NUM displays the same number of effects on hold in synchronization with the LED display unit LP, but the display content is automatically extinguished when the movable effector AMU is lowered and executed. Has been.

  In the special symbol display parts Da to Dc, a reach effect is executed to expect that a big hit state will be brought about by the big hit lottery, and the special symbol display parts Da to Dc and the surroundings indefinitely notify the success / failure result of the big win lottery. A notice effect is performed. The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the random number for lottery is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws, and when the stop symbol after the fluctuation of the normal symbol display unit 19 hits and the symbol is displayed, It is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start opening 15, an image effect in which the display symbols of the special symbol display portions Da to Dc change for a predetermined time is started on the condition that the timing is not being executed. The game stops at a stop symbol determined based on the jackpot lottery result corresponding to the winning timing of the game ball to 15. On the other hand, if a game ball wins in the symbol start opening 15 during the image production, the big hit lottery process is put on hold unless the hold upper limit value (4 pieces) is reached, and the increased number of production hold is held on the LED display LP It is displayed in synchronization with the number display part NUM. When the game ball is won at the symbol start opening 15 exceeding the holding upper limit value, the game ball is simply paid out as the winning ball operation, and the big hit lottery process is not executed.

  On the front surface of the display device DISP and / or around it, during the series of image effects, the effect motors Mx and MOi operate to execute various movable effects as the notice effects. For example, the movable effector AMU may drop to the position of the central opening HO. In this case, the movable effector AMU that has lowered to the target position performs an appropriate movable notice effect and then returns to the original origin area. Ascend towards.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. As described above, the frame-side member GM1 includes the first group of production motors MOi.

  On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 2 is the board side member GM2, and the board side member GM2 includes the second group of production motors Mx.

  3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, a lamp drive board 36, and a motor drive board 37. , And these circuit boards are respectively fixed at appropriate positions of the front frame 3. Here, each of the lamp drive board 36 and the motor drive board 37 has substantially the same configuration as the lamp drive board 29 and the motor drive board 30 that are the panel-side members GM2, and there are a plurality of general-purpose drivers DVi having the same configuration that receive serial signals. It is installed. Therefore, in the present embodiment, the serial signals transmitted to the general-purpose driver DVi of the motor drive board 30, the lamp drive board 29, the motor drive board 37, and the lamp drive board 36 can be expressed as channels CH0 to CH3. is there. Note that a serial transmission circuit is also mounted on the frame relay board 35 and may be expressed as a channel CH4.

  Continuing the description based on the above, the motor drive board 37 is provided with a plurality of effect motors MOi that realize an effect operation by an appropriate effector, and setting data for driving the plurality of effect motors MOi. SDATA2 passes through the effect control board 22 (serial output port S2 of the one-chip microcomputer 40) → the effect interface board 27 → the frame relay board 34 → the frame relay board 35 as the serial signal of the second channel CH2 together with the clock signal CK2. Then, it is transmitted to a plurality of general-purpose drivers DVi mounted on the motor drive board 37. The plurality of general-purpose drivers DVi can operate upon receiving an operation permission signal ENABLE2 at a permission level from the effect control board 22 (one-chip microcomputer 40).

  In addition, a sensor board SENS is arranged close to the motor drive board 37 effect, and a plurality of N (for example, 6) effect bodies driven by the effect motor MOi are respectively located at the origin position on the sensor board SENS. A plurality of N origin detection sensors (refer to FIG. 5B) for detecting whether or not they are positioned are mounted. The origin switch signal SN (6 bits) output from the origin detection sensor is transmitted to the frame relay board 35 together with the switch signal (2 bits) of the effect button 11, and is combined into a 1-bit serial signal by the frame relay board 35. On the above, serial transmission is performed through the route of the frame relay board 34 → the production interface board 27 → the production control board 22. This serial signal is transmitted as serial data SDATA4 of the fourth channel CH4 to the serial input port S4 of the one-chip microcomputer 40 of the effect control board 22.

  As shown in FIG. 16A, the frame relay board 35 is provided with a shift register 50 for converting 8-bit parallel data into 1-bit serial data. The serial transmission operation is realized based on the operation enable signal ENABLE4 and the clock signal CK4 received from the one-chip microcomputer 40. The serial transmission operation in FIG. 16 will be further described later.

  On the other hand, a plurality of LEDs are connected to the lamp drive board 36, and the setting data SDATA3 for driving these LED groups is also produced together with the clock signal CK3 as a serial signal of the third channel CH3. 22 (the serial output port S3 of the one-chip microcomputer 40) → the production interface board 27 → the frame relay board 34 → the frame relay board 35, and is transmitted to a plurality of general-purpose drivers DVi mounted on the lamp driving board 36. Yes. The general-purpose driver DVi mounted on the lamp drive board 36 is also operable upon receiving the permission level operation permission signal ENABLE3 from the effect control board 22 (one-chip microcomputer 40).

  In the case of the embodiment, the general-purpose drivers DVi mounted on the motor drive board 37 and the lamp drive board 36 all have the same circuit configuration. This is because the motor drive board 30 and the lamp drive board 29 belonging to the frame side member GM1. The same applies to the general-purpose driver DVi mounted on the. In response to the operation enable signal ENABLE and the setting data SDATA that is serial data, the internal circuit of the general-purpose driver DVi functions to output an output signal (maximum 24-bit analog signal).

  This output signal is a drive signal for stepping rotation of the stepping motor corresponding to the object to be driven or a lighting signal for controlling the blinking of the lamp. In any case, the analog level (gradation level) Can be set in 128 steps. Since each of the general-purpose drivers DVi has 24 output terminals, for example, if M general-purpose drivers DVi are mounted on the lamp driving boards 29 and 36, 24 × M lamps can be controlled respectively. If N general-purpose drivers DVi are mounted on the drive boards 37 and 30, 24 × N effect motors can be controlled. Thus, since the setting signal SDATA for controlling each effector is serially transmitted, even if the number of lamps and effect motors is increased to enrich the effect operation, the wiring becomes complicated and the control circuit becomes complicated. There is nothing.

  On the back surface of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  The system reset signal of the present embodiment is generated by a DC power source based on an AC power source. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset.

  The production control unit 22 ′ and the image control unit 23 ′ execute production operations dependently on the basis of a control command from the main control unit 21, and therefore, in order to avoid complication of the circuit configuration, A system reset signal SYS output from the substrate 20 is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 directly or via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 4). The effect control unit 22 ′ receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26.

  Then, the effect control unit 22 ′ sends the clock signal CK and the operation permission signal ENABLE to the general-purpose driver DVi mounted on the motor driving board 30 and the lamp driving board 29 via the effect interface board 27, respectively. Setting data SDATA is supplied as serial signals of CH0 and CH1. As described above, the general-purpose driver DVi mounted on the motor drive board 30 or the lamp drive board 29 has the same configuration as that of the general-purpose driver DVi mounted on the motor drive board 37 or the lamp drive board 36. The lamp group to be realized and the motor group to realize the motor effect are driven by a large number of general-purpose drivers DVi receiving signals CKj, SDATAj, and ENABLEj divided into four channels (j = 0 to 3).

  As described above, in this embodiment, not only the setting data SDATAj for driving the lamp but also the setting data SDATAj for driving the motor are serially transmitted, so that the number of effect motors Mx and MOi is increased in order to enrich the effect contents. Even if it increases, the number of wiring cables does not increase, and the device configuration is simplified. As will be described in detail later, the general-purpose driver DVi has its own channel among the setting data of each channel (j = 0 to 3) output from the serial output port Si of the one-chip microcomputer 40 of the effect control unit 22 ′. Only the relevant part of the setting data SDATAj of CHj is acquired, and the lamp group and motor group in charge are driven.

  By the way, in this embodiment, a sensor board SENS on the board side similar to the frame side is disposed in the vicinity of the motor drive board 30. Similar to the frame-side sensor substrate SENS, an appropriate origin detection sensor is also arranged on the panel-side sensor substrate SENS to determine whether or not the movable effector AMU is accommodated in the origin region. As described above, the origin switch signal SN output from the sensor substrate SENS on the frame side is transmitted to the serial input port S4 of the one-chip microcomputer 40 as the serial signal of the fourth channel CH4. The origin switch signal SN is transmitted to the input port Pi ′ of the one-chip microcomputer 40 via the effect interface board 27 (see FIG. 4).

  As shown in FIGS. 3 and 4, the effect control unit 22 ′ has two types of control commands CMD ′ and strobe signal STB ′, and a system reset signal SYS received from the power supply board 20, with respect to the image control unit 23 ′. DC voltage (12V, 5V).

  Then, the image controller 23 'drives the display device DS based on the control command CMD' to execute various image effects. The display device DS emits light by an LED backlight, and is driven by receiving five pairs of LVDS (Low voltage differential signaling) signals and a backlight power supply voltage (12 V) from the image interface board 28. (See FIG. 4).

  Next, the configurations of the effect control unit 22 'and the image control unit 23' will be described in more detail. As shown in FIG. 4, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed as power supply voltage of the digital logic circuit to the production interface board 27, the lamp driving board 29, the motor driving board 30, the image interface board 28, and the image control board 23, and is supplied to each digital circuit. Is operating.

  The direct current voltage 5V is not distributed on the effect control board 22, the direct current voltage 3.3V stepped down from 12V by the DC / DC converter, and the direct current voltage 1 further stepped down from 3.3V by the DC / DC converter. Only .8V is distributed from the production interface board 27 to the production control board 22.

  In this way, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. Therefore, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation.

  However, the DC voltage 12V received from the power supply board 20 is used as it is as the power supply voltage of the digital amplifier 46 and is distributed to the lamp drive board 29 and the motor drive board 30 to become the power supply voltage of the lamp group and motor group. The direct-current voltage 32V is stepped down to the direct-current voltage 13V in the DC / DC converter of the effect interface board and used as a drive power source for some effect motors Mx.

  As shown in FIG. 4, the effect control unit 22 ′ includes a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by a movable effector, and data transfer, and a control program for the one-chip microcomputer 40. A flash memory 41 to be stored, a voice synthesis circuit 42 that reproduces and outputs a voice signal based on an instruction from the one-chip microcomputer 40, and compressed voice data that is original data of the reproduced voice signal are stored. And an audio memory 43 that is configured.

  Here, the one-chip microcomputer 40, the flash memory 41, and the voice memory 43 operate at a power supply voltage of 3.3V, and the voice synthesis circuit 42 operates at a power supply voltage of 3.3V and a power supply voltage of 1.8V. It operates and significant power saving is realized. Here, 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  The one-chip microcomputer 40 includes a plurality of parallel input / output ports PIO (Pi + Pi ′ + Po + Po ′) and a plurality of serial input / output ports Si. Here, the serial input / output port Si functions as an input port or an output port based on a set value in the control register RG (see FIG. 6). Therefore, in this embodiment, the serial ports (S0 to S3) of CH0 to CH3 are set as serial output ports, and the serial port S4 of CH4 is set as a serial input port.

  Then, using the serial output ports (S0 to S3) of the four channels CH0 to CH3, the setting data SDATA0 to SDATA0 are transferred to the general-purpose drivers DVi mounted on the motor drive boards 30 and 37 and the lamp drive boards 29 and 36. SDATA3 is output in synchronization with the clock signals CK0 to CK3. That is, the serial output ports S0 to S3 transmit the setting data SDATA0 to SDATA3 to the corresponding motor drive boards 30 and 37 and lamp drive boards 29 and 36 based on the clock synchronization method. The motor drive setting data SDATA0 and SDATA2 include serial data obtained by connecting drive data Φ1 to Φ4 for controlling the stepping operation of the plurality of effect motors Mx and MOi, and the lamp drive setting data SDATA1. , SDATA3 includes serial data obtained by connecting brightness data for PWM control of the light emission brightness of each LED.

  On the other hand, the serial input port S4 acquires the serial signal SADATA4 of the fourth channel CH4 in synchronization with the clock signal CK4 output by itself. The serial signal of the fourth channel CH4 is 8-bit data in which the origin switch signal SN (6 bits) output from the sensor substrate SENS on the frame side and the switch signal (2 bits) of the effect button 11 are collected.

  Further, the motor drive boards 30 and 37 and the lamp drive boards 29 and 36 are also connected to the parallel output port Po ′ of the parallel input / output port PIO, and are mounted on the drive boards 30, 37, 29, and 36. The driver DVi starts operation based on one bit of the 4-bit operation enable signals ENABLE0 to ENABLE3 output from the parallel output port Po ′. The parallel output port Po ′ also outputs an operation permission signal ENABLE4 to the frame relay board 35 and permits the operation of the shift register 50 of the frame relay board 35.

  Note that all the signals ENABLEj, CKj, and SDATAj are digital data generated by the one-chip microcomputer 40 having a power supply voltage of 3.3V, but correspond to the power supply voltage of 5V by level conversion by the effect interface board 27. It becomes digital data. Therefore, even when the transmission distance from the production interface board 27 to the general-purpose driver DVi is long, a sufficient noise margin is ensured.

  The control command CMD and the strobe signal STB from the main control unit 21 are input to the input port Pi of the parallel input / output port PIO, and the control command CMD ′ and the strobe signal STB ′ are output from the command output port Po. It is configured. Specifically, a control command CMD and a strobe signal (interrupt signal) STB output from the main control board 21 correspond to the power supply voltage 3.3 V in the buffer 44 of the effect interface board 27 at the input port Pi. Converted to a logic level to be supplied in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ specifies (2) an outline of various effect operations resulting from winning at the symbol start opening, in addition to (1) abnormality notification and other notification control commands. A control command (variation pattern command) and a control command (designation command) for designating a design type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, according to the determined specific game content, the motor group M1 to M9 and MOi produce a motor effect, a lamp effect by blinking the LED group, and a sound effect preparation operation by a speaker, and an image control unit 23 ' On the other hand, the control command CMD ′ relating to the image effect synchronized with the effect operation by the lamp or the speaker is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′, along with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′, is sent to the image control unit 23 ′ through the command output port Po. CMD ′ is output toward the production interface board 27. When the production control unit 22 ′ receives a design designation command, a notification control command related to the display device DS, and other control commands, the control command is summarized in a 16-bit length. It is output toward the production interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the voice synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. In this case, the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit serial signals SD1 and SD2 are suppressed to a total of 4 bit signal lines. Note that the amplitude level of any signal is 3.3V.

  Here, SD1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SD2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The voice synthesis circuit 42 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted (see FIG. 4B). Note that since there is only one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is overwhelmingly smaller than parallel transmission. Note that when analog transmission is employed, the number of cables is the same, but noise is superimposed on an analog signal having an amplitude of 3.3 V, and the sound quality is greatly deteriorated. On the other hand, when the amplitude level is increased, the power supply wiring becomes complicated and the power consumption increases.

  Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  The effect interface board 27 is provided with output buffer circuits 47, 48, and 49 for transmitting various signals output from the parallel output port Po 'of the one-chip microcomputer 40 and the serial port Si. Here, the output buffer 47 is related to the motor group of the second channel CH2 and the LED group of the third channel CH3, and setting data SDATA2, SDATA3 for motor driving and lamp driving output from the one-chip microcomputer 40. The clock signals CK2 and CK3 and the operation permission signals ENABLE2 and ENABLE3 are output to the frame relay board 34 after the amplitude level is changed from 3.3V to 5V. The output 3 × 2 bit signal is transmitted to the general-purpose driver DVi of the motor drive board 37 and the lamp drive board 36 via the frame relay board 34 and the frame relay board 35.

  The output buffer 47 outputs an operation permission signal ENABLE4 separately from the above signal, and the operation permission signal ENABLE4 is transmitted to the shift register 50 of the frame relay board 35 via the frame relay board 34. Is done.

  Similarly, the output buffer 48 converts the lamp driving setting data SDATA1 output from the one-chip microcomputer 40, the clock signal CK1, and the operation enable signal ENABLE1 into an amplitude level of 5 V, and then converts the lamp driving board 29 into a level. The output buffer 49 converts the motor drive setting data SDATA0, the clock signal CK0, and the operation enable signal ENABLE0 to an amplitude level of 5V, and then drives the motor. It is transmitted to the general-purpose driver DVi of the substrate 30.

  Here, the general-purpose driver DVi mounted on the lamp driving board 29 drives the LED group of the first channel CH1, and the general-purpose driver DVi mounted on the motor driving board 30 is the rendering motors M1 to M9 of the 0th channel CH0. Is driving. Since each signal SDATAj, CKj, and ENABLEj is transmitted at an amplitude level of 5 V, as described above, it has a sufficient noise margin regardless of the transmission distance.

  Although not particularly limited, the production motors M1 to M9 of this embodiment are formed of unipolar stepping motors that are two-phase excited, and drive data Φ1 to Φ4 for two-phase excitation from the general-purpose driver DVi (FIG. 5 (d)) is driven by the motor driver OUT to receive an appropriate stepping operation.

  FIG. 7B shows effect motors M1 to M9, nine motor drivers OUT that drive the effect motors M1 to M9, and general-purpose drivers DV0 and DV1 that output drive data Φ1 to Φ4 to each motor driver OUT. The relationship is abbreviated. As illustrated, the general-purpose drivers DV0 and DV1 commonly receive a clock signal CK0, motor drive setting data SDATA0, and an operation permission signal ENABLE0 from the one-chip microcomputer 40. Further, the direct current voltage 12V is supplied from the effect interface board 27 to each of the effect motors M1 to M9.

  As shown in FIG. 5A, the motor driver OUT is configured to include four transistors Tr and four damper diodes Dp connected in Darlington, and receives drive data Φ1 to Φ4 from the general-purpose driver DVi. The production motor Mx is being driven. It should be noted that a high rotational torque is realized by flowing a higher level of drive current than the other effect motors Mx to the excitation windings Lx and Ly of the two effect motors M1 and M2 for reciprocating the movable effector AMU. Yes.

  FIG. 5A is a circuit diagram showing a connection relationship between the pair of motor drivers OUT and OUT and the pair of effect motors M1 and M3. As shown in the figure, in this embodiment, the motor driver OUT (driver IC) and the rendering motor Mx are not associated one-to-one, but a pair of motor drivers OUT, OUT and a pair of rendering motors. M1 and M3 are made to correspond. For each effect motor M1, M3, the motor driver OUT that supplies the drive current to the excitation winding Lx is configured separately from the motor driver OUT that supplies the drive current to the excitation winding Ly. FIG. 7C illustrates that the two-phase excitation windings Lx and Ly of the effect motor M1 are driven by different motor drivers OUT and OUT.

  Here, as the set of effect motors M1 and M3, effect motors that are not driven simultaneously or are unlikely to be driven simultaneously are selected. Therefore, the production motor M2 cooperating with the production motor M1 is combined with another production motor M4 to form another set (M2, M4). In this embodiment, since such a connection method is employed, two or more of the four transistors Tr incorporated in the motor driver OUT are not simultaneously turned on, and accordingly, a high drive current is supplied to the effect motor Mx. Even if it flows, the heat generation of the driver IC can be effectively suppressed.

  In addition, the connection relationship which suppresses the average power consumption of each driver IC by appropriately matching the set of two motor drivers OUT, OUT and the set of two stage motors Mx, My is 0th. The same applies to the other effect motors M5 to M8 of the channel and the effect motor MOi of the second channel CH2.

  FIG. 5B is a circuit diagram showing a configuration of a sensor substrate SENS (frame side member) for detecting that the movable effector AMU is accommodated in the origin region. The sensor substrate SENS, which is a panel side member, has the same circuit configuration, and each sensor substrate SENS includes, for example, an origin detection sensor PH and its associated circuit. Specifically, the origin detection sensor PH is a photo interrupter having a light emitting portion and a light receiving portion, the light emitting portion is constituted by a photodiode, and the light receiving portion is constituted by a phototransistor. A power supply voltage Vcc (= 5 V) is supplied to each of the photodiode and the phototransistor through a current limiting resistor, and the voltage at the collector terminal of the phototransistor is output as the origin switch signal SN.

  And between the light emission part and the light-receiving part, a part (light-shielding piece) of the movable effector AMU standing by in the origin area is positioned to block the inspection light of the photodiode. Therefore, as long as the movable effect body AMU is located in the origin area, the origin switch signal SN is at the H level. However, when the movable effect body AMU leaves the origin area, the origin switch signal SN becomes the L level (FIG. 5C). reference). As described above, since the origin switch signal SN is transmitted to the parallel input port Pi ′ of the one-chip microcomputer 40 (see FIG. 4), the effect control board 22 is based on the H / L level of the origin switch signal SN. Thus, it is possible to grasp whether or not the movable effector AMU is located in the origin area.

  The origin switch signal SN of the board side member is level-converted by the production interface board 27 and supplied to the parallel input port Pi ′ of the one-chip microcomputer 40 as the origin switch signal SN corresponding to the power supply voltage 3.3V. The On the other hand, the origin switch signal SN (6 bits) of the frame side member is serial-converted by the shift register 50 (FIG. 16A) of the frame relay board 35 and supplied to the serial input port S4 of the one-chip microcomputer 40. .

  FIG. 6A illustrates the internal configuration of the serial port Si built in the one-chip microcomputer 40. As shown in the figure, the serial ports S0 to S3 all have the same configuration as output ports, and receive a 1-byte data transfer from the transmission data register DR and a transmission data register DR that receives 1-byte data from the CPU core. , A transmission shift register SR that outputs serially as setting data SDATA, a number of control registers RG that manage the internal operation state of the serial port, and a frequency division ratio that is specified by the control register RG in response to the output pulse Φ of the counter circuit CT And a baud rate generator BG that outputs a clock signal CKj.

  In the case of the serial output port (S0 to S3), the control register RG includes a READable control register including the empty bit EMP, and indicates whether or not the transmission data register DR can accept new data. ing. That is, when transmission of 1-byte data in transmission shift register SR is completed, empty bit EMP changes to H level (empty level), indicating that new data can be written into transmission data register DR. Therefore, the CPU core (hereinafter referred to as CPU) writes new data into the transmission data register DR after confirming that the empty bit EMP is at the H level.

  On the other hand, the serial port S4 is an input port, and includes a reception shift register SR ′ that receives serial data SDATA4 from the outside and performs parallel conversion, and a reception data register DR ′ that receives 1-byte data from the reception shift register SR ′. , A transmission data register DR that receives 1-byte data from the CPU core, a number of control registers RG that manage the internal operation state of the serial port, and a frequency division ratio that is specified by the control register RG in response to the output pulse Φ of the counter circuit CT And a baud rate generator BG for outputting the clock signal CK4. Note that the internal circuit configurations of the serial ports S0 to S4 are all the same, and function as a serial input port or a serial output port based on differences in usage such as a difference in setting values in the control register RG.

  In the case of the serial input port (S4), the control register RG also includes a completion bit FULL indicating that 1-byte length data has been transferred to the reception data register DR ′. The CPU sets the completion bit FULL to H After confirming the level (completion level), the reception data is acquired from the reception data register DR ′.

  In addition, the control register RG of the serial port (S0 to S4) includes a WRITE control register including the transmission permission bit TXE and the reception permission bit RXE. When the CPU sets the transmission permission bit TXE to the ON (H) level, the transmission operation of the serial output ports (S0 to S3) is permitted, and when it is set to the OFF level, the transmission operation is prohibited. Therefore, in this embodiment, the CPU sets the transmission permission bit TXE to the ON state at the start of the transmission process, and resets the transmission permission bit TXE to the OFF level at the end of the transmission process.

  On the other hand, when the CPU sets the reception permission bit RXE to the ON (H) level, the reception operation of the serial input port (S4) is permitted, and when the CPU is set to the OFF level, the reception operation is prohibited. At the start, the reception permission bit RXE is set to the ON state, and at the end of the reception process, the reception permission bit RXE is reset to the OFF level.

  FIG. 6B is a time chart showing the operation at the start of transmission for the serial output ports S0 to S3. As shown in the figure, when the serial output ports S0 to S3 are in the transmission prohibited state (TXE = L), or after the data of the transmission data register DR is serially output, the clock signal CK is at the fixed H level. The transmission data register DR is empty, and the empty bit EMP is also at the H level (empty level).

  Then, after the CPU sets the transmission permission bit TXE to the ON state (transmission permission state) and then writes the first byte of transmission data to the transmission data register DR, the empty bit EMP transitions to the L level, and then After a predetermined time (τ) elapses, the first byte of transmission data is transferred to the transmission shift register SR, and the serial transmission operation is started.

  Further, since the transmission data is transferred to the transmission shift register SR, the empty bit EMP transitions to the H level (empty level) thereafter in response to the start of serial transmission of the first bit. Therefore, after confirming the H level empty bit EMP, the CPU writes the second byte of transmission data into the transmission data register DR.

  Then, in response to the data write operation to the transmission data register DR, the empty bit EMP transitions to the L level (full level). After that, when all the transmission data of the first byte is transmitted, the second byte of data is transferred from the transmission data register DR to the transmission shift register SR, and the data transmission of the second byte is started, and the empty bit EMP Transitions to the H level.

  The empty bit EMP changes to the L level in response to the data write operation of the third byte to the transmission data register DR. However, as shown in the figure, the empty bit EMP maintains the H level when no new data is written. . Further, after all the data is transmitted, the clock signal CK maintains the H level and does not change.

  Although not particularly limited, in this embodiment, in correspondence with the internal operation of the general-purpose driver DVi, transmission is performed in synchronization with the clock signal CK from the MSB (Most Significant Bit) of 1-byte data to the LSB (Least Significant Bit). The operation is set to be executed (MSB first), and an appropriate setting value is set in the corresponding control register RG. Further, as shown in the figure, the transmission operation proceeds in synchronization with the falling edge of the clock signal CK. Here, the flag sense system has been described in which the CPU determines the empty level of the empty bit EMP and then writes the next 1-byte data into the transmission data register DR. However, the empty bit EMP has changed to the H level. Corresponding to the above, it is also preferable to adopt an interrupt method for starting interrupt processing.

  FIG. 6C is a time chart showing the data reception operation for the serial input port S4. In the illustrated case, for the sake of convenience, the received data is 2 bytes long as a whole. However, when the serial input port S4 is in a reception prohibited state (RXE = L) or after the reception process of 2 bytes is finished, the clock signal CK4 is a fixed H level. The completion bit FULL is also at the L level (empty level).

  Then, after the CPU sets the reception permission bit RXE to the ON state, when the dummy data of the first byte is written in the transmission data register DR, the output of the clock signal CK4 is started. As will be described later, when the operation permission signal ENABLE = H, the shift register 50 of the frame relay board 35 outputs the serial data SDATA4 in synchronization with the falling edge of the clock signal CK4. Therefore, in response to the operation of the shift register 50, the serial input port S4 acquires the serial data SDATA4 in the reception shift register SR ′ for each bit in synchronization with the rising edge of the clock signal CK4 output by itself. To do.

  In this way, when the data acquired in the reception shift register SR ′ in synchronization with the clock signal CK4 reaches 8 bits, the 8-bit acquisition data is transferred from the reception shift register DR ′ to the reception data register DR ′. At the same time, the completion bit FULL is set to the H level (completion level). Therefore, after confirming the H level completion bit FULL, the CPU acquires the first byte of received data from the received data register DR '. Then, since the completion bit FULL returns from the H level to the L level (empty level) in response to the acquisition operation of the CPU, the CPU waits for the completion bit FULL to become the H level again. The received data is acquired.

  The clock signal CK4 returns to the steady level (H) when the transmission operation for the preset number of data bytes is completed or the reception permission bit RXE is set to the OFF level, so that excess data is serially transmitted. There is nothing. Here, the operation of the flag sense method for checking the completion bit FULL has been described. However, the operation is not limited at all, and an interrupt that automatically starts an interrupt process in response to the completion bit FULL transitioning to the H level is described. Of course, the method may be adopted.

  FIG. 7B and FIG. 7C schematically show the circuit configuration of the motor drive board 30. As shown in the drawing, two general-purpose drivers DV0 and DV1 and nine motor drivers OUT are mounted on the motor drive board 30, and nine effect motors M1 are supplied by supplying drive current from the motor driver OUT. -M9 realizes an appropriate stepping action. Note that the circuit configuration of the motor driver OUT is as shown in FIG. 5A, and it has also been described above that the nine motor drivers OUT and the nine effect motors M1 to M9 do not correspond one-to-one. (See FIG. 7C).

  The general-purpose driver DVi has a 24-bit output terminal and a 5-bit numbered terminal. As shown in the figure, the 24-bit output terminal is divided into four bits corresponding to the four input terminals (X, X bar, Y, Y bar) of the effect motor Mx, and one general-purpose driver DVi. From the maximum, drive data for six effect motors (six sets of Φ1 to Φ4) can be output.

  In this embodiment, the slave address (port address) is numbered by adopting a circuit configuration that fixes the voltage level of the numbered terminal of the general-purpose driver DVi. Specifically, the slave addresses of the general-purpose drivers DV0 and DV1 are 40H and 41H in hexadecimal notation (see FIG. 7B).

  Each general-purpose driver DVi includes a plurality of setting registers capable of setting operation contents, and each setting register is specified by a unique register number (for example, 00H to 2CH). . A setting value of 1 byte length is set in each setting register. Typically, ON / OFF information related to the output signal (24 bits) of the general-purpose driver DVi is set in the setting registers GR0 to GR2. The 24-bit ON / OFF information is set in a distributed manner in the three setting registers GR0 to GR2.

  Further, the gradation level related to the output signal (24 bits) of the general-purpose driver DVi can be set in another 24 setting registers MRx. The gradation level has 256 levels, and the output signal to which the gradation level is set is PWM-controlled based on the setting value (0 to 255) to the setting register, and the duty ratio based on the setting value (= 0 to 255 / 256). Therefore, it is possible to realize the restraint stop state in an optimally power-saving state with respect to the effect motor Mx in the pause state.

  In addition, if another three setting registers are used in MRy, it is possible to define the operation mode of fade-in and fade-out for each 24-bit output signal. Further, based on the set value in another setting register MRz. The fade-in speed and the fade-out speed can be set. Therefore, according to the present embodiment, the transition operation at the start or end of the rotation of the effect motor Mx can be optimized by appropriate fade-in control and fade-out control.

  FIG. 7A is a time chart for explaining the operations of the general-purpose drivers DV0 and DV1 that drive the effect motor Mx and the operation of the CPU as an example. Therefore, based on this time chart, the setting data SDATA0 output from the one-chip microcomputer 40 (actually the serial output port S0) and the setting registers (MR0 to MRn, GR0 to GR2) of the general-purpose driver DV0 receiving the setting data SDATA0 The relationship will be described. In addition, ON / OFF information related to the output signal of the general-purpose driver DVi is set in the setting registers GR0 to GR2, and (1) Transition control of motor driving current such as fade-in and fade-out is set in the other setting registers MR0 to MRn. And (2) setting values for gradation control of motor drive current by PWM control. However, it is also preferable to omit only (1) deviation control and (2) gradation control and stop only the output signal ON / OFF control.

  In any case, in order to set appropriate setting data SDATA in the setting registers MRx and GRx, prior to this, transmission processing of a slave address specifying each general-purpose driver DVi, and registers of the setting registers MRx and GRx It is necessary to execute transmission processing of number N (00H to ** H in the embodiment). However, if the register numbers N (= 00H to ** H) are consecutive, after the first register number N (= 00H) is transmitted, the settings to be set in the setting registers MRx and GRx after the register number 00H It is sufficient because the data Dn is output for each byte.

  The slave address is a 5-bit length port address (40H, 41H in the embodiment) that identifies the general-purpose driver DVi (see FIG. 7B), but is an 8-bit length with appropriate addition of 3 bits. The This 8-bit slave address is transmitted from the MSB to the LSB. As confirmed from the circuit configuration of FIG. 7B, the 8-bit slave address (40H or 41H) is commonly transmitted to the two general-purpose drivers DV0 and DV1, but the transmitted slave address ( Only the general-purpose driver DVi corresponding to 40H or 41H) receives subsequent transmission data (setting data).

  As shown in the time chart of FIG. 7A, specifically, in each of the general-purpose drivers DV0 and DV1, the first byte data is at the rising edge of the 24th (= 8 × 3) clock signal CK0. The slave address is acquired, and only the general-purpose driver DVi that matches its own slave address continues the subsequent reception process.

  Therefore, the serial port S0 of the one-chip microcomputer 40 next transmits the register number N (= 00H) of the setting register MR0 to the general-purpose driver DVi, and subsequently, setting data to the setting register MR0. Dn is transmitted. After that, the internal circuit of the general-purpose driver DVi functions, the register number N is automatically incremented, and the setting data Dn + 1, Dn + 2,. Registers GR0 to GR2 are set.

  Thus, in this embodiment, since n + 4 setting registers (MR0 to MRn, GR0 to GR2) in which register numbers N (= 00H to ** H) are continuous are used, the serial of the one-chip microcomputer 40 is used. The number of serial data transmitted from the port S0 to the general-purpose drivers DV0 and DV1 includes the slave address (1 byte), the register number (00H) of the setting register MR0, and n + 4 setting registers (MR0 to MRn, GR0 to GR2). ) And setting data (n + 4 bytes) to be set, the total is n + 6 bytes.

  As described with reference to FIG. 6B, the serial port S0 of the one-chip microcomputer 40 maintains the empty bit EMP of the control register RG at the H level after outputting the setting data of the (n + 4) th byte. In addition, the setting data of the (n + 4) th byte that has been written in the transmission data register DR is output from the transmission shift register SR toward the LSB for each bit from the transmission shift register SR in a state where the empty bit EMP = H level is maintained. Then, after the serial port S0 of the one-chip microcomputer 40 outputs the LSB of the setting data of the (n + 4) th byte, the clock signal CK maintains the H level.

  For this reason, the CPU of the one-chip microcomputer 40 returns the operation enable signal ENABLE0 to the L level at the timing when the setting data of the (n + 4) th byte is acquired by the corresponding general-purpose driver DVi, and the transmission enable bit of the control register RG. TXE is returned to the transmission prohibition level (see FIG. 7). Then, in response to the operation enable signal ENABLE0 = L, each of the general-purpose drivers DVi thereafter produces an effect motor based on the setting data newly set or set in the setting registers (MR0 to MRn, GR0 to GR2). Mx will be driven.

  The setting data SDATA0 output from the serial port S0 has been described above with respect to the general-purpose driver DVi of the channel CH0. However, the setting data SDATA1 to SDATA3 output from the other serial ports S1 to S3 and the general-purpose driver of the channels CH1 to CH3. The relationship with DVi is the same. In the above description, every time serial data SDATA (total of 2 + n + 4 bytes) for one general-purpose driver is transmitted, the transmission permission bit TXE is returned to the prohibition level. You may return to a prohibition level after transmission processing is completed. In particular, there is no need to return to the prohibited level.

  FIG. 8 is a flowchart for explaining the operation content of the effect control unit 22 ′, which is executed by the CPU of the one-chip microcomputer 40. The operation of the effect control unit 22 ′ includes a main process (FIG. 8A) executed in an infinite loop after the CPU reset, a timer interrupt process started every 1 mS (FIG. 8B), and a main control. And a reception interrupt process (not shown) for receiving a control command transmitted by the unit 21.

  First, the timer interrupt process (FIG. 8B) will be described. The timer interrupt process includes a motor update process (ST20) for updating excitation data to step up the effect motor Mx of channel CH0 and the effect motor MOi of channel CH2, and setting data SDATA including the excitation data as serial ports. Motor output process (ST21) for serial transmission from S0, S2 to each effect motor Mx, MOi, command output process (ST22) for outputting control command CMD 'to image control unit 23' when necessary, and effect button 11 switch A serial signal acquisition process (ST23) for acquiring a signal and an origin switch signal SN as a serial signal, and an interrupt counter increment process (ST24) are configured. As shown in FIG. 8E, the excitation data regarding the effect motor Mx (M1 to M9) is 9 × 4 bits corresponding to the number of motors and the drive data Φ1 to Φ4.

  By the way, the details of the motor update process (ST20) regarding the effect motors M1 to M9 of the channel CH0 will be described later based on FIG. 8 (d) and FIGS. 9 to 12, and the details of the motor output process (ST21) will be described. This will be described later with reference to FIG. The serial signal acquisition process (ST23) will be described later with reference to FIG.

  Then, the explanation will be shifted to the main process (FIG. 8A). In the main process, the CPU first repeatedly checks the interrupt counter in accordance with the configuration of the 1 mS timer interrupt (FIG. 8B). Then, it waits until the value of the interrupt counter becomes 16 (ST10). As described above, since the interrupt counter is updated every 1 mS (ST23), in step ST10, an elapsed time until 16 mS elapses from the process of the previous step ST11 is waited. Therefore, in this embodiment, the main processing of steps ST11 to ST17 is repeated every 16 ms.

  Next, when the standby time of 16 mS has elapsed, the interrupt counter is cleared to zero (ST11), and the control command CMD transmitted from the main control unit 21 is analyzed (ST12). The control command CMD includes a change pattern command, a notice effect command, a notification control command, a hold number command, and the like.

  Therefore, in the command analysis process, as shown in FIG. 8C, first, it is determined whether or not a variation pattern command is newly received (ST70). An effect lottery that specifically specifies is executed (ST71). Then, the initial setting process is executed for the production scenario to be executed (ST73). In addition, when a notice effect command is received, an initial setting is made for the effect scenario of the notice effect (ST72, ST73). The notice effect includes effects for rotating the effect motors M1 and M2 corresponding to the movable effect body AMU, the other effect motors M3 to M9 of the channel CH0, and the effect motor MOi of the channel CH2. The effect scenario initially set in this way is managed and progressed at intervals of 16 mS (ST14).

  Next, after determining the level of the switch signal such as the effect button 11 (ST13), the effect scenario that is set to start is updated (ST14). Then, the audio reproduction operation is advanced in response to the production scenario (ST15). The switch signal from the effect button 11 is acquired by the serial signal acquisition process (ST23).

  Subsequently, with respect to the LED groups connected to the lamp driving substrates 36 and 29, the brightness data defining the brightness of each lamp is updated based on the updated production scenario, and the LED output buffer (not shown) is updated. Luminance data is stored (ST16). Next, the setting data including the brightness data updated in the process of step ST16 is transmitted to the lamp driving boards 36 and 29 via the serial ports S1 and S3 (ST17).

  As described above, the serial ports S1, S2, and S3 are output ports having the same configuration as the serial port S0, and the general-purpose driver DVi mounted on the lamp driving boards 36 and 29 is mounted on the motor driving board 30. This is the same as the general-purpose driver DVi. Therefore, the specific content of the LED output process (ST17) is the same as the motor output process (ST21) shown in FIG. However, in this embodiment, in consideration of human visual perception, LED groups that do not require special high-speed processing are controlled to be turned on every 16 mS (see ST16 to ST17), while precise and diverse operations are smoothly realized. The production motors Mx and MOi are controlled at high speed every 1 mS (see ST20 to ST21) to realize the optimum production operation. Further, in this embodiment, by utilizing the serial ports S0 to S3, a complicated and sophisticated rendering operation is realized while greatly reducing the control burden on the CPU.

  Hereinafter, the motor update process (ST20) and the motor output process (ST21) that exhibit such effects will be described in particular with respect to the effect motor Mx of the channel CH0. The control operation for the effect motor Mx of the channel CH2 which is the frame side member GM1 is basically the same as the control operation for the effect motor Mx of the channel CH0 described below.

  FIG. 8D is a flowchart specifically showing the contents of the motor update process (ST20) of the channel CH0. This motor update process (ST20) defines the contents of each effect for the effect motors M1 to M9. It is executed based on the effect table TBL (see FIG. 9A) (ST50 to ST64). Here, the production table TBL specifically defines the contents of the production of a series of motor productions, and any one of a large number of production tables TBL... Is defined in the production scenario (see ST72 and ST14). ing.

  And about each production motor M1-M9 of channel CH0, when the start timing of the motor production prescribed | regulated to the production scenario is reached, the motor production flag will be set, and based on the production table TBL specified by the production scenario. Step ST52 and subsequent steps are executed. On the other hand, at other timings, the excitation data Φ1 ′ to Φ4 ′ of the motor output buffer BUF (see FIG. 8E) are maintained in the clear state. In this embodiment, the motor output buffer BUF has an area of 4 × 9 bits of excitation data corresponding to nine types of drive data (Φ1 to Φ4) of the effect motors M1 to M9 (FIG. 8). (E)) If the motor effect flag is in the set state, the excitation data Φ1 ′ to Φ4 ′ of the effect motor Mx corresponding thereto is updated every 1 ms.

  By the way, the motor effect of the present embodiment is configured by combining a group of unit effects, and the execution order, execution time, and execution speed of the unit effects are defined in the effect table TBL. As described above, in this embodiment, a large number of effect tables TBL... TBL are prepared, but in FIG. 9B, the effects defined in the effect table TBL of FIG. The operations of the motors M1 and M2, and the movable effector AMU moves to the target position after repeating the reciprocating motion near the origin region, and the effector motors M3 and M4 are executed based on the other effect table TBL ″. The case where the movable effect body AMU is collected in the origin area after the movable notice effect is shown.

  Here, the movable notice effect by the effect motors M3 and M4 is a notice effect having a high possibility of reaching a big hit state (high reliability). Therefore, there is also provided an effect table TBL ′ that defines an operation of returning to the origin area without executing the movable advance notice effect, although the movable effect body AMU repeats the reciprocating motion as the advance notice effect with low reliability. For the movable notice effect by the effect motors M3 and M4, various effect tables TBL "... are provided.

  As described above, in this embodiment, various production tables TBL... Are prepared, and any production table lists a series of motors by listing unit productions and management operations along the operation line LN. The control action is specified. Here, the unit effect means a group of rotation operations or stop operations for the effect motor Mx, and the management operation is an operation that defines an operation procedure of the unit effect, and includes repetitive processing, transition processing, Specify termination processing.

  More specifically, for the unit effects relating to the effect motors M1 and M2, (1) CW_OFF operation that repeats normal rotation until the origin switch signal SN is turned off (see FIG. 10C), (2) origin CCW_ON operation that repeats reverse rotation until the switch signal SN is turned on (see FIG. 10E), (3) CW_ALL operation that repeats normal rotation by the specified number of steps (see FIG. 10A), and (4) specified step CCW_ALL operation (see FIG. 10D) that repeats reverse rotation by the number of times and (5) KEEP operation that repeats stop operation for a specified unit time are included. In this embodiment, the movable effect body AMU moves away from the origin area by forward rotation (CW) of the effect motors M1 and M2, and approaches the origin area by reverse rotation (CCW).

  In addition, for the unit effects related to the other effect motors M3 to M9, (6) CW_ON operation (see FIG. 10B) that repeats normal rotation until the other switch signal SN ′ is turned on (see FIG. 10B), (7) Other CCW_OFF operation that repeats reverse rotation until the switch signal SN ′ is turned off (see FIG. 10 (f)), (8) CW_BTN operation that repeats forward rotation until the target position is reached if the effect button is pressed down (FIG. 11). (A)), and (9) CCW_BTN operation (see FIG. 11 (b)) that repeats reverse rotation until the target position is reached if the effect button is kept pressed.

  On the other hand, in the management operation, a LOOP_S command (refer to FIG. 12 (a)) for specifying the start position of the repetitive process, a LOOP_E command (refer to FIG. 12 (b)) for specifying the end position of the repetitive process, and the motor effect are normally ended. NOR_END command (see FIG. 12 (c)) to be executed, SYS_CK1 command (see FIG. 12 (d)) for determining the end of the ON state of the origin switch signal SN, and SYS_CK2 command (for determining the end of the OFF state of the other switch signal SN ′) 12), and a SYS_ERR command (not shown) that defines the start of the abnormality handling process.

  The effect table TBL of this embodiment includes an OPT field that defines the operation contents of the unit effect and the management operation, and a SPEED field that specifies the operation speed (more precisely, the operation cycle) of the unit effect specified in the OPT field. , A STEP column for specifying the number of repetitions of the unit effect specified in the OPT column is provided. In the case of a management operation, the SPEED column and the STEP column are often blank (NULL). However, in the case of the SYS_CK1 command and the SYS_CK2 command, the relative position regarding the update of the operation line LN is defined in the SPEED column. The

  Based on the above, when the operations of the rendering motors M1 and M2 defined by the rendering table TBL in FIG. 9A are confirmed, the rendering table TBL rotates the rendering motors M1 and M2 in the normal rotation by 8 steps at a low speed of 6 levels. After that (unit effect 1), based on the LOOP_S command and the LOOP_E command, it is specified that the processing of the unit effect 2 to the unit effect 7 is repeated five times.

  That is, in the effect table TBL of FIG. 9A, the normal rotation is performed until the detection switch is turned off at a high speed of 3 levels (unit effect 2), and the normal rotation is performed at a high speed of 40 steps (unit effect 3). Waiting for a unit time (1 mS) (unit effect 4) is first defined. Next, after reversing at high speed until the detection switch is turned on (unit effect 5), further reverse at 20 steps (unit effect 6), after waiting for 1 × 100 unit time (unit effect 7), and then to unit effect 1 It is stipulated that the same processing is repeated after returning. In the present embodiment in which the motor update process (ST20) and the motor output process (ST21) are executed every 1 mS, for example, when operating at a three-level speed, the processing time for one step is 3 ms.

  After such a loop process (unit effect 2 to unit effect 7), after waiting for 2 × 1000 unit time (= 2 seconds) (unit effect 8), it rotates forward at a low speed until the detection switch is turned off (unit effect 9). ) Further, after normal rotation at a high speed of 280 steps (unit effect 10), it waits for 3 × 1000 unit time (= 3 seconds) (unit effect 11). In this embodiment, the rotation of 800 steps in the unit effect 10 means the movement of the movable effector AMU to the target position. In addition, using the standby time (2 seconds / 3 seconds) of the unit effect 8 and the unit effect 11, it corresponds to the movable notice effect that the other effect motors M3 to M9 rotate and the movable effector position moved to the target position. The liquid crystal display effect is executed.

  Then, after reversing by 8 steps at a low speed (unit effect 12), it reverses at a high speed until the detection switch is turned on (unit effect 13), followed by a high speed reversal of 30 steps (unit effect 14), and a low speed by 20 steps. To reverse (unit effect 15).

  Thereafter, based on the SYS_CK1 command, it is determined whether or not the detection switch is in the ON state. If the detection switch is in the ON state, the operation line LN is +2, and the next NOR_END command is executed. On the other hand, if the detection switch is in the OFF state, the operation line LN is incremented (+1), and the abnormality handling process is started based on the SYS_ERR command.

  As confirmed from the above operation, in this embodiment, the movable effector AMU repeats the reciprocating motion prior to the highly reliable movable advance notice effect executed by moving to the target position. It is possible to effectively excite players who expect a movable notice effect.

  In the present embodiment configured as described above, if the movable effect body AMU does not accurately move to the target position, there is a possibility that the precious movable notice effect will not be normally executed. That is, for example, when a large number of effect motors M3 to M9 rotate in a complicated manner to execute a movable notice effect, if there is an obstacle on any rotation locus, the intended movable notice effect cannot be executed, The player will be whitened. In addition, when performing a liquid crystal display effect corresponding to the position of the movable effector moved to the target position, the liquid crystal display effect and the position of the movable effector do not correspond.

  However, in this embodiment, prior to the movement of the movable effector AMU to the target position (unit effect 10), the OFF transition of the origin switch signal SN is confirmed (unit effect 9), and the movable effector AMU is designed. Since it matches the upper absolute position (the end position of the origin area), the movable effector AMU can be accurately moved to the target position on the basis of the number of design steps (= 280). The notice effect can be executed normally.

  As described above, in this embodiment, even if the reciprocating operation of the movable effector AMU is repeated at a high speed, the current position of the movable effector AMU may be deviated from the design position based on the inertial force or the like. The shift can be eliminated by making the movable effector AMU coincide with the end point position of the origin region by the CCW_ON operation or the CW_OFF operation. Therefore, the reciprocating operation including the CW_OFF operation and the CCW_ON operation is not particularly required as in the unit effect defined by the effect table TBL in FIG. 9A, and precedes the final CW_ALL operation (unit effect 10). Then, by providing the CW_OFF operation (unit effect 9), it is possible to eliminate the deviation accumulated so far. If the CW_OFF operation (unit effect 9) is omitted, the CCW_ON operation (unit effect 5) is provided prior to (preferably immediately before) the final CW_ALL operation (unit effect 10), thereby causing a position shift. Can be eliminated.

  The production table TBL in FIG. 9A has been described in detail above, but the motor update process in FIG. 8D is executed with reference to the production table TBL specified in the production scenario. Note that the variable LN specifies a unit effect and a management operation corresponding to the operation line LN of the effect table TBL. The step counter STC manages the number of repetitions specified in the STEP column of the effect table TBL, and the standby counter WTC manages the operation speed (specifically, the operation cycle) specified in the SPEED column of the effect table TBL. .

  Based on the above, the motor update process (ST20) shown in FIG. 8 (d) will be described. If the production motor Mx to be controlled is in the middle of the motor production (YES in ST51), then the production motor Mx to be controlled is changed. With respect to the corresponding effect table TBL, it is determined whether or not the unit effect specified in the operation line LN or the process of management operation is started (analysis timing) (ST52). Although the analysis timing determination method is appropriate, if the step counter STC and the standby counter WTC relating to the corresponding effect table TBL are zero, the analysis timing is reached.

  If the present time is the analysis timing, the value of the OPT column of the effect table TBL is set to the variable KND, and the expiration values of the step counter STC and the standby counter WTC are specified from the values of the SPEED column and the STEP column ( ST53). In the present embodiment, since either the unit effect (FIGS. 10 to 11) or the management operation (FIG. 12) is defined in the OPT column of the effect table TBL, next, based on the value of the variable KND. Then, it is determined whether the process to be executed thereafter is a management operation system process (ST54).

  If the management operation system process is defined in the variable KND, the process is executed (ST55). For example, when the LOOP_S command is defined, the loop count is set based on the value in the SPEED column (SS45 in FIG. 12), the loop start point is set to the value of the operation line LN + 1 (SS46), and the operation The line LN is incremented to finish the process (SS47). Thereafter, the process immediately proceeds to step ST53 without waiting for the next timer interruption. Therefore, with respect to the operation line LN that has been incrementally updated, the value of the OPT column of the effect table TBL is set to the variable KND, and the expiration values of the step counter STC and the standby counter WTC are specified from the values of the SPEED column and the STEP column. (ST53). Needless to say, when the process proceeds to step ST53 during the subroutine processing, the jump instruction is executed after the stack area is arranged. This is the same in the following cases.

  As confirmed from the above operation, in the case of the effect table TBL of FIG. 9, when the unit effect 1 is finished, the unit effect 2 is immediately shifted to, and an extra time delay occurs due to the LOOP_S command. Absent. By the way, the number of loops and the loop start point set in the analysis process of the LOOP_S command are used when the LOOP_E command is analyzed. That is, when the LOO_E command is defined in the variable KND, if the loop count> 0, it is decremented (SS49 in FIG. 12). If the loop count = 0, the operation line LN is incremented (SS52). If the loop count ≠ 0, the operation line LN is set as the loop start point (SS51) and waits until the next timer interrupt. Immediately, the process proceeds to step ST53. Therefore, in the case of the effect table TBL of FIG. 9, when the unit effect 7 is finished, the unit effect 2 is started immediately without any extra time delay.

  On the other hand, when the NOR_END command is defined in the variable KND, the excitation data (for example, effect data) of the corresponding region for the motor output buffer BUF (FIG. 8 (e)) in which the excitation data Φ1 ′ to Φ4 ′ are stored. The excitation data [Phi] 1 'to [Phi] 4') of the motors M1 and M2 are cleared (SS53), the motor effect flag in the set state is cleared, and the process ends (SS54). The clearing process of the motor effect flag is a process of clearly indicating that the motor effect that has been executed (for example, by the effect motors M1 and M2) has ended. After that, based on the determination in step ST51, the effect motor For M1 and M2, the processing of steps ST52 to ST63 is skipped.

  The management operation system processing has been described above (ST55). When the unit effect is defined in the variable KND, the standby counter WTC is compared with the value in the SPEED column (ST56). The standby counter WTC is a variable for managing the operation speed of the motor effect, and is zero in the initial state. Therefore, if WTC <SPEED-1, the increment process (ST57) is repeated until WTC = SPEED-1, and the standby state (stopped state) is maintained. Thereafter, when WTC = SPEED-1 (ST56), the step counter STC is incremented and updated (ST58), and the unit effect specified in the OPT column is executed (ST59). Next, unless the step counter STC matches the value in the STEP column (ST60), the standby counter WTC is cleared to zero and the process ends (ST61).

  On the other hand, when the updated value of the step counter STC matches the value in the STEP column (ST60), the step counter STC and the standby counter WTC are cleared to zero (ST62), and the operation line LN is incremented to process this unit effect. (ST63).

  As described above, in this embodiment, the unit effect is executed after waiting for the number of times specified in the SPEED field. Therefore, the smaller the number of standby times, the faster the progress of the unit effect. The value in the column defines the operation speed (more precisely, the operation cycle) of the motor effect.

  Further, such a unit effect is repeated until the value of the step counter STC matches the value of the STEP column (ST60), so that the value of the STEP column eventually defines the number of repetitions of the unit effect. Since the step counter STC and the standby counter WTC are incremented every 1 mS (ST57, ST58), for example, the CW_ALL operation defined in the first row of the effect table in FIG. One step is moved every 6 mS, and such a stepping operation is repeated a total of eight times to complete the operation. If the operation period of the motor update or motor output process is τ, the operation duration time of the unit effect is SPEED value × STEP value × τ.

  Next, the unit effect defined in FIGS. 10 to 11 will be described. Note that the KEEP operation is not particularly described, but the standby process of waiting for the number of times specified in the SPEED column is only repeated for the number of times in the STEP column, and there is no processing as the rendering operation (ST59).

  On the other hand, for other unit effects, there is a substantial effect operation accompanied by the update process of the excitation counter MC. Here, the excitation counter MC is a variable for specifying the excitation data Φ1 ′ to Φ4 ′ to be stored in the motor output buffer BUF (FIG. 8E). As shown in FIG. It is updated cyclically in the range of 3.

  For example, in the CW_ALL operation shown in FIG. 10A, the excitation data Φ1 ′ to Φ4 ′ instructed by the excitation counter MC is stored in the motor output buffer BUF (SS1), and the excitation counter MC is incrementally updated. Then, the process is finished (SS2). On the other hand, in the case of the CCW_ALL operation shown in FIG. 10D, the excitation data Φ1 ′ to Φ4 ′ instructed by the complement of the excitation counter MC are stored in the motor output buffer BUF (SS13), and the excitation counter MC is circulated. Incremental updating is completed, and the process ends (SS14). Here, for the sake of convenience, the complement of the excitation counter MC means taking the NOT value for the lower 2 bits of the excitation counter MC.

  In this case, when the excitation counter MC is updated cyclically, the excitation counter MC changes in the forward direction from 0 → 1 → 2 → 3 → 0 → 1... → 1 → 0 → 3 → 2. Therefore, in this embodiment, excitation data Φ1 ′ to Φ4 ′ for normal rotation of the effect motor are generated in time sequence by the excitation counter MC that is incremented and updated, while the complement (lower 2 bits) of the excitation counter MC that is incremented and updated. Excitation data Φ1 ′ to Φ4 ′ for reversing the effect motor is generated by the NOT value).

  Therefore, the CW_XX operation and the CCW_XX operation are basically the same operation, and the excitation counter MC indicates the excitation data Φ1 ′ to Φ4 ′ or its complement indicates the excitation data Φ1 ′ to Φ4 ′. There is only a difference. For example, in the CW_ON operation shown in FIG. 10B, if the origin switch signal SN is in the OFF state, the excitation data Φ1 ′ to Φ4 ′ instructed by the excitation counter MC is stored in the motor output buffer BUF (SS6). The counter MC is incremented and updated (SS7). When the origin switch signal changes to the ON state, the standby counter WTC and the step counter STC are cleared (SS4), the operation line LN is incremented, and the process proceeds to step ST53 (SS5).

  On the other hand, in the CCW_ON operation shown in FIG. 10E, if the origin switch signal SN is in the OFF state, the excitation data Φ1 ′ to Φ4 ′ instructed by the complement of the excitation counter MC is stored in the motor output buffer BUF. Only (SS18) is different.

  This relationship is the same for the CW_OFF operation (FIG. 10C) and CCW_OFF (FIG. 10F). When the origin switch signal SN changes to the OFF state corresponding to the CW_ON operation and the CCW_ON operation, respectively. The process proceeds to step ST53 (SS10, SS22).

  In the CW_BTN operation, the forward rotation operation is continued as long as the effect button 11 is continuously pressed (SS33 to SS35). When the target position is reached (SS30), the standby counter WTC and the step counter STC are cleared (SS31), The operation line LN is incremented and the process proceeds to step ST53 (SS32). On the other hand, the CCW_BTN operation is different only in that the reverse rotation operation is executed instead of the normal rotation operation (SS40). In the CW_BTN operation and the CCW_BTN operation, when the hand is released from the effect button 11, the movement of the effect motor is stopped.

  FIG. 13 is a flowchart for explaining the motor output process (ST21) in more detail. In the motor output process (ST21), the processes of ST33 to ST43 are executed for the general-purpose drivers DV0 and DV1 on the condition that any one of the effect motors M1 to M9 is in the motor effect. This process is described as a process related to the serial port S0 of the channel CH0, but is basically the same for the serial port S2 of the channel CH2. Also in the case of the LED output process (ST17), similar processes (ST31 to ST45) are performed on the luminance data in the serial ports S1 and S3.

  Hereinafter, the motor output process (ST21) will be described. At the timing of step ST31, as shown in FIG. 6B, the transmission permission bit TXE of the control register RG is at the OFF (L) level, and the empty bit EMP is The clock signal CK is kept at the H level (empty level). Further, the operation permission signal ENABLE0 is at L level.

  Therefore, first, the ON (H) level operation enable signal ENABLE0 is output from the parallel output port Po ′, and the transmission enable bit TXE of the control register RG is set to the ON level to enable the transmission processing of the serial port S0. The state is set (ST31). Note that when the operation enable signal ENABLE0 = H, the two general-purpose drivers DV0 and DV1 can receive serial data.

  Therefore, subsequently, the processes of steps ST33 to ST43 are repeated for the general-purpose driver DV0 and the general-purpose driver DV1. Specifically, the slave address (40H or 41H) of the general-purpose driver DVi is written to the transmission data register DR of the serial port S0 (ST33).

  As shown in FIG. 8, by the process of step ST33, the empty bit EMP of the control register RG of the serial port S0 changes to the L level, and after a predetermined time (τ), the empty bit EMP returns to the H level and the slave The address transmission operation is started. Therefore, after the empty bit EMP returns to the H level (ST34), for the group of setting registers (MR0 to MRn, GR0 to GR2) of the general-purpose driver DVi, the head address of the register number is written to the transmission data register DR. (ST35). In this embodiment, since the register number N of the setting registers (MR0 to MRn, GR0 to GR2) is a serial number starting from 00H, 00H is written to the transmission data register DR in the process of step ST35. .

  Then, the empty bit EMP transits from the H level to the L level (full level) by the process of step ST35. After that, when transmission of the first slave address is completed, the empty bit EMP returns to the H level (empty level) (ST36), and thereafter, the process shifts to a transmission process of n + 4 setting data. Specifically, first, the variable j is initialized to zero (ST37). Here, the variable j is used for the purpose of counting the number of times set in the setting registers (MR0 to MRn, GR0 to GR2).

  Therefore, next, after the variable j is incremented (ST38), the setting data to be set in the setting registers (MR0 to MRn, GR0 to GR2) is written to the transmission data register DR of the serial port S0 (ST39). The first setting data is management data to be written to the setting register MR0.

  By the way, the empty bit EMP changes to the H level in the determination of step ST36, and then returns to the L level. In this state, the register number transmission operation is executed. When this transmission operation ends, the empty bit EMP transitions to the H level. Next, the system waits for the empty bit EMP to transition to the H level (ST40). Unless writing to MR0 to MRn, GR0 to GR2) is completed, the process proceeds to step ST38 (ST41).

  Therefore, thereafter, the write processing of the setting registers (MR0 to MRn, GR0 to GR2) is repeated by the processing of steps ST38 to ST41. When setting to the setting registers (MR0 to MRn), pre-defined management data is written to the transmission data register DR of the serial port S0, and when setting to the setting registers (GR0 to GR2), it is stored in the motor output buffer BUF. The stored excitation data Φ1 ′ to Φ4 ′ are written to the transmission data register DR of the serial port S0 (ST39).

  Even if the last byte of setting data is written in the transmission data register DR, the general-purpose driver DVi acquires this after the output of about eight clock signals CK. Therefore, after consuming about eight clock signals CK (ST42), the slave address is updated (ST43), and the setting process for the next general-purpose driver DV1 is repeated (ST33 to ST43). When the process for the general-purpose driver DV1 is completed, the operation permission signal ENABLE is returned to the prohibited level, and the transmission permission bit TXE of the control register RG is returned to the prohibited level (ST45). As a result, the rotation position of the effect motor Mj connected to the general-purpose driver DVi whose setting data has been updated is updated.

  As described above, in the present embodiment, the setting processing for the setting registers of the two general-purpose drivers DVi is completed at once by the processing of steps ST31 to ST45, and the drive data Φ1 to Φ4 are received from the general-purpose drivers DV0 to DV1. The effect motor Mx executes an appropriate stepping operation every 1 mS, and a precise motor effect is possible. In addition, a smooth transition operation (face-in / phase-out) is possible even when rotation is started or stopped.

  In the above embodiment, the operation permission signal ENABLE0 is used and the timing for updating the motor drive state is defined by the operation permission signal ENABLE0. However, the operation permission signal ENABLE0 is not limited at all. That is, if a configuration in which an end command (period command) is transmitted at the end of a series of serial data, the motor drive state can be updated based on the internal processing of the general-purpose driver DVi that recognizes that the period command has been received. . However, in this case, in order to control the operation permission state of the general-purpose driver DVi, it is necessary to transmit a start command (start command) prior to transmission of a series of setting data.

  In this embodiment, for example, when updating the setting data in the setting registers GR0 to GR2, [Start command] → [Slave address (40H) defining the general-purpose driver DV0] → [Specify setting register GR0] Sub-address to be set] → [setting data for setting register GR0] → [sub-address specifying setting register GR1] → [setting data to setting register GR1] → [sub-address specifying setting register GR2] → [setting data to setting register GR2] In other words, serial data having a plurality of bytes is transmitted to the general-purpose driver DV0. If n + 1 pieces of setting data are transmitted to the other setting registers (MR0 to MRn) prior to setting processing of the setting registers GR0 to DG2, the entire setting data has n + 4 bytes, and each has a subaddress. Therefore, the total amount of transmission data is 2 × (n + 4) bytes. In consideration of the start command and the end command, serial data of 2 × (n + 4) +2 bytes is transmitted.

  FIG. 14 is a flowchart showing a serial data transmission process for updating the setting data for the general-purpose driver DVi that does not use the operation enable signal ENABLE0. Also in this case, the same processing (ST71 to ST86) is repeated for a plurality of general-purpose drivers DVi (for example, DV0 and DV1).

  In the following, first, a 1-byte start command (for example, FFH) is written in the transmission data register DR of the serial port S0 (ST71). Then, the start bit serial transmission of the start command is awaited by determining the empty bit EMP of the control register RG (ST72). When the empty bit EMP of the control register RG becomes EMP = 1, the slave address of the general-purpose driver DVi is written into the transmission data register DR (ST73). The slave address is nothing but a port number (for example, 40H or 41H) assigned to the general-purpose driver DVi.

  Next, it waits for the empty bit EMP to become EMP = 1 (ST74), and when serial transmission of the slave address (port number) is started, the variable j is initialized to zero (ST75). Subsequently, after incrementing the variable j (ST76), the subaddress is written to the transmission data register DR of the serial port S0 (ST77). Here, the sub-address is a register number that specifies the setting register (MR0 to MRn, GR0 to GR2).

  Next, it waits for the empty bit EMP to become EMP = 1 (ST78). If EMP = 1, the setting data to be transmitted to the setting register specified by the previous subaddress (register number) is transmitted to the transmission data register DR. (ST79). Note that the setting data for the setting registers (MR0 to MRn) is a predetermined fixed value, and the setting data for the setting registers (GR0 to GR2) is read from the motor output buffer BUF.

  The same applies to the following. When serial transmission of setting data is started (ST80), unless it is final setting data (ST81 is No), the next subaddress (register number) is stored in the transmission data register DR of the serial port S0. Writing (ST76 to ST77) and similar serial data transmission processing are repeated.

  On the other hand, when serial transmission of the final setting data is started (Yes in ST81), a period command indicating that serial transmission to the general-purpose driver DVi is completed is subsequently written in the transmission data register DR ( ST82). When serial transmission of a period command is started (ST83), the transmission time is secured (ST84), the slave address (port number) is updated, and similar serial data transmission processing (ST71 to ST85) is performed. repeat.

  As described above, in the embodiments shown in FIGS. 13 and 14, the setting data for the setting registers (MR0 to MRn) is repeatedly set every 1 mS. However, when the setting data is a fixed value defined in advance, it is also preferable to execute this setting process only once and omit the subsequent setting process. In this case, the data to be repeatedly set every 1 mS is only 3-byte length setting data for the setting registers (GR0 to GR2), so that the serial transmission process can be greatly simplified. Incidentally, the amount of data serially transmitted to the general-purpose driver DV0 is a total of 5 bytes of slave address + start register number + 3 setting data (3 bytes) in the embodiment of FIG. 13, and in the embodiment of FIG. The total number of start command + slave address + 3 × (sub address + setting data) + period command is 9 bytes.

  When such a configuration is adopted, it is particularly preferable to use the serial port S0 provided with a FIFO buffer, and the serial data transmission processing can be simplified extremely. Here, the FIFO buffer means a storage area of a FIFO (First In First Out) structure in which parallel data of a predetermined unit length (a plurality of bytes) can be temporarily stored, and 1-byte serial data is transmitted from the serial port Si. Each time, the next 1-byte data is automatically supplied to the transmission data register DR. That is, as shown in FIG. 15B, the FIFO buffer is configured to be accessible from the CPU core, and is automatically transferred to the transmission data register DR for each byte in order from the data stored in the FIFO buffer first. (First In First Out) is output as serial data SDATA via the transmission shift register SR.

  Therefore, the CPU does not need to be particularly involved in the subsequent processing after writing a series of serial data in the FIFO buffer. The processing in this case is, for example, as shown in FIG. 15A, and the CPU may write a group of data into the FIFO buffer (ST91) and wait for the FIFO buffer to become empty (ST92).

  By the way, in each of the above embodiments, the CPU exclusively reads the control register repeatedly and checks the empty bit EMP of the control register, but the timing when the transmission data register DR becomes empty (empty). It is also preferable to adopt a configuration in which the CPU is interrupted at the timing when the FIFO buffer is empty (empty area). In this case, in response to the interrupt request, the CPU may write 1-byte data into the transmission data register DR or write data of a predetermined unit length into the FIFO buffer.

  The serial signal (setting data SDATA0 to SDATA3) output processing has been described in detail above for the general-purpose driver DVi of the channels CH0 to CH3. Subsequently, the switch signal of the effect button 11 and the origin switch signal SN are used as serial signals. The serial signal acquisition process (ST23) to be acquired will be described.

  FIG. 16 illustrates a circuit configuration of the frame relay board 35 related to transmission of a serial signal. As shown in FIG. 16A, the frame relay board 35 includes a shift register 50, an input buffer circuit 51, and a filter circuit 52. The input buffer circuit 51 includes a pull-up resistor R and an inverter IN, and logically inverts the switch signal received from the effect button 11 and the origin switch signals SN0 to SN5. In this embodiment, the origin switch signal SN for the frame-side effect motor MOi is 6 bits long, and the effect button 11 has two contacts, so that a switch signal having a total length of 8 bits is input to the input buffer circuit. 51 is supplied to eight input terminals (A to H) of the shift register 50.

  The filter circuit 52 constitutes a CR low-pass filter composed of resistors R1 and R2 of about 50 to 100Ω and capacitors C1 and C2 of about 50 to 100 pF. As described above, in this embodiment, the time constant of the filter circuit 52 is designed to be 2.5 to 10 × 10 −9 [S], and overshoot and undershoot are prevented even at a communication speed of about 2 Mbps to 8 Mbps. Suppressing and realizing serial communication without malfunction can be realized.

  As the shift register 50 of this embodiment, for example, TC74VHC165F (Toshiba) whose internal circuit is shown in FIG. 16B is used, and the above 8-bit switch signal is supplied to its parallel input terminals A to H. The data of these parallel input terminals A to H are configured to be acquired by an internal register in synchronization with the falling timing of the latch signal LT.

  The latch signal LT is a logical inversion of the operation enable signal ENABLE4 output from the parallel output port Po 'of the one-chip microcomputer 40. When the operation permission signal ENABLE4 becomes H level, the latch signal LT becomes L level, and the data of the parallel input terminals A to H is acquired by the shift register 50. The acquired data (8-bit length parallel data) is then output from the output terminal QH in synchronization with the clock signal CK4 and becomes serial data. As described above, the clock signal CK4 is output from the serial input port S4 of the one-chip microcomputer 40, and the serial data SDATA4 is acquired by the CPU for each byte.

  In this embodiment, since the serial input terminal INPUT and the prohibition terminal INHIBIT of the shift register 50 are fixed to the L level, the data acquired by the shift register 50 is synchronized with the rising edge of the clock signal CK4. Is output. The serial input port S4 sequentially acquires the serial switch signal SDATA4 in synchronization with the falling edge of the clock signal CK4 output by itself.

  FIG. 17 is a flowchart for explaining the serial signal acquisition process (ST23) of FIG. The serial signal acquisition process (ST23) is a process related to the serial port S4. The CPU first sets the operation permission signal ENABLE4 to the H level and then returns it to the L level at an appropriate timing (ST95). The operation enable signal ENABLE4 in the serial signal acquisition process (ST23) functions as a latch signal LT by logically inverting it. Therefore, the shift register 50 acquires the switch data of the origin detection sensors SN0 to SN5 and the effect switch 11 at the rising timing of the operation permission signal ENABLE4 = H.

  Therefore, the CPU sets the transmission permission bit TXE and the reception permission bit RXE to the H level (ST96). As a result, the serial input port S4 of the one-chip microcomputer 40 is in a transmission permission state and a reception permission state. Therefore, next, output of the clock signal CK4 from the serial input port S4 is started by outputting dummy data to the transmission data register DR (ST97).

  By this operation, the shift register 50 of the frame relay board 35 outputs the sensor signals SN0 to SN5 and the switch signal of the effect button 11 as the serial data SDATA4 of the channel CH4 for each bit. The serial data SDATA4 is acquired for each bit in the reception shift register SR ′. When the acquisition of 8 bits is completed, the serial data SDATA4 is transferred to the reception data register DR ′ as 1-byte data and stored in a predetermined control register RG. The completion bit FULL becomes H level (completion level). Therefore, when the CPU confirms that the completion bit FULL is at the H level (ST98), the CPU acquires the reception data from the reception data register DR '(ST99). Next, the CPU that has completed the necessary acquisition processing sets the transmission permission bit TXE and the reception permission bit RXE to the L level (ST100). The data acquired in this way is referred to in the input detection process (ST13) and the motor update process (ST20), thereby realizing an appropriate effect process related to the effect button 11 and the effect motors Mx and MOi. Is done.

  Although the embodiments have been described in detail above, the specific description does not limit the present invention and various modifications can be made. For example, in the embodiment, serial signal acquisition processing (ST23) is performed every 1 mS in order to control the production motors Mx and MOi with high accuracy. However, according to the rotation speed and control accuracy of the production motors Mx and MOi, 3 It is good also as a process for every 5 mS.

  In the embodiment, the production motor Mx that is the board side member GM2 is provided with only a single origin detection sensor PH for convenience of explanation, but is not limited in any way, and rather each of the production motors M1 to M9. In addition, it is preferable to provide a position sensor for detecting the origin and other positions. In this case, the multi-bit sensor output signal is transmitted as a serial signal to the serial input port Si of the one-chip microcomputer 40 through the same circuit as in FIG. 16, and is acquired by the CPU by the same process as in FIG. .

  In the above-described embodiment, the movable effector AMU driven exclusively by the effect motors Mx and MOi has been described. However, a plurality of movable effectors that reciprocate based on whether or not the electromagnetic solenoid is energized are additionally provided. Is preferred. In this case, the electromagnetic solenoids arranged on the frame side and the board side can also be driven and controlled in synchronization by the same general-purpose driver DVi as the general-purpose driver that drives the effect motor.

  In such a case, the electromagnetic solenoid on the frame side is controlled to open / close by setting data SDATA2 output from the serial output port S2 together with the effect motor MOi of the channel CH2, for example. The electromagnetic solenoid on the panel side is controlled to open and close by setting data SDATA2 output from the serial output port S0 together with the effect motor Mx of the channel CH0, for example.

  Similarly, in the embodiment, one shift register 50 that receives the origin switch signal SN of the effect motor MOi is arranged on the frame relay board 35, but there is no limitation, and another shift register 50 that receives other sensor signals is provided. It is also suitable to arrange.

  In this case, if a plurality of shift registers 50... 50 are connected in cascade, all sensor signals can be acquired simply by increasing the number of clock signals CK4 output from the serial input port S4. FIG. 18A illustrates a circuit configuration in which two shift registers 50 are arranged. The operation permission signal ENABLE4 is changed from H → L → H to convert 2-byte data into the shift registers 50, 50. Then, if a 16-bit clock signal CK4 is supplied, a 2-byte serial signal SDATA4 can be acquired. The serial signal acquisition process in this case is as shown by the broken line in FIG. 17, and 1-byte data is acquired a plurality of times.

  Needless to say, the present invention is not limited to the serial input port S4, and other serial ports may be used, and the present invention is not limited to sensor signals such as position sensors. Further, as described above, a similar shift register may be arranged on the board side.

  FIG. 18B illustrates a circuit configuration that precisely realizes an advanced performance operation. Regarding serial transmission of CH0 to CH5, the frame side member GM1, the panel side member GM2, and the performance control unit 22 ′ Showing the relationship.

  In this case, the serial ports (CH0, CH3) for controlling the lamp group, the serial ports (CH1, CH4) for controlling the motor group, and the serial ports (CH2, CH5) for receiving sensor signals and switch signals are separated. By doing so, the optimum operation interval corresponding to each purpose is realized. For example, at the time of motor production, the motor group is controlled at a time interval of about 1 mS, and the lamp group is constantly controlled at a time interval of about 16 mS. In addition, the sensor signal and the switch signal are acquired at a time interval of about 16 mS, for example, at a normal time, and are acquired at a time interval of about 1 mS, for a motor effect.

  In addition, each serial port is assigned separately depending on whether the target member is a frame side member or a board side member, so optimal control according to the type of gaming machine is possible It becomes.

  In addition, although the embodiment explained exclusively the bullet feeding game machine, it is needless to say that the application of the present invention is not limited to the ball ball game machine and the spinning cylinder game machine.

GM gaming machine 21 Other control means 22 'Production control means S0-S2 Serial port DRi Driver CK Clock signal SDATA Serial signal

However, various effect operation as described above, advanced this and a strong demand to be enriched.

To achieve the above object, the present invention provides a gaming machine in which a presentation control means for controlling a series of movable effects by the standby position and the target position reciprocate a movable directing member, the movable directing body A sensing sensor capable of outputting a detection signal indicating whether or not the vehicle is located at a standby position and an effect table that defines a series of movable effects of the movable effector are provided, and the effect table includes a rotation operation of an effect motor, The operation information for specifying various unit operations including the stop operation is stored in order, and the management information regarding the repetitive operation of the group of unit operations is stored, and the operation information for specifying the rotation operation of the effect motor includes The rotation direction, the rotation speed, and the operation end condition defined on the basis of the rotation amount or the detection signal are included, and the low speed is set to recover the movable effect body that has finished the movable effect at the target position to the standby position. The first A first unit for starting a unit operation for starting at a rotational speed, and thereafter starting a unit operation at a high-speed second rotational speed in which an operation end condition based on a change in the detection signal is defined; and at a second rotational speed The rotating effect motor is configured to include second means for starting a final unit operation at the first rotational speed in order to collect and stop the movable effector at the standby position .

In the present invention , since the predetermined operation information and the predetermined management information are stored in the effect table that defines a series of movable effects of the movable effector, in realizing the first means and the second means, The control burden on the CPU is not excessively increased.

Claims (9)

Based on a control command received from another control means, a gaming machine provided with an effect control means having a CPU for controlling a movable effector and a light emitter in a predetermined manner,
The production control means includes
A first serial port that periodically outputs a first serial signal to a driver that drives and controls a movable effect body, and a second serial signal that periodically outputs a second serial signal to a driver that drives and controls a light emitting body that is lit. 2 serial ports are provided separately,
A gaming machine, wherein an operation cycle of the first serial port is set shorter than an operation cycle of the second serial port. The output operation of the first and second serial signals is executed in synchronization with the clock signal corresponding to each serial signal,
2. The gaming machine according to claim 1, wherein each clock signal is configured to maintain a steady level until a subsequent output operation when the output operation of the serial signal in each operation cycle ends.   The gaming machine according to claim 1 or 2, wherein the driver that drives and controls the movable effector and the driver that drives and controls the light emitter have substantially the same configuration. The serial port is
A transmission data register that temporarily stores data output in parallel by the CPU, a transmission shift register that serially outputs data received from the transmission data register in synchronization with a clock signal, and a configuration that allows the CPU to grasp the operation contents being executed The gaming machine according to claim 1, wherein the gaming machine is configured to include a control register. The driver has unique address information, and has a built-in register that can set the driving state of the lighting object and the effector such as a movable effector.
The production control means includes
First means for outputting address information for identifying a driver;
Second means for outputting register information for specifying a predetermined register built in the predetermined driver specified by the address information output by the first means;
The gaming machine according to any one of claims 1 to 4, further comprising third means for outputting setting information to be set in the predetermined register. The production control means precedes the operation of the first means,
The gaming machine according to claim 5, wherein a start command indicating that transmission of a series of serial signals is started is output. The serial port is
A multi-byte transmission buffer capable of temporarily storing parallel data output by the CPU, a transmission data register capable of sequentially receiving 1-byte parallel data from the transmission buffer, and a 1-byte parallel received from the transmission data register A transmission shift register that serially outputs data in synchronization with the level change of the clock signal,
The gaming machine according to claim 1, further comprising output control means for transferring parallel data from the transmission buffer to the transmission data register at a necessary timing.   The gaming machine according to claim 7, wherein the output control means is realized by an internal circuit operation of a serial port in which a CPU is not directly involved.   The gaming machine according to claim 7 or 8, wherein the transmission buffer has a FIFO configuration.

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