JP2017156907A - Information processing apparatus, information processing method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing apparatus, an information processing method, and a program.SOLUTION: An image forming apparatus 120 of the present embodiment comprises a control part 130 including a CPU 104 that has a plurality of cores performing concurrent execution, and the CPU 104 of the control part 130 performs load distribution by issuing a plurality of types of processing to be subjected to concurrent execution to all the plurality of cores according to the priority of or load on the processing to be subjected to concurrent execution, or selecting a fixed core dedicated to the execution of the processing before issuing the processing.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program.

  There are SMP (Symmetrical Multi Processing) and AMP (Asymmetrical Multi Processing) as operation modes of the multi-core processor system. SMP dynamically distributes a plurality of programs to a plurality of CPU cores and distributes the load of each core. On the other hand, AMP improves the real-time property of a program by assigning a specific program to a specific CPU core.

  In an embedded device or the like, if there is a program that requires precise operation timing (for example, a program that directly operates hardware such as a driver), the CPU is changed during operation of the device when SMP control is performed. It is also known that the AMP control is used because the cache cannot be used effectively and the real time property of the process cannot be guaranteed. In a multi-core processor system, a configuration in which SMP control and AMP control are mixed is already known.

  However, in the case of the conventional SMP control, the program is equally allocated to the CPU core. On the other hand, in the case of AMP control, it is assumed that a period in which the CPU core is in an idle state occurs. In the case of SMP control, the execution destination of a program can be controlled in consideration of the priority of the program. However, in the case of an embedded apparatus such as an image forming apparatus, there is a high-load process such as image processing and HDD (hard disk drive) data erasing for improving security. In the case of SMP control, there is a problem that the above-described high-load processing and high-priority processing cannot be sufficiently handled even when other processing is postponed or preferentially executed.

  On the other hand, when the priority of a specific process is increased, other processes are affected, and there is a problem that, for example, a user's operation response is lowered. Until now, process control in an embedded device using a multi-core processor has been studied. For example, in Japanese Patent Laid-Open No. 2011-1000027 (Patent Document 1), in order to prevent the processing load from being biased to a specific processor, an AMP control core is determined from the activation core number recorded at the time of the previous activation when the system is activated. The load is not biased to a specific core by sequentially changing.

  However, in Patent Document 1, since the core for executing the specific program is fixed in advance and the program for fixing the core at the time of startup is fixedly assigned, the user's processing is performed by high priority processing or high load processing. It was not possible to improve the point where the operability deteriorated.

  An object of the present invention is to provide a technique for improving user operability in multi-core processing in program execution on an embedded device.

According to the present invention,
An information processing apparatus that performs parallel execution,
Control means including a CPU having a plurality of cores;
Means for distributing and issuing the processes to be executed in parallel to the plurality of cores, and means for distributing and issuing the processes to be executed in parallel to the plurality of cores,
Depending on the priority or load of the processes to be executed in parallel, a plurality of processes are issued for all of the plurality of cores, or a fixed core that exclusively executes the processes is selected and the process is issued. An apparatus is provided.

  According to the present invention, it is possible to provide a technique for improving user operability in multi-core processing in executing a program on an embedded device.

1 is a diagram illustrating a hardware block 100 of an image forming apparatus 120. FIG. The figure which shows the detailed structure of CPU104 of this embodiment. FIG. 3 is a diagram showing a software block 300 of the image forming apparatus 120 of the present embodiment. The conceptual diagram explaining the parallel execution of the program of this embodiment. The flowchart of the load distribution process of this embodiment. The figure which shows embodiment of the information which allocates the program identification value of the program which provides the function of an application to a specific core in embodiment. 9 is a flowchart of processing when returning to load distribution processing according to a first policy after a priority / high load job ends in the present embodiment. In the present embodiment, a flowchart of an embodiment for switching a load distribution policy during execution of a priority / high load application.

  Hereinafter, although this invention is demonstrated by embodiment, this invention is not limited to embodiment mentioned later. FIG. 1 shows a hardware block 100 of an image forming apparatus 120 on the assumption that the information processing apparatus of the present embodiment is an embedded apparatus, specifically, an image forming apparatus. For convenience of explanation, FIG. 1 also illustrates elements when the image forming apparatus 120 performs external access. The image forming apparatus 120 according to the present embodiment is configured as an embedded device, and controls the overall processing of the image forming apparatus 120, such as a device that outputs an image such as the plotter 101, a device that digitizes a document such as the scanner 102, and the like. Part 130 is included. The control unit 130 corresponds to the control unit in this embodiment.

  The control unit 130 includes, for example, an image processing circuit 103 including an application specific integrated circuit (AISC), and the image processing circuit 103 executes image processing in order to provide the functions of the plotter 101 and the scanner 102. Further, the control unit 130 includes a CPU 104, a RAM 105, and a ROM 106.

  The CPU 104 is a multi-core processor in this embodiment, and executes a plurality of programs in parallel while distributing the load to the CPU core. The RAM 105 provides an execution space for the CPU 104 to read a program such as an operating system (OS) and execute the program. In addition, it provides a storage space for storing data for the CPU 104 to execute the program.

  The ROM 106 stores a BIOS (Bacic Input Output System), a bootstrap (Bootstrap) program, and other programs for the CPU 104 to provide functions. When the CPU 104 is started, the program is read by the CPU 104 to initialize the hardware. Functions such as setting, OS startup, and execution monitoring are made possible. The above hardware blocks are interconnected by the system bus 112, and their operations are controlled according to the system clock.

  The control unit 130 includes an FCU 107, a UIF 108, an HDD 109, and a NIC 110 connected via a peripheral bus such as PCIe. The FCU 107 is a circuit for controlling facsimile communication of standards such as G3 and G4. The UIF 108 is a circuit for controlling user interfaces such as a display device, a touch panel, and a numeric keypad / keyboard. A hard disk drive (hereinafter referred to as HDD device 109) 109 is a circuit for controlling an external recording medium using a communication protocol such as ATA, SATA, or USB.

  A NIC (network interface card) 110 connects an image forming apparatus 120 to a network 113 to enable information communication with an external apparatus 111 such as a web server, a storage server, an authentication server, or a cloud server. . The network 113 of this embodiment includes Ethernet (registered trademark), FTH, IEEE802. A wired or wireless protocol such as x can be used to appropriately include a LAN and the Internet, and the communication protocol is not particularly limited.

  The CPU 104 used in the present embodiment is, for example, PENTIUM (registered trademark) DUAL CORE (registered trademark), CORE2 DUO (registered trademark), CORE2 QUAD (registered trademark), CELERON (registered trademark) DUAL CORE, or ATOM (registered trademark). , CORE2DUO (registered trademark), CORE2QUAD (registered trademark), COREi (registered trademark) series, XEON (registered trademark), PENTIUM (registered trademark) compatible CPU with multi-core configuration, POWER PC (registered trademark), etc. However, the present invention is not limited to these.

  As an operating system (OS) to be used, Windows Server (registered trademark), UNIX (registered trademark), LINUX (registered trademark), OPENBSD, CentOS, Ubuntu, or any other suitable OS can be cited. Further, the CPU 104 is written in a programming language such as assembler language, C, C ++, Visual C ++, VisualBasic, Java (registered trademark), JavaScript (registered trademark), Perl, Ruby, Python, etc., which operates on the OS described above. Application programs can be stored and executed.

  FIG. 2 shows the detailed structure of the CPU 104 of this embodiment. FIG. 2 also shows execution queues 201 to 204 and an execution program list 218 configured in an appropriate address area of the RAM 105 for explaining the function of the CPU 104. The execution program list 218 corresponds to list means for determining whether or not to fix the processing target core according to the identification value of the program in the present embodiment.

  The CPU 104 adopts a multi-core configuration including a plurality of cores 205, cores 206, cores 207, and cores 208 as shown in FIG. The cores 205 to 207 read the programs stored in the execution queues 201 to 204 prepared for the cores 205 to 207 in the order of first-in first-out, and execute the programs. The execution queue in the present embodiment corresponds to execution waiting means in the present embodiment.

  In this embodiment, when there is a request for executing a program for providing the function of the image forming apparatus 120, the OS that detects the program or the program call temporarily registers the program identification value in the execution program list 218. Then, through a core designation process by the execution core designation unit 320a of the OS 320, the program is sent to the execution queues 201 to 204 associated with the designated core, and can be executed by the designated core.

  The execution queues 205 to 208 in the present embodiment correspond to means for controlling the execution order of programs. After the execution core designation unit 320a completes the core designation process, the processed items in the execution program list 218 are deleted from the execution program list 218. Using the above processing, the execution program list 218 provides a function for the execution core specifying unit 320a to manage the program to be executed before the program is assigned to each queue, and then the core 205 to execute the program. It is possible to dynamically assign programs to .about.208.

  The CPU 104 includes L1 caches 209 to 212 used by the cores 205 to 208, respectively, to improve the access efficiency of the cores 205 to 208. Furthermore, the CPU 104 provides an L2 cache, which is also referred to as a so-called application cache, to each of the cores 205 to 208, and improves access efficiency to data used at the application level. Further, the CPU 104 includes an L3 cache 217 in the illustrated example. The L3 cache provides a function of storing data that can be shared by the cores 205 to 208, not data that is exclusively used by the cores 205 to 208, and shared data that may be used by the cores 205 to 208 Has improved access efficiency.

  The CPU 104 used in the present embodiment is not limited to the 4-core configuration, and can be increased according to processing requirements such as 2-core, 8-core, and 16-core. In another embodiment, a dual CPU configuration in which multi-core CPUs are mounted in a dual manner can also be used.

  FIG. 3 shows a software block 300 of the image forming apparatus 120 of the present embodiment. The image forming apparatus 120 is mounted with an application program (hereinafter simply referred to as “application”) for the image forming apparatus 120 to provide various functions. Examples of these applications include, but are not limited to, a copy application 310a, a printer application 310b, a scanner application 310c, a FAX application 310d, and an HDD deletion application 310e. In addition, it goes without saying that various applications such as Firefox (registered trademark), Mozilla (registered trademark), Internet Explorer (registered trademark), and Apache (registered trademark) can be implemented according to the functions to be provided. is there.

  Each of the applications 310a to 310e operates under the management of the OS 320, and each of the applications 310a to 310e is called by the OS, and an exception process such as an operation start / end and a runtime error is performed. In the present embodiment, the OS 320 further includes an execution core specifying unit 320a, and provides a function of specifying a core when executing an application according to the present embodiment. Examples of such an execution core specifying unit 320a include an OS module that can interpret and execute an OpenMP command, and a shell command area that executes a UNIX (registered trademark) and LINUX (registered trademark) taskset command. it can. The execution core designating unit 320a of the present embodiment corresponds to a means for distributing and issuing processes to be executed in parallel to a plurality of cores and an execution core designating means.

  Further, the image forming apparatus 120 monitors and manages the core load by monitoring the operating state, temperature, fan speed, and the like of the BIOS and CPU for interfacing with and controlling the hardware, and the BIOS / monitor program 330. It has. The OS 320 acquires information from the BIOS / monitor program 330 and controls programs / threads to be allocated to the cores 205 to 208.

  In general, when the load of a specific core exceeds a set threshold, the OS 320 moves the program identification value registered in the corresponding execution queue to the execution queue for other cores using a specific policy. By doing so, the load of the core with high load is reduced and the load is balanced. For example, the transfer destination core can be the core with the lowest operating rate at that time. Further, for example, it is possible to use a mode in which the content of the execution queue is transferred to another execution queue at regular intervals.

  In this embodiment, when distributing the processing load of the core, instead of transferring the core in units of execution queues, the execution core is specified when the OS fixes the execution of the application to a specific core. The application is left in the execution queues 201 to 204 corresponding to the execution cores 205 to 208, and another application is moved to another core. As a result, the application that should be executed with the core fixed is executed on the specific core, and the other application is executed on the other core defined by the load distribution policy. In other words, in the present embodiment, the execution queue corresponding to a specific core is replaced by moving other applications to the execution queue corresponding to the other core, leaving the program in which the core is designated.

  For this reason, an application for which an execution core is not specified is a target for exchanging execution queues performed at regular intervals. If the application that should fix the core is not registered in the execution queues 201 to 204, the content of the execution queue is transferred in a certain time, so that the cores 205 to 208 are load-balanced according to the policy set in the OS. It becomes possible. On the other hand, when an application whose core is to be fixed is registered in the execution queues 201 to 204, the execution queue is transferred to other remaining execution queues, leaving the application, and the execution queue is , No other apps will be assigned until the app is closed.

  FIG. 4 is a conceptual diagram illustrating parallel execution of the program of the present embodiment. FIG. 4A is a sequence of execution control according to the conventional process distribution policy, and FIG. 4B is a sequence of execution control according to the process distribution policy according to the present embodiment. 4A, the image forming apparatus 120 fixes the copy application 310a illustrated in FIG. 3 to be executed by the core 207 and the scanner application 301c by the core 208. Then, the cores are allocated so that other programs are executed in parallel by the cores 205 and 206.

  In the conventional example, when the image forming apparatus 120 starts to operate next time, the copy application 310a is assigned to the core 208, and the core 207 is assigned to the scanner application 310c to perform load distribution.

  However, as shown in FIG. 4A, if the user does not use the scanner function very much, the core 208 remains in the idle state, and even if the scanner application 310c is fixed to the core 207 after restarting, the core 208 It is the same that 208 is still idling. For this reason, a policy in which an application is simply assigned to a specific core cannot cope with the waste of the entire system.

  On the other hand, in the present embodiment, when the image forming apparatus 120 is activated, the application is not assigned to a specific execution core, and all the cores are released for the application. Then, when an app with an execution core specified is executed, a load balancing policy is adopted in which the app running on the core is transferred to another core, and the app with the execution core occupies the core capacity The CPU resources are effectively used.

  The operation of the present embodiment will be described in detail using the embodiment of FIG. 4B. The application that has been executed in the core 207 until the start of the copy application 310a is triggered by another core 208. Moved. The core 208 is assigned to the scanner application 310c as in FIG. 4A, but in this embodiment, the core 208 is the same as the other cores 205 and 206 unless the scanner application 310c is executed. In addition, other application processes 1-a, 1-b, 2-a, 2-b, and the like can be executed.

  In other words, according to the policy employed in the present embodiment, the load is applied according to the first policy in which all cores 205 to 208 execute the program equally until a program with high priority or a high load is started. Disperse. In addition, when an app with high priority or a request for a high load is requested, the core to be executed is fixed, and load balancing is achieved by the second policy that allows other apps to be executed without fixing the core To do. As a result, it is possible to achieve the load distribution of the core while giving priority to the occurrence of an interrupt due to a user request, and the usability of the core is improved.

  In the present embodiment, a high priority program includes a copy application 310a, a scanner application 310c, a FAX application 310d, a search application, a network access application, and the like that start operation upon an interruption by a user request. be able to. Further, examples of the application or process that requires a high load in the present embodiment include, but are not limited to, a data erasing process and an image drawing process performed by the HDD erasing application 310e.

  FIG. 5 is a flowchart of the load distribution process of this embodiment. The processing in FIG. 5 starts from step S500. When priority / high load processing is started in step S501, in step S502, a priority / high load application execution core request is sent by the app or OS according to the implementation format. Issue. In step S503, the execution core designation unit 320a of the OS 302 executes a process of securing an execution fixed core in response to the priority / high load application execution core request.

  This process involves, for example, a process of moving program identification values registered in the corresponding execution queues 201 to 204 to execution queues corresponding to other cores. Furthermore, in this process, if the core scheduled to be fixed at that time is executing another application, for example, by moving the process to a core with a low processing load, the core is fixedly secured to the application. Makes it possible to execute applications immediately.

  Thereafter, in step S504, the execution program list 218 is searched, and it is determined whether or not the application registered at the top is already a priority / high load application. This determination can be implemented by searching the execution program list 218 using the program identification value uniquely assigned to the application. If the application registered at the top of the execution program list 218 is a priority / high load application for which an execution core designation request is currently issued (yes), it has already been secured for the priority / high load application in step S506. Register the program in the execution queue corresponding to the core, and issue the application to the specified core. At this time, the corresponding execution queue is set to the empty state in the process of step S503, so that the application is immediately executed after being registered in the execution queue.

  On the other hand, if it is determined in step S505 that the application registered at the top of the execution program list 218 is not a priority / high load application that has issued an execution core designation request at that time (no), the application to be fixed in step S507. Publish app processing to the core. The process at this time is executed in the same manner as described in step S506.

  After issuing processing in steps S506 and S507, it is determined in step S508 whether or not the execution program list 218 is empty. If the execution program list 218 is empty (yes), there is no more application that has to be designated as a core, so the process advances to step S509 to end the process. On the other hand, if the execution program list 218 is not empty (no), the process returns to step S504, the core for executing the application is assigned and the process is issued, and the process is repeated until the execution program list 218 is empty in step S508. Let If the application registered at the top of the execution program list 218 is an application that does not require core designation, the execution core designation unit 320a assigns to any core that is not used exclusively according to the first policy. Run the app.

  With the above processing, until a priority / high load application activation interrupt occurs, the core specified for the program is assigned when a priority / high load application is requested while assigning the core to the application according to the core processing load. According to the policy of this embodiment, which can be processed by allocating. It enables load distribution among multiple cores.

  FIG. 6 shows an embodiment of information for assigning a program identification value of a program providing an application function to a specific core in this embodiment. The information in FIG. 6 can be created as runtime data of the execution core designation unit 320a of the OS 320 according to the implementation format of the program. Alternatively, the information shown in FIG. It can also be described in program code. The application shown in FIG. 6 is an application that requests a high load such as, for example, HDD data erasure, in addition to an application whose priority should be increased according to a user request.

  The application shown in FIG. 6 is merely an example, and other applications or processes that should start processing in response to an interruption by the user can be added to the information in FIG. Other than these, for example, device check, facsimile reception, operation status monitor, and other non-user-requested apps and services can be added to the information in FIG. 6 according to the specific use and purpose. Should be classified as “other apps”.

  FIG. 7 is a flowchart of a process when returning to the load distribution process based on the first policy after the priority / high load job ends in this embodiment. The processing in FIG. 7 starts from step S700. In step S701, the program identification value of the information to the priority / high load application shown in FIG. 6 is acquired, and the execution program list 218 is searched in step S702.

  If the program identification value of the priority / high load application is not registered at the top of the execution program list 218 in step S703 (no), the execution core designation is canceled in step S704, and the execution program list 218 is empty in step S705. Judge whether or not. If the execution program list 218 is not empty, the process returns to step S702, and a search is again made as to whether a priority / high load processing program is registered at the head.

  On the other hand, when the program identification value of the priority / high load application is registered in the execution program list 218 in the determination of step S703 (yes), the processing is left to the processing of FIG. 5 for securing and executing the execution core. The process of 7 proceeds to step S706 and ends. If it is determined in step S705 that the execution program list 218 is empty (yes), the process proceeds to step S706 and ends.

  The process of FIG. 7 is preferably called subsequent to the process of FIG. 5, but can be integrated with the process of FIG. 5 and implemented as a program module for the load distribution process.

  FIG. 8 is a flowchart of an embodiment in which the load balancing policy is switched during execution of the priority / high load application in the present embodiment. The processing in FIG. 8 starts from step S800. When a priority / high load application is called in step S801, for example, an application corresponding to the process management list is registered, and an execution flag is set for the application. After that, in step S802, step S506 or step S507 in FIG. 5 is called to start processing under the second policy in which the core is fixed.

  Next, when activation of a new application is requested in step S803, it is determined in step S804 whether the new application is a priority / high load application. If the new application is not a priority / high load application (no), the process proceeds to step S810. 7 and apply the processing of steps S702 to S705 in FIG. 7 to allocate cores according to the first policy from among the unfixed cores that can be used, and issue the application to the corresponding execution queues 201 to 204. To do.

  On the other hand, if it is determined in step S804 that a priority / high load application is requested (yes), in step S805, step S507 of FIG. Start processing at. Thereafter, in step S806, when the priority / high load application operating in advance is terminated, in steps S807, steps 702 to S705 in FIG. 7 are called to cancel the execution core. Thereafter, in step S808, the operation flag of the corresponding application in the process management list is canceled, and the process proceeds to step S809 and ends.

  With the above processing, it is possible to prevent unintended performance degradation due to contention with the priority / high load application even in a program started during execution of the priority / high load application. Note that the load distribution program of the present embodiment can describe OS commands for specifying and releasing cores in the program itself that provides the application functions.

  In another embodiment, an OS command such as ShellScript is prepared separately from a program for providing an application, and the OS program monitors the execution state of the application and switches and controls the first policy and the second policy. be able to. In addition, the program for executing the load distribution process of the present embodiment can be described in any language such as C ++, Java (registered trademark), ShellScript, and is not particularly limited.

  The present invention has been described with the embodiment. However, the present invention is not limited to the embodiment, and other embodiments, additions, modifications, deletions, and the like can be conceived by those skilled in the art. Any of the embodiments is included in the scope of the present invention as long as the operations and effects of the present invention are exhibited.

100: Hardware block 101: Plotter 102: Scanner 103: Image processing circuit 104: CPU
105: RAM
106: ROM
109: HDD device 111: External device 113: Network 120: Image forming device 130: Control units 201-204: Execution queues 205-208: Cores 209-212: L1 caches 213-216: L2 cache 217: L3 cache 218: Execution Program list 300: Software block 301c: Scanner application 310a: Copy application 310b: Printer application 310c: Scanner application 310d: FAX application 310e: HDD erasure application 320a: Execution core designation unit 330: Monitor program

JP 2011-1000027 A1

Claims (9)

An information processing apparatus that performs parallel execution,
Control means including a CPU having a plurality of cores;
Means for distributing and issuing the processes to be executed in parallel to the plurality of cores, and means for distributing and issuing the processes to be executed in parallel to the plurality of cores,
Depending on the priority or load of the processes to be executed in parallel, a plurality of processes are issued for all of the plurality of cores, or a fixed core that exclusively executes the processes is selected and the process is issued. apparatus.   The information processing apparatus according to claim 1, wherein the information processing apparatus allocates the fixed core by setting a process requested by a user as the process having a high priority.   The information processing apparatus according to claim 1, wherein the information processing apparatus causes the different fixed cores to process loads for data erasure processing and image drawing processing of the HDD device. The information processing apparatus further includes:
The list means for determining whether or not to fix the processing target core according to the identification value, while managing the identification value of the processing requested to the plurality of cores in a first-in first-out manner,
The execution core designating means for sending the process registered in the list means to an execution waiting means corresponding to the core that is to be executed in advance according to the determination. 4. The information processing apparatus according to any one of 3.   The information processing apparatus according to claim 1, wherein the information processing apparatus is an embedded apparatus. A device-executable information processing method executed by an information processing device performing parallel execution,
Determining the priority or load of the processes to be executed in parallel;
Distributing and issuing the processes to be executed in parallel to the plurality of cores;
Issuing the processes to be executed in parallel to the plurality of cores,
Distributing the processes to be executed in parallel to the plurality of cores,
Issuing a plurality of processes for all of the plurality of cores, or selecting a fixed core that exclusively executes the processes and issuing a process according to the priority or load of the processes to be executed in parallel Including an information processing method.   The step of distributing and issuing the processes to be executed in parallel to the plurality of cores includes a step of assigning the fixed core to a process having a high priority for a process requested by a user. Information processing method. further,
Managing the identification values of the processing requested to the plurality of cores by a first-in first-out method, determining whether to fix the processing target core according to the identification values, and preempting in accordance with the determination The information processing method according to claim 6, further comprising: sending the process to an execution waiting unit corresponding to the core that is to execute the process. An information processing apparatus executable program for executing processing in parallel, wherein the program is
Determining the priority or load of the processes to be executed in parallel;
Distributing and issuing the processes to be executed in parallel to the plurality of cores;
Issuing the processes to be executed in parallel to the plurality of cores,
Distributing the processes to be executed in parallel to the plurality of cores,
Issuing a plurality of processes for all of the plurality of cores, or selecting a fixed core that exclusively executes the processes and issuing a process according to the priority or load of the processes to be executed in parallel including,
program.