JP2017152066A - Nonvolatile semiconductor storage device and memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device that can improve performance.SOLUTION: A nonvolatile semiconductor storage device includes a memory cell array 101 and a controller 110. The memory cell array 101 includes a plurality of blocks. Each of the plurality of blocks includes a plurality of memory strings. Each of the plurality of memory strings includes a selection transistor and a plurality of memory cells connected to one end of the selection transistor in series. In response to a first command, the controller 110 determines whether or not a threshold value of the selection transistor is less than or equal to a first reference value in a first block specified by the first command. In response to a second command, the controller 110 outputs a determination result to an outside.SELECTED DRAWING: Figure 8

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a memory system.

  A NAND flash memory is known as a nonvolatile semiconductor memory device.

US Pat. No. 7,933,151

  Embodiments provide a nonvolatile semiconductor memory device and a memory system capable of improving performance.

  The nonvolatile semiconductor memory device according to the embodiment includes a plurality of blocks, each of the plurality of blocks includes a plurality of memory strings, and each of the plurality of memory strings includes a selection transistor and one end of the selection transistor. A threshold value of the selection transistor is equal to or lower than a first reference value in a memory cell array including a plurality of memory cells connected in series to each other and a first block designated by the first command in response to the first command. A controller that determines whether or not there is and outputs the determination result to the outside in response to the second command.

1 is a block diagram of a memory system including a semiconductor memory device according to a first embodiment. FIG. 2 is a block diagram of the NAND flash memory shown in FIG. 1. FIG. 3 is a block diagram of the memory cell array shown in FIG. 2. The circuit diagram of one block contained in a memory cell array. Sectional drawing of the partial area | region of a block. 10A and 10B illustrate a threshold value of a selection transistor. 5 is a flowchart showing the operation of the memory controller according to the first embodiment. 4 is a timing chart showing the operation of the memory system according to the first embodiment. 4 is a timing chart illustrating a threshold value check operation of a selection transistor according to the first embodiment. The figure explaining the management area | region of a memory cell array. 9 is a timing chart showing the operation of the memory system according to the second embodiment. Sectional drawing of the NAND string which concerns on 3rd Embodiment. Sectional drawing of the NAND string which concerns on 3rd Embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
The semiconductor memory device according to this embodiment is a nonvolatile semiconductor memory in which data can be electrically rewritten. In the following embodiments, a NAND flash memory will be described as an example of the semiconductor memory device.

[1] First Embodiment [1-1] Configuration of Memory System FIG. 1 is a block diagram of a memory system 1 including a semiconductor memory device according to a first embodiment. The memory system 1 includes a NAND flash memory 100 and a memory controller 200.

The memory system 1 may be configured by mounting a plurality of chips constituting the memory system 1 on a motherboard on which the host device 300 is mounted, or a system LSI (large-sized) that realizes the memory system 1 with one module. scale integrated circuit) or SoC (system on chip). Examples of the memory system 1 include a memory card such as an SD ^TM card, an SSD (solid state drive), an eMMC (embedded multimedia card), and the like.

  The NAND flash memory 100 includes a plurality of memory cells and stores data in a nonvolatile manner. Details regarding the configuration of the NAND flash memory 100 will be described later.

  For example, in response to a command from the host device 300, the memory controller 200 commands writing (also referred to as a program), reading, and erasing to the NAND flash memory 100. The memory controller 200 manages the memory space of the NAND flash memory 100. The memory controller 200 includes a host interface circuit (Host I / F) 201, a CPU (Central Processing Unit) 202, a RAM (Random Access Memory) 203, a buffer memory 204, a NAND interface circuit (NAND I / F) 205, and an ECC ( An error checking and correcting circuit 206 is provided.

  The host interface circuit 201 is connected to the host device 300 via the controller bus and performs interface processing with the host device 300. The host interface circuit 201 transmits and receives commands and data to and from the host device 300.

  The CPU 202 controls the overall operation of the memory controller 200. For example, when receiving a write command from the host device 300, the CPU 202 issues a write command based on the NAND interface to the NAND flash memory 100 in response thereto. The same applies to reading and erasing. Further, the CPU 202 executes various processes for managing the NAND flash memory 100 such as wear leveling.

  The RAM 203 is used as a work area for the CPU 202 and stores firmware loaded from the NAND flash memory 100 and various tables created by the CPU 202. The RAM 203 is composed of, for example, a DRAM. The buffer memory 204 temporarily holds data sent from the host device 300 and temporarily holds data sent from the NAND flash memory 100.

  When data is written, the ECC circuit 206 generates an error correction code for the write data, adds the error correction code to the write data, and sends it to the NAND interface circuit 205. In addition, when reading data, the ECC circuit 206 performs error detection and error correction on the read data by using an error correction code included in the read data. Note that the ECC circuit 206 may be provided in the NAND interface circuit 205.

  The NAND interface circuit 205 is connected to the NAND flash memory 100 via a NAND bus, and performs interface processing with the NAND flash memory 100. The NAND interface circuit 205 transmits and receives commands and data to and from the NAND flash memory 100.

[1-1-1] Configuration of NAND Flash Memory 100 FIG. 2 is a block diagram of the NAND flash memory 100. The NAND flash memory 100 includes a memory cell array 101, row decoder 102, column decoder 103, sense amplifier unit 104, page buffer 105, core driver 106, voltage generation circuit 107, input / output circuit 108, address register 109, controller 110, status. A register 111 and a fail bit counter 112 are provided.

  The memory cell array 101 includes a plurality of blocks, and each of the plurality of blocks includes a plurality of memory cell transistors MT (sometimes simply referred to as memory cells). The memory cell transistor MT is composed of an electrically rewritable EEPROM (registered trademark) cell. The memory cell array 101 is provided with a plurality of bit lines, a plurality of word lines, and a source line in order to control the voltage applied to the memory cell transistor MT. Details of the memory cell array 101 will be described later.

  The row decoder 102 receives a block address signal and a row address signal from the address register 109, and selects any word line in the corresponding block based on these signals. The column decoder 103 receives a column address signal from the address register 109 and selects one of the bit lines based on the column address signal.

  The sense amplifier unit 104 detects and amplifies data read from the memory cell to the bit line when reading data. The sense amplifier unit 104 transfers write data to the memory cell via the bit line when writing data. Data reading and writing to the memory cell array 101 are performed in units of a plurality of memory cells, and this unit is a page.

  The page buffer (data cache) 105 holds data in units of pages, for example. When reading data, the page buffer 105 temporarily holds data transferred from the sense amplifier unit 104 in units of pages, and transfers the data serially to the input / output circuit 108. The page buffer 105 temporarily holds data transferred serially from the input / output circuit 108 when data is written, and transfers this data to the sense amplifier unit 104 in units of pages.

  The core driver 106 supplies voltages necessary for data writing, reading, and erasing to the row decoder 102, the sense amplifier unit 104, a source line control circuit (not shown), and the like. The voltage supplied by the core driver 106 is supplied to memory cells (specifically, word lines, selection gate lines, bit lines, and source lines) through the row decoder 102, the sense amplifier unit 104, and the source line control circuit. Applied. The voltage generation circuit 107 generates an internal voltage (for example, a voltage obtained by boosting the power supply voltage) necessary for each operation, and supplies the internal voltage to the core driver 106.

  The controller (control circuit) 110 controls the entire operation of the NAND flash memory 100. The controller 110 receives various external control signals, for example, a chip enable signal CEn, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal WEn, and a read enable signal REn from the memory controller 200. “N” appended to the signal name indicates active low.

  The controller 110 identifies the address Add and the command CMD supplied from the input / output terminal I / O based on these external control signals. Then, the controller 110 transfers the address Add to the column decoder 103 and the row decoder 102 via the address register 109. In addition, the controller 110 decodes the command CMD. The controller 110 performs sequence control of data reading, writing, and erasing in accordance with the external control signal and the command CMD. Further, the controller 110 outputs a ready / busy signal R / Bn in order to notify the memory controller 200 of the operation state of the NAND flash memory 100. The memory controller 200 can know the state of the NAND flash memory 100 by receiving the ready / busy signal R / Bn.

  The input / output circuit 108 transmits / receives data (including command CMD, address Add, and data) to / from the memory controller 200 via the NAND bus.

  The status register 111 temporarily holds management data read from the ROM fuse of the memory cell array 101 at the time of power-on, for example. The status register 111 temporarily holds various data necessary for the operation of the memory cell array 101. The status register 111 is composed of, for example, an SRAM.

  The fail bit counter 112 compares the data read from the memory cell with the expected value in the verify operation after writing, and counts the number of mismatched bits (fail bits). The verify operation is an operation of comparing data actually written in the memory cell with an expected value (write data) to check whether the expected value is written in the memory cell. The number of fail bits counted by the fail bit counter 112 is used to determine the status of the write operation. That is, the controller 110 compares the number of fail bits counted by the fail bit counter 112 with a reference value, and determines that the write operation is a pass when the number of fail bits is equal to or less than the reference value.

[1-1-2] Configuration of Memory Cell Array 101 FIG. 3 is a block diagram of the memory cell array 101.
The memory cell array 101 includes a plurality of blocks BLK (BLK0, BLK1, BLK2,...). Each of the plurality of blocks BLK includes a plurality of string units SU (SU0, SU1, SU2,...). Each of the plurality of string units SU includes a plurality of NAND strings 10. The number of blocks in the memory cell array 101, the number of string units in one block BLK, and the number of NAND strings in one string unit SU can be arbitrarily set.

FIG. 4 is a circuit diagram of one block BLK included in the memory cell array 101.
Each of the plurality of NAND strings 10 includes a plurality of memory cell transistors MT and two select transistors ST1 and ST2. In this specification, a memory cell transistor may be called a memory cell or a cell. FIG. 4 shows a configuration example in which the NAND string 10 includes eight memory cell transistors MT (MT0 to MT7). However, the number of memory cell transistors MT included in the NAND string 10 can be arbitrarily set. The memory cell transistor MT includes a stacked gate including a control gate and a charge storage layer, and stores data in a nonvolatile manner. The memory cell transistor MT may be configured to store 1-bit data (binary) or may be configured to store data of 2 bits or more (or 3 values or more).

  The plurality of memory cell transistors MT are arranged between the select transistors ST1 and ST2 such that their current paths are connected in series. The current path of the memory cell transistor MT at one end of the series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT at the other end is connected to one end of the current path of the selection transistor ST2. The

  The gates of the plurality of selection transistors ST1 included in the string unit SU0 are commonly connected to the selection gate line SGD0. Similarly, the selection gate lines SGD1 to SGD3 are connected to the string units SU1 to SU3, respectively. The gates of the plurality of selection transistors ST2 in the same block BLK are commonly connected to the same selection gate line SGS. Note that the select transistor ST2 included in each string unit SU may be connected to separate select gate lines SGS0 to SGS3, similarly to the select transistor ST1. Control gates of memory cell transistors MT0 to MT7 in the same block BLK are connected to word lines WL0 to WL7, respectively.

  The NAND string 10 may include a dummy cell transistor. The dummy cell transistors are connected in series between the selection transistor ST1 and the memory cell transistor and between the selection transistor ST2 and the memory cell transistor. A dummy word line is connected to the gate of the dummy cell transistor. The structure of the dummy cell transistor is the same as that of the memory cell transistor. The dummy cell transistor is not for storing data, but has a function of reducing the disturbance received by the memory cell transistor and the select transistor during the write pulse application operation and the erase pulse application operation.

  Among the NAND strings 10 arranged in a matrix in the memory cell array 101, the other end of the current path of the select transistor ST1 of the plurality of NAND strings 10 in the same column is any of the bit lines BL0 to BL (m−1). Commonly connected. “M” is an integer of 1 or more. That is, one bit line BL commonly connects NAND strings 10 in the same column among a plurality of blocks BLK. The other ends of the current paths of the plurality of select transistors ST2 included in the same block BLK are commonly connected to the source line SL. For example, the source line SL connects a plurality of NAND strings 10 in common between a plurality of blocks.

  Data of a plurality of memory cell transistors MT in the same block BLK is erased at once, for example. Data reading and writing are collectively performed on a plurality of memory cell transistors MT commonly connected to one word line WL arranged in one block BLK. This data unit is called a page.

  FIG. 5 is a cross-sectional view of a partial region of the block BLK. A plurality of NAND strings 10 are formed on the p-type well region 20. That is, on the well region 20, for example, four wiring layers 27 functioning as the selection gate lines SGS, eight wiring layers 23 functioning as the word lines WL0 to WL7, and, for example, four layers functioning as the selection gate lines SGD. The wiring layers 25 are sequentially stacked. An insulating film (not shown) is formed between the stacked wiring layers.

  A memory hole 26 that penetrates the wiring layers 25, 23, and 27 to reach the well region 20 is formed, and a pillar-shaped semiconductor layer 31 is formed in the memory hole 26. On the side surface of the semiconductor layer 31, a gate insulating film 30, a charge storage layer (insulating film) 29, and a block insulating film 28 are sequentially formed. Thus, a memory cell transistor MT and select transistors ST1 and ST2 are formed. The semiconductor layer 31 functions as a current path of the NAND string 10 and becomes a region where the channel of each transistor is formed. The upper end of the semiconductor layer 31 is connected to the metal wiring layer 32 that functions as the bit line BL.

An n ⁺ -type impurity diffusion layer 33 is formed in the surface region of the well region 20. A contact plug 35 is formed on the diffusion layer 33, and the contact plug 35 is connected to a metal wiring layer 36 that functions as the source line SL. Further, a p ⁺ -type impurity diffusion layer 34 is formed in the surface region of the well region 20. A contact plug 37 is formed on the diffusion layer 34, and the contact plug 37 is connected to a metal wiring layer 38 functioning as a well wiring CPWELL. The well wiring CPWELL is a wiring for applying a potential to the semiconductor layer 31 through the well region 20.

  A plurality of the above configurations are arranged in the depth direction of the paper surface illustrated in FIG. 5, and a string unit SU is formed by a set of a plurality of NAND strings 10 arranged in the depth direction.

  The configuration of the memory cell array is described in, for example, US patent application Ser. No. 12 / 407,403 filed on Mar. 19, 2009 called “three-dimensional stacked nonvolatile semiconductor memory”. Also, US patent application Ser. No. 12 / 406,524 filed Mar. 18, 2009 entitled “Three-dimensional stacked nonvolatile semiconductor memory”, Mar. 25, 2010 entitled “Nonvolatile semiconductor memory device and manufacturing method thereof” No. 12 / 679,991, filed on Mar. 23, 2009, entitled “Semiconductor Memory and Method of Manufacturing the Same”. These patent applications are hereby incorporated by reference in their entirety.

  Data can be erased in units of blocks BLK or in units smaller than blocks BLK. The erasing method is described in, for example, US Patent Application No. 13 / 235,389 filed on September 18, 2011, called “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE”. Further, it is described in US Patent Application No. 12 / 694,690 filed on January 27, 2010, called “NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE”. Further, it is described in US Patent Application No. 13 / 483,610 filed on May 30, 2012, “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF”. These patent applications are hereby incorporated by reference in their entirety.

[1-2] Regarding the threshold value of the selection transistor In the three-dimensional stacked nonvolatile semiconductor memory device, from the experience, the upper and lower layers of the NAND string 10, that is, the selection gate lines SGD and SGS, the bit line BL, the source line SL, or the word WL. Short circuit with is easy to occur. Even if screening is performed in a test before product shipment, if a stress (W / E stress) due to repeated writing and erasing is applied after product shipment, an acquired defect occurs in the selection gate lines SGD and SGS. It is expected to be easy. As one form of this defect, threshold variation of the selection transistors ST1 and ST2 can be considered, and the block will eventually become defective due to the influence of this threshold variation. This defect includes a case where data exceeding the allowable number of bits cannot be normally written in the write operation.

  Therefore, it is possible to improve the performance and reliability of the system by checking the threshold value of the selected transistor before writing or erasing with the controller and detecting whether or not to stop accessing the block any longer. There is.

  FIG. 6 is a diagram for explaining the threshold value of the selection transistor ST1. The following description is the same for the select transistor ST2. FIG. 6 shows threshold distributions of a plurality of select transistors ST1 included in one block. The horizontal axis in FIG. 6 is the threshold value (Vt) of the selection transistor ST1, and the vertical axis in FIG. 6 is the number of selection transistors ST1.

  The select transistor ST1 has the same structure as the memory cell transistor MT and has a charge storage layer. Therefore, when charge is injected into the charge storage layer of the select transistor ST1, the threshold value of the select transistor ST1 varies.

  For example, in a test before product shipment, the threshold values of the plurality of selection transistors ST1 are less varied, and this state is indicated by a broken line in FIG. When stress (W / E stress) due to repeated writing and erasing after product shipment is applied to the selection transistor ST1, the threshold value of the selection transistor ST1 varies. The threshold value of the select transistor ST1 after the W / E stress is applied is indicated by a solid line in FIG.

  For example, in the operation of turning on the selection transistor ST1, if the selection transistor ST1 is turned off due to the threshold fluctuation of the selection transistor ST1, the operation cannot be performed. Thereby, in the block BLK including such a selection transistor ST1, an operation failure (writing failure, reading failure, etc.) occurs.

  Therefore, a reference determination voltage (readout voltage), for example, determination voltages VS1 and VS2 shown in FIG. 6 is applied to the gate of the selection transistor ST1 to determine whether the selection transistor ST1 is turned on or off. An abnormality in threshold distribution of the transistor ST1 can be detected.

[1-3] Operation of Memory System 1 The operation of the memory system 1 configured as described above will be described. FIG. 7 is a flowchart showing the operation of the memory controller 200. FIG. 8 is a timing chart showing the operation of the memory system 1.

  Prior to the write operation, a threshold value check operation of the select transistors ST1 and ST2 is performed (step S100). The target of the threshold check operation may be both the selection transistors ST1 and ST2, only the selection transistor ST1, or only the selection transistor ST2. Hereinafter, the target of the threshold check operation is referred to as a selection transistor ST in order to include all these forms. The target of the threshold check operation can be appropriately selected according to the structure of the memory cell array 101.

  First, the memory controller 200 sends a check command “X1h”, an address “Add1”, and an execution command “X2h” to the NAND flash memory 100. The check command “X1h” and the execution command “X2h” are commands (ST-Vth check) for checking the threshold value of the selection transistor ST. The address “Add1” is a block address subject to threshold check. In the present embodiment, the threshold value check operation is performed in units of blocks BLK, for example.

  In response to the execution command “X2h”, the NAND flash memory 100 changes the ready / busy signal R / Bn to a low level in order to notify that it is in an operating state, that is, a busy state. Subsequently, the NAND flash memory 100 performs the threshold check operation of the selection transistor ST in the selected block designated by the address “Add1”.

  As an example, the threshold value checking operation of the selection transistor ST1 will be described below. FIG. 9 is a timing chart showing the threshold check operation of the select transistor ST1. Information necessary for the threshold check operation (including the type of voltage) is stored in the management area of the memory cell array 101 in a nonvolatile manner, and stored in the register in the controller 110 or the status register 111 as necessary. The controller 110 executes various operations using the register data. The same applies to the write operation, the read operation, and the erase operation.

  At time t1, the sense amplifier unit 104 applies the voltage Vbl (ground voltage Vss <Vbl <power supply voltage Vdd) to all the bit lines. For example, the ground voltage Vss is applied to the source line SL.

  In the selected block BLK, the row decoder 102 applies the determination voltage VS2 illustrated in FIG. 6 to the selection gate line SGD, and applies the voltage Vsg to the selection gate line SGS. The voltage Vsg is a voltage that can turn on the selection transistors ST1 and ST2 regardless of the thresholds of the selection transistors ST1 and ST2. As a result, the selection transistor ST2 is turned on.

  Subsequently, at time t2, the row decoder 102 applies the read pass voltage Vread to all the word lines in the selected block BLK. The read pass voltage Vread is a voltage that can turn on the memory cell transistor MT regardless of the data held in the memory cell transistor MT.

  Due to the voltage relationship in the threshold check operation, when the threshold of the selection transistor ST1 is higher than the determination voltage VS2, no current flows through the NAND string. That is, the sense amplifier unit 104 senses the bit line current, and the sense result is stored in the page buffer 105. When the selection transistor ST1 is in the off state, for example, data 1 is stored in a predetermined data cache (data latch circuit) in the page buffer 105.

  Subsequently, the fail bit counter 112 counts the number of data 1 in the page buffer 105. The count value by the fail bit counter 112 is stored in the status register 111 via the controller 110.

  When one block BLK includes a plurality of string units SU, the above determination operation is repeated for the number of string units SU. Note that one string unit SU in the block BLK may be targeted as a reference for the threshold check of the selection transistor.

  Subsequently, the controller 110 compares the count value of the fail bit counter 112 with a reference value (allowable bit number). The controller 110 determines a pass if the count value is less than or equal to the reference value, and a fail if the count value exceeds the reference value. The determination result is stored in the status register 111.

  When the threshold value of the selection transistor ST2 is checked, the voltages of the selection gate line SGD and the selection gate line SGS are reversed.

  In addition, when the lower skirt of the threshold distribution is checked, the determination voltage VS1 is used, and accordingly, on / off determination of the selection transistor ST1 is reversed from the case of the determination voltage VS2. Further, a threshold value check operation using the determination voltage VS1 and a threshold value check operation using the determination voltage VS2 may be performed continuously. In this example, if at least one of the two threshold check operations is a failure, it is determined that the overall threshold check operation is a failure.

  Subsequently, after the threshold value check operation is completed, the NAND flash memory 100 changes the ready / busy signal R / Bn to a high level in order to notify that it is in a ready state.

  Subsequently, in response to the ready signal, the memory controller 200 sends a status read command “70h” to the NAND flash memory 100 (step S101). In response to the status read command “70h”, the NAND flash memory 100 sends status information regarding the threshold check operation to the memory controller 200. The memory controller 200 receives the status information read from the NAND flash memory 100 and recognizes whether the threshold check operation is a pass or a fail (step S102).

  When the threshold value check operation is a pass (step S103: Yes), the memory controller 200 executes a write operation on the block (selected block) BLK (step S104). That is, the memory controller 200 sends the write command “80h”, the address “Add2”, the write data “W-Data1”, and the execution command “10h” to the NAND flash memory 100. The write data “W-Data1” is user data, for example, and the address “Add2” is an arbitrary address including a block address, a column address, and a row address.

  In response to the execution command “10h”, the NAND flash memory 100 sends a busy signal to the memory controller 200 and executes a write operation. That is, the controller 110 of the NAND flash memory 100 writes the write data “W-Data1” to the memory cell array 101. The NAND flash memory 100 sends a ready signal to the memory controller 200 after the write operation is completed.

  On the other hand, when the threshold value check operation is a failure (step S103: No), the memory controller 200 executes a write operation on another block BLK (step S105). When a write operation is performed on another block, a threshold check operation may be performed on the block again.

  Subsequently, the memory controller 200 registers the block BLK in which the threshold value check operation is determined to be failed as a bad block in the management area (step S106). FIG. 10 is a diagram for explaining the management area of the memory cell array 101. The memory cell array 101 includes a management block (block BLKi). In the management block BLKi, management information of the NAND flash memory 100 is stored. This management information includes bad block information. In addition, the management information includes trimming information and the like.

  Bad block information is information related to a bad block (bad block), for example, a block address of a bad block. The block managed as a bad block is not used for data writing thereafter.

[1-4] Effects of First Embodiment As described in detail above, the first embodiment newly includes a mode for early detection of threshold distribution abnormality of the select transistors ST1 and ST2. That is, the memory controller 200 designates a block (or string unit) of the NAND flash memory 100 and issues a check command for performing a threshold check of the selected transistor. In response to this check command, the NAND flash memory 100 executes a threshold check operation for the selected transistor. Then, the memory controller 200 issues a status read command, and the memory controller 200 reads the determination result (pass / fail) of the threshold check of the selected transistor.

  For example, if a write operation is performed on a block in which a threshold distribution abnormality of the selection transistor has occurred and a write error occurs as a result, this processing time is wasted and the write time becomes long.

  On the other hand, according to the first embodiment, it is possible to detect the block in which the threshold distribution abnormality of the selection transistor has occurred before the write operation. Thereby, the performance of the memory system can be improved. In addition, the writing speed of the memory system can be improved, and the writing process can be optimized.

  In this embodiment, the threshold value of the selection transistor is checked before the write operation. However, the present invention is not limited to this, and the threshold value of the selection transistor may be checked before the erase operation.

[2] Second Embodiment In the second embodiment, write data is first input to the NAND flash memory 100, and the data-in process in the NAND flash memory 100 is performed in parallel with the threshold check operation of the selection transistor ST. Like to do.

FIG. 11 is a timing chart showing the operation of the memory system 1 according to the second embodiment.
Prior to the write operation, a threshold value check operation of the selection transistor ST is performed. The memory controller 200 sends a check command “X3h”, an address “Add1”, write data “W-Data1”, and an execution command “X4h” to the NAND flash memory 100. The check command “X3h” and the execution command “X4h” are commands for checking the threshold value of the selection transistor ST.

  In response to the execution command “X4h”, the NAND flash memory 100 changes the ready / busy signal R / Bn to a low level in order to notify that it is in a busy state. Subsequently, the NAND flash memory 100 performs the threshold check operation of the selection transistor ST in the selected block designated by the address “Add1”. The threshold check operation of the selection transistor ST is the same as that in the first embodiment.

  Furthermore, the NAND flash memory 100 executes data-in processing. That is, the controller 110 stores the write data “W-Data1” input from the input / output terminal I / O in a predetermined data cache in the page buffer 105.

  The NAND flash memory 100 changes the ready / busy signal R / Bn to a high level in order to notify that the ready state is entered after the threshold value check operation is completed.

  Subsequently, the memory controller 200 sends a status read command “70h” to the NAND flash memory 100 in response to the ready signal. In response to the status read command “70h”, the NAND flash memory 100 sends status information regarding the threshold check operation to the memory controller 200. The memory controller 200 receives the status information read from the NAND flash memory 100 and recognizes whether the threshold value check operation is a pass or a fail.

  When the threshold value check operation is a pass, the memory controller 200 performs a write operation on the block (selected block) BLK. That is, the memory controller 200 sends a write command “X5h”, an address “Add2”, and an execution command “X6h” to the NAND flash memory 100. With this write command “X5h”, write data is not input.

  In response to the execution command “X6h”, the NAND flash memory 100 sends a busy signal to the memory controller 200 and executes a write operation. That is, the controller 110 of the NAND flash memory 100 writes the write data “W-Data1” input together with the check command “X3h” to the memory cell array 101. The NAND flash memory 100 sends a ready signal to the memory controller 200 after the write operation is completed.

  On the other hand, if the threshold value check operation is a failure, the memory controller 200 executes a write operation on another block BLK (step S105). The write operation to another block BLK is performed using the write command “80h” shown in FIG. When a write operation is performed on another block, a threshold check operation may be performed on the block again.

  The subsequent process of registering the bad block in the management area is the same as in the first embodiment.

  As described above in detail, according to the second embodiment, the threshold check operation of the selection transistor and the data-in process can be performed in parallel. Therefore, when the writing is performed, the data-in process becomes unnecessary. Thereby, the writing speed can be improved. Other effects are the same as those of the first embodiment.

[3] Third Embodiment The threshold check operation can also be applied to a dummy cell transistor. FIG. 12 is a cross-sectional view of the NAND string 10 including the dummy cell transistor DT.

  For example, two dummy word lines WLDS0 and WLDS1 are arranged between the selection gate line SGS and the lowermost word line WL via an insulating film. For example, three dummy word lines WLDD0 to WLDD2 are arranged between the uppermost word line WL and the selection gate line SGD via an insulating film. The dummy cell transistor DT has the same configuration as the memory cell transistor MT. That is, in the example of FIG. 12, the NAND string 10 includes five dummy cell transistors DT. For example, the NAND string 10 is provided with 64 word lines WL and three select gate lines SGD.

  FIG. 13 is a cross-sectional view of a NAND string 10 including a dummy cell transistor DT according to another example. In the example of FIG. 13, the semiconductor pillar and the wiring layer group are roughly divided into two steps (twice processing). The convex part of the semiconductor layer 31 in the center part is a seam part that is processed twice.

  Two dummy word lines WLDL and WLDU are arranged so as to sandwich the joint portion. Further, for example, two dummy word lines WLDS0 and WLDS1 are arranged between the selection gate line SGS and the lowermost word line WL via an insulating film. For example, three dummy word lines WLDD0 to WLDD2 are arranged between the uppermost word line WL and the selection gate line SGD via an insulating film. That is, in the example of FIG. 13, the NAND string 10 includes seven dummy cell transistors DT. For example, the NAND string 10 includes 96 word lines WL (48 word lines WL below the dummy word lines WLDL and 48 word lines WL above the dummy word lines WLDU), two selections A gate line SGS and three selection gate lines SGD are provided.

  The dummy cell transistor DT is turned on in the write operation and the read operation. The dummy cell transistor DT has a predetermined threshold and has a threshold distribution similar to that in FIG. As in the case of the selection transistor, when the threshold value of the dummy cell transistor DT fluctuates to a reference value or more, an operation failure (writing failure, reading failure, etc.) occurs in the block BLK including such a dummy cell transistor DT. In particular, when misalignment occurs in the manufacturing process at the joint shown in FIG. 13, defects are likely to occur in the dummy word lines WLDL and WLDU.

  Therefore, the threshold value checking operation of the selection transistor described in the first and second embodiments can be applied to the dummy cell transistor DT. In the threshold check operation, the determination voltages VS1 and VS2 may be appropriately changed corresponding to the threshold of the dummy cell transistor DT with the aid of FIG. In the NAND string, all transistors other than the dummy cell transistor to be checked are turned on.

(Modification)
When one memory cell transistor MT holds 2-bit data, the threshold voltage takes one of four levels according to the held data. When the four levels are set in order from the lowest level, the erase level, the A level, the B level, and the C level, the voltage applied to the selected word line during the A level read operation is, for example, between 0V and 0.55V It is. Without being limited thereto, any of 0.1V to 0.24V, 0.21V to 0.31V, 0.31V to 0.4V, 0.4V to 0.5V, 0.5V to 0.55V, etc. It may be between. The voltage applied to the selected word line at the B level read is, for example, between 1.5V and 2.3V. Without being limited to this, it may be between 1.65V to 1.8V, 1.8V to 1.95V, 1.95V to 2.1V, 2.1V to 2.3V, and the like. . The voltage applied to the selected word line during the C level read operation is, for example, between 3.0V and 4.0V. Without being limited thereto, any of 3.0V-3.2V, 3.2V-3.4V, 3.4V-3.5V, 3.5V-3.6V, 3.6V-4.0V, etc. It may be between. The read operation time (tR) may be any one of 25 μs to 38 μs, 38 μs to 70 μs, 70 μs to 80 μs, and the like, for example.

  The write operation includes a program and a program verify. In the write operation, the voltage initially applied to the word line selected at the time of programming is, for example, between 13.7V and 14.3V. Without being limited thereto, for example, it may be between 13.7 V to 14.0 V, 14.0 V to 14.6 V, or the like. The voltage initially applied to the selected word line when writing odd-numbered word lines is different from the voltage initially applied to the selected word line when writing even-numbered word lines. May be. When the program operation is the ISPP method (Incremental Step Pulse Program), for example, about 0.5 V can be cited as a step-up voltage. The voltage applied to the non-selected word line may be between 6.0V and 7.3V, for example. It is not limited to this, For example, it may be between 7.3V-8.4V, and may be 6.0V or less. Depending on whether the non-selected word line is an odd-numbered word line or an even-numbered word line, the pass voltage to be applied may be different. The write operation time (tProg) may be, for example, between 1700 μs to 1800 μs, 1800 μs to 1900 μs, and 1900 μs to 2000 μs.

  In the erasing operation, a voltage initially applied to a well disposed on the semiconductor substrate and having the memory cell disposed above is, for example, between 12V and 13.6V. Without being limited thereto, for example, it may be between 13.6 V to 14.8 V, 14.8 V to 19.0 V, 19.0 V to 19.8 V, 19.8 V to 21 V, and the like. The erase operation time (tErase) may be, for example, between 3000 μs to 4000 μs, 4000 μs to 5000 μs, and 4000 μs to 9000 μs.

  The memory cell may have the following structure, for example. The memory cell has a charge storage film disposed on a semiconductor substrate such as a silicon substrate via a tunnel insulating film having a thickness of 4 nm to 10 nm. The charge storage film includes an insulating film such as a silicon nitride (SiN) film or a silicon oxynitride (SiON) film having a thickness of 2 nm to 3 nm, and a polysilicon (Poly-Si) film having a thickness of 3 nm to 8 nm. The laminated structure can be made. A metal such as ruthenium (Ru) may be added to the polysilicon film. The memory cell has an insulating film on the charge storage film. This insulating film is, for example, silicon oxide (SiO) having a thickness of 4 nm to 10 nm sandwiched between a lower High-k film having a thickness of 3 nm to 10 nm and an upper High-k film having a thickness of 3 nm to 10 nm. Has a membrane. As a material of the high-k film, hafnium oxide (HfO) or the like can be given. Further, the thickness of the silicon oxide film can be made larger than that of the high-k film. On the insulating film, a control electrode having a film thickness of 30 nm to 70 nm is provided via a work function adjusting film having a film thickness of 3 nm to 10 nm. Here, the work function adjusting film is a metal oxide film such as tantalum oxide (TaO) or a metal nitride film such as tantalum nitride (TaN). Tungsten (W) or the like can be used for the control electrode. An air gap can be disposed between the memory cells.

  In the present embodiment, a three-dimensional stacked nonvolatile semiconductor memory device in which a plurality of memory cells are stacked on a substrate is described as an example. However, the present invention is not limited to this, and a plurality of memory cells are arranged in a planar shape. It is also possible to apply to the two-dimensional nonvolatile semiconductor memory device.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Memory system, 10 ... NAND string, 100 ... NAND type flash memory, 101 ... Memory cell array, 102 ... Row decoder, 103 ... Column decoder, 104 ... Sense amplifier part, 105 ... Page buffer, 106 ... Core driver, 107 ... Voltage generation circuit 108 ... Input / output circuit 109 ... Address register 110 ... Controller 111 ... Status register 112 ... Fail bit counter 200 ... Memory controller 201 ... Host interface circuit 202 ... CPU 203 ... RAM 204 ... Buffer memory 205. NAND interface circuit 206. ECC circuit 300 300 Host device

Claims (6)

Each of the plurality of blocks includes a plurality of memory strings, and each of the plurality of memory strings includes a selection transistor and a plurality of memory cells connected in series to one end of the selection transistor. A memory cell array comprising:
In response to the first command, in the first block specified by the first command, it is determined whether the threshold value of the selection transistor is equal to or less than a first reference value, and the determination is performed in response to the second command. A non-volatile semiconductor memory device comprising: a controller that outputs a result to the outside. A data cache,
Data is input together with the first command,
The nonvolatile semiconductor memory device according to claim 1, wherein the controller stores the data in the data cache in parallel with the determination operation. A counter for counting the number of select transistors having a threshold value exceeding the first reference value;
The controller determines that the determination result of the first block is a pass when the count value is within a second reference value, and the first value when the count value exceeds the second reference value. The nonvolatile semiconductor memory device according to claim 1, wherein the determination result of one block is determined to be a failure. The controller is
If the determination result is a pass, in response to a third command, write data to the first block;
4. The nonvolatile semiconductor memory device according to claim 3, wherein when the determination result is a failure, data is written to a second block different from the first block in response to the third command.   5. The nonvolatile semiconductor memory device according to claim 3, wherein the controller stores, in a management area of the memory cell array, first information indicating that the first block is determined to be failed. 6. . A memory cell array including a plurality of blocks, each of the plurality of blocks including a plurality of memory strings, and each of the plurality of memory strings includes a selection transistor and a plurality of series connected to one end of the selection transistor A nonvolatile semiconductor memory device comprising a memory cell;
A memory controller for sequentially sending first and second commands to the semiconductor memory device;
The semiconductor memory device
In response to the first command, in the first block specified by the first command, it is determined whether or not a threshold value of the selection transistor is equal to or less than a first reference value;
A memory system, wherein the determination result is output to the memory controller in response to the second command.