JP2017135684A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2017135684A JP2017135684A JP2016016517A JP2016016517A JP2017135684A JP 2017135684 A JP2017135684 A JP 2017135684A JP 2016016517 A JP2016016517 A JP 2016016517A JP 2016016517 A JP2016016517 A JP 2016016517A JP 2017135684 A JP2017135684 A JP 2017135684A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- power semiconductor
- potential
- reset
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 263
- 230000002265 prevention Effects 0.000 claims abstract description 47
- 230000004044 response Effects 0.000 claims abstract description 29
- 238000001514 detection method Methods 0.000 claims description 80
- 239000000758 substrate Substances 0.000 claims description 38
- 230000000903 blocking effect Effects 0.000 claims description 24
- 230000002159 abnormal effect Effects 0.000 abstract description 8
- 238000013021 overheating Methods 0.000 description 12
- 230000005856 abnormality Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 238000002485 combustion reaction Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000001052 transient effect Effects 0.000 description 4
- 239000000567 combustion gas Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000007599 discharging Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01T—SPARK GAPS; OVERVOLTAGE ARRESTERS USING SPARK GAPS; SPARKING PLUGS; CORONA DEVICES; GENERATING IONS TO BE INTRODUCED INTO NON-ENCLOSED GASES
- H01T15/00—Circuits specially adapted for spark gaps, e.g. ignition circuits
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
- F02P3/00—Other installations
- F02P3/02—Other installations having inductive energy storage, e.g. arrangements of induction coils
- F02P3/04—Layout of circuits
- F02P3/055—Layout of circuits with protective means to prevent damage to the circuit, e.g. semiconductor devices or the ignition coil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
- F02P3/00—Other installations
- F02P3/02—Other installations having inductive energy storage, e.g. arrangements of induction coils
- F02P3/04—Layout of circuits
- F02P3/055—Layout of circuits with protective means to prevent damage to the circuit, e.g. semiconductor devices or the ignition coil
- F02P3/0552—Opening or closing the primary coil circuit with semiconductor devices
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
- F02P3/00—Other installations
- F02P3/02—Other installations having inductive energy storage, e.g. arrangements of induction coils
- F02P3/04—Layout of circuits
- F02P3/055—Layout of circuits with protective means to prevent damage to the circuit, e.g. semiconductor devices or the ignition coil
- F02P3/0552—Opening or closing the primary coil circuit with semiconductor devices
- F02P3/0554—Opening or closing the primary coil circuit with semiconductor devices using digital techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
【解決手段】制御信号に応じてゲートが制御されるパワー半導体素子と、予め定められた遮断条件が満たされたか否かを検出する遮断条件検出部と、パワー半導体素子をオンさせる制御信号が入力されたことに応じて、予め定められた期間の間リセットを指示するリセット信号を出力するリセット部と、リセット信号に応じてリセットされ、リセット後に遮断条件の発生が検出されたことをラッチするラッチ部と、ラッチ部が遮断条件の発生をラッチしていることに応じて、パワー半導体素子のゲートをオフ電位に制御する遮断回路と、ラッチ部のリセット期間中に、遮断条件が成立しているにもかかわらずパワー半導体素子のゲートがオン電位となることを防止する防止回路と、を備える半導体装置を提供する。
【選択図】図3
Description
特許文献1 特開2013−194530号公報
Claims (13)
- 制御信号に応じてゲートが制御されるパワー半導体素子と、
予め定められた遮断条件が満たされたか否かを検出する遮断条件検出部と、
前記パワー半導体素子をオンさせる制御信号が入力されたことに応じて、予め定められた期間の間リセットを指示するリセット信号を出力するリセット部と、
前記リセット信号に応じてリセットされ、リセット後に前記遮断条件の発生が検出されたことをラッチするラッチ部と、
前記ラッチ部が前記遮断条件の発生をラッチしていることに応じて、前記パワー半導体素子のゲートをオフ電位に制御する遮断回路と、
前記ラッチ部のリセット期間中に、前記遮断条件が成立しているにもかかわらず前記パワー半導体素子のゲートがオン電位となることを防止する防止回路と、
を備える半導体装置。 - 前記防止回路は、前記リセット部が前記リセット信号を出力した期間において、前記パワー半導体素子のゲートをオフ電位に制御する請求項1に記載の半導体装置。
- 前記防止回路は、前記遮断条件検出部が前記遮断条件の発生を検出した期間において、前記パワー半導体素子のゲートをオフ電位に制御する請求項1に記載の半導体装置。
- 前記遮断回路および前記防止回路は、前記パワー半導体素子のゲートおよびエミッタを電気的にそれぞれ接続して、前記パワー半導体素子のゲートをオフ電位にする請求項1から3のいずれか一項に記載の半導体装置。
- 前記防止回路は、前記ラッチ部から出力される、前記パワー半導体素子のゲートをオフ電位に制御することを指示する遮断信号と、前記リセット信号との論理和に応じて、前記パワー半導体素子のゲートをオフ電位に制御する請求項1に記載の半導体装置。
- 前記防止回路は、前記ラッチ部から出力される、前記パワー半導体素子のゲートをオフ電位に制御することを指示する遮断信号と、前記遮断条件検出部が前記遮断条件の発生を検出して出力する検出信号との論理和に応じて、前記パワー半導体素子のゲートをオフ電位に制御する請求項1に記載の半導体装置。
- 前記防止回路は、論理和回路を有し、演算した論理和を前記遮断回路に供給する請求項5または6に記載の半導体装置。
- 前記ラッチ部は、前記制御信号を動作電源としてラッチした値を保持する請求項1から7のいずれか一項に記載の半導体装置。
- 前記遮断条件検出部、および前記リセット部の少なくとも一方は、前記制御信号を動作電源とする請求項1から8のいずれか一項に記載の半導体装置。
- 前記遮断条件検出部は、前記パワー半導体素子が基準温度以上に加熱されたことに応じて、遮断条件が満たされたとする請求項1から9のいずれか一項に記載の半導体装置。
- 前記パワー半導体素子は、基板の第1面側に設けられたコレクタ端子、前記基板の第2面側に設けられたゲート端子およびエミッタ端子を有し、
前記遮断回路は、前記基板の前記第2面側に設けられたドレイン端子およびソース端子を有する請求項1から10のいずれか一項に記載の半導体装置。 - 前記パワー半導体素子は、IGBT(絶縁ゲートバイポーラトランジスタ)または縦型MOSFETである請求項1から11のいずれか一項に記載の半導体装置。
- 当該半導体装置は、外部からの制御信号に応じて点火コイルに流れる電流を制御するイグナイタである請求項1から12のいずれか一項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016016517A JP6707874B2 (ja) | 2016-01-29 | 2016-01-29 | 半導体装置 |
CN201611076287.1A CN107035596B (zh) | 2016-01-29 | 2016-11-29 | 半导体装置 |
US15/364,261 US9899804B2 (en) | 2016-01-29 | 2016-11-30 | Semiconductor apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016016517A JP6707874B2 (ja) | 2016-01-29 | 2016-01-29 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017135684A true JP2017135684A (ja) | 2017-08-03 |
JP6707874B2 JP6707874B2 (ja) | 2020-06-10 |
Family
ID=59386214
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016016517A Active JP6707874B2 (ja) | 2016-01-29 | 2016-01-29 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9899804B2 (ja) |
JP (1) | JP6707874B2 (ja) |
CN (1) | CN107035596B (ja) |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4075674A (en) * | 1972-12-18 | 1978-02-21 | Texas Instruments Incorporated | Expandable electronic protection system |
US4275701A (en) * | 1979-04-26 | 1981-06-30 | Fairchild Camera & Instrument Corp. | Ignition control system |
US4440130A (en) * | 1980-07-15 | 1984-04-03 | Tokyo Shibaura Denki Kabushiki Kaisha | Ignition control device |
JPS5949425B2 (ja) * | 1980-12-08 | 1984-12-03 | 株式会社デンソー | 内燃機関用点火装置 |
US4931940A (en) * | 1987-06-05 | 1990-06-05 | Honda Giken Kogyo Kabushiki Kaisha | Rotational position detector for controlling an internal combustion engine |
JP3544714B2 (ja) * | 1994-09-28 | 2004-07-21 | 株式会社東芝 | 半導体記憶装置 |
JP3477852B2 (ja) * | 1994-11-04 | 2003-12-10 | 株式会社デンソー | Igbt駆動回路および点火装置 |
JP3210561B2 (ja) * | 1995-06-14 | 2001-09-17 | 株式会社小糸製作所 | 放電灯点灯回路 |
JP3241279B2 (ja) * | 1996-11-14 | 2001-12-25 | 株式会社日立製作所 | 保護機能付きスイッチ回路 |
JP3484123B2 (ja) * | 2000-01-12 | 2004-01-06 | 株式会社日立製作所 | 内燃機関用点火装置 |
US7051724B2 (en) * | 2002-12-13 | 2006-05-30 | Hitachi, Ltd. | Car-mounted igniter using IGBT |
JP3968711B2 (ja) * | 2003-04-11 | 2007-08-29 | 株式会社デンソー | 内燃機関用点火装置およびそのイグナイタ |
JP4223331B2 (ja) * | 2003-06-13 | 2009-02-12 | 株式会社日立製作所 | 電力制御用半導体素子の保護装置及びそれを備えた電力変換装置 |
JP4287332B2 (ja) * | 2004-07-27 | 2009-07-01 | 株式会社ルネサステクノロジ | 積分回路、漸減回路、および半導体装置 |
JP4455972B2 (ja) * | 2004-10-08 | 2010-04-21 | 三菱電機株式会社 | 半導体装置 |
JP4732191B2 (ja) * | 2006-02-28 | 2011-07-27 | 矢崎総業株式会社 | 過熱保護機能付き半導体装置の制御回路 |
JP5201321B2 (ja) * | 2007-12-04 | 2013-06-05 | 富士電機株式会社 | イグナイタシステム |
JP4924705B2 (ja) * | 2009-04-15 | 2012-04-25 | 株式会社デンソー | 内燃機関点火装置 |
US8387598B2 (en) * | 2009-08-04 | 2013-03-05 | Fairchild Semiconductor Corporation | Ignition system open secondary detection |
JP5423377B2 (ja) * | 2009-12-15 | 2014-02-19 | 三菱電機株式会社 | イグナイタ用電力半導体装置 |
JP5951429B2 (ja) * | 2012-02-01 | 2016-07-13 | ルネサスエレクトロニクス株式会社 | ウォッチドッグ回路、電源ic、及びウォッチドッグ監視システム |
JP5929361B2 (ja) * | 2012-03-16 | 2016-06-01 | 富士電機株式会社 | 半導体装置 |
CN104321871B (zh) * | 2012-11-08 | 2017-10-10 | 富士电机株式会社 | 半导体装置和半导体装置的制造方法 |
-
2016
- 2016-01-29 JP JP2016016517A patent/JP6707874B2/ja active Active
- 2016-11-29 CN CN201611076287.1A patent/CN107035596B/zh active Active
- 2016-11-30 US US15/364,261 patent/US9899804B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN107035596A (zh) | 2017-08-11 |
US20170222407A1 (en) | 2017-08-03 |
JP6707874B2 (ja) | 2020-06-10 |
CN107035596B (zh) | 2021-01-08 |
US9899804B2 (en) | 2018-02-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6805496B2 (ja) | 半導体装置 | |
US8836042B2 (en) | Semiconductor device comprising an IGBT and a constant voltage circuit having switches and normally-on type MOSFETs connected in parallel | |
JP5900627B2 (ja) | イグナイタ、イグナイタの制御方法および内燃機関用点火装置 | |
US10008835B2 (en) | Semiconductor apparatus | |
US20160265501A1 (en) | Semiconductor device | |
CN106979114B (zh) | 开关装置 | |
CN107725248B (zh) | 半导体装置 | |
KR100423367B1 (ko) | 전력변환장치 및 반도체 장치 | |
CN107204365B (zh) | 开关装置以及点火装置 | |
JP2019046945A (ja) | 半導体装置 | |
US9559098B2 (en) | Semiconductor device including voltage dividing diode | |
CN108063612B (zh) | 半导体装置 | |
JP6707874B2 (ja) | 半導体装置 | |
JP2005150321A (ja) | 半導体装置 | |
JP6634752B2 (ja) | デバイス | |
JP2001244463A (ja) | 半導体装置 | |
JP5125899B2 (ja) | 内燃機関用点火装置 | |
EP1465342A1 (en) | Multichannel electronic ignition device with high voltage controller | |
JP2019074043A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20181214 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20191025 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20191105 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191210 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200421 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200504 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6707874 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |