JP2017091098A - Parallelization method, parallelization tool, and car onboard device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parallelization method and a parallelization tool with which it is possible to create a parallel program that allows a multicore microcomputer to execute each MT at fastest speed, and an on-vehicle device that allows a multicore microcomputer to execute each MT at fastest speed.SOLUTION: A computer 10 expands a single program into an assembly language, and analyzes the dependency relation of each process in the assembly language (10a-10c). The computer 10 expands the single program into the assembly language by a second compiler 10g that is capable of expanding into the assembly language that includes special instructions peculiar to a multicore processor 21. Meanwhile, the computer 10 estimates an execution time in each process on the basis of the number of execution cycles of each instruction included in the assembly language expanded by the second compiler 10g. Then, on the basis of the analyzed dependency relation and the estimated execution time, the computer 10 allocates each process to each core and generates a parallel program so that each process satisfies the dependency relation.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a parallelization method for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer, a parallelization tool, and an in-vehicle device on which the parallel program generated by the parallelization method is mounted.

  Conventionally, there is a parallel compilation method disclosed in Patent Document 1 as an example of a parallel method for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer.

  In this parallel compilation method, an intermediate language is generated by performing lexical analysis and syntactic analysis on the source code of a single program, and using this intermediate language, dependency analysis and optimization of multiple macro tasks (hereinafter referred to as processing MTs) are performed. To make it. In the parallel compilation method, scheduling is performed based on the dependency relationship of each process MT and the execution time for each process MT to generate a parallel program, and the parallel program is converted into binary data.

Japanese Patent Laid-Open No. 2015-1807

  By the way, normally, a microcomputer such as a multi-core microcomputer has different functions and performance depending on the model and specifications, that is, the type. For this reason, although it is not a prior art, it is also conceivable to generate a parallel program source code with a parallelization tool and convert the source code into binary data with a compiler provided separately from the parallelization tool. That is, the compiler generates binary data by developing a source code into an assembly language in consideration of special instructions that can be executed by the target microcomputer in addition to general-purpose instructions. Therefore, many of these compilers are specialized for the target microcomputer and have low versatility. The target microcomputer is a microcomputer that executes a compiled program. On the other hand, it can be considered that the parallelization tool supports general-purpose instructions but does not support special instructions.

  Therefore, in the parallelization tool, when the source code of the single program is expanded to the assembly language, it is expanded to an assembly language that does not include special instructions. As described above, in the parallelization tool, an instruction in an assembly language obtained by developing a single program source code through lexical analysis or syntax analysis may be different from an instruction actually executed by a microcomputer. That is, in the parallelization tool of the comparative example, the instruction in the assembly language generated by the parallelization tool may be different from the instruction in the assembly language generated by the compiler.

  Therefore, although this parallelization tool can estimate the execution time of each process MT in consideration of the number of execution cycles of general-purpose instructions, it can estimate the execution time of each process MT in consideration of special instructions. Can not. In addition, the number of execution cycles of each instruction varies depending on the function and performance of the microcomputer.

  Therefore, in this parallelization tool, the estimated value of the execution time in each process MT is different from the execution time when each process MT is actually executed by the microcomputer, and it may occur that scheduling cannot be performed optimally. Therefore, the parallelization tool of the comparative example has a problem that the multicore microcomputer generates a parallel program that cannot execute each processing MT at the highest speed.

  The present invention has been made in view of the above problems, and a parallelization method, a parallelization tool, and a multicore microcomputer capable of creating a parallel program that allows a multicore microcomputer to execute each process MT at the highest speed. An object is to provide an in-vehicle device that can be executed.

In order to achieve the above object, the present invention provides:
A plurality of processes (MT0 to MT11) including at least one instruction in a single program for a single core microcomputer having one core are parallelized for a multicore microcomputer (21) having a plurality of cores (21c, 21d). A parallelization method for generating a parallel program (21a1),
A parallel program is a program for a microcomputer that is compatible with a multi-core microcomputer, is subjected to lexical analysis and syntax analysis, expanded into assembly language, and compiled into binary data.
A first expansion procedure (10a, 10b) for performing lexical analysis and syntax analysis of a single program and expanding it into an assembly language;
An analysis procedure (10c) for analyzing the dependency of each process in the assembly language expanded in the first expansion procedure;
Including a second expansion procedure (10g1 to 10g3) for expanding a single program into assembly language by performing lexical analysis and syntax analysis by a compiler for a microcomputer;
An estimation procedure (10d) for estimating the execution time in each process based on the number of execution cycles of each instruction included in the assembly language expanded in the second expansion procedure;
A scheduling procedure (10e) that allocates each process to each core and generates a parallel program so that each process satisfies the dependency, based on the dependency analyzed by the analysis procedure and the execution time estimated by the estimation procedure. 10f).

  As described above, according to the present invention, a single program is subjected to lexical analysis and syntax analysis by a microcomputer compiler corresponding to a multi-core microcomputer, and is expanded into an assembly language. The present invention estimates the execution time in each process based on the number of execution cycles of each instruction included in the assembly language. Therefore, the present invention can estimate the execution time based on the number of execution cycles of instructions actually executed by the multi-core microcomputer. For this reason, this invention can suppress that the execution time of each estimated process differs from the execution time at the time of actually performing each process with a multi-core microcomputer.

  Then, the present invention generates a parallel program by allocating each of the plurality of processes to each core so that each of the plurality of processes satisfies the dependency based on the execution time and the dependency. Therefore, the present invention can create a parallel program that allows the multi-core microcomputer to execute each process at the highest speed.

Further features of the invention include
A plurality of processes (MT0 to MT11) including at least one instruction in a single program for a single core microcomputer having one core are parallelized for a multicore microcomputer (21) having a plurality of cores (21c, 21d). A parallelization tool including a computer for generating a parallel program (21a1),
A parallel program is a program for a microcomputer that is compatible with a multi-core microcomputer, is subjected to lexical analysis and syntax analysis, expanded into assembly language, and compiled into binary data.
A first expansion unit (10a, 10b) that performs lexical analysis and syntax analysis of a single program and expands the assembly language;
An analysis unit (10c) for analyzing the dependency of each process in the assembly language expanded in the first expansion procedure;
Including a second expansion unit (10g1 to 10g3) for analyzing a lexical analysis and a syntax analysis of a single program by a compiler for a microcomputer into an assembly language,
An estimation unit (10d) for estimating an execution time in each process based on the number of execution cycles of each instruction included in the assembly language expanded in the second expansion procedure;
Based on the dependency relationship analyzed by the analysis unit and the execution time estimated by the estimation unit, a scheduling unit (10e) that allocates each process to each core and generates a parallel program so that each process satisfies the dependency relationship 10f).

  As a result, similarly to the above, it is possible to create a parallel program that allows the multi-core microcomputer to execute each process at the fastest speed.

Further features of the invention include
A multi-core microcomputer (21) having a plurality of cores (21c, 21d) and a plurality of processes (MT0 to MT11) including at least one instruction in a single program for a single-core microcomputer having one core are used for a multi-core microcomputer. A parallelized parallel program (21a1), and an in-vehicle device comprising:
The parallel program is a lexical analysis and syntactic analysis performed by a microcomputer compiler that supports multi-core microcomputers, expanded into assembly language, and compiled into binary data.
The dependency of each process in the expanded assembly language is analyzed by lexical analysis and syntax analysis of a single program,
The execution time in each process is estimated based on the number of execution cycles of each instruction included in the assembly language expanded by analyzing the lexical analysis and syntax analysis of the single program by the compiler for microcomputers.
Based on the dependency and execution time, each processing is assigned to each core so that each processing satisfies the dependency.
The multi-core microcomputer is that each core executes a process assigned to itself.

  Thus, as described above, the present invention includes a parallel program that allows the multi-core microcomputer to execute each process at the highest speed. Therefore, in this way, the present invention can execute each process at the fastest speed.

  The reference numerals in parentheses described in the claims and in this section indicate the correspondence with the specific means described in the embodiments described later as one aspect, and the technical scope of the invention is as follows. It is not limited.

It is a block diagram which shows schematic structure of the computer in 1st Embodiment. It is a block diagram which shows schematic structure of the vehicle-mounted apparatus in 1st Embodiment. It is a block diagram which shows the function of the computer in embodiment. It is an image figure which shows the single program in embodiment. It is an image figure which shows the parallel program in embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the present embodiment, a parallel program 21a1 parallelized for a multicore processor 21 having a first core 21c and a second core 21d from a plurality of processes MT0 to MT11 in a single program for a single core microcomputer having one core is provided. Take the example of generating. This process can be paraphrased as a process block or a macro task. In addition, this process includes at least one instruction that can be executed by the first core 21c and the second core 21d. The processor can be rephrased as a microcomputer. Therefore, the multi-core processor can be rephrased as a multi-core microcomputer.

  As described above, the background for generating the parallel program 21a1 is that the multi-core processor 21 becomes mainstream due to an increase in the amount of heat generated by the processor, an increase in power consumption, and a limit problem of the clock frequency. The multi-core processor 21 needs to be applied also in the field of in-vehicle devices. In addition, the parallel program 21a1 is required to have a highly reliable and high-speed process execution while suppressing the software development period and development cost.

  When the parallel program 21a1 is generated, the dependency relationship between the processes MT0 to MT11 in the single program is analyzed, and the processes MT0 to MT11 are allocated to the different cores 21c and 21d of the multicore processor 21 (in other words, , Assign). Regarding this point, refer to JP-A-2015-1807. In this embodiment, as an example, a single program written in C language is adopted. However, the present invention is not limited to this. The single program may be described in a programming language different from the C language.

  In the present embodiment, as shown in FIG. 4, as an example of a single program, a program including a first process MT0 to a twelfth process MT11 is employed. The plurality of processes MT0 to MT11 include processes MT that are dependent on each other. In FIG. 4, processes having dependency relationships are shown connected by arrows. Therefore, in the present embodiment, for example, the first process MT0 and the fourth process MT3 have a dependency relationship.

  The dependency relationship is, for example, a relationship in which a certain process refers to data updated by a process executed before itself. That is, the plurality of processes includes a preceding process whose execution order in the single program is first, and a succeeding process that is executed after the execution of the preceding process is completed. The succeeding process is a process that is affected by the preceding process, for example, a process that uses data or the like whose contents may be updated by the preceding process.

  Here, the configuration of the computer 10 will be described with reference to FIG. The computer 10 corresponds to a parallelization tool that executes a parallelization method, and generates a parallel program 21a1. The computer 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, a reading unit 17, and the like. The computer 10 is configured to be able to read the storage contents stored in the storage medium 18. The storage medium 18 stores the automatic parallelizing compiler 1. HDD is an abbreviation for hard disk drive. CPU is an abbreviation for Central Processing Unit. ROM is an abbreviation for Read Only Memory. RAM is an abbreviation for Random Access Memory. For the configurations of the computer 10 and the storage medium 18, refer to the personal computer 100 and the storage medium 180 described in JP-A-2015-1807.

  The automatic parallelizing compiler 1 includes a procedure for generating the parallel program 21a1. Therefore, the automatic parallelizing compiler 1 corresponds to a parallelization method. That is, the automatic parallelizing compiler 1 is a program including a parallelizing method. The computer 10 generates the parallel program 21a1 by executing the automatic parallelizing compiler 1.

  Note that the automatic parallelizing compiler 1 includes a second expansion procedure in addition to the one described in JP-A-2015-1807. The second deployment procedure will be described later. Further, the automatic parallelizing compiler 1 is different from that described in Japanese Patent Laid-Open No. 2015-1807 in the content of the estimation unit 10d.

  Next, the configuration of the in-vehicle device 20 will be described. As illustrated in FIG. 2, the in-vehicle device 20 includes a multi-core processor 21, a communication unit 22, a sensor unit 23, and an input / output port 24. The multi-core processor 21 includes a ROM 21a, a RAM 21b, a first core 21c, and a second core 21d. The in-vehicle device 20 can be applied to, for example, an engine control device or a hybrid control device mounted on an automobile. Here, as an example, an example in which the in-vehicle device 20 is applied to an engine control device is adopted. In this case, the parallel program 21a1 can be said to be an automobile control program such as engine control. However, the parallel program 21a1 is not limited to this. The core can also be referred to as a processor element.

  The first core 21c and the second core 21d execute engine control by executing the parallel program 21a1. For the RAM 21b, the communication unit 22, the sensor unit 23, and the input / output port 24, refer to the RAM 420, the communication unit 430, the sensor unit 450, and the input / output port 460 described in Japanese Patent Application Laid-Open No. 2015-1807.

  In the ROM 21a, a parallel program 21a1 generated by the computer 10 according to the automatic parallelizing compiler 1 is written and stored. More specifically, the computer 10 generates a parallel program 21a1 that is source code written in C language from a single program that is source code written in C language. Then, the parallel program 21a1 written in the C language is converted by the first compiler 40 into a parallel program 21a1 composed of a machine language such as binary data. Therefore, the ROM 21a stores a parallel program 21a1 composed of binary data, that is, in a format executable by each of the cores 21c and 21d. Thus, the parallel program 21a1 before being converted by the first compiler 40 and the parallel program 21a1 stored in the ROM 21a differ only in the description method and can be said to be equivalent programs.

  The first compiler 40 includes a lexical analyzer, a syntax and semantic analyzer, an assembler expansion unit, and the like. Then, the first compiler 40 compiles the parallel program 21a1 described in the C language and converts it into binary data, for example, by developing it into an assembly language.

  The assembly language includes mnemonics and operands. The mnemonic is an instruction executed by an arithmetic unit such as the first core 21c or the second core 21d. The operand indicates the target of the mnemonic.

  The mnemonic is described as, for example, ADD, LD, ST, AND, NOP and the like. Note that ADD is an instruction indicating addition. LD is an instruction indicating a load. ST is an instruction indicating a store. AND is an instruction indicating a logical product. NOP is an instruction that means do nothing. Furthermore, mnemonics include not only these general-purpose instructions, but also special instructions (hereinafter referred to as special instructions) that lack generality. This special instruction is an instruction peculiar to a certain processor. Thus, special instructions may be executable on some processors but not on other processors.

  The first compiler 40 has a configuration corresponding to the multi-core processor 21. In other words, the first compiler 40 is a compiler dedicated to the multi-core processor 21. Therefore, the first compiler 40 can develop a single program into an assembly language including special instructions peculiar to the multi-core processor 21 when developing the single program into the assembly language. The first compiler 40 corresponds to a microcomputer compiler.

  In the parallel program 21a1, two processing MTs having a dependency relationship may be arranged in different cores 21c and 21d. Therefore, the parallel program 21a1 waits for the processing order allocated to the other cores to complete the execution of the previous processing MT when two processing MTs having dependencies are arranged in different cores 21c and 21d. The process order includes a synchronization process for executing the later process MT. In other words, when the execution of the process MT allocated to the own core is completed, the parallel program 21a1 waits for the execution of the process MT allocated to the other core to be completed, and then performs the next process allocated to the own core. A synchronization process for executing MT is included. The process MT allocated to the other core here is dependent on the next process MT allocated to the own core, and the execution order is ahead of the next process MT allocated to the own core.

  For this reason, when the execution of the process MT allocated to the first core 21c and the second core 21d is completed, the first core 21c and the second core 21d access the RAM 21b and indicate that they are waiting for synchronization ( Hereinafter, the completion information) is stored in the RAM 21b. Then, the self-core waiting for the completion of the execution of the process MT having the dependency in the other core periodically accesses the RAM 21b without executing the process MT, and whether or not the completion information is stored in the RAM 21b. Confirm. That is, the own core waiting for the completion of execution of the process MT having a dependency relationship in another core periodically operates during non-operation, accesses the RAM 21b, and checks whether completion information is stored. . As described above, the first core 21c and the second core 21d execute the processing MT while waiting for each other, in other words, while synchronizing. Therefore, it can be said that the synchronization process is a waiting process. The parallel program 21a1 includes a program executed by the first core 21c and a program executed by the second core 21d.

  Next, processing operations when the computer 10 executes the automatic parallelizing compiler 1 will be described with reference to FIGS. The computer 10 generates the parallel program 21a1 by executing the automatic parallelizing compiler 1. As described above, the computer 10 generates the parallel program 21a1 described in C language.

  FIG. 3 is a diagram showing the processing of the computer 10 as functional blocks. The computer 10 includes a first lexical analysis unit 10a, a first syntax analysis unit 10b, a dependency relationship analysis unit 10c, an estimation unit 10d, a core allocation unit 10e, and a scheduling unit 10f. Furthermore, the computer 10 includes a second compiler 10g.

  The first lexical analyzer 10a and the first syntactic analyzer 10b perform lexical analysis and syntax and semantic analysis on the source code of a single program written in C language, and develop it into an assembly language. That is, like the first compiler 40, the first lexical analyzer 10a and the first syntax analyzer 10b expand source code written in C language into assembly language. However, unlike the first compiler 40, the first lexical analyzer 10a and the first syntax analyzer 10b are not dedicated to the multi-core processor 21. For this reason, the assembly language developed by the first lexical analyzer 10a and the first syntax analyzer 10b includes general-purpose instructions, but does not include special instructions specific to the multi-core processor 21. The first lexical analyzer 10a and the first syntax analyzer 10b correspond to a first expansion unit. The first lexical analysis unit 10a and the first syntax analysis unit 10b correspond to the FE of Japanese Patent Application Laid-Open No. 2015-1807, so refer to Japanese Patent Application Laid-Open No. 2015-1807.

  The dependency relationship analysis unit 10c analyzes a single program and extracts processes that can be executed in parallel. That is, the dependency relationship analysis unit 10c analyzes the dependency relationship between the plurality of processes MT0 to MT11 in the single program, and extracts processes that can be executed in parallel. In addition, the dependency relationship analysis unit 10c analyzes the dependency relationship for the single program developed in the assembly language by the first lexical analysis unit 10a and the first syntax analysis unit 10b, and extracts processes that can be executed in parallel. . The dependency relationship analysis unit 10c corresponds to an analysis unit. Regarding this point, refer to JP-A-2015-1807.

  Here, before describing the estimation unit 10d and the core allocation unit 10e, the second compiler 10g will be described. The second compiler 10g includes a second lexical analyzer 10g1, a second syntax analyzer 10g2, and an assembler expansion unit 10g3. Similar to the first lexical analyzer 10a and the first syntax analyzer 10b, the second compiler 10g expands the single program into assembly language. However, unlike the first lexical analyzer 10a and the first syntax analyzer 10b, the second compiler 10g is dedicated to the multi-core processor 21. Therefore, the second compiler 10g can be developed into an assembly language including special instructions unique to the multi-core processor 21, like the first compiler 40. Therefore, it can be said that the computer 10 expands the single program into assembly language by performing lexical analysis and syntax analysis by the first compiler 40. The second compiler 10g corresponds to a second expansion unit.

  Note that the second compiler 10g may be provided separately from the computer 10. In this case, the computer 10 acquires the result of developing the single program into assembly language by the second compiler 10g provided separately from the computer 10 itself.

  The estimation unit 10d estimates the execution time in each process MT0 to MT11 based on the number of execution cycles of each instruction included in the assembly language expanded by the second compiler 10g. The estimation unit 10d corresponds to an estimation procedure.

  The execution time is the time required for the multi-core processor 21 to complete the execution of the processes MT0 to MT11, and can also be referred to as the processing time. The execution time corresponds to the number of execution cycles of instructions included in each process MT0 to MT11. For example, consider a case where the process MT0 includes an instruction X and an instruction Y. In this case, the execution time of the process MT0 is a value obtained by adding the number of execution cycles of the instruction X and the number of execution cycles of the instruction Y.

  For example, the estimation unit 10d estimates the execution time in each process MT0 to MT11 using information obtained from the microcomputer information 30. The microcomputer information 30 includes the number of execution cycles of each instruction including a special instruction executed by the multi-core processor 21. The microcomputer information 30 includes the number of execution cycles when each instruction is actually executed by the multi-core processor 21. That is, the number of execution cycles in the microcomputer information 30 is the number of execution cycles of each instruction according to the function and performance of the multi-core processor 21.

  The core allocation unit 10e allocates a plurality of processes MT0 to MT11 to different cores 21c and 21d of the multicore processor 21. And the scheduling part 10f rearranges each process MT0-MT11 by scheduling each process MT0-MT11. More specifically, the core allocating unit 10e and the scheduling unit 10f assign the processes MT0 to MT11 to the core 21c, based on the dependency analyzed by the dependency analyzing unit 10c and the execution time estimated by the estimating unit 10d. 21d is assigned. At this time, the core allocation unit 10e and the scheduling unit 10f allocate the processes MT0 to MT11 so as to satisfy the dependency, and generate the parallel program 21a1. In this way, the single program becomes a parallel program 21a1 in which the processes MT0 to MT11 are respectively assigned to the first core 21c and the second core 21d as shown in FIG. Regarding the core allocation unit 10e and the scheduling unit 10f, refer to Japanese Unexamined Patent Application Publication No. 2015-1807. The core allocation unit 10e and the scheduling unit 10f correspond to a scheduling unit.

  The computer 10 operates as described above by executing the automatic parallelizing compiler 1 to generate the parallel program 21a1. Therefore, it can be said that the first lexical analyzer 10a and the first syntax analyzer 10b correspond to the first expansion procedure. Further, it can be said that the second lexical analyzer 10g1, the second syntax analyzer 10g2, and the assembler expansion unit 10g3 correspond to a second expansion procedure. It can be said that the dependency relationship analysis unit 10c corresponds to an analysis procedure. It can be said that the second compiler 10g corresponds to a second expansion procedure. It can be said that the estimation unit 10d corresponds to an estimation procedure. It can be said that the core allocation unit 10e and the scheduling unit 10f correspond to a scheduling procedure.

  Moreover, the vehicle-mounted apparatus 20 performs engine control by executing the parallel program 21a1 generated in this way. That is, the first core 21c executes the second process MT1, the fourth process MT3, the seventh process MT6, the ninth process MT8, and the tenth process MT9. On the other hand, the second core 21d executes a first process MT0, a third process MT2, a fifth process MT4, an eighth process MT7, an eleventh process MT10, a twelfth process MT11, and a sixth process MT5.

  As described above, the computer 10 performs lexical analysis and syntax analysis on the single program by the second compiler 10g corresponding to the multi-core processor 21, and expands it into an assembly language. Then, the computer 10 estimates the execution time in each process MT0 to MT11 based on the number of execution cycles of each instruction included in the assembly language. Therefore, the computer 10 can estimate the execution time based on the number of execution cycles of instructions actually executed by the multi-core processor 21. For this reason, the computer 10 can suppress that the estimated execution time of each process MT0 to MT11 is different from the execution time when each process MT0 to MT11 is actually executed by the multi-core processor 21.

  Then, the computer 10 allocates each of the plurality of processes MT0 to MT11 to each of the cores 21c and 21d so that each of the plurality of processes MT0 to MT11 satisfies the dependency relation based on the execution time and the dependency relation. Generate a parallel program. Therefore, the computer 10 can create the parallel program 21a1 in which the multi-core processor 21 can execute the processes MT0 to MT11 at the highest speed. Furthermore, the computer 10 can create a parallel program that allows the multi-core processor 21 to execute the processes MT0 to MT11 at the highest speed while supporting various microcomputers, that is, maintaining versatility.

  In other words, the computer 10 can estimate the execution time of each process MT0 to MT11 corresponding to the multi-core processor 21. For this reason, the computer 10 can generate the parallel program 21a1 that can prevent the time waiting for the completion of the execution of the process MT having the dependency in the other cores from being increased. Similarly, the computer 10 can suppress the generation of the parallel program 21a1 in which a certain process MT is actually not arranged even though a certain process MT can be arranged between the two processes MT.

  As an example of a technique for estimating the execution time and generating a parallel program, actually, each process is executed by a multi-core processor, the execution time is measured, and the measured execution time is fed back to generate a parallel program. It is also possible. This technology can adopt an accurate value corresponding to the multi-core processor as the execution time. However, this technology cannot be applied without an actual multi-core processor. Therefore, this technique cannot be applied when developing an automatic parallelizing compiler and an in-vehicle device in parallel. In addition, this technique has a problem that development efficiency is poor because it is necessary to schedule again based on the measured execution time.

  On the other hand, since the computer 10 uses the microcomputer information 30 without an actual machine of the multi-core processor 21, an accurate value corresponding to the multi-core processor 21 can be adopted as the execution time. In addition, the computer 10 does not need to perform scheduling again and can suppress the deterioration of efficiency.

  The automatic parallelizing compiler 1 can achieve the same effects as the computer 10. Furthermore, since the in-vehicle device 20 executes the parallel program 21a1, the multi-core processor 21 can execute the processes MT0 to MT11 at the fastest speed.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

  In the present embodiment, the in-vehicle device 20 including the two first cores 21c and the second core 21d is employed. However, the present invention is not limited to this, and an on-vehicle device having three or more cores can be adopted. Therefore, the present invention can be adopted even in a computer and an automatic parallelizing compiler for generating a parallel program corresponding to three or more cores from a single program.

  1 automatic parallelizing compiler, 10 computer, 11 display, 12 HDD, 13 CPU, 14 ROM, 15 RAM, 16 input device, 17 reading unit, 18 storage medium, 20 in-vehicle device, 21 multi-core processor, 21a ROM, 21a1 parallel program , 21b RAM, 21c 1st core, 21d 2nd core, 22 communication part, 23 sensor part, 24 I / O port

Claims (6)

Parallel processing for a multi-core microcomputer (21) having a plurality of cores (21c, 21d) from a plurality of processes (MT0 to MT11) including at least one instruction in a single program for a single-core microcomputer having one core A parallelization method for generating the parallel program (21a1),
The parallel program is a compiler for a microcomputer corresponding to the multi-core microcomputer, is subjected to lexical analysis and syntax analysis, is expanded into an assembly language, and is compiled into binary data,
A first expansion procedure (10a, 10b) for performing lexical analysis and syntax analysis of the single program and expanding the assembly program into assembly language;
An analysis procedure (10c) for analyzing the dependency of each of the processes in the assembly language developed in the first development procedure;
A second expansion procedure (10g1 to 10g3) for performing lexical analysis and syntax analysis on the single program by the microcomputer compiler and expanding the assembly into assembly language;
An estimation procedure (10d) for estimating an execution time in each process based on the number of execution cycles of each instruction included in the assembly language expanded in the second expansion procedure;
Based on the dependency relationship analyzed by the analysis procedure and the execution time estimated by the estimation procedure, the parallel processing is performed by assigning the processing to each core so that the processing satisfies the dependency relationship. And a scheduling procedure (10e, 10f) for generating a program.   The parallelization method according to claim 1, wherein the second expansion procedure is expanded into an assembly language including special instructions unique to the multicore microcomputer. Parallel processing for a multi-core microcomputer (21) having a plurality of cores (21c, 21d) from a plurality of processes (MT0 to MT11) including at least one instruction in a single program for a single-core microcomputer having one core A parallelization tool including a computer for generating the parallel program (21a1),
The parallel program is a compiler for a microcomputer corresponding to the multi-core microcomputer, is subjected to lexical analysis and syntax analysis, is expanded into an assembly language, and is compiled into binary data,
A first expansion unit (10a, 10b) that performs lexical analysis and syntax analysis of the single program and expands into assembly language;
An analysis unit (10c) for analyzing a dependency relationship of each of the processes in the assembly language expanded by the first expansion unit;
A second expansion unit (10g1 to 10g3) that expands the single program into an assembly language by performing lexical analysis and syntax analysis by the microcomputer compiler;
An estimation unit (10d) for estimating an execution time in each of the processes based on the number of execution cycles of each of the instructions included in the assembly language expanded in the second expansion unit;
Based on the dependency relationship analyzed by the analysis unit and the execution time estimated by the estimation unit, each process is assigned to each core so that each process satisfies the dependency relationship. A parallelization tool comprising a scheduling unit (10e, 10f) for generating a program.   4. The parallelization tool according to claim 3, wherein the second expansion unit expands to an assembly language including special instructions unique to the multi-core microcomputer. A multi-core microcomputer (21) having a plurality of cores (21c, 21d) and a plurality of processes (MT0 to MT11) including at least one instruction in a single program for a single-core microcomputer having one core. An in-vehicle device comprising a parallel program (21a1) parallelized for
The parallel program is a compiler for a microcomputer corresponding to the multi-core microcomputer, which is subjected to lexical analysis and syntax analysis, expanded into an assembly language, and compiled into binary data.
The dependency of each processing in the assembly language expanded by performing lexical analysis and syntax analysis of the single program is analyzed,
Based on the number of execution cycles of each instruction included in the assembly language expanded by performing lexical analysis and syntax analysis on the single program by the microcomputer compiler, the execution time in each process is estimated,
Based on the dependency relationship and the execution time, each of the plurality of processes is allocated to each core so that each process satisfies the dependency relationship,
The multi-core microcomputer is an in-vehicle device that executes the processing in which each core is assigned to itself.   6. The in-vehicle apparatus according to claim 5, wherein the single program is expanded into an assembly language including special instructions unique to the multi-core microcomputer by the microcomputer compiler.

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