JP2017069397A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of increasing the number of contacts between upper- and lower-stage semiconductor devices while suppressing warpage equally to the lower-stage semiconductor device of a semiconductor device with a PoP structure, and of improving a communication speed of data (data communication speed), and to provide a manufacturing method of efficiently manufacturing the semiconductor device at a low cost.SOLUTION: Provided are a semiconductor device and a method of manufacturing the same. In the semiconductor device, on a first substrate, a semiconductor element is connected so that a circuit surface (a first surface) of the semiconductor element is opposed to the substrate. On a second surface at an opposite side to the first substrate, of the semiconductor element, a second substrate on which a terminal to be connected with a second semiconductor device is formed is mounted. The first substrate and the second substrate are fixed via a resin material and electrically connected with each other.SELECTED DRAWING: Figure 10

Description

  The present invention relates to a semiconductor device having a package-on-package structure and a manufacturing method thereof.

  As a typical three-dimensional semiconductor device, there is a package-on-package (hereinafter referred to as PoP) in which a memory package is stacked on a logic package. Since PoP can increase the mounting density in the surface direction by stacking semiconductor devices on a semiconductor device, it is widely adopted for smartphones and tablet terminals, and is an essential item for speeding up and increasing functionality.

  By the way, PoP needs to electrically connect upper and lower semiconductor devices. Conventionally, the lower semiconductor device has a simple structure in which a semiconductor element is flip-chip mounted on a circuit board, and the upper semiconductor device is connected via a solder ball.

However, due to recent demands for reduction in size, thickness, warpage of the lower semiconductor device has increased, and it has become difficult to ensure connection with the upper semiconductor device. Therefore, a structure in which the semiconductor element of the lower semiconductor device is sealed with a sealing material to suppress warpage of the semiconductor device has been proposed and put into practical use (see, for example, Non-Patent Document 1).
In the above method, terminals for communicating data between upper and lower semiconductor devices are formed by opening through vias in the sealing material of the lower package (see, for example, Non-Patent Document 2). For this reason, in order to increase the communication capacity of the semiconductor device, in order to increase the number of connection terminals between the upper and lower semiconductor devices, the area of the lower substrate is increased to increase the number of terminals, or the through resin via diameter is reduced to reduce the via density. It is necessary to raise.
However, increasing the area of the lower substrate leads to an increase in package size, which is contrary to market requirements, and the pitch of through-plastic vias is limited to about 0.3 mm due to CO ₂ laser processing limitations. It is also difficult to increase.

As one of the methods that can solve these problems, a method of disposing a substrate electrically connected to the lower package substrate on the upper surface of the lower package is disclosed.
For example, Patent Document 1 discloses a method of disposing a package connection substrate on a lower semiconductor element, and connecting the lower semiconductor element and the package connection substrate, and connecting the lower semiconductor element and the lower package substrate by wire bonding.
Patent Document 2 discloses a method in which a package connection substrate is arranged on a lower semiconductor element via a spacer and the package connection substrate and the lower package substrate are directly connected by wire bonding.
Alternatively, as disclosed in Patent Document 3, after the lower package is sealed once, a package connecting substrate is arranged, wire-bonded to the lower package substrate, and further sealed and integrated.
However, in all of the disclosed structures, wire bonding is required twice, and the package connection substrate is also required to have a multilayer board, which requires many steps, and the package connection substrate is expensive and inexpensive to manufacture. It's hard to say.

JP 2011-211077 A JP 2011-233672-A Special table 2008-535264 gazette

Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012

A three-dimensional semiconductor device is highly demanded for miniaturization and high density, and the conventional PoP structure semiconductor device is required to have higher performance. Also, it is required to manufacture such a semiconductor device sufficiently efficiently and at a low cost.
The present invention has been made in view of the above problems, and can suppress the warpage equivalently to the lower semiconductor device of the current sealed PoP structure semiconductor device while increasing the number of connection terminals, and the upper and lower semiconductor devices A semiconductor device capable of improving the data communication speed and a manufacturing method capable of manufacturing the semiconductor device efficiently and at low cost are provided.

As a result of intensive studies, the present inventors have found that the problem can be solved by the following semiconductor device and manufacturing method thereof.
That is, in the semiconductor device of the present invention, the semiconductor element is connected on the first substrate so that the circuit surface (first surface) of the semiconductor element faces the substrate, and the first substrate of the semiconductor element is A second substrate on which a terminal for connecting to the second semiconductor device is formed is mounted on the second surface on the opposite side, and the first substrate and the second substrate are fixed via a resin material. And are electrically connected.
In the semiconductor device of the present invention, the thermal expansion coefficient of the second substrate is larger than that of the first substrate, and the bending rigidity of the second substrate is larger than that of the first substrate. And small.
In the semiconductor device of the present invention, it is preferable to use a base material having an average coefficient of thermal expansion of 20 to 260 ° C. exceeding 12 × 10 ⁻⁶ (/ K) as the first substrate.
In the semiconductor device of the present invention, as the second substrate, an average coefficient of thermal expansion from 20 ° C. to 260 ° C. is 15 × 10 ⁻⁶ (/ K) or more and 70 × 10 ⁻⁶ (/ K) or less. It is preferable to use a material.
In the semiconductor device of the present invention, the resin material may have a bending rigidity D, a substrate thickness h (mm), a substrate width b (mm), a substrate bending elastic modulus E (GPa), D = E × (b × h ³ ) / 12 When the bending rigidity of the first substrate is D1 and the bending rigidity of the second substrate is D2, D1 / D2 is 100 <D1 / D2 <1000000 A ratio is preferred.
In the semiconductor device of the present invention, as the resin material, an insulating resin having an average coefficient of thermal expansion from 20 ° C. to 260 ° C. of 25 × 10 ⁻⁶ (/ K) or more and 200 × 10 ⁻⁶ (/ K) or less. It is preferable to use an adhesive.

Another aspect of the present invention is a method of manufacturing the above semiconductor device,
(I) mounting at least one semiconductor element on a first substrate so that a circuit surface of the semiconductor element faces the first substrate;
(II) A resin material is disposed on the surface of the first substrate on which the semiconductor element is mounted, the surface on which the semiconductor element is mounted, the surface of the second substrate facing the first substrate, or both surfaces. Process,
(III) disposing a second substrate on the second surface of the semiconductor element opposite to the first substrate;
(IV) connecting the wiring of the second substrate and the first substrate;
(V) separating the package substrate connected to the second substrate into individual pieces;
A method for manufacturing a semiconductor device is provided.

Since the semiconductor device uses the second substrate on which the terminals are formed, the upper part of the semiconductor element, which cannot arrange the connection terminals in the conventional lower semiconductor device, can be utilized as the arrangement location of the connection terminals. And the lower semiconductor device can be connected. In general, the pitch of the vias of the flexible substrate can be made narrower than the pitch of the through resin vias. Therefore, when a flexible substrate is used as the second substrate on which the terminals are formed, the number of connection terminals can be increased, and high performance of the semiconductor device can be dealt with.
The flexible substrate used in the present invention may have a larger thermal expansion than the package substrate. Accordingly, when the flexible substrate as the second substrate and the package substrate as the first substrate are arranged via the resin material (insulating resin material) and the connection terminal portion is thermocompression bonded, the flexible substrate expands greatly. The flexible substrate can be bent (see reference numeral 14 in FIG. 9). Accordingly, the connection terminals of the flexible substrate (second substrate) and the package substrate (first substrate) can be in contact with each other, and the flexible substrate and the package substrate can be connected without using wire bonding or the like.
As described above, the present invention has fewer steps such as wire bonding and can be manufactured at a reduced cost and at a lower cost than the known package manufacturing method of the same type.
For this reason, the semiconductor device and the manufacturing method thereof of the present invention are particularly suitable for a three-dimensional semiconductor device that requires miniaturization and thinning, and can suppress warping.

It is a schematic sectional drawing for one semiconductor device which shows the process of forming a connection terminal in the package board | substrate as a 1st board | substrate of the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention. It is a schematic top view which shows the mounting process of the semiconductor element of the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention. It is a schematic sectional drawing for one semiconductor device which shows the mounting process of the semiconductor element of the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention. It is a schematic top view which shows the flexible substrate as a 2nd board | substrate of the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention. It is a schematic sectional drawing for one semiconductor device which shows a flexible substrate (2nd board | substrate) of the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention. It is a schematic sectional drawing for one semiconductor device which shows the form which formed the connecting terminal in the flexible substrate (2nd board | substrate) of the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention. 1 is a schematic cross-sectional view of one semiconductor device showing a step of bonding an insulating resin adhesive as a resin material to a package substrate (first substrate) in a method for manufacturing a semiconductor device according to an embodiment of the present invention. is there. The semiconductor device which shows the process of mounting a flexible substrate (2nd board | substrate) on the package board | substrate (1st board | substrate) which affixed the insulating resin adhesive of the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention It is a schematic sectional drawing for one piece. A semiconductor device 1 showing a step of bonding (thermocompression bonding) wiring of a package substrate (first substrate) and wiring of a flexible substrate (second substrate) in a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. It is a schematic sectional drawing for one semiconductor device which shows the process of mounting an external connection terminal in a package board | substrate of the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention. Schematic showing steps of dicing a package substrate (first substrate) to which a flexible substrate (second substrate) is connected in a method for manufacturing a semiconductor device according to an embodiment of the present invention, and separating the substrate into individual semiconductor devices. It is a top view. It is a schematic sectional drawing explaining the conventional semiconductor device.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted. Further, the dimensional ratio, the number of connection terminals, etc. in the drawings are not limited to the illustrated ratio and number. In this specification, the term “process” is not limited to an independent process, and is included in the term if the intended purpose of the process is achieved even when it cannot be clearly distinguished from other processes. . Moreover, the numerical range shown using "to" shows the range which includes the numerical value described before and behind "to" as a minimum value and a maximum value, respectively. In addition, in the numerical ranges described stepwise in the present specification, the upper limit value or lower limit value of a numerical range of a certain step may be replaced with the upper limit value or lower limit value of the numerical range of another step. Further, in the numerical ranges described in this specification, the upper limit value or the lower limit value of the numerical range may be replaced with the values shown in the examples.

FIG. 10 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
On the upper surface of the semiconductor device 20, connection terminals (connection terminals for connecting the upper and lower package on the flexible substrate) 12 for connection with the upper semiconductor device (second semiconductor device) are formed.
The connection terminal 6 of the flexible substrate (second substrate) is connected to and electrically connected to the connection terminal 4 of the package substrate (first substrate). Therefore, the upper semiconductor device (second semiconductor device) and the semiconductor device of the present invention can transmit and receive data.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.
A method for manufacturing the semiconductor device shown in FIG. 10 will be described below with reference to FIGS.

A flexible substrate will be described as an example of the second substrate on which terminals for connecting to the second semiconductor device are formed.
First, the connection terminals 12 that connect the upper and lower packages on the flexible substrate are formed on the flexible substrate (second substrate) 5 as necessary (see FIGS. 4 and 5). 1, 3, 5 to 10, and 12, the case of one semiconductor element will be described as an example. One semiconductor device may include a plurality of semiconductor elements. 2, 4, and 11, the case where 18 semiconductor devices are manufactured will be described as an example, but this embodiment is not limited thereto.
The flexible substrate 5 to be mounted may be a single-sided plate, a double-sided plate, or a laminated plate having one or more inner layers. The practitioner can make a selection in view of the necessary number of wires and cost. Moreover, since the flexible substrate 5 used in the present invention is finally fixed using a resin material (insulating resin adhesive or the like), so-called flex resistance is not necessarily required.
Examples of usable flexible substrates include polyimide-based flexible substrates and epoxy-based flexible substrates. The flexible substrate is more preferably one using a polyimide resin film.
When an example of a method for forming terminals on the second substrate is shown, drilling is performed on the flexible substrate as the second substrate using a laser processing machine, and drilling is performed through the flexible substrate (formation of vias). Drilling may be performed by etching instead of the laser processing machine. Then, if necessary, a roughening process for removing smear and adhesion is performed.
Next, electroless copper plating is performed to form a seed layer. The plating thickness is about 0.3 μm, and a dry film resist is laminated on each of the front and back surfaces of the flexible substrate. Then, a mask for forming a pattern for forming terminals, wirings, vias, and the like is brought into close contact, and exposure and development are performed to form a plating resist pattern. Copper plating is formed by electrolytic copper plating at a portion not covered with the plating resist pattern. Thereafter, the plating resist pattern is stripped with a stripping solution, and the seed layer covered with the plating resist pattern is removed with an etching solution. Then, if necessary, a solder resist is formed on the portion excluding the connection terminals and covered with insulation. In this way, the substrate shown in FIG. 5 is formed, and the connection terminals 6 are provided as shown in FIG. 6 to obtain the second substrate on which the terminals are formed.
As a method for forming the connection terminal 12 (6 in FIG. 6), a method of mounting a solder ball or forming a bump shape by mask printing using a solder paste or the like can be used.
The height of the connection terminal 6 in FIG. 6 needs to be set to a thickness suitable for the thickness from the front surface of the package substrate (first substrate) to the back surface of the semiconductor element (second surface). As shown in FIG. 3, when the thickness from the package substrate surface to the semiconductor element back surface is A and the thickness to the connection terminal 4 is B, AB is -50 μm or more, 100 μm or less, more preferably −20 μm. The thickness is 80 μm or less, more preferably 0 μm or more and 60 μm or less. If AB is large, it is impossible to connect to the connection terminal of the second substrate. If AB is small (minus), the thickness of the semiconductor device increases or the volume of the connection terminal 4 becomes too large. It may cause short circuit with other bumps.

Next, a package substrate as a first substrate will be described as an example.
1 and 2 show a package substrate as a first substrate. As the package substrate 1, a double-sided board, a multilayer board, and a build-up board are used, and terminals on the outermost layers on both sides are electrically connected as necessary (not shown). On the surface of the substrate on which the semiconductor element is mounted, a terminal for connecting to the circuit surface of the semiconductor element, a lead-out wiring from the terminal, a terminal for connecting to the second substrate, and for conducting to the opposite surface of the substrate Terminals etc. are formed, and pads 10 and the like of external connection terminals are formed on the opposite side of the substrate on which the semiconductor element is mounted. And the terminal periphery is coat | covered with the soldering resist, and the connection terminal 4 is formed.
Next, the semiconductor element 2 is mounted on the package substrate 1. Underfill 3 may be performed as necessary. (See Figs. 2 and 3)
As shown in FIG. 2, if the first substrate can be mounted with a plurality of semiconductor elements 2, a large number of semiconductor devices can be manufactured through a series of steps, and the first substrate can be manufactured at a low cost by individualizing them. Can do.

Next, on the connection terminal surface of the flexible substrate (second substrate, FIG. 6) on which the connection terminals 6 are formed, the connection terminal surface on which the connection terminals 4 (first substrate, FIG. 1) of the package substrate are located, or both An insulating resin adhesive (resin material) 7 is attached. Here, as shown in FIG. 7, an insulating resin adhesive (resin material) 7 is attached to the connection terminal surface of the connection substrate 4 of the package substrate as the first substrate.
As shown in FIG. 7, the thickness of the insulating resin adhesive at this time is defined as A from the surface of the package substrate to the back surface of the semiconductor element, and the height of the package substrate surface and the insulating resin adhesive 7 after pasting. Assuming C, AC may be −100 μm or more and 100 μm or less, more preferably −50 μm or more and 60 μm or less, and still more preferably −20 μm or more and 30 μm or less. If A-C is large, connection cannot be established, and if A-C is excessively small, the thickness of the semiconductor device increases.

Next, as shown in FIGS. 8 and 9, the terminals of the flexible substrate (second substrate) 5 and the package substrate (first substrate) 1 are bonded to each other. At this time, the step of positioning and mounting the flexible substrate on the package substrate (FIG. 8) and the step of connecting the terminals (FIG. 9) may be performed simultaneously or separately.
At this time, in order to connect the terminals of the flexible substrate and the package substrate, the flexible substrate is preferably stretched and bent. In order to realize this, the thermal expansion coefficient (thermal expansion coefficient) of the flexible board is made larger than the thermal expansion coefficient (thermal expansion coefficient) of the package board, and heat and pressure are applied to the flexible board and stretched. The way to do it is reasonable. That is, thermocompression bonding may be used. In addition, even if the thickness of the insulating resin adhesive is changed between the region where the semiconductor element is present and the region where the semiconductor element is not present before and after the flexible substrate is bent, it does not change. Also good.

Therefore, the average thermal expansion coefficient of the package substrate (first substrate) from 20 ° C. to 260 ° C. is preferably 0 × 10 ^{−6 to} 12 × 10 ⁻⁶ (/ K), and 2 × 10 ⁻⁶ to 10 × 10. ⁻⁶ (/ K) is more preferable, and 4 × 10 ⁻⁶ to 8 × 10 ⁻⁶ (/ K) is still more preferable. A material of 0 × 10 ⁻⁶ (/ K) or higher is easily available, and a substrate of 12 × 10 ⁻⁶ (/ K) or lower improves connection reliability with a semiconductor element and is easy to use.

The average thermal expansion coefficient of the flexible substrate (second substrate) from 20 ° C. to 260 ° C. is preferably 15 × 10 ⁻⁶ to 70 × 10 ⁻⁶ (/ K), and 20 × 10 ^{−6 to} 60 × 10. ⁻⁶ (/ K) is more preferable, and 25 × 10 ⁻⁶ to 50 × 10 ⁻⁶ (/ K) is still more preferable. When it is 15 × 10 ⁻⁶ (/ K) or more, the effect of stretching and bending at the time of thermocompression bonding is improved, and when it is 70 × 10 ⁻⁶ (/ K) or less, the reliability of the wiring formed on the flexible substrate is improved. .

In addition, the flexible substrate 5 may be more easily bent than the package substrate 1 in order to more reliably realize the state in which the flexible substrate is stretched and bent. That is, the second substrate may be more easily bent than the first substrate. In other words, the second substrate may be a combination of a flexible substrate and the first substrate may be a combination of a rigid substrate, the first substrate is a flexible substrate, and the second substrate is more flexible than the first substrate. It may be a combination of substrates. The bendability can be evaluated by the bending rigidity D. In the case of a plate-like shape such as a substrate, the values are as follows: the thickness of the plate is h (mm), the width of the plate is b (mm), The elastic modulus is E (GPa), and it is expressed by D = E × (b × h ³ ) / 12. The larger the value, the harder it is to bend.
When the bending rigidity of the flexible substrate (second substrate) 5 is D2 and the bending rigidity of the package substrate (first substrate) 1 is D1, the ratio D1 / D2 of the bending rigidity of the flexible substrate 5 and the package substrate 1 is: 100 <D1 / D2 <1000000 is preferable, 500 <D1 / D2 <500000 is more preferable, and 1000 <D1 / D2 <100000 is still more preferable. When D1 / D2 exceeds 100, the bending of the package substrate 1 is appropriately reduced, so that the use as a semiconductor device is hardly hindered, and the combination of D1 / D2 being less than 1000000 is thick. This means that the semiconductor device has a POP structure as an object of the present invention.

When the bonding between the terminals is completed, the insulating resin adhesive 7 is fully cured. The conditions for the main curing can be performed under conditions suitable for the insulating resin adhesive to be used.
The resin material may be an insulating resin adhesive, and the average thermal expansion coefficient of this insulating resin adhesive from 20 ° C. to 260 ° C. is 25 × 10 ⁻⁶ to 200 × 10 ⁻⁶ (/ K). 30 × 10 ^{−6 to} 170 × 10 ⁻⁶ (/ K) is more preferable, and 35 × 10 ^{−6 to} 140 × 10 ⁻⁶ (/ K) is still more preferable. When it is 25 × 10 ⁻⁶ (/ K) or more, it is difficult to warp the convex shape, and when it is 200 × 10 ⁻⁶ (/ K) or more, the package is difficult to warp to the concave shape, and the use as a semiconductor device becomes easy. It is.
Next, the external connection terminal 9 is formed (FIG. 10). When the external connection terminals 9 are formed, Ni plating or Au plating may be performed on the pads 10 of the external connection terminals as an under barrier metal layer or the like. The external connection terminal 9 can be formed by mounting solder balls or applying a cream solder using a mask or the like and performing reflow.

  Next, as shown in FIG. 11, along the dicing line 11, it is divided into individual semiconductor devices by dicing. As a dividing method, a dicer for dividing a semiconductor element can be used, and a method used for dividing a general semiconductor device can be used. It is completed when it is separated into individual semiconductor devices.

  The present invention is not limited to the illustrated structure, but can be modified as necessary within the scope of the claims. For example, in FIG. 9, the flexible substrate is shown as being connected to the package substrate on four sides, but may be one side, two sides, or three sides.

  Although the embodiments of the semiconductor device and the manufacturing method thereof according to the present invention have been described above, the present invention is not necessarily limited to the above-described embodiments, and may be appropriately changed without departing from the spirit thereof. .

Example 1
(1) Preparation of Semiconductor Element A semiconductor element 2 (manufactured by Waltz Co., Ltd., trade name “WALTS-TEG CC80-0101JY_ (PI) _ModelI”) was prepared as a semiconductor element.
The wafer thickness was back-grinded to a thickness of 50 μm. Thereafter, dicing was performed to obtain a semiconductor element having a length of 7.3 mm, a width of 7.3 mm, and a thickness of 0.05 mm. (Thickness does not include terminal height)

(2) Production of connection terminal Cream solder is mask-printed on a board (product name “WALTS-KIT CC80-0102JY [MAP]”) prepared as a package board as the first board, and the connection terminal is printed It produced (FIG. 1). The produced terminal height was about 50 μm from the surface of the package substrate.
The product name “MCL-E-679FGBS” manufactured by Hitachi Chemical Co., Ltd. is used as the material of the substrate, the average thermal expansion coefficient of the material of the substrate is 7 × 10 ⁻⁶ (/ K), and the flexural modulus (rigidity, 25 C) was 25 (GPa) and the thickness was 0.36 (mm). The average coefficient of thermal expansion of the substrate was measured under the following conditions.

Measurement of thermal expansion coefficient The average thermal expansion coefficient at 20 to 260 ° C. of the package substrate, flexible substrate, and insulating resin adhesive used in each example and comparative example was measured by a thermomechanical analyzer (manufactured by Seiko Instruments Inc., (Trade name: TMA / SS6100) was measured under the following conditions.
<Measurement conditions>
-Sample shape of substrate: 20 mm x 3 mm x 0.1 mm
Measurement temperature range: room temperature (20 ° C.) to 260 ° C.
・ Raising rate: 5 ° C / min
・ Measurement mode: Tensile mode

(3) Mounting of Semiconductor Device Using a flip chip bonder (trade name “FCB3” manufactured by Panasonic Factory Solutions Co., Ltd.), the semiconductor element was mounted on a package substrate by flip chip connection.
After mounting, underfill (trade name “CEL-C-3750” manufactured by Hitachi Chemical Co., Ltd.) was supplied between the semiconductor element and the substrate, and heated and cured at 175 ° C. for 2 hours (see FIGS. 2 and 3).
Further, when the thickness from the package substrate surface to the back surface of the semiconductor element is A and the height of the connection terminal 4 is B, AB is about 60 μm.

(4) Preparation of flexible substrate Kapton 100H (thickness 25 μm) manufactured by Toray DuPont Co., Ltd. was prepared. The average thermal expansion coefficient was 27 × 10 ⁻⁶ (/ K), and the flexural modulus (25 ° C.) was 3.4 (GPa).

Drilling was performed on the prepared flexible substrate with a laser processing machine (trade name “LC-2F21B / 1C” manufactured by Hitachi Via Mechanics Co., Ltd.). The conditions were an energy density of 1700 J / cm ² and a pulse width of 80 μs. By this processing, a via penetrating the flexible substrate was formed (FIG. 4).

<Formation of seed layer>
Next, 0.3 μm of copper was plated by electroless copper plating to form a seed layer.
The plating bath was ATS AD COPPER IW manufactured by Okuno Pharmaceutical Co., Ltd., and the conditions were 32 ° C. and 25 minutes.

<Formation of dry film resist>
Using a dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name “Phototec RY-3525”), it was laminated on the seed layer with a roll laminator. Subsequently, the photo tool which formed the pattern was stuck, and it exposed by the energy amount of 100 mJ / cm < ² > using the exposure machine (The Oak Co., Ltd. make, brand name "EXM-1201 type | mold"). Next, spray development was performed for 90 seconds with a 1% by mass sodium carbonate aqueous solution at 30 ° C., and a dry film resist was opened to form a resist pattern.
After the surface pattern was formed, the back pattern was prepared in the same manner as the front.
The pattern has a pad diameter of 100 μm, a pad pitch of 350 μm, a pad pattern of 21 rows, 21 rows, and 441 pads arranged in a range of 7.3 mm in length and 7.3 mm in width. Minimum line / minimum space = 25 μm / The thickness was 25 μm.
The substrate size is 92 mm in width, 64 mm in length, 12 mm in length and 12 mm in width, and a pattern in which 5 in the long direction and 3 in the short direction are arranged at 17 mm pitch (ie, a substrate different from FIG. 4). Was used.

<Formation of wiring pattern>
Next, a wiring pattern was formed by electrolytic copper plating.
The plating bath used was a copper sulfate having a concentration of 220 g / l, and was performed at 25 ° C. for 25 minutes. The applied current at that time was 34A.

<Removal of dry film resist>
Next, the dry film resist was removed with a stripping solution.
The stripping solution used was NaOH having a concentration of 3% by mass, and was performed for 4 minutes.

<Removal of seed layer>
Next, the seed layer was removed with an etching solution.
The etching bath was prepared by diluting WLC-C2 manufactured by Mitsubishi Gas Chemical Co., Ltd. with pure water twice and at 25 ° C. for 90 seconds.

<Formation of insulating layer>
Next, an insulating layer was formed on the wiring pattern. Specifically, a solder resist (manufactured by Hitachi Chemical Co., Ltd., trade name “SN-9000”) is attached to a flexible substrate using a vacuum laminator at a pressure of 70 ° C. and 0.46 MPa, and UV is directly applied by a drawing exposure machine. The exposure was performed with an energy amount of 0.2 J / cm ² . Subsequently, the back surface was exposed in the same process and developed with a developer having a concentration of 1% by weight of NaOH for 1 minute.
Next, post-UV irradiation ( ² J / cm ² ) was performed, and then thermosetting was performed by heating at 160 ° C. for 1 hour in a nitrogen atmosphere (oxygen concentration of 50 ppm or less).

<Formation of upper connection pads>
The solder resist-formed flexible substrate prepared above is immersed in an electroless nickel plating solution (trade name “ICP Nicolon GM-NP” manufactured by Okuno Pharmaceutical Co., Ltd.) at 80 ° C. for 1350 seconds, and then a substitution gold plating solution (Okuno at 60 ° C.). The product was soaked for 900 seconds in “trade name Muden Noble AU” manufactured by Pharmaceutical Industries, Ltd., and the upper connection pad 12 was processed to have a nickel plating thickness of about 2 μm and a gold plating thickness of about 0.05 μm. (See FIGS. 5 and 6).

(5) Affixing insulating resin adhesive to package substrate 70 μm thick insulating resin adhesive 7 (trade name “HS-260”, manufactured by Hitachi Chemical Co., Ltd.) is applied to the package substrate using a vacuum laminator. C. and a pressure of 0.46 MPa (see FIG. 7). At this time, the thickness of the insulating resin adhesive was about 60 μm, because the semiconductor element was embedded and the thickness increased from the original film.
When this insulating resin adhesive was cured at 175 ° C. for 2 hours, the average coefficient of thermal expansion from 20 ° C. to 260 ° C. was measured to be 110 × 10 ⁻⁶ (/ K).
As shown in FIG. 7, the thickness of the insulating resin adhesive at this time is set to A from the surface of the package substrate surface to the back surface of the semiconductor element, and the thickness of the package substrate surface and the insulating resin adhesive 7 after pasting is high. Assuming that C is AC, AC was -10 μm.

(6) Mounting of flexible substrate The flexible substrate prepared in (4) was placed on the package substrate with the insulating resin adhesive 7 prepared in (5) after alignment. Thereafter, it was pasted at 70 ° C. and a pressure of 0.46 MPa using a vacuum laminator (see FIG. 8).

(7) Connection of flexible substrate The flexible substrate bonded to the package substrate in (6) and the wiring of the package substrate were connected. Prepare a tool with four protrusions 8mm long and 2mm wide in a square shape with no corners, set a heater with a flip chip bonder so that the connection temperature is 260 ° C, and press for 100N for 5 seconds (See FIG. 9).

  Thereafter, the package substrate was held at 175 ° C. for 2 hours to cure the insulating resin adhesive.

(8) Production of external connection terminal Next, a solder ball (diameter 0.25 mm) is mounted on the lower package substrate, and a nitrogen atmosphere is used using a reflow apparatus (trade name “TNP25-337EM” manufactured by Tamura Corporation). The solder balls were melted at an oxygen concentration of 200 ppm or less to form external connection terminals 9 (see FIG. 10).

(9) Dividing into individual semiconductor devices The sample produced above was divided into individual semiconductor devices using a dicer (DAD3350, manufactured by DISCO Corporation). A dicer blade having a width of 0.2 mm was used. The division size was 12 mm in length and 12 mm in width (see FIG. 11).

The bending rigidity at this time is D1 = 25 GPa × 12 mm × (0.36 mm) where D2 is the bending rigidity of the flexible substrate (second substrate) 5 and D1 is the bending rigidity of the package substrate (first substrate) 1. ³ /12=1.17 GPa · mm ⁴ , D2 = 3.4 GPa × 12 mm × (0.025 mm) ³ /12=0.0000531 GPa · mm ⁴
D1 / D2 is about 22000.

Comparative Example 1
<Installation of semiconductor elements>
Using the same package substrate and semiconductor element as in Example 1, the semiconductor element was mounted on the package substrate by flip-chip connection in the same manner as in Example 1, and the underfill was supplied between the semiconductor element and the substrate and cured. .

<Sealing>
A package substrate on which a semiconductor element is mounted is sealed using a sealing material (trade name “CEL-420” manufactured by Hitachi Chemical Co., Ltd.) with a compression sealing device (WCM300 manufactured by Apic Yamada Co., Ltd.) so as to cover the semiconductor element. did.
The sealing conditions were a press hot plate temperature of 140 ° C., a mold clamping force of 150 KN, and a cure time of 300 seconds.

Next, the sealed sample was drilled with a laser processing machine (trade name “LC-2F21B / 1C” manufactured by Hitachi Via Mechanics Co., Ltd.). The conditions were an energy density of 1700 J / cm ² and a pulse width of 80 μs. By this processing, a via penetrating the sealing material and reaching the lower package substrate was formed (see FIG. 12).
Further, since the pattern can be formed in 24 holes and 3 rows on the four sides of the package, the total number of contacts is 252.

  Thereafter, the semiconductor device was held at 175 ° C. for 5 hours to cure the sealing material.

  Next, solder balls (diameter 0.25 mm) are mounted on the lower package substrate, and solder is used in a nitrogen atmosphere (oxygen concentration of 200 ppm or less) using a reflow apparatus (trade name “TNP25-337EM” manufactured by Tamura Corporation). The external connection terminal 109 was obtained by melting the ball.

The sample produced above was divided into individual semiconductor devices using a dicer (DAD3350, manufactured by DISCO Corporation). A dicer blade having a width of 0.2 mm was used. The division size was 12 mm in length and 12 mm in width.
Table 1 summarizes the number of connection terminals and the total number of contacts connecting the upper and lower packages of Example 1 and Comparative Example 1.

  In Example 1, the number of connection terminals connecting the upper and lower stages is larger than that in Comparative Example 1, and the effect of the invention is clear.

  From the above results, according to the present invention, it is possible to manufacture a semiconductor device having a PoP structure having a large number of upper and lower connection terminals by using a generally used apparatus for manufacturing a semiconductor device.

  The semiconductor device of the present invention can be used for a smartphone, a tablet terminal, or the like as a three-dimensional semiconductor device.

1 Package substrate (first substrate)
2 Semiconductor element 3 Underfill 4 Connection terminal of package substrate 5 Flexible substrate (second substrate)
6 Flexible PCB connection terminals 7 Insulating resin adhesive (resin material)
DESCRIPTION OF SYMBOLS 8 Connection part of package substrate and flexible substrate 9 External connection terminal 10 Pad of external connection terminal 11 Dicing line 12 Connection terminal connecting upper and lower packages on flexible substrate 13 Via of flexible substrate 14 Deflection of flexible substrate 20 Lower semiconductor of the present invention Device 101 Semiconductor element 102 Underfill 103 Package substrate 107 Sealing material 108 Through resin via (sealing resin through connection terminal)
109 External connection terminal 110 Upper semiconductor device 111 Lower semiconductor device with conventional structure 112 Semiconductor device with POP structure

Claims (7)

  A semiconductor element is connected on the first substrate so that a circuit surface of the semiconductor element faces the substrate, and a second surface of the semiconductor element opposite to the first substrate is connected to the second semiconductor device. A semiconductor device on which a second substrate on which a terminal is formed is mounted, the first substrate and the second substrate being fixed via a resin material and electrically connected.   The thermal expansion coefficient of the second substrate is larger than that of the first substrate, and the bending rigidity of the second substrate is smaller than that of the first substrate. Semiconductor device. 3. The semiconductor device according to claim 1, wherein a base material having an average coefficient of thermal expansion from 20 ° C. to 260 ° C. exceeding 12 × 10 ⁻⁶ (/ K) is used as the first substrate. The base material whose average coefficient of thermal expansion of 20 to 260 ^degreeC is 15 * 10 < ^-6 > (/ K) or more and 70 * 10 < ^-6 > (/ K) or less is used as said 2nd board ^| substrate. The semiconductor device according to any one of the above. The bending rigidity D is defined as D = E × (b × h ³ ) / 12 where the thickness of the substrate is h (mm), the width of the substrate is b (mm), and the bending elastic modulus of the substrate is E (GPa). When the bending rigidity of the first substrate is D1, and the bending rigidity of the second substrate is D2,
The semiconductor device according to claim 1, wherein D1 / D2 is a ratio of 100 <D1 / D2 <1000000. The said resin material is comprised from the insulating resin adhesive whose average thermal expansion coefficient of 20 to 260 ^degreeC is 25 * 10 < ^-6 > (/ K) or more and 200 * 10 < ^-6 > (/ K) or less. The semiconductor device as described in any one of -5.
(I) mounting at least one semiconductor element on a first substrate so that a circuit surface of the semiconductor element faces the first substrate;
(II) A resin material is disposed on the surface of the first substrate on which the semiconductor element is mounted, the surface on which the semiconductor element is mounted, the surface of the second substrate facing the first substrate, or both surfaces. Process,
(III) disposing a second substrate on the second surface of the semiconductor element opposite to the first substrate;
(IV) connecting the wiring of the second substrate and the first substrate;
(V) separating the package substrate connected to the second substrate into individual pieces;
A method for manufacturing a semiconductor device comprising:

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