JP2016536949A - Silicon-based image sensor with improved read dynamic range - Google Patents

Abstract

In the image sensor, the effective capacitance of the storage node NS of the pixel, which stores the charge (electrons) collected by the light sensitive element of the pixel, affects the supply VREFP of the follower transistor T3 connected to the storage node. Using the loop 100, the storage node's apparent capacitance is changed in a manner that depends on the loop gain GL. By changing the gain, the capacitance of the storage node, and hence the charge / voltage conversion coefficient inversely proportional to the capacitance, is changed.

Description

  The field of the invention is that of both silicon-based image sensors, matrix sensors and linear sensors, and is intended to improve their dynamic range.

  The dynamic range of the sensor is expressed in decibels (dB) and is observable at the output by the ratio of the strongest signal corresponding to high illumination to the background noise level of the sensor that determines the weakest signal corresponding to low illumination. Defined. This background noise level depends on the technology of the sensor and the characteristics of the electronic system for reading the pixel. The term sensor with a large scene dynamic range generally refers to a sensor with a dynamic range greater than 80 dB.

  The dynamic range of the sensor is a characteristic of the pixel and its structure, in particular its ability to convert photons to electrons, ie quantum efficiency, and its ability to convert collected electrons to voltage, ie charge / voltage conversion. Gain, as well as the characteristics inherent in the readout circuit downstream of the pixel: depends on the gain of the readout circuit and the voltage excursion allowable by the analog / digital converter of the readout circuit. This dynamic range is also constrained by technical factors. Within the light sensitive region where the pixel is formed, this is related, inter alia, to the pixel fill factor, i.e. the ratio of the pixel light sensitive region to the total surface area of the pixel, and within the peripheral region around the light sensitive region, This is related to the silicon surface area available for the read circuit. Conversion speed and power consumption must also be considered.

  When seeking to fabricate a sensor that provides a large scene dynamic range of 80, 84, 90 dB or more, it has a pixel structure that allows a large amount of charge to accumulate during the sensor integration period. It will be necessary. Otherwise there is a risk of saturating the measurement system at the level of pixels illuminated at high illumination. However, at this time, the gain of the conversion of charge to voltage must be relatively low. Otherwise, the reading circuit and the analog / digital conversion circuit will be saturated.

  The object of the present invention is to provide a gain that can be adapted to the received illuminance in order to avoid saturation in high illuminance and maintain a sufficiently high charge / voltage conversion gain in low illuminance. In order to obtain, it is to provide a solution for adjusting the charge / voltage conversion gain of the pixel.

The basic structure of a sensor pixel comprising a silicon-based active pixel comprises:
A separate capacitor formed by the intrinsic capacitance of the light sensitive element or connected to the light sensitive element by a charge transfer transistor in an active pixel structure comprising an intermediate storage node (comprising four or more transistor pixels) A capacitive storage node for storing charge (electrons) collected by the light sensitive elements of the pixel, and a follower transistor connected to the storage node, the amount of charge on the storage node at its output A follower transistor that provides a voltage level representative of

  The technical solution on which the present invention is based is such that by using a feedback loop that affects the supply of the follower transistor connected to the storage node, the apparent capacitance of the storage node depends on the loop gain. It mainly relies on changing the effective capacitance of the pixel storage node. By changing the gain, the capacitance of the storage node, and hence the charge / voltage conversion coefficient inversely proportional to the capacitance, is changed.

  This change in the effective capacitance of the storage node means that the effective capacitance is the sum of the intrinsic capacitance of the storage node, the gate / source capacitance of the follower transistor connected to the storage node, and the gate / drain capacitance. These latter two capacitances are each provided with a respective weighting factor in parallel with the storage node by the Miller effect, the weighting factor for the gate / drain capacitance being the follower transistor's This is mainly caused by the fact that it depends on the gain and the gain of the feedback loop.

  Accordingly, the present invention is an image sensor comprising active pixels, comprising a pixel and a readout circuit, each pixel comprising at least one light sensitive element, a node for accumulation of charge generated by the light sensitive element, And the gate of the follower transistor is connected to the storage node, the source of the follower transistor is connected to the column conductor, which itself is connected to the read circuit, and the drain of the follower transistor is In an image sensor that receives a supply voltage, a feedback loop is provided that has an input connected to the column conductor and an output connected to the drain of the follower transistor to provide the supply voltage of the follower transistor. And a function of the received illuminance. It means for changing the behavior of the feedback loop and in that is provided, to provide an image sensor.

  The behavior of the feedback loop may be altered by enabling or disabling the loop as a function of received illumination. Alternatively, it may be changed by changing the gain of the loop as a function of received illumination.

  In either case, the received illuminance may be the total illuminance received by the sensor, or it may be the illuminance received by the pixel itself.

  If the illuminance is the total illuminance of the sensor, it is possible to provide automatic detection of the total illuminance and an operation on the behavior of the loop as a function of this detection or a manual operation by the user can be provided is there. The user decides whether he wants to enter the high light mode or the low light mode, and as a result changes the gain or enables or disables the loop.

  On the other hand, if the illuminance is the illuminance received by the pixel itself independent of other pixels, the behavior of the loop preferably changes as a function of the voltage present on the column conductor when the storage node charge is read. Will be. This is because this voltage represents the illuminance received by the pixel. For example, different loop gains will be chosen according to the voltage level present on the column.

  In particular, the loop gain may be positive or negative. If it is negative, it increases the effective capacitance of the storage node and consequently decreases the charge / voltage conversion factor. If it is positive, it reduces the effective capacitance of the storage node and greatly increases the charge / voltage conversion factor. Thus, preferably, provisions may be made to make the loop gain positive or negative as a function of received illumination.

  The feedback loop is preferably disabled during the phase of reinitializing the storage node prior to transfer of charge from the photosensitive element to the storage node.

  Preferably, the feedback loop is a first amplifier having a negative gain, the first amplifier having its input connected to the column conductor and the second amplifier having a negative gain, the A second amplifier having an input connected to the output of the first amplifier, a comparator having two inputs connected to the outputs of the two amplifiers, respectively, and path selection means controlled by the comparator, Path selection means for guiding either the output of the first amplifier or the output of the second amplifier to the drain of the follower transistor.

  Preferably, the first amplifier has a first input connected to the first reference voltage, a second input connected to the input capacitor, a feedback capacitor, and during the step of initializing the storage node. A switch for shorting the feedback capacitor, and the second amplifier includes a first input connected to the second reference voltage, a second input connected to the input capacitor, a feedback capacitor, A switch for shorting the feedback capacitor during the phase of initializing the storage node.

  The proposed solution does not affect the pixel fill factor. This is a further advantage.

  Other features and advantages of the present invention will be set forth in the following detailed description which is provided, without implying any limitation, with reference to the accompanying drawings.

1 shows the basic structure of a CMOS sensor pixel comprising four transistors according to the prior art. Fig. 3 shows a related sequence signal for reading a CMOS sensor pixel comprising four transistors according to the prior art. Fig. 4 shows a feedback loop between the conductors of the pixel columns and the drains of the follower transistors of these pixels according to the invention. 1 illustrates a first embodiment of a feedback loop having an amplifier with negative gain according to the present invention. Figure 5 shows a time diagram illustrating the effect of a feedback loop during the charge transfer phase. Two amplifiers each having a negative gain, and the loop gain can be fixed to a positive or negative value as a function of the voltage provided by the column conductor during the reading of the charge stored in the storage node 2 shows a second embodiment of a feedback loop according to the invention with a comparator Fig. 4 is a time diagram of individual signals in a sequence reading a pixel with the above feedback loop with two amplifiers, corresponding to the low illumination level of the pixel in the case of column voltage. Fig. 4 is a time diagram of individual signals in a sequence reading a pixel with the above feedback loop with two amplifiers, corresponding to the high illumination level of the pixel in the case of a column voltage.

  The invention will be described in an application to an active pixel structure of a CMOS sensor with four transistors. However, the field of application of the present invention is actually the various structures of pixels with charge storage nodes coupled to follower transistors: pixels with more complex structures, using more transistors, or capacitive storage It is more widely adapted to pixels having a structure with three transistors, where it is the capacitance of the photosensitive element that directly constitutes the node.

  1a and 1b show the structure of a pixel PIX comprising four transistors of a CMOS sensor matrix and the sequence for reading the signal of the pixel PIX. The matrix is organized as rows and columns of pixels having the same structure.

  Each pixel PIX is connected to a column conductor that connects all the pixels in a given column of pixels. Each column conductor is generally common to all columns of the matrix and is selected for reading, a current source CC that provides the current required to read the pixels selected for reading of the column. Connected to a circuit ADC for reading the pixels of the column, which converts the voltage level Vcol applied to the column conductor by the pixel PIX into a digital form. This voltage level Vcol represents the illuminance received by the pixel.

  In this example, the light sensitive element of the pixel is a photodiode Dph. Other light sensitive elements such as MOS capacitors may be used.

  This photodiode is connected to the capacitive storage node NS by a transistor T1 during the stage TRA of transferring the charges collected by the photodiode to the capacitance Cs of the storage node NS.

A follower transistor T3 provides an output voltage representing the amount of charge transferred on the capacitive storage node on its source supplied with a constant current provided by the current source CC. When the pixel is selected for reading, its gate g is connected to the storage node NS, and its drain d is sufficient supply voltage V to bias transistor T3 in follower mode (bias in saturation mode). Upon receiving the _REFP , it becomes possible to replicate the voltage of the storage node onto the column conductor.

  A selection transistor T4 is connected between the source of the follower transistor T3 and the column conductor COL connecting the pixels of a given column. Its gate is connected to a conductor line LI to which a selection signal (SEL) for the pixel is applied. When the pixel is selected for reading, transistor T3 operates as a follower and the voltage Vcol on the column conductor is set to the output voltage of the pixel.

A reinitialization transistor T2 is provided for reinitializing the storage node NS. In this example, it is connected between the supply voltage V _REFP and the storage node NS, bringing this node to the voltage V _REFP .

When the pixel is selected for reading (when the signal SEL becomes active), the step of initializing the storage node NS, where the voltage at the node is set and stabilizes at the reinitialization level V _REFP , is the signal RS _NS The charge collected by the light sensitive element Dph is set to a working level representing the amount of charge accumulated by the node NS as a function of the pixel charge / voltage conversion factor. Is transferred to the storage node NS by the signal TRA. During this time, therefore, the voltage Vcol on the column COL, which is a replica of the voltage on the storage node within the threshold voltage of the follower transistor, is set to the corresponding reinitialization level and then to the corresponding operating level.

In general, the reading of the pixel by the reading circuit ADC is performed between the initialization phase (RS _NS ) and the transfer phase (TRA) to obtain a first digital value representing the reinitialization level of the voltage Vcol. Between the first analog / digital conversion and the second conversion of the voltage Vcol, which is performed after the transfer phase to obtain a second digital value representing the operating level, and the subsequent two digital values obtained Of subtraction. A digital calculation result is obtained that represents the illuminance received by the pixel and is a measurement that does not include correlated noise associated with the capacitive storage node.

  Having described the pixel structure and the corresponding read sequence, then, in order to improve the usable dynamic range of the pixel, how the present invention affects the charge / voltage conversion coefficient at the capacitive storage node of the pixel. Explain how to get.

  The pixel charge / voltage conversion factor is expressed in volts per electron and defines for the pixel the voltage level that will be obtained at the input of the reading circuit ADC for electrons collected by the light sensitive element of the pixel.

FIG. 2 shows the details of the pixel elements or parameters involved in the definition of the conversion factor: the capacitance C _NS of the pixel storage node _NS , and the gain and intrinsic capacitance of the follower transistor. The gain of the follower transistor represented by G _f is close to 1 and is about 0.8 or 0.9. The intrinsic capacitance of the follower transistor is the capacitance C _gs between the gate and the source of the transistor T3 and the capacitance C _gd between the gate and the drain of the follower transistor T3. This follower transistor has an inherent gain.

Thus, the total capacitance seen by the storage node NS includes contributions of capacitances C _NS and C _gd , as well as contributions of capacitance C _gs , but the latter is due to the Miller effect (1-G _f ) C _This is due to the reduced ratio to _gs .

ここで、ｑは電子の電荷である。 At this time, the charge / voltage conversion coefficient for this pixel structure is described as:

Here, q is the charge of electrons.

This definition is for a pixel structure with a capacitive storage node connected to a follower transistor biased with a fixed reference voltage V _REFP provided to all pixels of the sensor by a power supply according to the prior art (FIG. 1a). Applies to

In the present invention, as shown in FIG. 2, the voltage V _REFP is fed back between the column conductor and the drain of the follower transistor of the column pixel during the pixel reading, with a loop gain _GL. Provided by loop 100.

  More precisely, the feedback loop 100 has its input 101 connected to the column conductor COL. Its output 102 is connected to a supply conductor that feeds the drain of the follower transistor T3 of each pixel in column COL.

  Therefore, in practice, there will be one feedback loop per column.

At this time, the drain voltage applied during the pixel reading depends on the voltage Vcol provided by the column conductor during the pixel reading. Thus, when viewed from the storage node NS, the contribution of the gate / drain capacitance C _gd of the transistor to the conversion factor CVF is also proportional to the Miller effect added by the feedback loop according to the present invention. This ratio depends on the gain of the follower transistor and the gain of the loop.

More precisely, for this pixel structure having a feedback loop with a gain _GL , the charge / voltage conversion factor is then described as:

Therefore, the feedback loop 100 allows the use of the gate / drain capacitance of the follower transistor to change the value of the charge / voltage conversion coefficient. With a negative loop gain _GL , the contribution of this gate / drain capacitance to the effective capacitance of the storage node increases. As a result, the charge / voltage conversion coefficient CVF decreases. The dynamic range of the sensor at the higher illumination level is improved. Conversely, if it has a positive loop gain, this gate / drain capacitance contribution will be further “negative”, which allows the coefficient CVF to be increased. This is advantageous at low illumination levels.

  Thus, the feedback loop 100 allows the usable dynamic range of the pixel to be improved for a given pixel structure and readout electronic system. It may actually be implemented to improve the dynamic range for high and / or low illumination levels.

  Referring now to FIGS. 3 and 4, various practical exemplary embodiments are described that allow the invention and its applications to be better understood. For ease of understanding, elements common to the individual figures have the same reference numerals.

FIG. 3 shows a first exemplary embodiment of a feedback loop having a predetermined negative loop gain _GL . The figure shows two consecutive pixels PIX _i and PIX _{i + 1 in} the same column COL of pixels. These two pixels, the pixel PIX _i, is controlled by a signal SEL _i for selection of a row of rank i of the matrix, the pixel _{PIX i + 1,} the signal _{SEL i + 1} for the selection of the next row of rank i + 1 Connected to the column conductor COL by their respective select transistors to be controlled. The selection signals are ordered so that a single pixel in the column is selected for reading at a time. When a column of pixels is selected for reading, the transistor T3 of that pixel has its source connected to the current source CC and operates as a follower.

A feedback loop 100 having a gain _GL is formed by an amplifier AMP1 having a negative gain G1. Here, G _L = G1. The amplifier has an input e1 connected to the column conductor COL. The other input e2 receives a reference voltage _VREF . This reference voltage V _REF is common to all pixels of the matrix. The output of the amplifier forms the output 102 of the loop. It is connected to the drain supply conductor of the follower transistor T3 of all the pixels in the column.

Preferably, the input e1 is connected to the column conductor COL by an input capacitor C11, and a feedback capacitor C12 is connected between this input and the output of the amplifier. A switch controlled by the initialization signal RS _AMP1 is arranged in parallel with the capacitor C12. The switch controlled by the signal RS _AMP1 and the two capacitors make it possible to perform the initialization of the amplifier according to the follower mode configuration and to duplicate the input reference voltage at the output (the output S1 of the amplifier) Changes until the voltage difference between the two inputs e1 and e2 cancels). Therefore, a reference voltage level _VREF is applied on the output S1 of the amplifier. In practice, this initialization of the loop amplifier is performed in the phase of reinitializing the storage node. The voltage V _REF is used to reinitialize the storage node NS and the corresponding voltage level Vcol reappears on the column conductor COL. At this stage, the feedback loop is disabled and has no gain effect. Changes in the voltage level of the column do not affect the voltage level applied to the drain of the follower transistor. The latter is constant and equal to Vref. After reinitialization of the storage node NS and the amplifier AMP1, the signal RS _AMP1 is relaxed, enabling the feedback loop. Thereafter, any voltage difference between the column voltage Vcol and the reference voltage _{V REF,} a negative gain is amplified by an amplifier AMP1 is G1 = -C11 / C12.

FIG. 4 shows this feedback effect. The figure shows the change in the voltage V _REFP applied to the drain of the pixel by the feedback loop. This occurs during or after the stage of transferring charges (electrons) to the storage node (TRA). In this stage (TRA), the charge of the photodiode transferred to the storage node NS changes (decreases) the voltage at this node and thus also the voltage Vcol on the column according to the charge / voltage conversion coefficient.

In this example, since the loop gain _GL is negative, it reduces the charge / voltage conversion factor at the storage node of the pixel. The voltage level at the storage node, and hence the level of the voltage Vcol on the column, decreases more slowly, and at the end of the transfer, the level that would have been obtained for the same transfer charge if it had no feedback loop Reach higher levels. The change in voltage Vcol with and without the loop is shown in FIG. 4 by a solid curve and a dashed curve, respectively. This configuration is advantageous at high illumination levels and makes it possible to avoid saturation of the reading electronic system. If the total illuminance of the sensor is lower, it may be necessary to disable the feedback loop during the stage of reading the storage node charge, for example by shorting capacitor C12 even outside the reinitialization stage. The operation may be executed. This operation may be determined by the user or as a function of automatic detection of the total illumination of the sensor. Alternatively, an operation determined by the user or automatic detection may be provided to change the gain of the amplifier. This may be done, for example, by selecting another capacitor C11 or C12 with a different value as a function of illumination.

By using the same principle, a feedback loop having a predetermined positive loop gain _GL is created by using two amplifiers each having a structure equivalent to that of the amplifier of FIG. 3, alternately connected in series. A positive loop gain _GL increases the charge / voltage conversion factor at the storage node of the pixel. For a given transfer charge amount, the voltage level at the storage node decreases more rapidly and at the end of the transfer, the level that would have been obtained for the same transfer charge amount without a feedback loop Reach a lower level. This configuration is advantageous at low illumination levels. If the total illuminance of the sensor is higher, it may be necessary to disable the feedback loop during the stage of reading the storage node charge, for example by shorting capacitor C12 even outside the reinitialization stage. An operation may be performed. This operation may be determined by the user or as a function of automatic detection of the total illumination of the sensor. Alternatively, an operation determined by the user or automatic detection may be provided to change the gain of one of the amplifiers. This may be done, for example, by selecting other values of capacitors associated with each of the amplifiers as a function of illumination.

  This invalidation or validation, or this gain change, can be obtained, for example, by means of external setting of the sensor (programming, control buttons, etc.) or alternatively in the measurement of the average brightness of the scene obtained at the sensor. Obtained on the basis.

  The feedback loop may also be prepared so that it can be enabled to have a positive loop gain or a negative loop gain G as a function of illumination. This selection of positive or negative gain may be obtained by setting means external to the sensor (programming, control buttons, selectors, etc.) or based on a measurement of the average brightness of the scene performed by the sensor May be obtained.

  At this time, such a sensor allows the user to obtain a gain most suitable for the illuminance of the scene intended to be captured, a negative gain when the illuminance is high, and a positive gain when it is low. It becomes possible to enable a feedback loop having

FIG. 5 shows a feedback loop according to the invention in which the loop gain _GL is set to a value that is a function of the voltage level provided by the column conductor during the stage of transferring the charge stored in the storage node. An improved embodiment is shown. In other words, the loop gain _GL is dependent on the illuminance received by the pixel. As a result, the usable dynamic range of the pixels towards the two ends is improved.

  In the embodiment of FIG. 5, a change in the behavior of the feedback loop is prepared to rely on the choice between a positive loop gain and a negative loop gain. However, the dependency as a function of column voltage depends on the choice between two positive gains or two negative gains with different values, or alternatively the choice between enabling or disabling the loop. Would be able to.

In FIG. 5, the feedback loop 100 comprises two amplifiers with the same structure and having a negative gain in series:
A first amplifier AMP1 having a negative gain G1, comprising on the input e1 a switch controlled by an input capacitor C11, a feedback capacitor C12 and an initialization signal RS _AMP1 ; The first amplifier AMP1, which receives the reference voltage V _{REF1 and} has a negative gain G1 = −C11 / C12.
A second amplifier AMP2 having a negative gain G2, comprising on the input e′1 a switch controlled by an input capacitor C21, a feedback capacitor C22 and an initialization signal RS _AMP2 , on the input e′2 , The second amplifier AMP2, which receives the second reference voltage V _REF2 and whose gain is G2 = −C21 / C22.

The column conductor COL is connected to the input e1 of the first amplifier by its input capacitor C11, and the output S1 of the first amplifier is connected to the input of the second amplifier by its input capacitor C21. The amplifier outputs S1 and S2 are applied to the input of the comparator COMP. The output of the comparator COMP controls a circuit SW for routing one or the other output S1 or S2 onto the output 102 of the feedback loop. Thus, depending on the controlled path selection for the pixel selected for reading, the output voltage S1 or S2 is obtained as the drain voltage V _REFP of the pixel follower transistor T3. In practice, this voltage is applied to the drains of the follower transistors of all the pixels in the column, the pixels selected for reading and the pixels not selected for reading.

  Thus, there is a different loop gain, negative gain G1 or positive gain G1 × G2 depending on whether the comparator switches in one direction or the other. This switching depends on the voltage level on the column conductor. This is because the state of the comparator depends on this level. For high illumination, the comparator routes signal S1 to the drain of the follower transistor and the loop gain G1 is negative. At this time, the charge / voltage conversion coefficient is low. Conversely, in the case of low illumination, it routes signal S2 to the drain of the follower transistor and the loop gain is G1G2. At this time, the charge / voltage conversion coefficient increases. During the phase of reinitializing the pixel, there is no loop gain and the voltage Vref2 is applied on the drain of the follower transistor.

The reference voltage V _REF2 of the amplifier AMP2 is selected to be higher than the voltage V _{REF1 of the} amplifier AMP1. In one example, V _REF2 is set to 3.3 volts and voltage V _REF1 is set to 3 volts. The comparator COMP is configured to apply the voltage V _REF2 at the output 102 of the feedback loop via the path selection means SW during the phase of initializing the storage node.

At this time, the outputs S1 and S2 change inversely with respect to each other as a function of the column voltage Vcol received at the input. This voltage decreases during the transfer of charge from the photodiode to the storage node:
S2 starts at V _REF2 and then decreases with a slope that is a function of the product of gains G1 and G2.
S1 starts with V _REF1 <V _REF2 and increases with a slope that is a function of gain G1.

Output S2 is applied during the initialization phase and continues to be applied in the case of low illumination levels. Voltage Vcol reaches the threshold voltage, thereby to value _{V B,} the outputs S1 and S2 intersect the output S1 is added. This switching value V _B of the comparator is fixed by the reference voltage and the respective gains of the amplifiers AMP1 and AMP2. In practice, it is equal to (V _REF2 −V _REF1 ) / (G1 + G1 × G2).

These reference voltages and gains G1, G2 are also selected so that the loop output 102 provides a drain voltage V _REFP that ensures that the follower transistor T3 is always biased to saturation (follower mode).

In practice, G1 and G2 are selected such that the product G _f × G1 is close to −1 and G _f × G1 _× G2 is greater than 1 and preferably less than 3. Ideally, it is about 2 to 2.5. In conventional MOS transistor technology, the follower transistor gain _Gf is approximately 0.8 or 0.9.

  Next, with reference to the time diagrams of FIGS. 6 and 7, the manner in which pixels are read using such a loop with a loop gain that varies as a function of illumination is described. FIG. 6 shows the case of reading a small charge collected pixel corresponding to a low illumination level, and FIG. 7 shows the reading of a large charge collected pixel corresponding to a high illumination level.

  As can be seen in these time diagrams, the feedback loop operates during or after the transfer of charge into the collection storage node.

Before this, there is first a step of reinitializing the storage node NS of the pixels, which is performed by the signal RS _NS . During this phase, the two amplifiers AMP1 and AMP2 are each initialized as described with reference to FIG. 3, so that the reference voltage V _REF1 appears at the output S1 and the reference voltage at the output S2. V _REF2 appears. In practice, as shown, the duration of each of the initialization signals RS _NS , RS _AMP1 , RS _AMP2 is the stabilization of the voltage at the storage node, then the stabilization of the output S1, and then the output S2 Stipulated to obtain the stabilization of As explained above, it is the output S2 that is switched to the loop output 102 during this stage. Therefore, the reinitialization level of the storage node is set to voltage V _REF2 . The voltage Vcol, which is its replica on the column conductor, is set to substantially this same level (within the threshold voltage _{Vth of the} follower transistor).

  Note that during the reinitialization phase, the reinitialization voltage Vref2 could be applied to the storage node without passing through the amplifier. Note also that the reinitialization transistor T2 could be connected as a diode whose gate is not controlled by the reinitialization signal. The reinitialization is performed as a result of applying a voltage Vref2 to the drain of this transistor connected as a diode.

Next, during the phase of transferring charge into the storage node, performed by the signal TRA, the (negative) charge decreases the voltage on the storage node and thus the voltage Vcol. Since the loop gain is positive, the output voltage S2, and thus the drain voltage V _REFP , decreases more rapidly than the voltage on the storage node NS, and hence the voltage Vcol on the column conductor, and the conversion factor increases.

In the case of a low illumination level, a small amount of electrons is transferred. Even having an increased conversion coefficient, voltage Vcol does not reach the threshold _{V B} switching of the comparator COMP, the voltage S2 applied as the drain voltage _{V REFP} throughout transfer phase. At the end of this transfer phase, the voltage Vcol stabilizes at a level significantly lower than the level at which it would be stabilized for the same amount of transfer charge in the absence of a feedback loop. This is illustrated in FIG. On the time diagram showing the change in voltage Vcol during pixel reading, the dashed curve shows the voltage level Vcol that would otherwise have been without the feedback loop according to the present invention, whereas the solid line This curve shows the change in the voltage level Vcol in the case of having a loop.

Since the transfer charge amount is small, the outputs S1 and S2 do not intersect. None reached the trip threshold V _B of the comparator. Throughout the sequence of reading the pixel, the voltage V _REFP remains fixed by the comparator output S2, and changes as it changes.

FIG. 7 shows, conversely, what happens when the amount of collected charge is high. As described with reference to FIGS. 3 and 4, the column voltage will decrease more slowly than without feedback, but because of the higher transfer charge, in this case the outputs 1 and S2 Will cross and cause the comparator to switch. The voltage V _REFP initially fixed by the output S2 at the beginning of the transfer phase then follows the output S1 and increases. The conversion factor is reduced and the voltage Vcol is prevented from reaching an excessively high voltage level.

In practice, we have seen that pixel reading generally involves two analog / digital conversions followed by a subtraction of the two resulting digital values. First conversion are those of the previous initialization level of charge transfer stages, rather than the loop gain, voltage Vcol corresponds to a reference voltage V _REF2. The second conversion is at the operational level after charge transfer and the loop gain varies as a function of illumination. The resulting voltage Vcol will depend on the actual conversion factor at the storage node at the end of the transfer phase and therefore as a function of G1 and G2 or alternatively G1 only.

  Thus, means are provided in the reading circuit for making the two transformations homogeneous. In particular, preparations are made for transmitting the signal coming from the comparator to the reading circuit.

  In the above description, the sensor operates using automatic switching between two values of the charge / voltage conversion factor, one corresponding to the highest illuminance and the other corresponding to the lowest illuminance, It was assumed to result as a result of using different loop gains. Alternatively, it would be possible to provide automatic control of switching between three or more transform coefficient values resulting from using three or more different gains.

Claims (10)

An image sensor comprising an active pixel comprising a pixel and a readout circuit, each pixel comprising at least one light sensitive element, a capacitive node (NS) for accumulation of charge generated by said light sensitive element, and A follower transistor (Tf), the gate (g) of the follower transistor (Tf) is connected to the storage node, and the source (s) of the follower transistor (Tf) is a column conductor (Col _i ) In an image sensor, a feedback loop is connected to a column conductor (Col _i ) itself connected to a reading circuit (ADC), and the drain (d) of the follower transistor (Tf) receives a supply voltage (V _REFP ). (100) is provided, and the loop is connected to the column conductor (COL). And having an output (102) connected to the drain of the follower transistor to provide the supply voltage of the follower transistor and to change the behavior of the feedback loop as a function of received illumination An image sensor is provided.   The image sensor of claim 1, wherein the behavior of the loop is changed by enabling or disabling the loop as a function of the received illuminance. 3. An image sensor according to claim 2, characterized in that the operation of the loop is changed by changing the gain ( _GL ) of the loop as a function of the received illuminance.   4. The image sensor according to claim 3, wherein the gain of the loop is changed between a positive value and a negative value.   The image sensor according to any one of claims 1 to 4, wherein the received illuminance used to change the behavior of the loop is the total illuminance received by the sensor. .   The image sensor according to claim 1, wherein the received illuminance used to change the behavior of the loop is illuminance received by the pixel.   The behavior of the loop is changed as a function of the voltage present on the column conductor when the charge on the storage node is read, the voltage representing the illuminance received by the pixel. The image sensor according to claim 6. During the charge transfer stage (TRA) after each pixel re-initializes the storage node (RS- _NS ), the charge collected by the photosensitive element of the pixel is stored in the capacitive storage node. 8. The image sensor according to claim 1, comprising a transfer transistor (T <b> 1) for transferring to (NS), wherein the feedback loop is during the step of reinitializing the storage node. An image sensor characterized in that it is disabled.   A first amplifier (AMP1), wherein the feedback loop (100) is a first amplifier (AMP1) having a negative gain (G1), connected to the column conductor at its input (e1); A second amplifier (AMP2) having a negative gain (G2), connected at its input (e′1) to the output (S1) of the first amplifier. A comparator (COMP) that receives the outputs (S1, S2) of the two amplifiers, wherein the output (S1) of the first amplifier or the output (S1) of the second amplifier ( A comparator (COMP) for providing a control signal (Sc) for path selection means (SW) for guiding any of S2) to the drain (d) of the follower transistor Characterized Rukoto, image sensor according to claim 1. The first amplifier has a first input (e1) connected to the column conductor by an input capacitor (C11), and a second input (e2) connected to a first reference voltage (V _REF1 ). A feedback capacitor (C12) and a switch for shorting the feedback capacitor during the initialization of the storage node, and the second amplifier is connected to the column conductor by an input capacitor (C21) The first input (e′1) connected, the second input (e′2) connected to the second reference voltage (V _REF2 ), the feedback capacitor (C22), and the storage node are initialized. The image sensor according to claim 9, further comprising a switch for short-circuiting the feedback capacitor during the converting step.

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