JP2016161753A - Video processing device, display device, and video processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video processing device that can efficiently execute a plurality of processes to video data, and have a simple circuit configuration, and a display device and a video processing method.SOLUTION: A video processing unit 2 of a projector 1 comprises: a DRAM22; a first processing unit that executes processing without accompanying writing into the DRAM22 with respect to video data to be input; and a second processing unit that executes image processing accompanying writing into the DRAM22 with respect to the video data. The video processing unit 2 further comprises a block transfer unit 28 that reads the video data from the DRAM22 to input the read video data to the first processing unit, and the second processing unit is configured to write the video data processed in the first processing unit into the DRAM22.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a video processing device, a display device, and a video processing method for processing video data.

  2. Description of the Related Art Conventionally, in an apparatus that displays a video, a function of stopping an image when adjusting image quality is known (see, for example, Patent Document 1). The device described in Patent Document 1 converts a video signal into digital data, writes it into a frame memory, reads out the frame data from the frame memory, and displays it. When the “image freeze” switch is operated, this apparatus stops writing to the frame memory and repeatedly reads out one frame from the frame memory and displays it, thereby making the display image stationary. In this way, the user performs an image quality adjustment operation while the display image is stationary. When an image quality adjustment operation is performed, the data read from the frame memory is processed by the image quality adjustment calculator and displayed.

Japanese Patent Laid-Open No. 2002-10281

The apparatus described in Patent Document 1 requires a frame memory in order to make an image stationary and perform image quality adjustment. As described above, the apparatus for processing video data has a problem that the frequency of access to the frame memory increases as the types of processing increase. For example, in order to perform a process of generating a single video by synthesizing a video whose image quality has been adjusted with another video, or a process for converting the frame rate, it is necessary to write the video whose image quality has been adjusted to the frame memory again. is there. In addition to this, if a separate frame memory is used only to freeze the image, the processing unit that accesses the frame memory and the required memory capacity increase, the circuit configuration becomes complicated, and the memory access bandwidth is increased. There is concern about the tightness.
The present invention has been made in view of the above-described circumstances, and is capable of efficiently performing a plurality of processes on video data and having a simple circuit configuration, a display apparatus, and a video process It aims to provide a method.

In order to achieve the above object, a video processing apparatus according to the present invention includes a memory, a first processing unit that executes processing that does not involve writing the input video data in the memory, and the video data. A second processing unit that performs image processing with writing to the memory, and a transfer unit that reads out the video data from the memory and inputs the video data to the first processing unit, and the second processing unit includes: The video data processed by the first processing unit is written in the memory.
According to the present invention, the video data is written in the memory using the function of the second processing unit, and the video data in the memory is input to the first processing unit, whereby the video data is repeatedly processed in the first processing unit. It can be carried out. Also, the video can be stopped by displaying the video data written in the memory. The video displayed during the stop can reflect the processing of the first processing unit. Therefore, a plurality of processes can be efficiently performed on video data without complicating the circuit configuration.

In the video processing apparatus according to the present invention, the second processing unit can write the video data processed by the first processing unit into the memory without performing the image processing. Features.
According to the present invention, video data can be written into a memory whether or not image processing is performed on the video data.

In the video processing device according to the present invention, the second processing unit writes the video data to the memory when the first processing unit performs processing on the video data. And
According to the present invention, the operation can be stopped when access to the memory is unnecessary, such as when the first processing unit does not process the video data, the processing can be made efficient, and the power consumption can be reduced.

In the video processing apparatus according to the present invention, the video processing device further includes a third processing unit that processes the video data, and the second processing unit writes the video data input from the first processing unit to the memory. An operation of outputting the video data input from the first processing unit to the third processing unit can be executed.
According to the present invention, the video data processed by the first processing unit can be output from the second processing unit to another processing unit without using a memory. As a result, the types of processing for video data can be increased without increasing the frequency of memory access.

Further, the present invention is the video processing apparatus, wherein the third processing unit acquires and outputs the video data output by the second processing unit, and reads and outputs the video data in the memory Performing the operation to perform.
According to the present invention, when the second processing unit outputs video data, the video data is output from the third processing unit, and when the second processing unit does not output video data, the video data in the memory is subjected to the third processing. Can be output from the department. For this reason, the second processing unit can be stopped while continuing the output of the video data, so that the processing efficiency can be improved and the power consumption can be reduced.

In the video processing apparatus according to the present invention, the third processing unit is connected to a display unit that displays an image, and outputs the video data to the display unit.
According to the present invention, the video data output from the second processing unit and the video data written in the memory can be output to the display unit for display.

In the video processing apparatus according to the present invention, the video processing device further includes an input processing unit that outputs the video data to the first processing unit, and the input video data is processed by the first processing unit and the second processing unit. The first operation mode to be output and the second operation mode in which the video data to be written to the memory by the second processing unit is read from the memory and output. When switching from the first operation mode to the second operation mode, the input of the first processing unit is switched from the video data output by the input processing unit to the video data output by the transfer unit. To do.
According to the present invention, when the operation mode is switched, the operation mode can be quickly switched in a simple circuit configuration by switching the flow of data including the input of the first processing unit.

Further, the present invention is characterized in that, in the video processing apparatus, when the first and second operation modes are switched, the operation of the first processing unit is switched and the operation of the second processing unit is switched. And
According to the present invention, operation modes of a plurality of processing units can be quickly switched.

In the video processing device according to the present invention, the video processing device further includes a plurality of first processing units, and the second processing unit writes the video data input from each of the plurality of first processing units to the memory. The processing is performed.
According to the present invention, by providing a plurality of paths for processing video data, it is possible to efficiently process input video data and video data read from the memory by the transfer unit.

In the video processing apparatus according to the present invention, the transfer unit inputs the video data read from the memory to the first processing unit to which the video data to be processed is not input. .
According to the present invention, the input video data and the video data read from the memory by the transfer unit can be efficiently processed by a plurality of paths for processing the video data.

In order to achieve the above object, a display device according to the present invention includes a memory, a first processing unit that executes processing that does not involve writing the input video data into the memory, and the video data. On the other hand, a second processing unit that performs image processing with writing to the memory, and a transfer unit that reads the video data from the memory and inputs the video data to the first processing unit, A video processing unit that writes the video data processed by the first processing unit to the memory, and a display unit that displays video based on the video data processed by the video processing unit. .
According to the present invention, the video data is written in the memory using the function of the second processing unit, and the video data in the memory is input to the first processing unit, whereby the video data is repeatedly processed in the first processing unit. It can be carried out. In addition, the video data written in the memory can be output to the display unit, the video displayed on the display unit can be stopped, and the processing of the first processing unit can be reflected on the video displayed during the stop. Therefore, a plurality of processes can be efficiently performed on video data without complicating the circuit configuration.

In order to achieve the above object, the video processing method of the present invention controls a device having a memory in which video data can be written, and the first processing unit transfers the input video data to the memory. The video data processed by the first processing unit is written to the memory by a second processing unit that executes processing without writing the image and performs image processing with writing to the memory on the video data. The video data is read from the memory and input to the first processing unit.
According to the present invention, the processing of the first processing unit can be repeatedly performed on video data, and the video to be displayed can be stopped by displaying the video data written in the memory. Furthermore, the process of the first processing unit can be reflected in the video displayed during the stop. Therefore, a plurality of processes can be efficiently performed on video data without complicating the circuit configuration.

1 is a functional block diagram of a projector according to a first embodiment. The functional block diagram of the image processing part with which a projector is provided. Explanatory drawing of the function of a video processing part. The flowchart which shows operation | movement of a projector. The flowchart which shows operation | movement of a projector. The flowchart which shows operation | movement of a projector. The flowchart which shows operation | movement of a projector. The flowchart which shows operation | movement of a projector. The flowchart which shows operation | movement of a projector. The flowchart which shows operation | movement of a projector. Explanatory drawing of operation | movement of a video processing part. Explanatory drawing of operation | movement of a video processing part. The timing chart which shows operation | movement of a projector. Explanatory drawing of operation | movement of the professional 7 projector of 2nd Embodiment. Explanatory drawing of operation | movement of the projector of 2nd Embodiment. Explanatory drawing of operation | movement of the projector of 3rd Embodiment.

[First Embodiment]
Embodiments to which the present invention is applied will be described below with reference to the drawings.
FIG. 1 is a functional block diagram of a projector 1 according to a first embodiment to which the present invention is applied, and shows various peripheral devices connected to the projector 1 together.
The projector 1 as a display device includes an interface (I / F) unit 11 for connecting a video supply device 3 that outputs video data. A plurality of video supply devices 3 can be connected to the interface unit 11, and FIG. 1 shows an example in which two video supply devices 3 are connected.

  Examples of the video supply device 3 include a video playback device such as a DVD player, a broadcast receiving device such as a digital TV tuner, and a video output device such as a video game machine and a personal computer. The video supply device 3 may be a communication device that communicates with a personal computer or the like to receive video data. The video supply device 3 is not limited to a device that outputs digital video data, and may be a device that outputs an analog video signal. In this case, an analog / digital conversion device that generates digital video data from an analog video signal may be provided on the output side of the video supply device 3 or the interface unit 11 of the projector 1. The specific specifications and number of connectors and interface circuits included in the interface unit 11 are arbitrary.

  The video supply device 3 outputs digital video data in a data format that can be supported by the interface unit 11. The data format specifically includes resolution, frame rate, number of gradations (number of colors), color space, transfer rate, and the like. The projector 1 can operate even when still image data is input from the video supply device 3. In this case, the data output from the video supply device 3 has a form in which a plurality of frames are continuous at the same frame rate as the data format of the video data, and the images of the frames are the same image. That is, the data input from the video supply device 3 to the projector 1 may be a still image or a video (moving image) as long as the data format is compatible with the interface unit 11. In the following description, data input from the video supply device 3 to the projector 1 is referred to as video data.

  The projector 1 includes a control unit 10 that controls each unit of the projector 1 and an image forming unit 12 that displays (projects) video based on video data input to the interface unit 11 on a screen SC. The interface unit 11 is connected to a video processing unit 2 (video processing device) that processes video data and outputs a video signal for display to the image forming unit 12.

The image forming unit 12 (display unit) includes a light source 13, a modulation unit 14, a projection optical system 15, a light source control unit 16, and a display drive unit 17.
The light source 13 includes lamps such as a xenon lamp and an ultrahigh pressure mercury lamp, or a solid light source such as an LED and a laser light source. The light source 13 is turned on by the electric power supplied from the light source control unit 16 and emits light toward the modulation unit 14. The light source control unit 16 can adjust the light emission luminance of the light source 13 according to the control of the control unit 10.

The modulation unit 14 modulates the light emitted from the light source 13 to generate image light, and irradiates the projection optical system 15 with the image light. In the present embodiment, the modulation unit 14 includes three liquid crystal light valves corresponding to each color of red (R), green (G), and blue (B), and the light emitted from the light source 13 is used as the liquid crystal light valve. The structure which permeate | transmits is illustrated.
A display driving unit 17 is connected to the three liquid crystal light valves of the modulation unit 14. The display driving unit 17 drives each pixel of the liquid crystal light valve based on the video signal output from the video processing unit 2 and draws an image on the liquid crystal light valve in units of frames (screens).

  The optical path between the light source 13 and the modulation unit 14 or the modulation unit 14 may be provided with a reflector, a lens group, a polarizing plate, a light control element, and the like (all not shown). Further, the modulation unit 14 may be configured to use a reflective liquid crystal panel. In this case, the modulator 14 reflects the light emitted from the light source 13 to the liquid crystal panel and guides the reflected light to the projection optical system 15. Further, the modulation unit 14 may be configured using a digital mirror device (DMD), and may be configured including one DMD and a color wheel.

  The projection optical system 15 guides the image light modulated by the modulation unit 14 toward the screen SC and forms an image on the screen SC. For example, the projection optical system 15 may include a prism that synthesizes light that has passed through three liquid crystal light valves, a lens group that guides image light, and an optical element such as a mirror. Furthermore, the projection optical system 15 includes a zoom lens for enlarging / reducing the image on the screen SC, a focus lens for adjusting the focus, a zoom adjusting motor for adjusting the zoom level, a focus adjusting motor for adjusting the focus, and the like. May be.

  The video processing unit 2 executes processing to be described later, such as color tone correction, on the video data input to the interface unit 11 under the control of the control unit 10. The video data processed by the video processing unit 2 is converted into a video signal for each frame and input to the display driving unit 17.

  The control unit 10 includes a processor that controls each unit of the projector 1, and includes, for example, a CPU 10a, a ROM 10b, and a RAM 10c. . The control unit 10 may execute a program stored in a connected nonvolatile storage unit (not shown). Further, the control unit 10 is not limited to a configuration that controls the projector 1 by software, and may be configured by hardware such as an ASIC (Application Specific Integrated Circuit).

The control unit 10 controls execution timing, execution conditions, and the like of processing executed by the video processing unit 2. The control unit 10 also controls the light source control unit 16 of the image forming unit 12 to adjust the luminance of the light source 13 and the like.
The control unit 10 is connected to an operation unit 18 that receives user input operations. The operation unit 18 can be configured as an infrared light receiving unit that receives a signal from an operation panel including a switch or a remote control device (not shown). The projector 1 is not limited to the configuration including the operation unit 18, and the operation unit 18 may be externally connected to the projector 1. Further, the projector 1 may process control data transmitted from an external personal computer in the same manner as the operation on the operation unit 18. In this case, the projector 1 may include a communication unit that communicates with an external device such as a personal computer.

  The control unit 10 is connected to a position detection unit 19 that detects an operation by the indicator 5. The indicator 5 has, for example, a pen-shaped main body, and is used by the user with the hand. The position detector 19 detects a position indicated by the indicator 5 for a predetermined position detection range on the screen SC. When the user indicates an arbitrary position on the screen SC with the indicator 5, the position detector 19 detects the indicated position and outputs coordinate data indicating the indicated position to the controller 10. The position detection range in which the position detection unit 19 can detect the designated position is set, for example, to a range including a display area where the projection optical system 15 projects an image. As a specific method for the position detection unit 19 to detect the indication position of the indicator 5, for example, a method in which the position detection unit 19 includes an image sensor and detects an image of the indicator 5 from the captured image data can be used. In this case, instead of the indicator 5, for example, a user's finger can be used as the indicator. Further, for example, there is a method in which the indicator 5 includes a light emitting unit that emits infrared light, visible light, ultraviolet light, and the like, and the position detection unit 19 detects light emission of the indicator 5. Of course, other methods can be used.

FIG. 2 is a functional block diagram showing in detail the video processing unit 2 provided in the projector 1.
The video processing unit 2 includes an input processing unit 21 to which video data is input from the interface unit 11, various processing units that process video data input to the input processing unit 21, and a memory that stores the processed video data. Prepare. The specific specification of the memory included in the video processing unit 2 is not particularly limited, and may be a volatile memory or a nonvolatile memory.
In the present embodiment, a configuration will be described in which the video processing unit 2 includes a DRAM 22 as a memory for storing video data, and a DRAM controller 23 that controls writing and reading of video data to and from the DRAM 22 is connected to the DRAM 22. The DRAM 22 also functions as a so-called frame memory and stores video data in units of frames. The DRAM 22 can also store a frame of video data and control data related to this frame in association with each other.

The DRAM controller 23 is connected to each of a two-screen control unit 24, an OSD processing unit 25, a rate conversion unit 26, and a block transfer unit 28 as processing units provided in the video processing unit 2. The DRAM controller 23 performs arbitration according to the memory write request and the memory read request of each processing unit, and controls writing (writing) and reading (reading) with respect to the DRAM 22.
The video processing unit 2 can be mounted as, for example, one ASIC, and the DRAM 22 may be built in the ASIC, or the DRAM 22 may be externally connected to the ASIC.

  A main video path 30 and a sub video path 40 are connected to the input processing unit 21 in parallel. The main video path 30 includes a video input unit 31, a scaler 32, and a color correction unit 33, and the color correction unit 33 is connected to the two-screen control unit 24. The sub-video path 40 includes a video input unit 41, a scaler 42, and a color correction unit 43, and the color correction unit 43 is connected to the two-screen control unit 24.

The input processing unit 21 outputs the video data input from the interface unit 11 to the main video path 30 and / or the sub video path 40. Of the main video path 30 and the sub video path 40, the output destination to which the input processing unit 21 outputs video data is set by the control of the control unit 10 (FIG. 1).
The input processing unit 21 may perform processing on the video data input from the interface unit 11 and output the processed video data to the main video path 30 and / or the sub video path 40. The processing executed by the input processing unit 21 is, for example, noise removal processing, conversion processing of 2D (planar) video data to 3D (stereoscopic) video data, intermediate frame generation (frame interpolation) processing, sharpening processing, and the like. Can do. Further, the input processing unit 21 may perform keystone (trapezoidal distortion) correction processing.

  The video input unit 31 included in the main video path 30 acquires the video data input from the input processing unit 21 and outputs the video data to the scaler 32.

  The scaler 32 executes resolution conversion processing for enlarging or reducing the frame of the video data output from the video input unit 31. Further, the scaler 32 may be configured to perform a sharpening process such as a super-resolution process when increasing the resolution. The scaler 32 matches the timing of the resolution conversion processing with the timing at which the video input unit 31 outputs the video data, and outputs the video data whose resolution has been converted to the color correction unit 33 without writing the video data to the DRAM 22.

  The color correction unit 33 performs color correction processing on the video data. This color correction processing includes, for example, gamma correction processing of video data, processing for correcting color characteristics, and the like. In these processes, for example, the control unit 10 calculates a correction parameter and sets it in the color correction unit 33 according to an adjustment value or a target value input by the user by operating the operation unit 18 (FIG. 1), and performs color correction. The unit 33 performs correction based on parameters set by the control unit 10.

Similar to the video input unit 31, the video input unit 41 acquires the video data input from the input processing unit 21 and outputs it to the scaler 42.
The scaler 42 is configured similarly to the scaler 32. The scaler 42 performs resolution conversion processing on the video data output from the video input unit 41, and outputs the processed video data to the color correction unit 43. Similar to the color correction unit 33, the color correction unit 43 executes color correction processing on the video data under the control of the control unit 10.

  It can be said that the video input unit 31 and the color correction unit 33 included in the main video path 30 and the video input unit 41 and the color correction unit 43 included in the sub-video path 40 respectively correspond to the first processing unit of the present invention. . The main video path 30 may be considered as one processing unit and may be the first processing unit of the present invention, and the sub-video path 40 may be considered as one processing unit and may be the first processing unit of the present invention.

  The two-screen control unit 24 executes a two-screen generation process according to the control of the control unit 10. In the two-screen generation process, the two-screen control unit 24 combines the two video data input from each of the main video path 30 and the sub-video path 40 to generate composite video data. The two-screen control unit 24 can output the composite video data generated by the two-screen generation process to the DRAM controller 23 and write it to the DRAM 22. The two-screen control unit 24 writes at least one of the video data to the DRAM 22 in order to adjust the timing of the video data input from the main video path 30 and the video data input from the sub-video path 40 in the two-screen generation process. But you can. Further, the two-screen control unit 24 can perform an operation of outputting the composite video data to the OSD processing unit 25.

The two-screen control unit 24 outputs the video data input from the main video path 30 or the sub-video path 40 to the DRAM controller 23 without writing the above-described composite video data, and writes it to the DRAM 22. be able to. The video data can also be output to the OSD processing unit 25.
The operation of the two-screen control unit 24 is controlled by the control unit 10. That is, whether or not the two-screen control unit 24 executes the two-screen generation process is controlled by the control unit 10. Also, the control unit 10 controls whether the two-screen control unit 24 writes the video data to the DRAM 22 and outputs it to the OSD processing unit 25.

  The OSD processing unit 25 performs a process of superimposing an OSD image on the composite video data or video data input from the two-screen control unit 24.

Here, operations of the two-screen control unit 24 and the OSD processing unit 25 will be described in detail.
FIG. 3 is an explanatory diagram of the operation of the projector 1, FIG. 3A shows one aspect of the composite video data generated by the two-screen control unit 24, and FIG. 3B shows another aspect of the composite video data. Indicates. FIG. 3C shows an example of an image superimposed by the OSD processing unit 25.

  In the two-screen generation process described above, the two-screen control unit 24 generates one composite video data by combining the frames of the video data output from the main video path 30 and the sub-video path 40. The composite video data generated by the two-screen control unit 24 is projected onto the screen SC as shown in FIGS. 3A and 3B, for example. Here, the video data output from the main video path 30 is referred to as main video data, and the video data output from the sub video path 40 is referred to as sub video data.

The example of FIG. 3A is a so-called picture-in-picture form. In this example, the main video V1 based on the main video data is displayed in the display area VA of the screen SC, and the sub video V2 based on the sub video data is arranged so as to overlap a part of the main video V1. The size of the main video V1 is substantially equal to the entire display area VA, and the size of the sub-video V2 is smaller than the main video V1.
The example in FIG. 3B is a so-called split screen. In this example, the main video V1 and the sub video V2 are arranged in the same size. Since both the main video V1 and the sub video V2 are reduced to a size smaller than the display area VA while maintaining the aspect ratio, there are black strip-like non-display areas above and below the display area VA.

  When combining video data with picture-in-picture, the two-screen control unit 24 acquires a frame of sub-video data output from the sub-video path 40 and writes the acquired frame to the DRAM 22. Here, the two-screen control unit 24 arranges the acquired frame at the size specified by the control unit 10 and the specified position, and sets it as a frame corresponding to the display area VA. The two-screen control unit 24 executes processing for acquiring a frame of main video data output from the main video path 30 and processing for acquiring a frame of sub-video data from the DRAM 22. In this process, the two-screen control unit 24 superimposes the frame of the sub-video data on the frame of the main video data and synthesizes it to generate the frame of the composite video data shown in FIG.

When synthesizing video data on a split screen, the two-screen control unit 24 writes the main video data frame output from the main video path 30 and the sub video data frame output from the sub video path 40 to the DRAM 22.
At this time, the frames of the main video data and the sub video data are both reduced and written in the designated positions of the main video data area and the sub video area in the DRAM 22. In this method, main video data and sub-video data are reduced when written to the DRAM 22 and are combined in the DRAM 22. The frames of the main video data and the sub video data may be written from the beginning of the main video data area and the sub video data area after being reduced. The two-screen control unit 24 reads the once written main video data frame and sub-video data frame, and generates composite video data to which a non-display area is added.

  In the process of combining video data with a split screen, a method of combining main video data frames and sub-video data frames into the DRAM 22 and reading out from the DRAM 22 may be used. In this case, the two-screen control unit 24 does not reduce or only reduces the main video data frame output from the main video path 30 and the sub video data frame output from the sub video path 40 to the DRAM 22. Write. At this time, the two-screen control unit 24 may write the frame of the main video data into the area of the DRAM 22 for main video data from the head, and the frame of the sub video data is similarly headed in the area of the DRAM 22 for sub video data. You may write from. The two-screen control unit 24 reads out the frames of the main video data and the sub-video data from the DRAM 22 and combines them at a timing according to the size and arrangement when combining in the split screen format.

Therefore, the two-screen control unit 24 executes writing and reading to the DRAM 22 when generating the composite video data of FIGS. 3A and 3B.
The main video path 30 outputs main video data, and the sub video path 40 outputs sub video data. For example, the main video path 30 alternates between main video data frames and sub video data frames. Can also be output. In this case, the data output from the main video path 30 is added with identification data indicating whether it is main video data or sub-video data to the frame of the video data, and the two-screen control unit 24 based on this identification data. Writing to and reading from the DRAM 22 and generation of composite video data are performed.

Further, the two-screen control unit 24 acquires the frame of the video data output from either the main video path 30 or the sub-video path 40, and performs the process of generating the composite video data to the OSD processing unit 25. It can also be output. In this case, the two-screen control unit 24 may write the acquired frame of video data in the DRAM 22 or may output the frame to the OSD processing unit 25 without writing the frame in the DRAM 22.
The operations of these two-screen control units 24 are controlled by the control unit 10.

  The OSD processing unit 25 reads an OSD (On Screen Display) image such as a menu image for operating and setting the projector 1 from the DRAM 22 and superimposes it on a frame of video data output from the two-screen control unit 24. The OSD processing unit 25 synthesizes the OSD image on the DRAM 22 by α (alpha) blending without changing the size, display position, resolution, etc. of the frame output by the two-screen control unit 24.

The OSD image that the OSD processing unit 25 reads out from the DRAM 22 and is superimposed is an image that is written in the DRAM 22 under the control of the control unit 10. The control unit 10 reads out the OSD image data stored in advance in the ROM 10 b or a storage unit (not shown) according to the operation of the operation unit 18, and writes it in the DRAM 22. The control unit 10 may generate OSD image data by calculation in accordance with the operation of the operation unit 18 and write the OSD image data in the DRAM 22. The OSD image data superimposed by the OSD processing unit 25 uses an index (palette) format, and can have a smaller number of colors than the number of colors (the number of gradations) that can be displayed by the video processing unit 2.
The OSD processing unit 25 reads out the OSD image data from the DRAM 22 in accordance with the output timing of the frame data output from the two-screen control unit 24, and α-blends and outputs the frame data and the OSD image data.

  In addition, when the operation of the indicator 5 is detected by the position detection unit 19, the control unit 10 can draw an image corresponding to the indication position of the indicator 5 and write the drawn image data in the DRAM 22. For example, the control unit 10 draws a geometric figure whose apex is the position indicated by the indicator 5 or a straight line or curved image along the locus of the indication position of the indicator 5. The image data drawn by the control unit 10 and written to the DRAM 22 is stored in the DRAM 22 in the same manner as the OSD image data. Therefore, this image data is superimposed on the frame of the video data by the OSD processing unit 25, like the OSD image.

FIG. 3C shows an example of a projected image on the screen SC when the image drawn by the control unit 10 is superimposed. In the display area VA, a drawn image V3 composed of a curve drawn along the locus of the indicator 5 is displayed. In the example of FIG. 3C, there is no video in the background of the drawing image V3, but the drawing image V3 can be superimposed on the video processed by the main video path 30 or the sub video path 40.
The control unit 10 draws an image, and the OSD processing unit 25 performs a process of superimposing the drawn image on the video, whereby the drawing operation by the indicator 5 can be performed.

  The rate conversion unit 26 converts the frame rate of the video data output from the OSD processing unit 25 when the liquid crystal light valve of the modulation unit 14 is driven at double speed or quadruple speed. For example, when the video data input to the video processing unit 2 is 60 fps and the liquid crystal light valve is driven at a quadruple speed, the rate conversion unit 26 outputs 240 fps video data to the panel correction unit 27. Therefore, the rate conversion unit 26 writes the frame output from the OSD processing unit 25 to the DRAM 22, reads this frame in accordance with the converted frame rate, and outputs it to the panel correction unit 27. Even if the modulation unit 14 does not include a liquid crystal light valve, the rate conversion unit 26 may perform frame rate conversion.

  The panel correction unit 27 corrects the video data in accordance with the voltage-transmittance characteristic (VT characteristic) of the liquid crystal light valve included in the modulation unit 14 and the color unevenness characteristic of the individual liquid crystal light valve. The panel correction unit 27 performs correction using, for example, a gamma correction LUT (LookUp Table) or a color unevenness correction LUT. The panel correction unit 27 outputs a video signal for displaying the corrected frame data to the display driving unit 17 (FIG. 1) of the image forming unit 12.

  The video processing unit 2 includes a block transfer unit 28 (transfer unit). The block transfer unit 28 is connected to the DRAM controller 23 and can read frame data stored in the DRAM 22. The block transfer unit 28 inputs the read data to the video input unit 31 or the video input unit 41. The block transfer unit 28 generates a video frame control signal such as a vertical synchronization signal (VSYNC) or a horizontal synchronization signal (HSYNC) corresponding to the frame data, and matches the timing with the frame data to generate the video input unit 31 or Input to the video input unit 41.

  The projector 1 has a pause function for stopping the display video in accordance with the operation of the operation unit 18. During execution of the pause function, the same frame is continuously projected on the screen SC. When executing the pause function, the control unit 10 controls the video processing unit 2 and causes the rate conversion unit 26 to read and output the frame data. That is, when the pause function is instructed by the operation of the operation unit 18, the control unit 10 controls the rate conversion unit 26 so as to read and output the frame data stored in the DRAM 22. . In this case, the rate conversion unit 26 does not write to the DRAM 22, but reads the frame data written by the rate conversion unit 26 to the DRAM 22 before that, or the data written by the two-screen control unit 24 or the like. Therefore, the rate conversion unit 26 continuously outputs the same frame data to the panel correction unit 27. For this reason, an image of the same frame is displayed on the screen SC.

While the pause function is being executed, the video displayed on the screen SC stops, which is suitable when the user adjusts the color of the video. The user confirms the color of the video while viewing the image on the screen SC, performs an operation on the operation unit 18 and designates the content of the color correction. Based on the user's operation, the control unit 10 determines conditions such as parameters for color correction performed by the color correction units 33 and 43 and updates the operation settings of the color correction units 33 and 43.
When the control unit 10 updates the settings for the color correction units 33 and 43, it is preferable to correct the video data based on the updated settings and project a video based on the corrected video data onto the screen SC. Therefore, as will be described later, the control unit 10 updates the frame data stored in the DRAM 22 with the frame data corrected after the setting change during execution of the temporary stop function.

  When the frame data written in the DRAM 22 is updated during the execution of the temporary stop function, the rate conversion unit 26 reads the updated data from the DRAM 22. That is, the video displayed on the screen SC can be updated even when the pause function is being executed. In this case, since the rate conversion unit 26 does not change the operation, the frame data of the DRAM 22 is read and output at a preset frame rate (for example, 120 fps of double speed driving). Therefore, even if the frame data is updated during the pause function, the display can be continued at the set frame rate.

FIG. 4 is a flowchart showing the operation of the projector 1, and shows the operation of the video processing unit 2. 5 to 10 are flowcharts showing in detail the operation of each step shown in FIG.
The operation shown in FIG. 4 is executed in an operation mode (user adjustment mode) in which the user performs color adjustment and the like, not in a normal display mode in which an image based on the image data output from the image processing unit 2 is projected onto the screen SC. . Therefore, prior to the operation of FIG. 4, the control unit 10 shifts to the user adjustment mode in accordance with the operation of the user's remote controller or the like.

When execution of the pause function is instructed by a user operation, the control unit 10 controls each unit of the video processing unit 2 and starts the pause function (step ST1). The state in which the user adjustment mode or the pause function is executed corresponds to the second operation mode. The normal display mode corresponds to the first operation mode.
The controller 10 executes a one-frame memory write process (step ST2). The one-frame memory write process in step ST2 is a process for writing one frame of data to be displayed during the stop to the DRAM 22 in order to pause the video.

FIG. 5 shows a one-frame memory write process.
The control unit 10 changes the operation setting of the processing unit of the video processing unit 2 (step ST21). The video processing unit 2 includes a register (not shown) that stores operation settings of the processing units of the two-screen control unit 24, the OSD processing unit 25, the rate conversion unit 26, the main video path 30, and the sub video path 40. . The control unit 10 changes the operation setting by rewriting the setting value of the register. In step ST21, the operations of the scalers 32 and 42 are turned off, and the color correction processing and intermediate frame generation operations of the color correction units 33 and 43 are set off. The frames displayed during the pause are preferably processed in the same order as the normal display, and the video output from the video processing unit 2 is preferably written to the DRAM 22 as much as possible. Therefore, the control unit 10 turns off operations for changing the content of the video, such as resolution conversion, color correction, and intermediate frame generation, by the main video path 30 and the sub video path 40.

In step ST21, the control unit 10 turns on the writing to the DRAM 22 of the two-screen control unit 24 and sets the output to the OSD processing unit 25 of the two-screen control unit 24 to off. Further, the rate converter 26 repeatedly reads out the frame data from the DRAM 22 and outputs the data to the panel corrector 27 (repeat output).
As a result, the two-screen control unit 24 can write one frame of data into the DRAM 22. Furthermore, since the output from the two-screen control unit 24 to the OSD processing unit 25 is stopped and the rate conversion unit 26 does not write to the DRAM 22, the data in the DRAM 22 is prevented from being updated unintentionally.

Subsequently, the control unit 10 performs an update process (step ST22).
FIG. 10 is a flowchart showing the update process. The update process is an operation for reflecting the change when the control unit 10 changes the setting of each unit of the video processing unit 2. Specifically, the control unit 10 updates the value of an update register (not shown) included in the video processing unit 2 (step ST81), waits for completion of the update (step ST82; NO), and performs this processing when the update is completed. Is terminated (step ST82; YES). The update register included in the video processing unit 2 is a register that holds a value indicating whether the setting is updated.

When the one-frame memory write process of FIG. 5 is completed and the value of the update register is updated, the operation of each part of the video processing unit 2 is switched in synchronization with VSYNC, and the video input to the input processing unit 21 is one frame. Only written to the DRAM 22.
That is, the control unit 10 rewrites the value of the update register to 1 in step ST81 for the processing unit whose setting has been changed. The processing unit whose update register is rewritten to 1 switches its operation in synchronization with the next VSYNC, and the value of the update register is rewritten to 0 along with this switching. Therefore, in step ST82, the control unit 10 can detect that the operation of the processing unit has been switched with reference to the value of the update register.

Subsequently, the control unit 10 executes a one-frame advance display process (step ST3).
FIG. 6 shows a one-frame advance display process.
In this one-frame advance display process, the frame data written to the DRAM 22 in the one-frame memory write process in step ST2 is displayed. Since the output of the two-screen control unit 24 is turned off in step ST2, the video data written in the DRAM 22 in step ST2 is not displayed on the screen SC. Therefore, an image based on one frame of video data is displayed by the operation of FIG.
Thus, when the video is stopped by the pause function, it is possible to prevent a change in the video of one frame from occurring first and causing a sense of incongruity.

  The control unit 10 rewrites the register value and changes the setting regarding the operation setting of the processing unit of the video processing unit 2 (step ST31). In step ST31, the control unit 10 switches the video data input of the video input unit 31 to the block transfer unit 28 side. Also, the resolution conversion operation of the scaler 32 is turned on, and the color correction processing of the color correction units 33 and 43 is set to on. As a result, the frame data stored in the DRAM 22 can be input to the main video path 30, and the frame data can be processed in the main video path 30 and output to the two-screen control unit 24. In the present embodiment, since the block transfer unit 28 does not input video data to the sub-video path 40, the control unit 10 does not need to change the setting related to the sub-video path 40 in step ST31. In step ST31, the intermediate frame generation operation is set to be off. This is because it is not necessary to generate an intermediate frame when the video is stopped.

Further, in step ST31, the control unit 10 turns off the writing to the DRAM 22 of the two-screen control unit 24 and sets the output to the OSD processing unit 25 of the two-screen control unit 24 to be on. Further, the repeat output of the rate conversion unit 26 is set to OFF.
When this setting is reflected, the two-screen control unit 24 outputs the video data output from the main video path 30 to the OSD processing unit 25 and updates the frame data stored in the DRAM 22. Further, the rate conversion unit 26 writes the video data output from the OSD processing unit 25 to the DRAM 22, reads it at the set frame rate, and outputs it to the panel correction unit 27.
Here, since the two-screen control unit 24 outputs the video data output from the main video path 30 to the OSD processing unit 25 without being written in the DRAM 22, the main video data and the sub-video data are combined in a picture-in-picture. It becomes the same operation as the case.

  After setting the register in step ST31, the control unit 10 executes an update process (step ST32) to reflect the setting. This update process is as shown in FIG. Thereafter, the control unit 10 outputs a command for instructing reading and transfer of frame data of the DRAM 22 to the block transfer unit 28, and the frame data is transferred (step ST33). As a result, the frame data stored in the DRAM 22 is projected onto the screen SC through resolution conversion and color correction processing by the main video path 30.

When one frame is displayed in advance in step ST3 and the displayed video stops, the user can adjust the color by operating the remote controller. The control unit 10 performs user adjustment processing (step ST4).
FIG. 7 shows the user adjustment process.
In the user adjustment process, the control unit 10 stands by in a state of waiting for an operation of the remote controller or the like by the user (step ST41). When a user operation is performed and the operation unit 18 detects this operation, the control unit 10 changes the parameter corresponding to the user operation (step ST42). In step ST42, the control unit 10 determines parameters of the color correction units 33 and 43 based on the color adjustment value designated by the user's operation. When the color adjustment value is specified by specifying either the main video or the sub-video by the user's operation, the control unit 10 determines any parameter of the color correction unit 33 or the color correction unit 43.

  In step ST41, the control unit 10 may OSD display a menu image or the like for the user to perform color adjustment or the like. The control unit 10 writes the OSD image data to the DRAM 22, and the OSD processing unit 25 superimposes the OSD image on the frame of the video data output by the two-screen control unit 24 in the one-frame advance display process (step ST3). In this case, the OSD image may be changed by an operation by the user, and the control unit 10 writes new OSD image data in the DRAM 22.

  After the user adjustment process in step ST4, the control unit 10 executes a one-frame update display (step ST5). In the one-frame update display process, the control unit 10 updates the video displayed on the screen SC by reflecting the result of the user adjustment process in step ST4 in the one-frame video data.

FIG. 8 shows a one-frame update display process.
The control unit 10 changes the operation setting of each unit of the video processing unit 2 based on the user adjustment process of step ST4 (step ST51). In step ST51, the parameter determined and changed in step ST42 (FIG. 7) is written in a register (not shown) corresponding to the color correction unit 33 and / or the color correction unit 43. In step ST51, the control unit 10 sets whether or not the OSD image is superimposed by the OSD processing unit 25, and rewrites the register value. When the OSD image is updated in step ST42 or when the display of the OSD image is continued, the operation of the OSD processing unit 25 is set to ON. In addition, when the display of the OSD image is stopped in response to a user operation, the operation of the OSD processing unit 25 is turned off.

Subsequently, the control unit 10 executes an update process (step ST52). The update process in step ST52 is as shown in FIG. Thereafter, the control unit 10 outputs a command for instructing reading and transfer of the frame data of the DRAM 22 to the block transfer unit 28, and the frame data is transferred (step ST53). As a result, the frame data stored in the DRAM 22 is corrected according to the parameter changed in step ST52 and projected onto the screen SC. Further, when the OSD image of the DRAM 22 is updated, a video on which the updated OSD image is superimposed is displayed on the screen SC.
In this one-frame update display process, a frame that is the same as the frame displayed in the one-frame advance display process in step ST3 and whose color correction content has been changed by a user operation is displayed. For this reason, the user can easily confirm the effect of the color correction.

  In step ST52, if only the OSD image is changed without changing the parameters of the color correction unit 33 or the color correction unit 43, the block transfer unit 28 does not need to read frame data from the DRAM 22. In this case, the two-screen control unit 24 may read the frame data from the DRAM 22, output the frame data to the OSD processing unit 25, and perform a process of superimposing the OSD image on the OSD processing unit 25. Thereby, unnecessary circuit operation can be reduced and the power consumption can be reduced.

  The control unit 10 determines whether or not to end the adjustment based on the user operation or the like (step ST6). If the adjustment is not finished (step ST6; NO), the process returns to step ST4, and the color correction parameters and the like are changed based on the user's operation. When the adjustment is finished (step ST6; YES), the control unit 10 executes a normal display return process (step ST7) and finishes the operation.

FIG. 9 is a flowchart showing normal display return processing.
The control unit 10 rewrites the value of the register and changes the setting regarding the operation setting of the processing unit of the video processing unit 2 (step ST71). Specifically, the control unit 10 changes the setting to switch the video data input of the video input unit 31 to the input processing unit 21 side.

After setting the register in step ST71, the control unit 10 executes an update process (step ST72) to reflect the setting. This update process is as shown in FIG.
As a result, the main video data output from the input processing unit 21 to the main video path 30 is processed by the main video path 30, and after the processing of the two-screen control unit 24, OSD processing unit 25 and rate conversion unit 26, the panel correction unit. 27. In step ST71, the control unit 10 switches on the operation in which the color correction unit 33 generates the intermediate frame as necessary.

Here, the operation of the video processing unit 2 is shown by the flow of data between the processing units.
11 and 12 are explanatory diagrams showing the operation of the video processing unit 2. FIG. 11A shows the operation in the normal display mode, FIG. 11B shows the 1-frame memory write process, and FIG. Indicates one-frame advance display processing. 11 and 12, the output line from the block transfer unit 28 to the video input unit 41 is not shown.

  11 and 12, the output of main video data from the input processing unit 21 to the main video path 30 is output S1, and the output of main video data from the color correction unit 33 to the two-screen control unit 24 is output S2. Writing to the DRAM 22 by the two-screen control unit 24 is set as an output S3. Also, the output of the video data from the two-screen control unit 24 to the OSD processing unit 25 is set as output S5, the reading from the DRAM 22 by the OSD processing unit 25 is set as output S6, and the output from the OSD processing unit 25 to the rate conversion unit 26 The output is S7. Writing from the rate conversion unit 26 to the DRAM 22 is output S8, reading from the DRAM 22 is output S9, and output from the rate conversion unit 26 to the panel correction unit 27 is output S10. Reading from the DRAM 22 by the block transfer unit 28 is output S21, and output from the block transfer unit 28 to the video input unit 31 is output S22.

  FIG. 11A illustrates an operation when main video data is input to the input processing unit 21 and no sub-video data is input. A path through which video data is actually output is indicated by a broken line. In the normal display mode, the input processing unit 21 outputs the main video data to the video input unit 31 (output S1), and the video input unit 31 outputs the main video data to the scaler 32. The scaler 32 performs resolution conversion processing and outputs the main video data to the color correction unit 33. The color correction unit 33 performs color correction processing and generation of an intermediate frame, and the processed main video data is transmitted to the two-screen control unit. 24 (output S2).

  In this example, since no sub-picture data is input, the two-screen control unit 24 outputs the main video data output from the color correction unit 33 to the OSD processing unit 25 (output S5). The OSD processing unit 25 reads the OSD image data from the DRAM 22 (output S6), and outputs the superimposed video data to the rate conversion unit 26 (output S7). The rate conversion unit 26 writes the video data to the DRAM 22 (output S8), reads the video data at the set frame rate (output S9), and outputs it to the panel correction unit 27 (output S10).

  In the one-frame advance display process of FIG. 11B, the input processing unit 21 outputs video data to the video input unit 31 (output S1) by the control described in FIG. Data is written (output S3). Then, the rate conversion unit 26 reads the video data from the DRAM 22 (output S9) and outputs it to the panel correction unit 27 (output S10).

  In the one-frame update display process shown in FIG. 12, the block transfer unit 28 reads video data from the DRAM 22 (output S21) and outputs it to the video input unit 31 (output S22) by the control described in FIG. After the video data is processed by the main video path 30, the processed video data is output to the two-screen control unit 24 (output S2), and the two-screen control unit 24 outputs the main video data output from the color correction unit 33. And output to the OSD processing unit 25 (output S5). In the following, the video data is processed by the OSD processing unit 25, the rate conversion unit 26, and the panel correction unit 27 and output to the panel correction unit 27 (output S10), as in the normal display operation of FIG. .

FIG. 13 is a timing chart showing the operation of the projector 1, and shows the operation of the video processing unit 2 in detail. FIG. 13A shows VSYNC input to the main video path 30, and FIG. 13B shows a frame of video data input to the input processing unit 21. For convenience, serial numbers starting from 0 are attached to the frames in (B), and VSYNC in FIG. 13A is assigned a number starting from the number F0 corresponding to the input frame.
FIG. 13C shows the execution state of the update set in the update process (FIG. 10), and becomes high level when the operation of the processing unit is switched. 13D shows a frame (output S3) written to the DRAM 22 by the two-screen control unit 24, and FIG. 13E shows a frame (output S22) output by the block transfer unit 28 to the video input unit 31. (F) shows a frame (output S5) that the two-screen control unit 24 outputs to the OSD processing unit 25, (G) shows a frame (output S8) that the rate conversion unit 26 writes to the DRAM 22, and (H) shows an image. The frame displayed on the formation part 12 is shown.

  Frame data is input to the input processing unit 21 in synchronization with VSYNC input at a constant cycle. The first frame 0 is sequentially processed by the video processing unit 2 and written to the DRAM 22 by the rate conversion unit 26. Then, after the writing of frame 0 is completed, the rate conversion unit 26 reads the frame data from the DRAM 22, and the image of this frame is displayed on the image forming unit 12. In the example of FIG. 13, the rate conversion unit 26 outputs frame data at a frequency twice that of VSYNC in order to drive the liquid crystal light valve of the modulation unit 14 at a double speed.

FIG. 13 shows an example in which the pause function is instructed by the user's operation between VSYNC at F1 and VSYNC at F2, and the timing at which the control unit 10 detects this instruction is indicated by T1. The control unit 10 executes steps ST21 and ST22 of the one-frame memory write process (FIG. 5) after the time T1 is input. Then, in synchronization with the next VSYNC F2, the operation of the processing unit of the video processing unit 2 is switched according to the setting in step ST21.
First, the frame 2 is written in the DRAM 22 by the two-screen control unit 24 between F2 and F3. During the period from F2 to F3, the output S5 from the two-screen control unit 24 to the OSD processing unit 25 is off according to the setting of step ST21, and the rate conversion unit 26 does not write to the DRAM 22. For this reason, the rate conversion unit 26 continues to output the frame 1 already written in the DRAM 22.

  Furthermore, the control unit 10 changes the operation setting of the processing unit in step ST31 of the one-frame advance display process (FIG. 6), and the operation is switched in synchronization with F3 which is the next VSYNC in accordance with this setting change. Thereby, between F3 and F4, the block transfer unit 28 reads the data of frame 2 from the DRAM 22 and inputs it to the video input unit 31 (output S22), and this data is sent from the two-screen control unit 24 to the OSD processing unit 25. Is output (output S5). As a result, the rate conversion unit 26 writes the data of frame 2 to the DRAM 22, and after this writing is completed, the video of frame 2 is displayed on the screen SC.

  Here, when the operation is switched in synchronization with F3, the value of the update register is rewritten from 1 to 0. Therefore, the update is completed after F4, and the operation of the processing unit of the video processing unit 2 is not switched. Therefore, after F4, data output by the block transfer unit 28 (output S22), data output by the two-screen control unit 24 (output S5), and data writing by the rate conversion unit 26 (output S8) do not occur. By omitting unnecessary circuit operations in this way, power consumption can be reduced. Further, since the rate conversion unit 26 continues to read and output the frame 2 written in the DRAM 22, it can continue to display the video on the screen SC.

After F4, the control unit 10 executes user adjustment processing (FIG. 7). When the color adjustment value is set by the user's operation at time T2, the control unit 10 performs the operation of step ST42 to determine the parameter. Further, the control unit 10 executes a one-frame update display process (FIG. 8), and changes the operation setting of the processing unit in step ST51.
Then, the operation of the processing unit of the video processing unit 2 is switched in synchronization with F6 which is the next VSYNC, and the data of the frame 2 is corrected based on the parameter changed by the control unit 10. The corrected data of frame 2 is defined as frame 2 ′. The frame 2 'is written into the DRAM 22 by the rate conversion unit 26, and is displayed on the screen SC after the writing is completed. Since the value of the update register is rewritten to 0 by F6, the operation of each unit is stopped after the next VSYNC F7. Then, the normal display is resumed from the frame 8 by the control unit 10 executing the normal display return process (FIG. 9).

  As described above, the projector 1 according to the embodiment to which the invention is applied includes the video processing unit 2. The video processing unit 2 includes a DRAM 22, a first processing unit that executes processing that does not involve writing to the DRAM 22 for input video data, and first processing that performs image processing that involves writing to the DRAM 22 for video data. 2 processing units. The first processing unit corresponds to, for example, the scalers 32 and 42, the color correction units 33 and 43, or the entire main video path 30 and the entire sub video path 40. The second processing unit corresponds to, for example, the two-screen control unit 24 and the rate conversion unit 26. The video processing unit 2 includes a block transfer unit 28 that reads video data from the DRAM 22 and inputs the video data to the first processing unit, and the second processing unit writes the video data processed by the first processing unit to the DRAM 22. Therefore, the video data is written in the DRAM 22 using the function of the second processing unit, and the video data in the DRAM 22 is input to the first processing unit, whereby the video data is repeatedly processed in the first processing unit. it can. Further, if the video data written in the DRAM 22 is displayed, the video can be stopped. The video displayed during the stop can reflect the processing of the first processing unit. Therefore, a plurality of processes can be efficiently performed on video data without complicating the circuit configuration.

  The second processing unit can write the video data processed by the first processing unit to the DRAM 22 without performing image processing. For example, the two-screen control unit 24 can write the frame data into the DRAM 22 without performing the process of combining the main video data and the sub-video data. Using the function of the two-screen control unit 24, the frame data can be written into the DRAM 22, and the block transfer unit 28 can input the frame data to the main video path 30. In this way, one frame of data can be input again to the input side of the color correction unit 33, and processing such as color correction by the color correction unit 33 can be repeated. Furthermore, when the video to be displayed is stopped and color correction is performed, the video can be promptly displayed in the corrected state. In this way, a multi-functional configuration can be realized by using the two-screen control unit 24 without increasing the number of functional units for writing to the DRAM 22. Therefore, the multifunctional video processing unit 2 can be realized without complicating the circuit configuration and causing a tight memory access.

The second processing unit writes the video data to the DRAM 22 when the first processing unit performs processing on the video data. Therefore, the operation can be stopped when access to the DRAM 22 is unnecessary, such as when the first processing unit does not process the video data, the processing can be made efficient, and the power consumption can be reduced.
The video processing unit 2 includes a third processing unit that processes video data. The second processing unit writes the video data input from the first processing unit to the DRAM 22 and the video input from the first processing unit. The operation of outputting data to the third processing unit can be executed. The third processing unit is a processing unit located on the output side of the second processing unit. When the two-screen control unit 24 corresponds to the second processing unit, the OSD processing unit 25, the rate conversion unit 26, and the panel correction unit 27 are used. Corresponds to a third processing unit. When the rate conversion unit 26 corresponds to the second processing unit, the panel correction unit 27 corresponds to the third processing unit. In this case, the video data processed by the first processing unit can be output from the second processing unit to another processing unit without going through the DRAM 22. As a result, the types of processing for video data can be increased without increasing the frequency of DRAM 22 access.

Further, the third processing unit may execute an operation of acquiring and outputting the video data output from the second processing unit, and an operation of reading out and outputting the video data of the DRAM 22. In this configuration, when the second processing unit outputs video data, the video data is output from the third processing unit. When the second processing unit does not output video data, the video data of the DRAM 22 is output from the third processing unit. Can output. For this reason, the second processing unit can be stopped while continuing the output of the video data, so that the processing efficiency can be improved and the power consumption can be reduced.
Further, the front third processing unit may be connected to the image forming unit 12 that displays the video and output the video data to the image forming unit 12. In this case, the video data output from the second processing unit and the video data written in the DRAM 22 can be output to the image forming unit 12 for display.
The video processing unit 2 may include a plurality of first processing units, and the second processing unit may perform a process of writing video data input from each of the plurality of first processing units to the DRAM 22. That is, the two-screen control unit 24 writes the sub video data in the DRAM 22 when the main video data and the sub video data are combined in the picture-in-picture format. Further, when the main video data and the sub video data are combined in the split screen format, the main video data and the sub video data may be written in the DRAM 22.

In addition, the video processing unit 2 performs normal display mode in which input video data is processed and output by the main video path 30 or sub-video path 40 and the two-screen control unit 24, and the block transfer unit 28 inputs video data as video It can be executed by switching the pause operation input to the unit 31. At the time of switching the operation mode, the input of the video input unit 31 is switched to the block transfer unit 28 side. More specifically, the input of the video input unit 31 is switched from video data output from the input processing unit 21 to video data output from the block transfer unit 28. For this reason, when the operation mode is switched, the operation mode can be quickly switched in a simple circuit configuration by switching the data flow.
Also, the video processing unit 2 sets the operation of each unit of the video processing unit 2 in the operations shown in FIGS. 5, 6, 8 and 9, and switches the settings in accordance with the timing in the update process. For this reason, operation | movement of a some process part can be switched rapidly.

[Second Embodiment]
14 and 15 are explanatory diagrams illustrating the operation of the projector 1 according to the second embodiment to which the present invention is applied.
The projector 1 according to the second embodiment has a configuration in which a path for newly outputting video data is provided in the video processing unit 2 of the projector 1 described in the first embodiment. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  In the second embodiment, the input of the video input unit 41 can be switched between main video data output from the input processing unit 21 and sub-video data. In other words, the output destination from which the main video data is output from the input processing unit 21 can be switched between the video input unit 31 and the video input unit 41. Similarly to the first embodiment, it is possible to output video data from the block transfer unit 28 to the video input unit 41. However, for convenience of explanation, the video data is output from the block transfer unit 28 in FIGS. Illustration of the output line to the input unit 41 is omitted.

  In the second embodiment, an example of processing video data using both the main video path 30 and the sub video path 40 when main video data is input to the video processing unit 2 and no sub video data is input. Show. Specifically, the sub-video path 40 that is paused while the sub-video data is not input is used for the operation of writing the main video data to the DRAM 22.

  FIG. 14A shows the operation in the normal display mode, FIG. 14B shows the 1-frame memory write process, and FIG. 15 shows the 1-frame advance display process.

  FIG. 14A illustrates an operation when main video data is input to the input processing unit 21 and no sub-video data is input. In each of FIGS. 14 and 15, a path through which video data is actually output is indicated by a broken line. In the normal display mode, the input processing unit 21 outputs the main video data to the main video path 30 side. That is, the main video data is input to the video input unit 31 and is output to the two-screen control unit 24 through the video input unit 31, the scaler 32, and the color correction unit 33. The subsequent operation is as described with reference to FIG.

  On the other hand, when the main video data is processed in the sub-video path 40, the main video data is output from the input processing unit 21 to the video input unit 41 as shown in FIG. 14B (output S31). The output destination from which the input processing unit 21 outputs main video data can be switched by the control unit 10 controlling either or both of the input processing unit 21 and the video input unit 41.

The main video data is processed by the video input unit 41, the scaler 42, and the color correction unit 43 included in the sub video path 40 and is input to the two-screen control unit 24. The two-screen control unit 24 writes the main video data input from the sub-video path 40 into the DRAM 22. The subsequent operation is as described with reference to FIG.
In the operation of FIG. 14B, the operation of writing the main video data into the DRAM 22 can be performed by using the sub video path 40 that is paused.

  FIG. 15 shows an operation in which the block transfer unit 28 reads frame data from the DRAM 22 while the input processing unit 21 outputs the main video data. In the operation of FIG. 15, as described with reference to FIG. 12, the block transfer unit 28 outputs frame data to the video input unit 31, and this data is processed by the main video path 30 to be processed by the two-screen control unit 24. Is output. Accordingly, the color correction unit 33 and the color correction unit 43 share the processing of the main video data output from the input processing unit 21 and the processing of the frame data read out by the block transfer unit 28. For this reason, in the said 1st Embodiment, the control which switches on and off of the color correction operation | movement of the color correction part 33 becomes unnecessary. Specifically, the color correction unit 43 may be in a state suitable for the operation of writing the main video data to the DRAM 22, that is, color correction may be turned off. In addition, the color correction unit 33 may be in a state where color correction is performed according to the parameters specified by the control unit 10. Therefore, the control by the control unit 10 can be simplified, and the processing efficiency can be improved.

  Thus, according to the second embodiment, the input processing unit 21 outputs the main video data to either the main video path 30 or the sub video path 40, and the block transfer unit 28 determines that the video data to be processed is The video data read from the DRAM 22 is input to the non-input side. The input video data and the video data read from the DRAM 22 by the block transfer unit 28 can be efficiently processed by a plurality of paths for processing the video data.

[Third Embodiment]
FIG. 16 is a functional block diagram of the video processing unit 2a according to the third embodiment to which the present invention is applied. The video processing unit 2a can be mounted on the projector 1 in place of the video processing unit 2 described in the first and second embodiments.

  The video processing unit 2a has one path for processing video data. Specifically, it includes a video input unit 31a, a scaler 32a, and a color correction unit 33a connected to the input processing unit 21. The video processing unit 2a processes one system of input video data without synthesizing the main video data and sub-video data described in the first and second embodiments. Similar to the video input unit 31, the video input unit 31a acquires the video data output by the input processing unit 21 and outputs the video data to the scaler 32a.

Similar to the scaler 32, the scaler 32a performs resolution conversion processing on the video data output from the video input unit 31a. The scaler 32a may be configured to perform a sharpening process such as a super-resolution process. Similar to the color correction unit 33, the color correction unit 33 a executes color correction processing under the control of the control unit 10.
The DRAM 22, DRAM controller 23, OSD processing unit 25, rate conversion unit 26, and panel correction unit 27 included in the video processing unit 2a have the same configuration as described above.

  The retiming control unit 29 is a circuit unit that performs writing to and reading from the DRAM 22. Further, the retiming control unit 29 may perform timing conversion of video data, a conversion function between 2D (planar) video data and 3D (stereoscopic) video data, and the like. Further, the retiming control unit 29 may regenerate the blanking period and the video body data stream in accordance with the specifications of the OSD processing unit 25 and the panel correction unit 27.

  In this configuration, the video input unit 31a, the scaler 32a, and the color correction unit 33a correspond to a first processing unit, and the retiming control unit 29 and the rate conversion unit 26 correspond to a second processing unit.

The video input unit 31a, the scaler 32a, the color correction unit 33a, and the retiming control unit 29 are the main video path 30 and the two-screen control unit in the one-frame memory write process, the one-frame advance display process, and the one-frame update display process. The operation is the same as 24.
In a projector that does not need to synthesize main video data and sub-video data by the two-screen control unit 24, the two-screen control unit 24 and the video processing unit 2a that omits the sub-video path 40 are provided, as in the first embodiment. The effect of can be obtained. For this reason, the circuit configuration can be further simplified, and improvement in efficiency and further reduction in power consumption can be expected.

  Each of the above-described embodiments is merely an example of a specific mode to which the present invention is applied, and the present invention is not limited thereto. The present invention can be applied as a mode different from the above-described embodiment. For example, in each of the above-described embodiments, the configuration in which the video processing units 2 and 2a are built in the projector 1 is illustrated. However, the present invention is not limited to this, and for example, the device is configured separately from the projector 1. Video processing units 2 and 2a may be provided. Furthermore, the video processing units 2 and 2a are not limited to those configured by hardware such as ASIC, and may be realized by one processor executing a program. Other specific detailed configurations of other parts can be arbitrarily changed without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Projector (display apparatus) 2, 2a ... Video processing part (video processing apparatus), 3 ... Video supply apparatus, 5 ... Indicator, 10 ... Control part, 11 ... Interface part, 12 ... Image formation part (display part) ), 18 ... operation unit, 19 ... position detection unit, 21 ... input processing unit, 22 ... DRAM (memory), 23 ... DRAM controller, 24 ... 2 screen control unit, 25 ... OSD processing unit, 26 ... rate conversion unit, 27 ... Panel correction unit, 28 ... Block transfer unit (transfer unit), 29 ... Retiming control unit, 30 ... Main video path, 31, 31a ... Video input unit, 32, 32a ... Scaler, 33, 33a ... Color correction unit , 40 ... sub-picture path, 41 ... video input section, 42 ... scaler, 43 ... color correction section, SC ... screen.

Claims (12)

Memory,
A first processing unit that executes processing that does not involve writing to the memory with respect to input video data;
A second processing unit for performing image processing with writing to the memory on the video data;
A transfer unit that reads out the video data from the memory and inputs the video data to the first processing unit,
The second processing unit writes the video data processed by the first processing unit into the memory;
A video processing apparatus characterized by the above. The second processing unit can write the video data processed by the first processing unit into the memory without performing the image processing;
The video processing apparatus according to claim 1. The second processing unit writes the video data to the memory when the first processing unit performs processing on the video data;
The video processing apparatus according to claim 1, wherein: A third processing unit for processing the video data;
The second processing unit includes an operation of writing the video data input from the first processing unit to the memory, and an operation of outputting the video data input from the first processing unit to the third processing unit. Be feasible,
The video processing apparatus according to claim 1, wherein: The third processing unit performs an operation of acquiring and outputting the video data output by the second processing unit, and an operation of reading and outputting the video data of the memory;
The video processing apparatus according to claim 4. The third processing unit is connected to a display unit for displaying an image, and outputs the video data to the display unit;
The video processing apparatus according to claim 4 or 5, wherein An input processing unit for outputting the video data to the first processing unit;
A first operation mode in which the input video data is processed and output by the first processing unit and the second processing unit;
The second processing unit is configured to be able to switch and execute the second operation mode in which the video data to be written to the memory is read from the memory and output.
When switching from the first operation mode to the second operation mode, switching the input of the first processing unit from the video data output by the input processing unit to the video data output by the transfer unit;
The video processing apparatus according to claim 1, wherein: When switching between the first and second operation modes, switching the operation of the first processing unit and switching the operation of the second processing unit,
The video processing device according to claim 7 or 8. A plurality of the first processing units;
The second processing unit performs processing of writing the video data input from each of the plurality of first processing units into the memory;
The video processing apparatus according to claim 1, wherein: The transfer unit inputs the video data read from the memory to the first processing unit to which the video data to be processed is not input.
The video processing apparatus according to claim 9. Memory,
A first processing unit that executes processing that does not involve writing to the memory with respect to input video data;
A second processing unit for performing image processing with writing to the memory on the video data;
A transfer unit that reads out the video data from the memory and inputs the video data to the first processing unit,
A video processing unit for writing the video data processed by the first processing unit into the memory by the second processing unit;
A display unit for displaying video based on the video data processed by the video processing unit;
A display device comprising: Control the device with memory that can write video data,
The first processing unit executes processing that does not involve writing to the memory on the input video data,
A second processing unit that performs image processing with writing to the memory with respect to the video data, writes the video data processed by the first processing unit to the memory,
Reading the video data from the memory and inputting it to the first processing unit;
A video processing method characterized by the above.

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