JP2016114681A - Liquid crystal display device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which does not cause breaking of wire or increase of wiring resistance after a finishing shape of a wiring pattern becomes thin even when the pattern is formed by being joined by division exposure.SOLUTION: A joined region 103 of division exposure between a first exposure region 101 and a second exposure region 102 is set approximately parallel to an extended direction of a wiring pattern so that the joined region 103 does not across the wiring pattern 47b1. The joined region 103 of the division exposure is set so that the joined region 103 is superposed with the wiring pattern 47b1.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a liquid crystal display device and a manufacturing method thereof.

  A liquid crystal display device is usually configured such that a pair of upper and lower electrode substrates each having a transparent electrode formed thereon are bonded together by a sealing material formed on the outer edge of the image display portion of the substrate, and liquid crystal is enclosed therein. . Liquid crystal display devices include an active matrix type and a passive matrix type. An active matrix liquid crystal display device includes a TFT array substrate in which thin film transistors serving as switching elements are formed in a matrix. The TFT array substrate and the counter substrate are bonded to each other with a sealing material. Liquid crystal is sealed between the TFT array substrate and the counter substrate.

  In the display area of the TFT array substrate, scanning signal lines, display signal lines, and pixel electrodes are formed. The TFT which is a switching element is ON / OFF controlled by a scanning signal propagating through the scanning signal line. A display signal propagating through the display signal line is supplied to the pixel electrode via the TFT. When a display signal is supplied to the pixel electrode, a display voltage corresponding to the display signal is applied between the counter electrode and the pixel electrode, and the liquid crystal is driven. The scanning signal propagating through the scanning signal line and the display signal propagating through the display signal line are supplied from the driver IC. Accordingly, a lead-out wiring from the driver IC to the scanning signal line and the display signal line is formed in the frame area outside the display area. Further, a seal material and common wiring are formed in the frame region. A common signal for applying a common potential is propagated by the common wiring.

  In general, the TFT array pattern is formed by photolithography. In photolithography, first, a resist applied on a TFT array substrate is irradiated with light through a reticle (mask) including a desired pattern such as an element or wiring, thereby exposing the resist to a desired pattern. Then, a desired TFT array pattern is formed by performing etching using the obtained resist film as a protective film.

  In such a photolithography technique, an exposure apparatus is used to expose a resist. The exposure apparatus is an apparatus that irradiates a resist with light emitted from an ultraviolet source or the like via a reticle. The exposure apparatus has a maximum exposure area that can be irradiated with light. When a panel with a size exceeding the exposure area is exposed, the reticle is divided into a plurality of pieces, and the desired exposure is performed by sequentially connecting the reticles. Divided exposure for forming the TFT array pattern is performed.

  In the joint area of the divided exposure, generally, compared to other areas, the amount of light to be irradiated is larger, so that it is formed smaller than the desired TFT array pattern. When there is a joining region so as to cross the routing wiring, the routing wiring is disconnected. Therefore, it is necessary to widen the pitch of the wiring to form a correction pattern or to thicken the routing wiring itself. (See Patent Document 1)

Japanese Examined Patent Publication No. 63-048331

  When measures against disconnection are carried out by the method described in Patent Document 1, it is necessary to increase the thickness of all the wiring lines, so that the frame area becomes large and it is difficult to reduce the size of the liquid crystal display device. There was a point. The present invention has been made to solve the problems as described above, and provides a TFT array substrate and a liquid crystal display device capable of reducing the frame area.

  In order to solve the above-described problems, a liquid crystal display device according to the present invention is a liquid crystal display device having a substrate and a plurality of wiring patterns formed on the substrate. A feature is that the joining area of the divided exposure does not cross the wiring pattern.

In a liquid crystal display device manufactured using divided exposure, the frame area can be reduced without causing disconnection.

It is a top view which shows the structure of the TFT array substrate used for the liquid crystal display device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the liquid crystal display device which concerns on Embodiment 1 of this invention. It is a top view which shows the display area of the TFT array substrate which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the display area of the TFT array substrate which concerns on Embodiment 1 of this invention. It is an exposure field conceptual diagram of the division exposure of the TFT array substrate concerning Embodiment 1 of the present invention. It is a detailed view of the TFT array substrate according to the first embodiment of the present invention. It is a detailed view of the TFT array substrate according to the second embodiment of the present invention.

Embodiment. 1
The preferred embodiments of the present invention will be described below. The following description explains the embodiment of the present invention, and the present invention is not limited to the following embodiment. In addition, the following description and drawings are omitted and simplified as appropriate for clarity of explanation. The drawings are schematic and do not reflect the exact size of the components shown. In addition, what attached | subjected the same code | symbol in each figure has shown the same element, and duplication description is abbreviate | omitted suitably.

  First, the liquid crystal display device according to the first embodiment of the present invention will be described. FIG. 1 is a plan view showing a TFT array substrate 100 constituting the liquid crystal display device according to the first embodiment. As shown in FIG. 1, the TFT array substrate 100 constituting the liquid crystal display device according to the first embodiment has a display voltage applied to the liquid crystal corresponding to the pixel 50 serving as a unit for displaying an image on the substrate. A TFT 51 serving as a switching element for controlling on / off of supply is disposed. Since the TFTs 51 are arranged in an array for each pixel 50, the substrate on which the TFTs 51 are arranged is called a TFT array substrate 100.

  The TFT array substrate 100 has a substrate 1. The substrate 1 is composed of, for example, a glass substrate or a semiconductor substrate. The TFT array substrate 100 is provided with an array region which is a region where the TFTs 51 are arranged in an array and a frame region provided so as to surround the array region. Specifically, in a display device such as a liquid crystal display device, an array region, which is a region where TFTs 51 are arranged in an array, is surrounded by a display region 41 (a dotted line in the drawing). For the frame area provided so as to surround the array area, the frame area 42 provided so as to surround the display area 41 (area excluding the area surrounded by the dotted line in the figure of the TFT array substrate) ).

  In the display area 41, a plurality of gate lines (scanning signal lines) 43 and a plurality of source lines (display signal lines) 44 are formed. The plurality of gate wirings 43 are provided in parallel. Similarly, the plurality of source lines 44 are provided in parallel. The gate wiring 43 and the source wiring 44 are formed so as to cross each other. A region surrounded by the adjacent gate wiring 43 and source wiring 44 is a pixel 50. Accordingly, in the display area 41, the pixels 50 are arranged in a matrix.

  In the frame area 42 of the TFT array substrate 100, a scanning signal driving circuit 46a, a display signal driving circuit 46b, a wiring conversion unit 45, lead-out wirings 47a1, 47a2, 47b1, 47b2, and external connection terminals 48a1, 48a2, 48b1, 48b2, etc. Is provided. The gate line 43 extends from the display area 41 to the frame area 42, and is drawn out to the end of the TFT array substrate 100 by a lead line 47a1 formed of the same material as the gate line 43 in the frame area 42. At the end of 100, the scanning signal driving circuit 46a is connected via an external connection terminal 48a1 arranged in plural at the end of the lead-out wiring 47a1.

  The source wiring 44 is electrically connected to the first conductive film formed in the same layer by the same material as the gate wiring 43 in the wiring conversion unit 45, and the extraction wiring 47b1 formed of the first conductive film causes the TFT to It is drawn out to the end of the array substrate 100, and further connected to the display signal driving circuit 46b through the external connection terminal 48b1 provided in a plurality at the end of the lead-out wiring 47b1 at the end of the TFT array substrate 100. . In the vicinity of the scanning signal drive circuit 46a, an external wiring 49a is connected via a lead-out wiring 47a2 and an external connection terminal 48a2. Further, in the vicinity of the display signal drive circuit 46b, an external wiring 49b is connected via a lead-out wiring 47b2 and an external connection terminal 48b2. The external wirings 49a and 49b are wiring boards such as FPC (Flexible Printed Circuit).

  Various external signals are supplied to the scanning signal drive circuit 46a through the external wiring 49a and the lead-out wiring 47a2, and to the display signal drive circuit 46b through the external wiring 49b and the lead-out wiring 47b2. The scanning signal driving circuit 46 a supplies a gate signal (scanning signal) to the gate wiring 43 based on an external control signal. The gate wiring 43 is sequentially selected by this gate signal. The display signal drive circuit 46b supplies a display signal to the source wiring 44 based on an external control signal or display data. As a result, a display voltage corresponding to the display data can be supplied to each pixel 50.

  At least one TFT 51 is formed in the pixel 50. The TFT 51 is disposed in the vicinity of the intersection of the source wiring 44 and the gate wiring 43. For example, the TFT 51 supplies a display voltage to the pixel electrode. That is, the TFT 51 as a switching element is turned on by the gate signal from the gate wiring 43. Thereby, a display potential is applied from the source wiring 44 to the pixel electrode connected to the drain electrode of the TFT 51. Further, the pixel electrode is a plate-like electrode, and is disposed to face a common electrode (counter electrode) having a comb-like electrode or a slit electrode via an insulating film. A common potential is applied to the common electrode (counter electrode), and a fringe electric field corresponding to a display voltage (a potential difference between the display potential and the common potential) is generated between the pixel electrode and the counter electrode. A detailed configuration of the pixel 50 will be described later.

  Next, the overall configuration of the liquid crystal display device according to Embodiment 1 will be described with reference to the cross-sectional view of FIG. As shown in FIG. 2, an alignment film 61 is formed on the surface of the TFT array substrate 100 described in detail above. Further, a counter substrate 60 is disposed to face the TFT array substrate 100. The counter substrate 60 is, for example, a color filter substrate, and is disposed on the viewing side. On the counter substrate 60, a color filter 64, a black matrix (BM) 63, an alignment film 61, and the like are formed. A liquid crystal layer 62 is sandwiched between the TFT array substrate 100 and the counter substrate 60. That is, liquid crystal is introduced between the TFT array substrate 100 and the counter substrate 60. Further, a polarizing plate 65 is provided on the outer surfaces of the TFT array substrate 100 and the counter substrate 60 to constitute a liquid crystal display panel. In addition, a backlight unit 67 is disposed on the back side of the TFT array substrate 100 on the opposite side of the liquid crystal display panel via an optical film 66 such as a phase difference plate. The liquid crystal display panel and its peripheral members are made of resin or metal. The frame is appropriately stored in a frame (not shown) composed of the above. The liquid crystal display device according to the first embodiment is configured as described above.

  The liquid crystal is driven by a fringe electric field between the pixel electrode and the counter electrode. That is, the alignment direction of the liquid crystal between the substrates changes. As a result, the polarization state of the light passing through the liquid crystal layer 62 changes. That is, the polarization state of the light that has passed through the polarizing plate 65 and has become linearly polarized light is changed by the liquid crystal layer 62. Specifically, the light from the backlight unit 67 becomes linearly polarized light by the polarizing plate 65 on the TFT array substrate side. As the linearly polarized light passes through the liquid crystal layer 62, the polarization state changes. The amount of light passing through the polarizing plate 65 on the counter substrate side varies depending on the polarization state. That is, the amount of light that passes through the polarizing plate 65 on the viewing side among the transmitted light that passes through the liquid crystal display panel from the backlight unit 67 changes. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate 65 can be changed by controlling the display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel 50.

  Next, a detailed configuration of the display region 41 in which the TFT 51 of the liquid crystal display device according to the first embodiment is arranged will be described with reference to FIGS. 3 is a plan view showing a pixel configuration in the vicinity of the center portion of the display area 41 of the TFT array substrate 100 according to the first embodiment, and FIG. 4 is a cross-sectional view taken along the line A1-A2 in FIG. It is a thing. 3 and 4, for example, a gate wiring 43 connected to the gate electrode of the TFT 51 is formed on the substrate 1 made of an insulating material such as a glass substrate. Here, the gate wiring 43 is formed so that a part thereof constitutes a gate electrode.

  The gate electrode and the gate wiring 43 are, for example, refractory metals or low resistance metals such as Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, and Ag, alloy films containing these as main components, or these films. The first conductive film is formed of a laminated film. A semiconductor layer 3 is formed on the first insulating film 8 to be a gate insulating film. The semiconductor layer 3 is formed on the first insulating film 8 so as to overlap with the gate wiring 43, and is formed of amorphous silicon, polycrystalline silicon, In—Ga—Zn—O, or the like. Further, an ohmic contact film 4 doped with conductive impurities is formed on the semiconductor layer 3. The ohmic contact film 4 is disposed on almost the entire surface of the semiconductor layer 3 except for the channel region of the TFT 51. Of the semiconductor layer 3 overlapping with the gate electrode, the region of the semiconductor layer 3 corresponding to the ohmic contact film 4 becomes a source / drain region. Specifically, the region of the semiconductor layer 3 corresponding to the left ohmic contact film 4 in FIG. 4 overlapping with the gate electrode (gate wiring 43) becomes the source region. The region of the semiconductor layer 3 corresponding to the right ohmic contact film 4 in FIG. 4 overlapping with the gate electrode (gate wiring 43) becomes the drain region. A region sandwiched between the source / drain regions of the semiconductor layer 3 becomes a channel region. The ohmic contact film 4 is not formed on the channel region of the semiconductor layer 3. The ohmic contact film 4 is formed of, for example, n-type amorphous silicon or n-type polycrystalline silicon doped with an impurity such as phosphorus (P) at a high concentration.

  A source electrode 53, a drain electrode 54, and a source wiring 44 are formed on the ohmic contact film 4. Specifically, the source electrode 53 is formed on the ohmic contact film 4 on the source region side of the semiconductor layer 3. A drain electrode 54 is formed on the ohmic contact film 4 in the drain region. In this way, a channel etch type TFT 51 is configured. The source electrode 53 and the drain electrode 54 are formed so as to extend outside the channel region of the semiconductor layer 3. That is, the source electrode 53 and the drain electrode 54 are not formed on the channel region of the semiconductor layer 3 like the ohmic contact film 4. The source electrode 53 extends outside the channel region of the semiconductor layer 3 and is connected to the source wiring 44. That is, the source wiring 44 is connected to the source electrode 53. The source wiring 44 is arranged on the substrate 1 so as to extend linearly in a direction intersecting with the gate wiring 53. Accordingly, the source wiring 44 branches at the intersection with the gate wiring 43 and then extends along the gate wiring 43 to become the source electrode 53.

  The source electrode 53, the drain electrode 54, and the source wiring 44 are composed of a high-melting-point metal such as a metal film whose upper layer is mainly Al and a lower layer such as Cr, Ta, Ti, Mo, W, Ni, Cu, Au, or Ag. It is a metal pattern formed by a second conductive film composed of a low resistance metal or a laminated film of alloy films containing these as main components. That is, the source wiring 44 is a metal pattern formed in the same layer with the same material as the source electrode 53 and the drain electrode 54. The drain electrode 54 extends outside the channel region of the semiconductor layer 3 and is electrically connected to the pixel electrode 55.

  In the first embodiment, the pixel electrode 55 is formed directly on the drain electrode 54. That is, the lower surface (lower surface) of the pixel electrode 55 is formed in direct contact with the upper surface (upper surface) of the drain electrode 54. The pixel electrode 55 extends from the drain electrode 54 into the pixel 50, and as shown in FIGS. 3 and 4, the pixel electrode 55 is in a region surrounded by the source wiring 44 and the gate wiring 43 constituting the pixel 50. It is formed on almost the entire surface. That is, the pixel electrode 55 is disposed so that a part thereof overlaps the drain electrode 54. The pixel electrode 55 is a transparent conductive film pattern formed of a transparent conductive film such as ITO. Thus, the pixel electrode 55 is formed directly on the upper layer of the drain electrode 54 without using an insulating film. With such a configuration, a contact hole for electrically connecting the pixel electrode 55 to the drain electrode 54 becomes unnecessary. This is because an electrical connection between them can be obtained by arranging a part of the pixel electrode 55 so as to directly overlap the drain electrode 54. Therefore, the pixel 50 can be formed without providing an area for arranging the contact hole for the connection between the drain electrode 54 and the pixel electrode 55, and the aperture ratio can be increased.

  In the above description, the transparent conductive film pattern in the portion directly overlapping the drain electrode 54 and the transparent conductive film pattern formed on almost the entire area surrounded by the source wiring 44 and the gate wiring 43 are integrally formed. Therefore, the pixel electrode 55 is collectively referred to for explanation. However, since the latter transparent conductive film pattern substantially functions as the pixel electrode 55, the former transparent conductive film pattern is formed in the same layer by a transparent conductive film that is the same material as the pixel electrode 55. Further, the first transparent conductive film pattern 6 may be interpreted separately from the pixel electrode 55. Further, the latter transparent conductive film pattern that substantially functions as the pixel electrode 55 also has a first layer formed in the same layer by a transparent conductive film that is the same material as the pixel electrode 55, with the adjacent pixel electrode 55 as a main component. Therefore, the entire pixel electrode 55 may be interpreted as the first transparent conductive film pattern 6 without particular distinction.

  A second insulating film 9 is provided as an upper insulating film covering the pixel electrode 55 and the first transparent conductive film pattern 6. The second insulating film 9 covers the TFT 51 and functions as a protective film for the TFT 51. The second insulating film is formed of an insulating film such as silicon nitride or silicon oxide, a coating type insulating film (formed by coating), or a laminated film thereof. In the first embodiment, the counter electrode 56 is formed on the second insulating film 9. The counter electrode 56 is disposed on the opposite side of the pixel electrode 55 via the second insulating film 9, and a slit 59 for generating a fringe electric field is provided between the counter electrode 56 and the pixel electrode 55. With the configuration of the pixel electrode 55 and the counter electrode 56 described above, an FFS mode liquid crystal display device can be configured by driving a liquid crystal by generating a fringe electric field.

  Since the counter electrode 56 and the pixel electrode 55 are insulated by the second insulating film 9, the second insulating film 9 also functions as an interlayer insulating film. The counter electrode 56 is integrally formed so as to be connected to the counter electrode 56 of the adjacent pixel 50 with the gate wiring 43 interposed therebetween. Specifically, the counter electrodes 56 of the pixels 50 adjacent to each other with the gate wiring 43 interposed therebetween are connected by the counter electrode connecting portion 57. Here, the counter electrode connecting portion 57 of the counter electrode 56 is formed so as to straddle the gate wiring 43 in a region not overlapping with the source wiring 44 or the TFT 51. That is, the counter electrode 56 is formed so as to overlap at least a part of the gate wiring 43. The counter electrode 56 and the counter electrode connecting portion 57 are a transparent conductive film pattern formed integrally with a transparent conductive film such as ITO.

  Next, divided exposure at the time of forming the TFT array pattern of the liquid crystal display device according to the first embodiment will be described. FIG. 5 is a conceptual diagram of an exposure area at the time of divided exposure. In FIG. 5, reference numeral 47b1 denotes a lead-out line, which is connected to the external connection terminal 48b1 of the display signal drive circuit 46. Furthermore, the external connection terminal 48b1 of the display signal drive circuit 46 and the external connection terminal 48b2 of the external wiring 49 are connected via a lead wiring 47b2.

  In the first embodiment, as shown in FIG. 5, the divided exposure is divided into two areas of a first exposure area A (101) and a second exposure area B (102) adjacent to the first exposure area. To do. In this case, even if a stitching area for exposing the exposure area A (101) and the exposure area B (102) is provided, the stitching area does not cross the wiring pattern. A TFT array pattern can be formed.

  Furthermore, it demonstrates in detail using FIG. FIG. 6 is a detailed view of a portion indicated by 104 in FIG. In the frame region 42, as shown in FIG. 6, the joining region 103 is set so as to be substantially parallel to the lead-out wiring 47b1. Here, by arranging the joining region so as to overlap with the lead-out wiring 47b3 which is thickened in consideration of the process variation of the divided exposure, the frame region can be obtained without changing the pitch of the lead-out wiring 47b1 other than the lead-out wiring 47b3. A TFT array pattern can be formed without expanding 42.

  Next, the manufacturing method will be described. After forming a conductive film (not shown) such as a metal film that forms wiring on the substrate, a positive photosensitive resist material is applied to form a first exposure region 101 and a second exposure region as shown in FIG. Photoengraving processing is performed to irradiate the exposure region 102 with light. At that time, exposure is performed so that the boundary between the reticle used for the first exposure region 101 and the reticle used for the second exposure region 102 overlaps the wiring. Thereafter, the resist material other than the region corresponding to the wiring pattern is removed, and the exposed conductive film is removed by etching, whereby a wiring pattern as shown in FIG. 6 can be obtained.

  Here, although two exposure steps are performed in the joining region 103, the boundary between the first exposure region and the second exposure region, in other words, the end portion of the first exposure region and the first exposure region. No light is irradiated to the overlapping portion with the end portion of the second exposure region. That is, in the overlapping portion of the joining region and the lead-out wiring 47b3, the lead-out wiring 47b3 is provided at both the location corresponding to the end of the first exposure region 101 and the location corresponding to the end of the second exposure region 102. This is because a reticle provided with a pattern for forming a film is used for exposure. Note that it is important that the patterns are arranged at the end portions of both exposure regions, and the pattern does not necessarily have to be formed at the end portions of the reticle.

  Therefore, the wiring pattern formed at the position corresponding to the boundary portion is formed thicker than the other wiring patterns by combining the end of the first exposure region 101 and the end of the second exposure region 102. Will be. Thereby, there is no problem because the lead-out wiring 47b3 is set to be thick in advance. With this manufacturing method, the TFT array pattern can be formed without changing the pitch of the lead-out wiring 47b1 other than the lead-out wiring 47b3 and without expanding the frame region 42.

Embodiment 2. FIG.
FIG. 7 shows a TFT array pattern of the liquid crystal display device according to the second embodiment. FIG. 7 also shows the joining region 103 of the exposure regions in the frame region 42. In the first embodiment, the connection region 103 of the exposure region is set to overlap the wiring pattern. However, in the second embodiment, the same effect can be obtained by arranging the connection region 103 at the lead-out wiring interval 47b4. Can be obtained.

  In other words, the second embodiment is characterized in that a connection region of exposure regions is provided between the wirings. Furthermore, if the distance between adjacent wirings that are adjacent to the connection area of the exposure area is larger than the distance between wirings that do not have the connection area of the exposure area, the allowable width of the process margin also increases. good.

  Next, the manufacturing method will be described. After forming a conductive film (not shown) such as a metal film that forms wiring on the substrate, a positive photosensitive resist material is applied to form a first exposure region 101 and a second exposure region as shown in FIG. Photoengraving processing is performed to irradiate the exposure region 102 with light. Thereafter, the resist material other than the region corresponding to the wiring pattern is removed, and the exposed conductive film is removed by etching, whereby a wiring pattern as shown in FIG. 7 can be obtained.

  Here, the connection region 103 is irradiated twice, but there is no problem because the region is a region between adjacent wirings and does not form a wiring pattern. Rather, since the resist material between the wirings is further removed by performing the exposure twice, a short circuit between the wirings can be further prevented. With this manufacturing method, the TFT array pattern can be formed without changing the pitch of the lead-out wiring 47b1 other than the lead-out wiring 47b4 and without expanding the frame region 42.

  5-7, the frame region 42 where the lead-out wiring 47b1 is disposed has been described. However, the same effect can be obtained by adopting the same configuration in the frame region 42 where the lead-out wiring 47a1 is formed. it can. Further, although the positive resist material has been described, a negative resist material may be used as long as the relationship between the presence and absence of light irradiation is reversed.

  The array substrate having the TFT array pattern formed as described above is bonded to a counter substrate via a sealing material, and a liquid crystal display panel is formed by sealing liquid crystal therebetween. A liquid crystal display device is formed by mounting a light source and a drive circuit on the liquid crystal display panel. In addition, an electroluminescent display device can be manufactured by forming a light emitting layer that emits light by applying an electric field over the pixel electrodes of the array substrate, and then covering the insulating substrate with an insulating film and forming a common electrode. Furthermore, it is also possible to manufacture an electrophoretic display device that drives microcapsules containing white and black pigment particles by an electric field generated by an array substrate and an external circuit, and an electropowder fluid display device. . Although different from the display device, an image sensor for visible light, ultraviolet light, or radiation can be manufactured by providing a photoelectric conversion element instead of a pixel electrode in the array substrate according to the present invention.

1 substrate, 3 semiconductor film, 4 ohmic contact film,
8 first insulating film, 9 second insulating film, 41 display area, 42 frame area,
43 gate wiring, 44 source wiring, 45 wiring converter,
46a scanning signal drive circuit, 46b display signal drive circuit,
47a1, 47a2, 47b1, 47b2, 47b3 lead-out wiring,
47b4 Lead-out wiring interval,
48a1, 48a2, 48b1, 48b2 external connection terminals,
49a, 49b external wiring, 50 pixels, 51 TFT, 53 source electrode,
54 drain electrode, 55 pixel electrode, 56 counter electrode, 57 counter electrode connecting portion,
59 slit part, 60 counter substrate, 61 alignment film, 62 liquid crystal layer,
63 Black matrix, 64 color filter, 65 polarizing plate,
66 optical film, 67 backlight unit, 100 TFT array substrate,
101 first exposure area, 102 second exposure area,
103 Joining area of exposure areas

Claims (10)

In a liquid crystal display device having a substrate and a plurality of wiring patterns formed on the substrate,
The liquid crystal display device according to claim 1, wherein a joining region of the divided exposure when forming the wiring pattern does not cross the wiring pattern. The liquid crystal display device according to claim 1, wherein the joining region is substantially parallel to an extending direction of the wiring. 3. The liquid crystal display device according to claim 1, wherein an interval between the wirings adjacent to each other across the joining region is wider than an interval between the wirings in which the joining region is not set. . Forming a conductive film on the substrate;
Forming a photosensitive resist material on the conductive film;
Irradiating the photosensitive resist material with light for exposure; and
Forming a plurality of lead wiring patterns by etching away the conductive film after partially removing the photosensitive resist material, and a method for manufacturing a liquid crystal display device,
The exposure light irradiation is performed separately in a first exposure area and a second exposure area,
The first exposure area and the second exposure area have a joining area overlapping each other,
The method of manufacturing a liquid crystal display device, wherein the joining region is formed so as not to cross the lead-out wiring pattern. 5. The method for manufacturing a liquid crystal display device according to claim 4, wherein the joining region is substantially parallel to the extending direction of the lead-out wiring. 6. The method for manufacturing a liquid crystal display device according to claim 4, wherein the joining region is set so as to overlap with the lead-out wiring. The method of manufacturing a liquid crystal display device according to claim 6, wherein the lead-out wiring is thicker than the lead-out wiring that does not overlap with the joining region. In the overlapping portion between the joining region and the lead-out wiring, the lead-out wiring is provided at both a location corresponding to the end of the first exposure region and a location corresponding to the end of the second exposure region. 8. The method for manufacturing a liquid crystal display device according to claim 6, wherein exposure is performed such that a pattern for forming the pattern is provided. 6. The method for manufacturing a liquid crystal display device according to claim 4, wherein the joining region is set between the lead-out wiring and an adjacent lead-out wiring. 10. The liquid crystal display device according to claim 9, wherein an interval between the lead-out lines adjacent to each other across the joining region is wider than an interval between the lead-out wires in which the joining region is not set. Manufacturing method.

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