JP2016092829A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve accuracy of an oscillating frequency or provide a circuit configuration which can achieve improvement in accuracy of an oscillating frequency.SOLUTION: A semiconductor device includes an oscillation circuit which has first through n-th (n is an odd number equal to or larger than 3) inverters, a first circuit and a second circuit. A first terminal of each of the first circuit and the second circuit is electrically connected with an output terminal of the i-th (i is any one of first through (n-1)) and a second terminal of each of the first circuit and the second circuit is electrically connected with an input terminal of the (i+1)-th inverter. A total length of a wiring path between the output terminal of the i-th inverter and the first terminal of the first circuit and a wiring path between the second terminal of the first circuit and the input terminal of the (i+1)-th inverter is substantially equivalent with a total length of a wiring path between the output terminal of the i-th inverter and the first terminal of the second circuit and a wiring path between the second terminal of the second circuit and the input terminal of the (i+1)-th inverter.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a device such as a semiconductor device or a driving method thereof.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, a driving method thereof, Alternatively, the production method thereof can be given as an example.

  Development of PLL (Phase Locked Loop) is being actively promoted (see Non-Patent Document 1). The PLL is used in a circuit such as a CPU or a programmable logic device to operate the circuit at a desired operation speed.

X. Gao, A.A. M.M. Klumperink, P.M. F. J. et al. Geraedts, B.A. Nauta, "Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops" IEEE Trans. On Circuits and Systems-II, vol. 56, no. 2, pp. 117-121, Feb. 2009

  In the conventional PLL circuit, it is difficult to switch the oscillation frequency instantaneously.

  An object of one embodiment of the present invention is to provide a novel circuit configuration. An object of one embodiment of the present invention is to switch an oscillation frequency or provide a circuit configuration that can realize the switching. An object of one embodiment of the present invention is to improve the accuracy of an oscillation frequency or provide a circuit configuration capable of realizing the same.

  Note that an object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not necessarily have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention includes an oscillation circuit, and the oscillation circuit includes first to n-th (n is an odd number of 3 or more) inverters, a first circuit, and a second circuit. The first terminal of the first circuit is electrically connected to the output terminal of the i-th inverter (i is any one of 1 to n-1), and the second terminal of the first circuit is The first terminal of the second circuit is electrically connected to the output terminal of the i-th inverter, and the second terminal of the second circuit is electrically connected to the input terminal of the i + 1 inverter. a wiring path between the output terminal of the i-th inverter and the first terminal of the first circuit; the second terminal of the first circuit; and the i + 1-th terminal. The length of the wiring path between the input terminal of the inverter and the output terminal of the i-th inverter and the first terminal of the second circuit And a wiring path between the second terminal of the second circuit and the input terminal of the (i + 1) th inverter are approximately equal in length. .

  Another embodiment of the present invention includes an insulating film over at least part of the first circuit and the second circuit, and is electrically connected to the output terminal of the i-th inverter over the insulating film. A first wiring connected to the input terminal of the (i + 1) th inverter; and the first wiring is connected to the first wiring through the first opening provided in the insulating film. Electrically connected to the first terminal of the first circuit and electrically connected to the first terminal of the second circuit through the second opening provided in the insulating film. The wiring is electrically connected to the second terminal of the first circuit through the third opening provided in the insulating film, and is connected to the second terminal through the fourth opening provided in the insulating film. And the distance between the first opening and the second opening is the distance between the third opening and the fourth opening. Substantially it is preferably equal.

  In another embodiment of the present invention, a first region in which a j-th inverter (j is an odd number from 1 to n) is provided, and a second region in which a first circuit and a second circuit are provided. And a third region provided with a k-th (k is an even number not less than 2 and not more than n−1) inverter, and the second region is between the first region and the third region. It is preferred that the region is located.

  According to another embodiment of the present invention, the first circuit has a function of storing first data, and the first circuit makes the first terminal and the second terminal non-conductive. Or a function of switching the resistance value between the first terminal and the second terminal to a value based on the first data, and the second circuit is a function of storing the second data And the second circuit makes the first terminal and the second terminal non-conductive, or the resistance value between the first terminal and the second terminal is based on the second data It is preferable to have a function of switching between values.

  In another embodiment of the present invention, the first data and the second data may be analog potentials.

  According to another embodiment of the present invention, the first circuit includes a first transistor and a first capacitor, and the second circuit includes a second transistor and a second capacitor. And the first data is input to the first capacitor through the first transistor, and the second data is input to the second capacitor through the second transistor. The first transistor may include an oxide semiconductor in the channel formation region, and the second transistor may include an oxide semiconductor in the channel formation region.

  According to another embodiment of the present invention, the first circuit includes a third transistor and a fourth transistor, and the second circuit includes a fifth transistor, a sixth transistor, The third transistor and the fourth transistor are electrically connected in series between the first terminal of the first circuit and the second terminal of the first circuit, and the fifth transistor The transistor and the sixth transistor are electrically connected in series between the first terminal of the second circuit and the second terminal of the second circuit, and between the source and drain of the third transistor. Has a value based on the first data, and the fourth transistor controls conduction or non-conduction between the first terminal of the first circuit and the second terminal of the first circuit. The resistance value between the source and drain of the fifth transistor is the second data. It has Zui value, the sixth transistor may have a function of controlling conduction or non-conduction between the second terminal of the first terminal and the second circuit of the second circuit.

  The above apparatus may have a PLL. The PLL includes an oscillation circuit, a frequency divider, a phase comparator, and a loop filter.

  According to one embodiment of the present invention, a novel circuit configuration can be provided. According to one embodiment of the present invention, an oscillation frequency can be switched or a circuit configuration that can realize the switching can be provided. According to one embodiment of the present invention, the accuracy of an oscillation frequency can be improved, or a circuit configuration that can realize this can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

The figure which shows the structure of an apparatus. The figure which shows the structure of an apparatus. The figure which shows the structure of an apparatus. The figure which shows operation | movement of an apparatus. The figure which shows operation | movement of an apparatus. The figure which shows operation | movement of an apparatus. The figure which shows operation | movement of an apparatus. The figure which shows the structure of PLL. The figure which shows the planar structure of an apparatus. The figure which shows the cross-section of an apparatus. FIG. 6 illustrates a structure of a transistor. FIG. 6 illustrates a structure of a transistor. The figure which shows the cross-section of an apparatus. The figure which shows the cross-section of an apparatus. Illustration of electronic equipment. The photograph of the device concerning an example. The figure which shows the planar structure of the apparatus which concerns on an Example. The graph explaining operation | movement of an apparatus. The graph explaining operation | movement of an apparatus. The graph explaining operation | movement of an apparatus. The graph explaining operation | movement of an apparatus. The graph explaining operation | movement of an apparatus. The graph explaining operation | movement of an apparatus. The graph explaining operation | movement of an apparatus. The graph explaining operation | movement of an apparatus.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  One embodiment of the present invention includes, in its category, any semiconductor device including transistors, such as an integrated circuit, an RF tag, and a semiconductor display device. The integrated circuit includes a microprocessor, an image processing circuit, a DSP (Digital Signal Processor), an LSI (Large Scale Integrated Circuit) including a microcontroller, an FPGA (Field Programmable Gate Array), and a CPLD (Complex Programmable PLD). A circuit (PLD: Programmable Logic Device) is included in the category. In addition, the semiconductor display device includes a liquid crystal display device, a light emitting device including a light emitting element typified by an organic light emitting element (OLED) in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), A semiconductor display device having a circuit element using a semiconductor film, such as a field emission display (FED), in a driver circuit is included in its category.

  In this specification, a semiconductor display device includes, in its category, a panel in which display elements such as liquid crystal elements and light-emitting elements are formed in pixels, and a module in which an IC including a controller is mounted on the panel. Including.

  For example, in this specification and the like, when X and Y are explicitly described as being connected, when X and Y are electrically connected, X and Y are functionally connected. The case where they are connected and the case where X and Y are directly connected are included. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and includes things other than the connection relation shown in the figure or text.

  Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do.

  Note that in the case where X and Y are explicitly described as being connected, when X and Y are electrically connected (that is, another element or another element between X and Y) When the circuit is connected) and when X and Y are functionally connected (that is, when another circuit is interposed between X and Y) And a case where X and Y are directly connected (that is, a case where another element or another circuit is not connected between X and Y). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

  Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

  For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

  Note that in this specification, the source of a transistor means a source region that is part of a semiconductor film functioning as an active layer or a source electrode connected to the semiconductor film. Similarly, a drain of a transistor means a drain region that is part of the semiconductor film or a drain electrode connected to the semiconductor film. The gate means a gate electrode.

  The terms “source” and “drain” of a transistor interchange with each other depending on the conductivity type of the transistor and the level of potential applied to each terminal. In general, in an n-channel transistor, a terminal to which a low potential is applied is called a source, and a terminal to which a high potential is applied is called a drain. In a p-channel transistor, a terminal to which a low potential is applied is called a drain, and a terminal to which a high potential is applied is called a source. In this specification, for the sake of convenience, the connection relationship between transistors may be described on the assumption that the source and the drain are fixed. However, the names of the source and the drain are actually switched according to the above-described potential relationship. .

(Embodiment 1)
In this embodiment, an apparatus according to one embodiment of the present invention is described. In the case where a semiconductor element such as a transistor is used for the device according to one embodiment of the present invention, the device according to one embodiment of the present invention may be referred to as a semiconductor device.

  FIG. 1 illustrates an example of a structure of a semiconductor device according to one embodiment of the present invention. The device illustrated in FIG. 1 has a function of generating an AC signal such as a clock signal by oscillating, and may be called an oscillator (also referred to as an oscillation circuit). In particular, the apparatus illustrated in FIG. 1 has a function of changing a signal frequency (also referred to as an oscillation frequency) based on an input voltage, and may be referred to as a voltage controlled oscillator (also referred to as a voltage controlled oscillation circuit).

  The apparatus illustrated in FIG. 1 includes circuits 101 [1] to 101 [n] (n is an odd number of 3 or more). The circuits 101 [1] to 101 [n] are connected in a ring shape. Specifically, each of the circuits 101 [1] to [n-1] has an output terminal connected to an input terminal of a circuit at the next stage. The output terminal of the circuit 101 [n] is connected to the input terminal of the circuit 101 [1]. The output terminal of the circuit 101 [n] is connected to the terminal OUT. A signal generated when the device illustrated in FIG. 1 oscillates is output from the terminal OUT.

  Note that a signal generated when the apparatus illustrated in FIG. 1 oscillates may be output via a buffer or the like.

  Each of the circuits 101 [1] to [n] has a function of outputting a signal that is inverted with respect to the input signal. Each of the circuits 101 [1] to 101 [n] has a function of storing a plurality of data, and has a function of setting a delay time based on the stored data. The delay time is a delay time of the output signal with respect to the input signal. Since each of the circuits 101 [1] to 101 [n] can store a plurality of data, the delay time can be switched.

  The apparatus illustrated in FIG. 1 can change the oscillation frequency by switching the delay times of the circuits 101 [1] to 101 [n].

  The circuits 101 [1] to 101 [n] preferably include the circuits 102 [1] to 102 [n] and the inverters 103 [1] to 103 [n], respectively. In the circuit 102 [i] (i is a natural number of 1 to n−1), the terminal A is electrically connected to the output terminal of the inverter 103 [i], and the terminal B of the circuit 102 [i] is connected to the inverter 103 [i + 1]. ] Is electrically connected to the input terminal. In the circuit 102 [n], the terminal A is electrically connected to the output terminal of the inverter 103 [n], and the terminal B of the circuit 102 [n] is electrically connected to the input terminal of the inverter 103 [1] and the terminal OUT. Is done. That is, the inverters 103 [1] to 103 [n] are connected in a ring shape to form an inverter ring. A corresponding one of the circuits 102 [1] to 102 [n] is connected between the inverters 103 [1] to 103 [n]. Note that the circuit 102 [1] to 102 [n] may be referred to as the circuit 102 when there is no particular limitation. In addition, the inverters 103 [1] to 103 [n] may be referred to as the inverter 103 when there is no particular limitation.

  Each of the circuits 102 [1] to 102 [n] has a function of storing a plurality of data and a function of setting a resistance value between the terminal A and the terminal B based on the stored plurality of data. . Since each of the circuits 102 [1] to 102 [n] can store a plurality of data, the resistance value between the terminal A and the terminal B can be switched.

  Each of the inverters 103 [1] to 103 [n] has a function of outputting a signal that is inverted with respect to the input signal.

  Note that a circuit having a function of outputting a signal inverted with respect to an input signal may be employed instead of the inverters 103 [1] to 103 [n]. Examples of such a circuit include a NAND circuit and a NOR circuit.

  The device illustrated in FIG. 1 can change the oscillation frequency by switching the resistance value between the terminal A and the terminal B of the circuit 102 in each of the circuits 101 [1] to 101 [n]. Specifically, when the resistance value between the terminal A and the terminal B of the circuit 102 is switched, the load applied to the output terminal of the inverter 103 changes. Accordingly, since the delay time changes in each of the circuits 101 [1] to 101 [n], the oscillation frequency also changes.

  In the device shown in FIG. 1, a corresponding one of the circuits 102 [1] to 102 [n] is connected between the inverters 103 [1] to 103 [n]. However, the semiconductor device shown in this embodiment is not limited to this. If the circuit 102 is connected between at least two of the inverters 103 [1] to 103 [n], the oscillation frequency can be changed.

The circuits 102 [1] to 102 [n] include circuits 104 [1] to 104 [m] (m is a natural number of 2 or more), respectively. In the circuits 104 [1] to 104 [m], the terminals C _{1 to} C _m are electrically connected to the terminal A of the circuit 102, and the terminals D _{1 to} D _m are electrically connected to the terminal B of the circuit 102. . Each of the circuits 104 [1] to 104 [m] includes one of the wiring BL, the wiring CONTEXT [1] to CONTEXT [m], and the wiring WL [1] to WL [m]. It is electrically connected to one corresponding wiring. A corresponding one of the wirings WL [1] to WL [m] is the wiring WL [j] in the circuit 104 [j] (j is any one of 1 to m). Further, the corresponding one of the wirings CONTEXT [1] to CONTEXT [m] is the wiring CONTEXT [j] in the circuit 104 [j]. Further, the terminals C _{1 to} C _m may be referred to as terminals C when there is no need to particularly limit them. Further, the terminals D _{1 to} D _m may be referred to as terminals D when there is no need to particularly limit them.

  Hereinafter, a direction in which the wiring WL and the wiring CONTEXT are extended may be referred to as a row direction, and a direction in which the circuits 104 [1] to 104 [m] are arranged may be referred to as a column direction.

Here, the terminal A of the circuit 102 is electrically connected to the output terminal of the inverter 103 in the same stage, and the terminal B of the circuit 102 is electrically connected to the input terminal of the inverter 103 in the next stage. Therefore, in this specification and the like, the terminal A of the circuit 102 may be replaced with the output terminal of the inverter 103 in the same stage. In this specification and the like, the terminal B of the circuit 102 may be replaced with the input terminal of the inverter 103 in the next stage. That is, in the circuit 104 [1] to 104 [m], the terminal _{C 1} to _{C m} is the output terminal electrically connected to the inverter 103 of the same stage of the circuit 102, terminals _{D 1} to _{D m} is the next stage It can be said that it is electrically connected to the input terminal of the inverter 103.

  As an example of a detailed configuration of the circuit 102, a configuration of the circuit 102 [i] will be described with reference to FIG.

  Each of the circuits 104 [1] to 104 [m] includes a transistor 105, a transistor 106, a transistor 107, and a capacitor 108. Hereinafter, a connection relation of the circuit 104 [j] will be described as an example of the circuit 104. Note that the connection relationships between the circuits 104 [1] to 104 [j−1] and the circuits 104 [j + 1] to 104 [m] are the same as those of the circuit 104 [j].

In the circuit 104 [j], the first terminal of the transistor 105 is electrically connected to the wiring BL, the second terminal of the transistor 105 is electrically connected to the gate of the transistor 106, and the gate of the transistor 105 is connected to the wiring WL. [J] is electrically connected. The first terminal of the transistor 106 is electrically connected to the terminal _Cj . The first terminal of the transistor 107 is electrically connected to the second terminal of the transistor 106, the second terminal of the transistor 107 is electrically connected to the terminal D _j, and the gate of the transistor 107 is a wiring CONTEXT [j]. And electrically connected. A first terminal of the capacitor 108 is electrically connected to the gate of the transistor 106, and a second terminal of the capacitor 108 is electrically connected to a wiring to which a predetermined potential is supplied.

Note that the transistors 106 and 107 need only be connected in series between the terminal C _j and the terminal D _j, and the positions of the transistors 106 and 107 may be opposite.

  The resistance value between the terminal A and the terminal B of the circuit 102 is approximately equal to the combined resistance of the resistance values between the terminals C and D of the circuits 104 [1] to 104 [m]. Therefore, switching of the resistance value between the terminal A and the terminal B of the circuit 102 is performed by controlling the resistance value between the terminal C and the terminal D in each of the circuits 104 [1] to 104 [m]. be able to.

  Each of the circuits 104 [1] to 104 [m] stores a potential in the node SN and based on the potential, the first terminal and the second terminal of the transistor 106 (hereinafter, referred to as a source and a drain in some cases). There is a function to set a resistance value between The potential is stored in the node SN by turning on the transistor 105 to input the potential of the wiring BL to the node SN and accumulating charges based on the potential of the wiring BL in the capacitor 108. it can. In addition, each of the circuits 104 [1] to 104 [m] can store an analog potential in the node SN. Thus, in each of the circuits 104 [1] to 104 [m], different potentials can be stored in the node SN, and the resistance value between the first terminal and the second terminal of the transistor 106 can be made different. When the transistor 106 is an n-channel transistor, the resistance value between the first terminal and the second terminal of the transistor 106 decreases as the potential of the node SN increases. In addition, when the transistor 106 is a p-channel transistor, the resistance value between the first terminal and the second terminal of the transistor 106 decreases as the potential of the node SN decreases.

  As the transistor 105, a transistor including an oxide semiconductor in a channel formation region is preferably used. As described later, a transistor including an oxide semiconductor in a channel formation region has low off-state current, so that leakage of charge from the capacitor 108 can be reduced. In particular, in the case where charges based on an analog potential are accumulated in the capacitor 108, there is a fear that data may be changed even by a slight change in potential compared to a digital potential. Therefore, the effect of employing a transistor including an oxide semiconductor in the channel formation region as the transistor 105 is more remarkable.

  Note that the potential stored in the node SN is preferably a potential at which the transistor 106 is turned on. Thus, the resistance value between the source and the drain of the transistor 106 can also be referred to as the on-resistance of the transistor 106.

  Note that the capacitor 108 may be omitted as long as charges based on the potential of the wiring BL can be accumulated in the parasitic capacitance of the node SN such as the gate capacitance of the transistor 106.

  Each of the circuits 104 [1] to 104 [m] has a function of switching between conduction and non-conduction between the terminal C and the terminal D. Switching between conduction and non-conduction between the terminal C and the terminal D can be performed by controlling on or off of the transistor 107. In the circuits 104 [1] to 104 [m], when the transistor 107 is on, the terminal C and the terminal D are brought into conduction, so that the resistance value between the terminal C and the terminal D is the source and drain of the transistor 106. It becomes a value depending on the resistance value between. Specifically, the resistance value between the terminal C and the terminal D is the resistance value between the source and the drain of the transistor 106 and the resistance value between the source and the drain when the transistor 107 is on. It is almost equal to the sum. On the other hand, when the transistor 107 is off, the conduction between the terminal C and the terminal D is non-conduction, so that the terminal C and the terminal D have high impedance regardless of the resistance value between the source and the drain of the transistor 106. become.

  That is, each of the circuits 104 [1] to 104 [m] makes the terminal C and the terminal D non-conductive, or sets the resistance value between the terminal C and the terminal D to a value based on the stored data. It has a function to switch between.

  Various methods can be used for switching the resistance value between the terminal A and the terminal B of the circuit 102.

  The switching of the resistance value between the terminal A and the terminal B of the circuit 102 is performed by selecting one or more circuits that make the terminal C and the terminal D conductive from the circuits 104 [1] to 104 [m]. This can be done by controlling the number. When the same data is stored in each of the circuits 104 [1] to 104 [m], the resistance value between the source and the drain of the transistor 106 is the same in each of the circuits 104 [1] to 104 [m]. is there. Therefore, the resistance value between the terminal A and the terminal B of the circuit 102 is controlled by controlling the number of the circuits that make the terminal C and the terminal D conductive among the circuits 104 [1] to 104 [m]. be able to.

  To switch the resistance value between the terminal A and the terminal B of the circuit 102, one circuit that makes the terminal C and the terminal D conductive is selected from the circuits 104 [1] to 104 [m]. Can be performed based on the data stored in the. In the case where different data is stored in each of the circuits 104 [1] to 104 [m], the resistance value between the source and the drain of the transistor 106 is different in each of the circuits 104 [1] to 104 [m]. Therefore, the resistance value between the terminal A and the terminal B of the circuit 102 can be controlled depending on which of the circuits 104 [1] to 104 [m] is selected.

  The above two examples may be appropriately combined. That is, a circuit that stores different data in at least two of the circuits 104 [1] to 104 [m] and makes the terminals C and D conductive from the circuits 104 [1] to 104 [m]. The resistance value between the terminal A and the terminal B of the circuit 102 may be switched by selecting one or more.

  By the way, in terms of improving the accuracy of the oscillation frequency, it is preferable that the oscillation frequencies corresponding to specific data are substantially equal. Specifically, in the case where specific data is stored in any one of the circuits 104 [1] to 104 [m], the oscillation occurs regardless of which of the circuits 104 [1] to 104 [m] stores the data. The frequencies are preferably approximately equal.

  As described above, the semiconductor device described in this embodiment can change the oscillation frequency by switching the delay times of the circuits 101 [1] to 101 [n]. The delay times of the circuits 101 [1] to 101 [n] are determined by the resistance values between the terminals A and B of the circuits 102 [1] to 102 [n]. The resistance value between the terminals B is controlled by data stored in the circuits 104 [1] to 104 [m].

  In other words, even if the data stored in the circuits 104 [1] to 104 [m] is the same, the oscillation frequency may change if the resistance value between the terminal A and the terminal B of the circuit 102 is different. There is.

  For example, a case where specific data is stored only in the circuit 104 [1] and a case where the same data as the specific data is stored only in the circuit 104 [m] are considered. At this time, if the wiring path from the terminal A to the terminal B via the circuit 104 [1] and the wiring path via the circuit 104 [m] have different lengths, the terminal A is selected depending on the selection of the wiring path. And the terminal B have different wiring resistances. That is, even if the same data is stored in the circuit 104 [1] and the circuit 104 [m], the oscillation frequency may be different.

  Therefore, in the semiconductor device described in this embodiment, the length of the wiring path between the terminal A and the terminal B is approximately equal in the circuit 102 regardless of which wiring path the circuit 104 is selected. Note that in this specification and the like, when it is described that “the length of A and the length of B are approximately equal” or the like, the length of A and the length of B do not have to completely match. For example, if the difference between the length of A and the length of B is in the range of 20% or less, preferably 10% or less, more preferably 5% or less of the length of A or B, it is considered to be approximately equal. Can do.

Specifically, as shown in FIG. 1, in the circuit 102, the length of the wiring path (a ₁ ) between the terminal A and the terminal C ₁ and the length of the wiring path between the terminal D ₁ and the terminal B ( b ₁ ) is the sum of the length (a ₂ ) of the wiring path between the terminal A and the terminal C ₂ and the length (b ₂ ) of the wiring path between the terminal D ₂ and the terminal B Similarly, it is also equal to the sum of the length (a _m ) of the wiring path between the terminal A and the terminal C _m and the length (b _m ) of the wiring path between the terminal D _m and the terminal B. Although not shown in FIG. 1, the same applies to the wiring path between the terminal A and the terminals C _{3 to} C _m−1 and the wiring path between the terminals D _{3 to} D _m−1 and the terminal B. .

In other words, in the semiconductor device described in this embodiment, the length of the wiring path provided between the terminal A and the terminals C _{1 to} C _{m in} the circuit 102 and between the terminals D _{1 to} D _m and the terminal B are provided. The relationship between the lengths of the given wiring paths is
a ₁ + b ₁ = a ₂ + b ₂ =... = a _m + b _m These are represented by the following formula (1).

Here, in the circuit 102 and the circuit 104 [j] (j is any one of 1 to m), the length of the wiring path between the terminal A and the terminal C _j is a _j , and the terminals D _j and B _Let b _{j be} the length of the wiring path between them. L _L represents an arbitrary length.

By the wiring provided between terminals A and C ₁ to C _m, wiring provided between terminals D ₁ to D _m and the terminal B satisfy the relationship of formula (1) in the circuit 102, the wiring Regardless of the route selection, the wiring resistance between the terminal A and the terminal B can be made approximately equal. As a result, the semiconductor device described in this embodiment can substantially equalize the oscillation frequency corresponding to specific data, so that the accuracy of the oscillation frequency can be improved.

By the way, as shown in FIG. 1, in the semiconductor device described in this embodiment, circuits 102 [1] to 102 [n] and inverters 103 [1] to 103 [n] are provided separately. That is, the inverter 103 [k ₁ ] (k ₁ is an odd number of 1 to n) is in the first region 113a, the circuits 102 [1] to [n] are in the second region 112a, and the inverter 103 [k ₂ ]. _{(k 2} is 2 or more n-1 following an even number) is provided in the third area 113b. On the substrate plane, the second region 112a is located between the first region 113a and the third region 113b.

  When attention is paid to the circuit 101 [1] and the circuit 101 [2], the inverter 103 [1] of the circuit 101 [1] is provided in the first region 113a, and the circuit 102 [1] and the circuit of the circuit 101 [1] are provided. The circuit 102 [2] of 101 [2] is provided in the second region 112a, and the inverter 103 [2] of the circuit 101 [2] is provided in the third region 113b.

As described above, since the circuits 102 [1] and [2] are provided in the region between the inverter 103 [1] and the inverter 103 [2], the terminal A in the circuit 102 [1] is on the first region 113a side. The terminal B is provided on the third region 113b side. In the circuit 102 [2], the terminal A is provided on the third region 113b side, and the terminal B is provided on the first region 113a side. At this time, the circuit 102 [1] and 102 [2] of the wiring provided between terminals A and _{C 1} to _{C m} in each wiring provided between terminals _{D 1} to _{D m} and the terminal B When viewed in a plan view, it has a shape having approximately two-fold rotational symmetry. Thus, the corresponding one of the length of the provided wires during one and the length of the wiring which is provided, the terminal D ₁ to D _m and the terminal B between the terminals A and C ₁ to C _m And the sum is constant.

  By providing the circuit 101, the circuit 102, and the inverter 103 in such a positional relationship, the wiring of the circuit 102 can be provided so as to satisfy the above formula (1) without extra routing of the wiring. Therefore, the semiconductor device described in this embodiment can improve the accuracy of the oscillation frequency while suppressing an increase in the occupied area.

If the third region 113b is not provided and all the inverters 103 are provided in the first region 113a, in the circuit 102, both the terminal A and the terminal B are provided on the first region 113a side. In this case, the relationship between the length of the wiring path provided between the terminal A and the terminals C _{1 to} C _{m in} the circuit 102 and the length of the wiring path provided between the terminals D _{1 to} D _m and the terminal B is , A ₁ + b ₁ <a ₂ + b ₂ <...... <a _m + b _m Therefore, the wiring resistance between the terminal A and the terminal B is changed by the selection of the wiring path, and the accuracy of the oscillation frequency is lowered.

  In addition, as shown by a circuit 101 [1] and a circuit 101 [2] in FIG. 1, it is preferable to provide an odd-numbered circuit 101 and an even-numbered circuit 101 in pairs. As a result, spaces corresponding to the width (the width of two circuits 102) in the direction parallel to the extending direction of the wiring CONTEXT of the odd-numbered circuit 102 and the even-numbered circuit 102 (the width corresponding to two of the circuits 102) are respectively converted into odd-numbered stages. It can be used for the inverter 103 and the even number of inverters 103. Therefore, it is effective to increase the channel width of the transistor included in the inverter 103 in a direction parallel to the extending direction of the wiring CONTEXT.

  In the structure illustrated in FIG. 1, the circuits 101 [1] to 101 [n], the circuits 102 [1] to 102 [n], and the inverters 103 [1] to 103 [n] are connected to the first region 113a and the first region 113a. Although divided into the second region 112a and the third region 113b, the semiconductor device described in this embodiment is not limited thereto. For example, as illustrated in FIG. 3, the circuits 101 [1] to 101 [n], the circuits 102 [1] to 102 [n], and the inverters 103 [1] to 103 [n] are connected to the first region 113a and the second region The first region 112a, the third region 113b, the fourth region 112b, and the fifth region 113c may be provided separately. Note that the detailed structure of the circuit 102 in FIG. 3 is omitted because FIG. 1 can be referred to.

Here, the inverter 103 [k ₃ ] (k ₃ is an odd number from 1 to (n + 1) / 2) and the inverter 103 [k ₄ ] (k ₄ is an even number from (n + 3) / 2 to n−1) Provided in the first region 113a. Further, the inverter 103 [k ₅ ] (k ₅ is an even number of 2 or more and (n−1) / 2 or less) is provided in the third region 113b. The inverter 103 [k ₆ ] (k ₆ is an odd number greater than or equal to (n + 5) / 2 and less than or equal to n) is provided in the fifth region 113c. Further, the circuit 102 [k ₇ ] (k ₇ is a natural number of 1 or more and (n + 1) / 2 or less) is provided in the second region 112a. Further, the circuit 102 [k ₈ ] (k ₈ is a natural number of (n + 3) / 2 to n) is provided in the fourth region 112b.

  On the substrate plane, the second region 112a is located between the first region 113a and the third region 113b, and the fourth region 112b is located between the first region 113a and the fifth region 113c. To do.

  Similar to the configuration shown in FIG. 1, the circuit 101, the circuit 102, and the inverter 103 are provided in such a positional relationship, so that the above-described equation (1) can be satisfied without extra wiring. Wiring can be provided. Therefore, the semiconductor device shown in FIG. 3 can improve the accuracy of the oscillation frequency while suppressing an increase in the occupied area.

  Further, similarly to the structure illustrated in FIG. 1, it is preferable to provide the odd-numbered stage circuit 101 and the even-numbered stage circuit 101 in pairs. As a result, spaces corresponding to the width (in the row direction) parallel to the extending direction of the wiring CONTEXT of the odd-numbered circuit 102 and the even-numbered circuit 102 are used for the odd-numbered inverter 103 and the even-numbered inverter 103, respectively. be able to. Therefore, it is effective to increase the channel width of the transistor included in the inverter 103 in a direction parallel to the extending direction of the wiring CONTEXT.

  Note that as the ratio of the resistance value of the transistor 106 to the resistance value between the terminal A and the terminal B increases, the amount of change in the oscillation frequency with respect to the resistance value between the source and the drain of the transistor 106 can be increased. it can. Therefore, W (channel width) of the transistor 106 is preferably smaller than W of the transistor 107. Alternatively, W of the transistor 106 is preferably smaller than W of any one or all of the transistors included in the inverter 103 or a circuit that can be used instead of the inverter 103.

  Note that as described above, a NAND circuit or a NOR circuit may be employed instead of the inverter 103. In the NAND circuit or the NOR circuit, an output terminal of the NAND circuit or the NOR circuit corresponds to an output terminal of the inverter 103, and a first input terminal of the NAND circuit or the NOR circuit corresponds to an input terminal of the inverter 103. That is, the output terminal of the NAND circuit or the NOR circuit is connected to the terminal A of the circuit 102, and the first input terminal is connected to the terminal B of the circuit 102 in the previous stage. In each of the circuits 101 [1] to 101 [n], the second input terminal of the NAND circuit or the NOR circuit is preferably connected to the same wiring. Then, the potential of the terminal A of the circuit 102 can be fixed by controlling the potential of the wiring to which the second input terminal of the NAND circuit or the NOR circuit is connected. Therefore, since the potential of the wiring BL can be input to the gate of the transistor 106 with the potential of the first terminal of the transistor 106 fixed, the potential difference between the gate and the source of the transistor 106 can be accurately set. Can do. Therefore, the resistance value between the source and the drain of the transistor 106 can be set accurately.

  With the above structure, the semiconductor device described in this embodiment can provide a novel circuit structure. Alternatively, the semiconductor device described in this embodiment can switch an oscillation frequency or provide a circuit configuration capable of realizing it. Alternatively, the semiconductor device described in this embodiment can improve the accuracy of the oscillation frequency or provide a circuit configuration capable of realizing it.

  Next, an example of the operation of the apparatus illustrated in FIG. 1 will be described with reference to the timing chart of FIG. 4 illustrates the potential of the node SN of the wiring BL, the wirings CONTEXT [1] to CONTEXT [m], the wirings WL [1] to WL [m], the circuits 104 [1] to 104 [m], and the output terminal OUT. An example of a potential is shown.

  Note that since the operations of the circuits 101 [1] to 101 [n] are the same, only one operation of the circuits 101 [1] to 101 [n] will be described.

  First, data is stored in each of the circuits 104 [1] to 104 [m], and a resistance value between the source and the drain of the transistor 106 is set based on the data.

  At time t0, the wiring WL [1] is set high and the wiring BL is set to the potential V1. Accordingly, the circuit 104 [1] operates as follows. Since the transistor 105 is turned on, the potential V1 of the wiring BL is input to the node SN through the transistor 105, and electric charge based on the potential V1 is accumulated in the capacitor 108. After that, when the wiring WL [1] is set to a low level, the transistor 105 is turned off, so that the node SN is maintained at the potential V1 by the charge accumulated in the capacitor 108. Thus, data based on the potential V1 is stored in the circuit 104 [1].

  At time t1, the wiring WL [2] is set high and the wiring BL is set to the potential V2. Accordingly, the circuit 104 [2] operates as follows. Since the transistor 105 is turned on, the potential V2 of the wiring BL is input to the node SN through the transistor 105, and electric charge based on the potential V2 is accumulated in the capacitor 108. After that, when the wiring WL [2] is set to a low level, the transistor 105 is turned off, so that the node SN is maintained at the potential V2 by the charge accumulated in the capacitor 108. Thus, data based on the potential V2 is stored in the circuit 104 [2].

  Even after the time t2, the wirings WL [3] to WL [m-1] are sequentially set to a high level, and the potentials of the wirings BL are appropriately set in accordance therewith, whereby the circuits 104 [3] to 104 [m-1] are set. Data based on the potential of the wiring BL is stored.

  At time t3, the wiring WL [m] is set high and the wiring BL is set to the potential Vm. As a result, the circuit 104 [m] operates as follows. Since the transistor 105 is turned on, the potential Vm of the wiring BL is input to the node SN through the transistor 105 and electric charge based on the potential Vm is accumulated in the capacitor 108. After that, when the wiring WL [m] is set to a low level, the transistor 105 is turned off, so that the node SN is maintained at the potential Vm by the charge accumulated in the capacitor 108. Thus, data based on the potential Vm is stored in the circuit 104 [m].

  As described above, the wirings WL [1] to [m] are sequentially set to a high level and the potential of the wiring BL is set as appropriate, so that the circuits 104 [1] to 104 [m] are based on the potential of the wiring BL. Data can be stored sequentially.

  Note that at the times t0 to t4, the wirings CONTEXT [1] to CONTEXT [m] may be set to a high level or a low level. That is, in each of the circuits 104 [1] to 104 [m], the transistor 107 may be on or off. FIG. 4 illustrates the case where the transistors 107 are turned off in each of the circuits 104 [1] to 104 [m] by setting the wirings CONTEXT [1] to CONTEXT [m] to a low level at time t0 to t4. Is illustrated. Accordingly, since the terminals C and D are non-conductive in each of the circuits 104 [1] to 104 [m], the terminals A and B of the circuit 102 have high impedance. Therefore, the apparatus illustrated in FIG. 1 does not oscillate from time t0 to t4. In each of the circuits 104 [1] to 104 [m], the transistor B is turned off, so that the terminal B is brought into a floating state. Therefore, the potential of the terminal B gradually becomes a predetermined potential such as ground. For example, when the potential at the terminal B is a potential corresponding to a low level, the output of the inverter 103 at the next stage is a high level potential. That is, the potential of the terminal A can be fixed. Therefore, since the potential of the wiring BL can be input to the gate of the transistor 106 with the potential of the first terminal of the transistor 106 fixed, the potential difference between the gate and the source of the transistor 106 can be accurately set. Can do. Therefore, the resistance value between the source and the drain of the transistor 106 can be set accurately.

  FIG. 4 illustrates the case where the potentials V1 to Vm have the same value. However, it is not limited to this.

  Note that the potential of the wiring BL stored in the circuit 104 [j] is denoted as a potential Vj.

  Note that FIG. 4 illustrates the case where the wirings WL [1] to WL [m] are sequentially set to a high level, but the present invention is not limited to this operation. The wirings WL [1] to WL [m] may be set to the high level in any order. Two or more of the wirings WL [1] to WL [m] may be simultaneously set to the high level. The wirings WL [1] to WL [m] may include wirings that are not set to a high level. Moreover, you may combine the matter mentioned above.

  Note that FIG. 4 illustrates the case where the transistor 105 is turned on by setting the wirings WL [1] to WL [m] to a high level; however, the operation is not limited thereto. The transistor 105 may be turned on by setting the wirings WL [1] to WL [m] to a low level. The potentials of the wirings WL [1] to WL [m] where the transistor 105 is turned on are referred to as active, and the potentials of the wirings WL [1] to WL [m] where the transistor 105 is turned off are inactive (also referred to as inactive). You may call it. Similarly, the potentials of the wirings CONTEXT [1] to CONTEXT [m] in which the transistor 107 is turned on are referred to as active, and the potentials of the wirings CONTEXT [1] to CONTEXT [m] in which the transistor 107 is turned off are referred to as inactive. Good.

  Next, in each of the circuits 104 [1] to 104 [m], the resistance value between the terminal A and the terminal B of the circuit 102 is switched by controlling conduction or non-conduction between the terminal C and the terminal D. . Then, the frequency of the signal at the terminal OUT is changed based on the resistance value between the terminal A and the terminal B of the circuit 102.

  At time t4, the wiring CONTEXT [1] is set to a high level, and the wirings CONTEXT [2] to CONTEXT [m] are set to a low level. Accordingly, in the circuit 104 [1], the transistor 107 is turned on, so that the resistance value between the terminal C and the terminal D becomes a value based on the resistance value between the source and the drain of the transistor 106. That is, the resistance value between the terminal C and the terminal D of the circuit 104 [1] is a value based on the stored data. In each of the circuits 104 [2] to 104 [m], the transistor 107 is turned off, so that the terminal C and the terminal D are brought out of conduction. Therefore, the frequency of the signal at the terminal OUT is determined based on data stored in the circuit 104 [1].

  At time t5, the wirings CONTEXT [1] to CONTEXT [2] are set to high level, and the wirings CONTEXT [3] to [m] are set to low level. Accordingly, in each of the circuits 104 [1] to 104 [2], the transistor 107 is turned on, so that the resistance value between the terminal C and the terminal D is the resistance value between the source and the drain of the transistor 106. The value is based on. That is, the resistance value between the terminal C and the terminal D of the circuits 104 [1] to 104 [2] is a value based on the stored data. Further, since the transistors 107 in the circuits 104 [3] to [m] are turned off, the terminal C and the terminal D are brought out of conduction. Thus, the frequency of the signal at the terminal OUT is determined based on data stored in the circuits 104 [1] to 104 [2].

  At time t5, terminals C and D are electrically connected in two of the circuits 104 [1] to 104 [m], whereas at time t4, one of the circuits 104 [1] to 104 [m] is 1 In one circuit, terminal C and terminal D are conducted. Therefore, the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t5 is smaller than the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t4. The frequency of the signal at the terminal OUT determined at t5 is higher than the frequency of the signal at the terminal OUT determined at time t4.

  At time t6, the wirings CONTEXT [1] to CONTEXT [m] are set to a high level. Accordingly, in the circuits 104 [1] to [m], each transistor 107 is turned on, and thus the resistance value between the terminal C and the terminal D is based on the resistance value between the source and the drain of the transistor 106. Value. That is, the resistance value between each of the terminals C and D of the circuits 104 [1] to 104 [m] is a value based on the stored data. Thus, the frequency of the signal at the terminal OUT is determined based on data stored in the circuits 104 [1] to 104 [m].

  At time t6, the terminals C and D are electrically connected in the m circuits among the circuits 104 [1] to 104 [m], whereas at the time t4, the terminals C and 104D are connected. In one circuit, the terminal C and the terminal D are brought into conduction, and at time t5, the terminal C and the terminal D are conducted in two circuits out of the circuits 104 [1] to [m]. Therefore, the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t6 is smaller than the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t4 and the time t5. Therefore, the frequency of the signal at the terminal OUT determined at time t6 is higher than the frequency of the signal at the terminal OUT determined at time t4 and time t5.

  As described above, the frequency of the signal at the terminal OUT can be changed based on the number of circuits in which the terminal C and the terminal D are electrically connected among the circuits 104 [1] to 104 [m].

  Note that FIG. 4 illustrates the case where the potentials V1 to Vm of the wiring BL have the same value, that is, the case where the same data is stored in each of the circuits 104 [1] to [m]. It is not limited to. For example, the potentials V1 to Vm of the wiring BL may be different from each other. That is, different data may be stored in each of the circuits 104 [1] to 104 [m]. Alternatively, at least two of the potentials V1 to Vm of the wiring BL may have different values. That is, different data may be stored in at least two of the circuits 104 [1] to 104 [m].

  FIG. 5 illustrates the case where the potential of the wiring BL is increased each time the wirings WL [1] to WL [m] are at a high level. The potentials V1 to Vm have such a relationship that the potential Vj is higher than the potential Vj-1 and lower than the potential Vj + 1, such that the potential V2 is higher than the potential V1 and the potential Vm is higher than the potential Vm-1.

  FIG. 5 illustrates a case where the wiring CONTEXT [1] is set to a high level at time t4, the wiring CONTEXT [2] is set to a high level at time t5, and the wiring CONTEXT [m] is set to a high level at time t6. That is, the frequency of the signal at the terminal OUT is determined based on the data stored in the circuit 104 [1] at time t4, and determined based on the data stored in the circuit 104 [2] at time t5. At time t6, the determination is made based on the data stored in the circuit 104 [m].

  Since the potential V2 is higher than the potential V1, the resistance value between the source and the drain of the transistor 106 in the circuit 104 [2] is smaller than the resistance value between the source and the drain of the transistor 106 in the circuit 104 [1]. Become. Therefore, the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t5 is smaller than the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t4. The frequency of the signal at the terminal OUT determined at t5 is higher than the frequency of the signal at the terminal OUT determined at time t4.

  Since the potential Vm is higher than the potential V1 and the potential V2, the resistance value between the source and the drain of the transistor 106 in the circuit 104 [m] is the source and the drain of the transistor 106 in the circuit 104 [1] and the circuit 104 [2]. It becomes smaller than the resistance value between. Therefore, the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t6 is smaller than the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t4 and the time t5. Therefore, the frequency of the signal at the terminal OUT determined at time t6 is higher than the frequency of the signal at the terminal OUT determined at times t4 and t5.

  As described above, the frequency of the signal of the terminal OUT can be changed based on data stored in a circuit in which the terminal C and the terminal D are electrically connected among the circuits 104 [1] to 104 [m].

  FIG. 6 illustrates the case where the potentials V1 to Vm-1 are the same value and the potential Vm is lower than the potentials V1 to Vm-1.

  In FIG. 6, the wiring CONTEXT [m] is set to a high level at time t4, the wiring CONTEXT [1] is set to a high level at time t5, and the wirings CONTEXT [1] to CONTEXT [2] are set to a high level at time t6. Illustrate. That is, the frequency of the signal at the terminal OUT is determined based on the data stored in the circuit 104 [m] at time t4, and determined based on the data stored in the circuit 104 [1] at time t5. At time t6, it is determined based on data stored in the circuits 104 [1] to 104 [2].

  Since the potential V1 is higher than the potential Vm, the resistance value between the source and the drain of the transistor 106 in the circuit 104 [1] is smaller than the resistance value between the source and the drain of the transistor 106 in the circuit 104 [m]. Become. Therefore, the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t5 is smaller than the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t4. The frequency of the signal at the terminal OUT determined at t5 is higher than the frequency of the signal at the terminal OUT determined at time t4.

  At time t6, the terminals C and D of the circuits 104 [1] to 104 [2] are electrically connected, whereas at time t5, the circuit 104 [1] terminal C and the terminal D are electrically connected. Therefore, the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t6 is smaller than the resistance value between the terminal A and the terminal B of the circuit 102 set at the time t5. The frequency of the signal at the terminal OUT determined at t6 is higher than the frequency of the signal at the terminal OUT determined at time t5.

  As described above, the operations illustrated in FIGS. 4 and 5 may be combined.

  Next, a method of storing data in each of the circuits 104 [1] to 104 [m] for accurately setting the frequency of the signal at the terminal OUT will be described with reference to FIG.

  For convenience, the case where m is 2 will be described. That is, the circuit 102 includes a circuit 104 [1] and a circuit 104 [2].

  Note that as an initial state, data is not stored in the circuit 104 [1] and the circuit 104 [2]. That is, in each of the circuits 104 [1] and 104 [2], the potential of the node SN is a potential at which the transistor 106 is turned off.

  At time t0, the wiring CONTEXT [1] is set to a high level. Accordingly, the transistor 107 is turned on in the circuit 104 [1]. However, since the transistor 106 is off, the terminal C and the terminal D are brought out of conduction. Therefore, the device illustrated in FIG. 1 does not oscillate.

  At time t1, the wiring WL [1] is set high and the wiring BL is set to the potential V1. Accordingly, in the circuit 104 [1], the transistor 105 is turned on, so that the potential V1 of the wiring BL is input to the node SN through the transistor 105, and charges based on the potential V1 are accumulated in the capacitor 108. The The resistance value between the source and drain of the transistor 106 is a value based on the potential V1. In the circuit 104 [1], since the transistor 107 is on, the device illustrated in FIG. 1 oscillates and the frequency of the signal at the terminal OUT becomes f (V1).

  At time t2, the wiring CONTEXT [1] is set to a low level. Accordingly, in the circuit 104 [1], the transistor 107 is turned off. Therefore, the apparatus illustrated in FIG. 1 does not oscillate.

  At a time t3, the wiring CONTEXT [2] is set to a high level. Accordingly, in the circuit 104 [2], the transistor 107 is turned on. However, since the transistor 106 is off, the terminal C and the terminal D are brought out of conduction. Therefore, the device illustrated in FIG. 1 does not oscillate.

  At time t4, the wiring WL [2] is set high and the wiring BL is set to the potential V2. Accordingly, in the circuit 104 [2], the transistor 105 is turned on, so that the potential V2 of the wiring BL is input to the node SN through the transistor 105, and charges based on the potential V2 are accumulated in the capacitor 108. The The resistance value between the source and the drain of the transistor 106 is a value based on the potential V2. In the circuit 104 [2], since the transistor 107 is on, the device illustrated in FIG. 1 oscillates and the frequency of the signal at the terminal OUT becomes f (V2).

  At time t5, the wiring CONTEXT [2] is set to a low level. Accordingly, the transistor 107 is turned off in the circuit 104 [2]. Therefore, the apparatus illustrated in FIG. 1 does not oscillate.

  At a time t6, the wiring CONTEXT [1] is set to a high level. Accordingly, the transistor 107 is turned on in the circuit 104 [1]. Therefore, the apparatus illustrated in FIG. 1 oscillates. However, since the transistor 106 is on in the circuit 104 [2] at the time t6, the load between the terminal A and the terminal B of the circuit 102 is increased as compared with the time t1. Therefore, the frequency of the signal at the terminal OUT at time t6 is lower than the frequency f (V1) of the signal at the terminal OUT at time t1.

  At time t7, the wiring WL [1] is set high and the wiring BL is set to the potential V1 '. Accordingly, in the circuit 104 [1], the transistor 105 is turned on, so that the potential V1 ′ of the wiring BL is input to the node SN through the transistor 105, and the charge based on the potential V1 ′ is supplied to the capacitor 108. Accumulated. The resistance value between the source and drain of the transistor 106 is a value based on the potential V1 '. In the circuit 104 [1], since the transistor 107 is on, the device illustrated in FIG. 1 oscillates. Here, the potential V1 'is a value that sets the frequency of the signal at the terminal OUT at time t7 to f (V1), and is higher than the potential V1. Therefore, the frequency of the signal at the terminal OUT is substantially equal to f (V1).

  At time t8, the wiring CONTEXT [1] is set to a low level. Accordingly, in the circuit 104 [1], the transistor 107 is turned off. Therefore, the apparatus illustrated in FIG. 1 does not oscillate.

  At a time t9, the wiring CONTEXT [2] is set to a high level. Accordingly, in the circuit 104 [2], the transistor 107 is turned on. Therefore, the apparatus illustrated in FIG. 1 oscillates. Note that the potential of the node SN of the circuit 104 [1] at time t9 is higher than the potential of the node SN of the circuit 104 [1] at time t4. That is, the resistance value between the source and the drain of the transistor 106 in the circuit 104 [1] at time t9 is smaller than the resistance value between the source and the drain of the transistor 106 in the circuit 104 [1] at the time t4. Yes. Alternatively, the gate capacitance of the transistor 106 in the circuit 104 [1] at time t9 is larger than the gate capacitance of the transistor 106 in the circuit 104 [1] at time t4. Therefore, the load between the terminal A and the terminal B of the circuit 102 at time t9 is increased as compared with the time t4. Therefore, the frequency of the signal at the terminal OUT at time t9 is lower than the frequency f (V2) of the signal at the terminal OUT at time t4.

  At time t10, the wiring WL [2] is set high and the wiring BL is set to the potential V2 '. Accordingly, in the circuit 104 [2], the transistor 105 is turned on, so that the potential V2 ′ of the wiring BL is input to the node SN through the transistor 105, and the charge based on the potential V2 ′ is supplied to the capacitor 108. Accumulated. The resistance value between the source and the drain of the transistor 106 is a value based on the potential V2 '. In the circuit 104 [2], since the transistor 107 is on, the device illustrated in FIG. 1 oscillates. Here, the potential V2 'is a value that sets the frequency of the signal at the terminal OUT at time t10 to f (V2), and is higher than the potential V2. Therefore, the frequency of the signal at the terminal OUT is approximately equal to f (V2).

  At time t11, the wiring CONTEXT [2] is set to a low level. Accordingly, the transistor 107 is turned off in the circuit 104 [2]. Therefore, the apparatus illustrated in FIG. 1 does not oscillate.

  After that, by repeating the operation from time t6 to t11, the frequency of the signal at the terminal OUT when the wiring CONTEXT [1] is set to high level is converged to f (V1), and the wiring CONTEXT [2] is set to high level. Then, the frequency of the signal at the terminal OUT can be converged to f (V2).

  With the above structure, the semiconductor device described in this embodiment can provide a novel circuit structure. Alternatively, the semiconductor device described in this embodiment can switch an oscillation frequency or provide a circuit configuration capable of realizing it. Alternatively, the semiconductor device described in this embodiment can improve the accuracy of the oscillation frequency or provide a circuit configuration capable of realizing it.

  This embodiment can be implemented in appropriate combination with the configurations disclosed in this specification and the like of other embodiments.

(Embodiment 2)
In this embodiment, a PLL using the apparatus described in Embodiment 1 will be described.

  The PLL illustrated in FIG. 8 includes a phase comparator 201, a loop filter 202, a voltage controlled oscillator 203, and a frequency divider 204.

  The phase comparator 201 has a function of detecting a phase difference between two input signals and outputting a detection result as a voltage signal. In other words, the phase comparator 201 has a function of outputting a phase difference between a fin frequency signal and a fout / N frequency signal as a voltage signal.

  The loop filter 202 has a function of generating a DC voltage signal DATA to be input to the voltage controlled oscillator 203. The loop filter 202 has a function of removing high frequency components contained in the output signal of the phase comparator 201. As the loop filter 202, there is a low-pass filter.

  The voltage controlled oscillator 203 has a function of outputting a clock signal indicating a specific oscillation frequency depending on DATA. As the voltage controlled oscillator 203, the apparatus illustrated in FIG. 1 can be employed. Note that DATA corresponds to the potential of the wiring BL. The apparatus illustrated in FIG. 1 may output a signal through a buffer as shown in FIG.

  The frequency divider 204 has a function of generating a clock signal obtained by changing the clock signal indicating the specific oscillation frequency output from the voltage controlled oscillator 203 to 1 / N times.

  Note that DATA corresponds to the potential of the wiring BL. DATA can be controlled by changing N in the frequency divider 204. That is, the data stored in each of the circuits 101 [1] to 101 [n] of the voltage controlled oscillator 203 can be controlled by changing N in the frequency divider 204.

  This embodiment can be implemented in appropriate combination with the configurations disclosed in this specification and the like of other embodiments.

(Embodiment 3)
<Example of planar structure and cross-sectional structure of semiconductor device>
In this embodiment, an example of the structure of the semiconductor device described in the above embodiment will be described with reference to FIGS.

  Note that the structure described below is merely an example of the semiconductor device described in the above embodiment, and the specific structure of the semiconductor device, such as a material and a structure to be used, is not necessarily limited to that shown here.

  In the above embodiment, an example of a structure in the case where m = 2 is described with reference to FIGS. 9 and 10 for the circuits 104 [1] and 104 [2] illustrated in FIGS. 9A and 9B are plan views of the circuit 104 [1] and the circuit 104 [2]. FIG. 10 is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 and alternate long and short dash line X3-X4 shown in FIGS. 9A and 9B.

  9A is a plan view showing the main structure located below the insulating film 314 shown in FIG. 10, and FIG. 9B is a main view located above the insulating film 314 shown in FIG. It is the top view which showed the structure. In FIG. 9, the reference numerals and detailed description of the structure of the circuit 104 [2] that overlaps the circuit 104 [1] are omitted, and the description of the structure of the circuit 104 [1] is omitted. Can be considered.

  As an example of the semiconductor device illustrated in FIGS. 9 and 10, a transistor 106 [1] and a transistor 107 [1] using a first semiconductor material as a channel formation region are formed in a lower portion, and a second semiconductor material is channeled in an upper portion. The case where the transistor 105 [1] used for the formation region is formed is described.

  The first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide), and the second semiconductor material can be an oxide semiconductor. A transistor using single crystal silicon as a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor has low off-state current.

  Note that the semiconductor device according to one embodiment of the present invention is not limited to this, and the transistor 105, the transistor 106, and the transistor 107 may be formed using the same semiconductor material. In this case, the transistor 105, the transistor 106, and the transistor 107 can be formed in the same layer.

  The transistor 106 [1] and the transistor 107 [1] are formed over the insulating film 310 formed over the substrate 300.

  The transistor 106 [1] includes a semiconductor film 320 formed over the insulating film 310, a gate insulating film 322a formed over the semiconductor film 320, a gate electrode 324a provided over the gate insulating film 322a, and gate insulation. And a sidewall insulating film 326a provided on the film 322a so as to be in contact with the side surface of the gate electrode 324a. The transistor 106 [1] includes a channel formation region 320f in a portion overlapping with the gate electrode 324a of the semiconductor film 320, and the impurity region 320a and the impurity region 320b are provided so as to sandwich the channel formation region 320f. The impurity region 320a and the impurity region 320b function as a source region or a drain region of the transistor 106 [1]. In the semiconductor film 320, the impurity region 320d is preferably provided in a region overlapping with the sidewall insulating film 326a between the impurity region 320a and the impurity region 320b and the channel formation region 320f. The impurity region 320d preferably functions as an LDD (Lightly Doped Drain) region having a lower impurity concentration than the impurity regions 320a and 320b.

  The transistor 107 [1] includes a semiconductor film 320 formed over the insulating film 310, a gate insulating film 322b formed over the semiconductor film 320, a gate electrode 324b provided over the gate insulating film 322b, A sidewall insulating film 326b provided on the gate insulating film 322b so as to be in contact with the side surface of the gate electrode 324b; The transistor 107 [1] includes a channel formation region 320g in a portion overlapping with the gate electrode 324b of the semiconductor film 320, and the impurity region 320b and the impurity region 320c are provided so as to sandwich the channel formation region 320g. The impurity region 320b and the impurity region 320c function as a source region or a drain region of the transistor 107 [1]. In the semiconductor film 320, the impurity region 320e is preferably provided in a region overlapping with the sidewall insulating film 326b between the impurity region 320b and the impurity region 320c and the channel formation region 320g. Impurity region 320e preferably functions as an LDD region having a lower impurity concentration than impurity region 320b and impurity region 320c.

  Here, the semiconductor film 320 can be formed using a semiconductor such as silicon, silicon carbide, germanium, or silicon germanium which is amorphous, microcrystalline, polycrystalline, or single crystal. In the case where the semiconductor film 320 is formed using a silicon thin film, the thin film is processed by vapor deposition such as a plasma CVD method or amorphous silicon manufactured by a sputtering method or laser annealing or the like. It is possible to use polycrystalline silicon crystallized by the above, single crystal silicon in which hydrogen ions are implanted into a single crystal silicon wafer and the surface layer portion is peeled off.

  The insulating film 310 includes, for example, aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and oxide. An insulator containing one or more selected from hafnium, tantalum oxide, and the like can be used. The gate insulating film 322a, the gate insulating film 322b, the sidewall insulating film 326a, and the sidewall insulating film 326b can also be formed using the above insulating film that can be used for the insulating film 310.

  As the substrate 300, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, or a compound semiconductor substrate made of silicon germanium can be used.

  Further, an insulating substrate may be used as the substrate 300. Examples of the insulating substrate include a glass substrate, a quartz substrate, a plastic substrate, a flexible substrate, a bonded film, paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, and papers.

  In this embodiment mode, an SOI (Silicon on Insulator) substrate in which the insulating film 310 is provided over the substrate 300 and the semiconductor film 320 is provided over the insulating film 310 is illustrated, but the structure is limited to this. It is not a thing. For example, a transistor may be formed on a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate by an element isolation method. As an element isolation method, a trench isolation method (STI method: Shallow Trench Isolation), a LOCOS (Local Oxidation of Silicon) method, or the like can be used. As the substrate 300, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, or the like may be used.

  As the gate electrode 324a and the gate electrode 324b, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, or the like, or an alloy material or a compound material containing these metals as main components. Alternatively, polycrystalline silicon to which an impurity such as phosphorus is added can be used. Alternatively, the gate electrode 324a and the gate electrode 324b may be formed using a stacked structure of a metal nitride film and the above metal film. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

  The impurity regions 320 a to 320 e are formed by adding an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity to the semiconductor film 320. Phosphorus (P), arsenic (As), or the like may be used as an impurity element imparting n-type, and boron (B), aluminum (Al), or the like may be used as an impurity element imparting p-type.

  An insulating film 311 is formed over the transistors 106 [1] and 107 [1], and conductive films 328a to 328c are formed over the insulating film 311. The conductive film 328 a is connected to the impurity region 320 a through an opening provided in the insulating film 311, the conductive film 328 b is connected to the impurity region 320 c through an opening provided in the insulating film 311, and the conductive film 328 c is The gate electrode 324a is connected through an opening provided in the insulating film 311.

  Here, the conductive film 328a functions as one of the source electrode and the drain electrode of the transistor 106 [1], and the conductive film 328b functions as one of the source electrode and the drain electrode of the transistor 107 [1]. Note that the transistor 106 [1] and the transistor 107 [1] illustrated in FIGS. 10A and 10B explicitly do not have the other of the source electrode and the drain electrode, but may be referred to as transistors including elements in such a state for convenience. is there. In this case, in order to describe the connection relation of the transistors, the source and drain electrodes including the source and drain regions may be expressed.

  As the conductive films 328a to 328c, copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co) low-resistance material alone, an alloy of low-resistance material, or these as a main component It is preferable to form a single layer or a stacked layer of a conductive film containing the compound to be processed. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. The conductive films 328a to 328c are preferably formed using a low-resistance conductive material such as aluminum or copper. Further, it is preferable to use a Cu—Mn alloy for the conductive films 328 a to 328 c because manganese oxide is formed at the interface with the insulator containing oxygen and the manganese oxide has a function of suppressing diffusion of Cu. The conductive films 328a to 328c and the like can be formed by a sputtering method, a CVD method, or the like.

  The insulating film 311 can be formed using the above insulating film that can be used for the insulating film 310. The insulating film 311 can also be formed using an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin.

  Note that when the insulating film 311 is formed by a CVD method, the hydrogen content of the insulating film 311 is increased. By performing heat treatment in the presence of such an insulating film 311, the semiconductor film 320 can be hydrogenated, dangling bonds can be terminated with hydrogen, and defects in the semiconductor film 320 can be reduced. In this manner, by terminating dangling bonds in the semiconductor film 320, the reliability of the transistor 106 [1] and the transistor 107 [1] can be improved.

  The insulating film 312 is formed over the conductive films 328 a to 328 c and the insulating film 311, and the conductive films 330 a to 330 c, the conductive film 332, the conductive film 334, and the conductive film 336 are formed over the insulating film 312. Yes. The conductive film 330 a is connected to the conductive film 328 a through an opening provided in the insulating film 312, the conductive film 330 b is connected to the conductive film 328 b through an opening provided in the insulating film 312, and the conductive film 330 c is The conductive film 328 c is connected through an opening provided in the insulating film 312. Although not illustrated in FIG. 10, the conductive film 332 is gated through an opening provided in the insulating film 312 and the insulating film 311 in the same manner as the conductive film 330 c is electrically connected to the gate electrode 324 a. It is electrically connected to the electrode 324b.

  Here, the conductive film 332 is provided to extend in the row direction in FIG. 9A and functions as the wiring CONTEXT [1] described in the above embodiment. The conductive film 334 functions as the second terminal of the capacitor 108 [1]. Note that the conductive film 334 is provided so as to extend in the row direction in FIG. 9A. In the circuits 104 [1] to 102 [n] in the circuits 102 [1] to 102 [n], the first conductive elements 334 [1] 2 functions as a terminal.

  The conductive film 336 functions as a back gate of the transistor 105 [1]. By providing such a conductive film 336, the threshold voltage of the transistor 105 [1] can be controlled. The conductive film 336 may be in a floating state where it is electrically insulated, or may be in a state where a potential is applied from another wiring. The state of the conductive film 336 can be set as appropriate in accordance with control of the threshold voltage of the transistor 105 [1]. Note that the conductive film 336 is provided so as to extend in the row direction in FIG. 9A, and the back gate of the transistor 105 [1] is included in the circuit 104 [1] of the circuits 102 [1] to 102 [n]. Function as. The transistor 105 [1] only needs to have at least one gate electrode, and the conductive film 336 functioning as a back gate is not necessarily provided.

  The conductive films 330a to 330c, the conductive film 332, the conductive film 334, and the conductive film 336 can be formed using any of the above materials that can be used for the conductive films 328a and 328b.

  The insulating film 312 can be formed using the above insulating film that can be used for the insulating film 310. The insulating film 312 can be formed using an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin.

  Note that the insulating film 312 is preferably improved in planarity by performing a planarization process such as a CMP (Chemical Mechanical Polishing) method.

  An insulating film 314 is formed over the insulating film 313, and an insulating film 315 is formed over the insulating film 314.

  As described above, the dangling bonds of silicon were terminated with hydrogen in the insulating film 311 and the like provided in the vicinity of the semiconductor film 320 of the transistor 106 [1] and the transistor 107 [1]. However, since hydrogen in the insulating film provided in the vicinity of the oxide semiconductor film 340 of the transistor 105 [1] is one of the factors that generate carriers in the oxide semiconductor, the reliability of the transistor 105 [1] is increased. It may be a factor to reduce. Therefore, the insulating film 314 located between the transistor 106 [1] and the transistor 107 [1] provided in the lower layer and the transistor 105 [1] provided in the upper layer has a function of preventing hydrogen diffusion. Providing an insulating film is particularly effective. In addition to improving the reliability of the transistor 106 [1] and the transistor 107 [1] by confining hydrogen in the lower layer with the insulating film 314, the insulating film 314 suppresses diffusion of hydrogen from the lower layer to the upper layer. Thus, the reliability of the transistor 105 [1] can be improved at the same time.

  Examples of the insulating film 314 include silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and yttria-stabilized zirconia (YSZ). Etc. can be used.

  The insulating film 315 is preferably formed using an oxide insulating film from which part of oxygen is released by heating. As the oxide insulating film from which part of oxygen is released by heating, an oxide insulating film containing more oxygen than that in the stoichiometric ratio is used. As the insulating film 315, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, or aluminum oxynitride can be used as a single layer or a stacked layer.

  Note that the insulating film 315 is preferably planarized by a CMP method or the like to improve planarity.

  The transistor 105 [1] is formed over the insulating film 315. The transistor 105 [1] includes an oxide semiconductor film 340 over the insulating film 315, a conductive film 344a and a conductive film 344b which are electrically connected to the oxide semiconductor film 340 and function as a source electrode or a drain electrode, The gate insulating film 346 is formed over and in contact with the oxide semiconductor film 340 and the gate electrode 348 overlaps with the oxide semiconductor film 340 with the gate insulating film 346 interposed therebetween. The conductive film 344a functions as a first terminal of the capacitor 108 [1].

  Here, the case where the oxide semiconductor film 340 includes the oxide semiconductor films 340 a to 340 c sequentially stacked over the insulating film 315 is illustrated. Note that in one embodiment of the present invention, the oxide semiconductor film 340 included in the transistor 105 [1] may be a single metal oxide film.

  A conductive film 342a and a conductive film 342b are also formed over the insulating film 315. The conductive film 342a is connected to the conductive film 330a through an opening provided in the insulating films 313 to 315, and the conductive film 342b is connected to the conductive film 330b through an opening provided in the insulating films 313 to 315. The conductive film 344a is connected to the conductive film 330c through an opening provided in the insulating films 313 to 315.

  The conductive films 342a, 342b, 344a, and 344b can be formed using any of the above materials that can be used for the conductive films 328a and 328b.

  The gate insulating film 346 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film containing one or more of them can be used. The gate insulating film 346 may be a stacked layer of the above materials. Note that the gate insulating film 346 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity.

  An example of a stacked structure of the gate insulating film 346 will be described. The gate insulating film 346 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, the gate insulating film 346 preferably contains hafnium oxide and silicon oxide or silicon oxynitride. Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, when hafnium oxide is used, the gate insulating film 346 can be made thicker than when silicon oxide is used. Therefore, even when the equivalent oxide film thickness is 10 nm or less or 5 nm or less, the leakage due to the tunnel current is caused. The current can be reduced. That is, a transistor with a small off-state current can be realized.

  Here, the gate electrode 348 is provided so as to extend in the row direction in FIG. 9B and functions as the wiring WL [1] described in the above embodiment.

  The gate electrode 348 is formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy including any of the above metal elements, or an alloy combining any of the above metal elements. can do. Alternatively, a metal element selected from one or more of manganese and zirconium may be used. The gate electrode 348 may have a single-layer structure or a stacked structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film There are a layer structure, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film, a titanium film, and a three-layer structure in which an aluminum film is stacked on the titanium film and a titanium film is further formed thereon. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

  The gate electrode 348 includes indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal element can be employed.

  Note that a transistor including a channel formation region in an oxide semiconductor film and a detailed description of the oxide semiconductor film will be described later.

  An insulating film 316 is formed over the transistor 105 [1] and the insulating film 315, and an insulating film 317 is formed over the insulating film 316.

  The insulating film 316 preferably has a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. As the insulating film 316, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

  An aluminum oxide film is preferable for application to the insulating film 316 because it has a high blocking effect of preventing both hydrogen, moisture and other impurities, and oxygen from permeating the film. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor film 340.

  The insulating film 317 can be formed using the above insulating film that can be used for the insulating film 310.

Conductive films 350 a to 350 c are formed over the insulating film 317. The conductive film 350a is connected to the conductive film 342a through the opening _{C 1} provided in the insulating film 316 and the insulating film 317, the conductive film 350b is via the opening _{D 1} provided in the insulating film 316 and the insulating film 317 The conductive film 350c is connected to the conductive film 344b through an opening provided in the insulating film 316 and the insulating film 317.

The conductive film 350a, in FIG. 9 (B) is provided to extend in the column direction, the circuit 104 [2] In the transistor 106 [2] via an opening _{C 2} provided in the insulating film 311 to 317 It is electrically connected to one of the source region and the drain region. One of the conductive films 350a extends to the first region 113a illustrated in FIG. 1 and is electrically connected to the output terminal of the inverter 103 in the same stage. The other of the conductive films 350a has the circuit illustrated in FIG. since exemplifies the case of m = 2, interrupted via the opening C ₂ and the transistors 106 [2] where took contact. That is, the conductive film 350a functions as wiring between the terminals in the above embodiments A and the terminal C ₁ and the terminals A and C _2.

The conductive film 350b is, and FIG. 9 (B) is provided to extend in the column direction in the circuit 104 the transistors 107 through the opening _{D 2} provided in the insulating film 311 to 317 in [2] [2 ] Is electrically connected to one of the source region and the drain region. Further, since the circuit shown in FIG. 9 illustrates the case of m = 2, one of the conductive film 350b are interrupted where took contact with transistors 107 [1] via the opening D _1, conductivity The other side of the film 350b extends to the third region 113b shown in FIG. 1 and is electrically connected to the input terminal of the inverter 103 at the next stage. That is, the conductive film 350b serves as wiring between the above terminals D ₁ shown in the embodiment of the terminal B and the terminal D ₂ and the terminal B.

Here, the conductive film provided on the opening portion C ₁ is electrically connected to one of a source region and a drain region of the transistor 106 [1] can be regarded as the terminal C ₁ shown in FIG. Similarly, the conductive film provided on the opening portion C _2, can be considered as a terminal C ₂ shown in FIG. 2, the conductive film formed in the opening D _1, be regarded as the terminal D ₁ shown in FIG. 2 can be, conductive film formed in the opening D ₂ can be regarded as the terminal D ₂ shown in FIG.

Therefore, the distance between the openings _{C 1} and the opening _{C 2} regarded as _a 2 -a _1, a distance between the opening _{D 1} and the opening portion _{D 2} can be regarded as _b 1 -b _2. As shown in FIG. 9, in the semiconductor device described in this embodiment, the relationship is a ₂ −a ₁ = b ₁ −b ₂ . This satisfies the equation (1) shown in the previous embodiment.

That is, the distance between the opening C ₁ and the opening C ₂ is substantially equal to the distance between the opening D ₁ and the opening D _2. The wiring resistance between the terminal A and the terminal B of 102 can be made substantially equal. Further, in other words, the conductive film 350a, the distance between the portion overlapping the portion and the opening _{C 2} overlapping with the opening _{C 1} overlaps the conductive film 350b, the portion and the opening portion _{D 2} overlapping the opening _{D 1} By adopting a configuration that is substantially equal to the distance between the portions, the wiring resistance between the terminal A and the terminal B of the circuit 102 can be made approximately equal regardless of the selection of the wiring path of the circuit 104. As a result, the semiconductor device described in this embodiment can substantially equalize the oscillation frequency corresponding to specific data, so that the accuracy of the oscillation frequency can be improved.

  The conductive film 350c is provided to extend in the column direction in FIG. 9B, and the transistor 105 [2] is formed through an opening provided in the insulating film 317 and the insulating film 316 in the circuit 104 [2]. ] Is electrically connected to one of the source electrode and the drain electrode. Further, since the circuit illustrated in FIG. 9 illustrates the case where m = 2, one of the conductive films 350c is disconnected when the transistor 105 [1] is contacted through the opening. That is, the conductive film 350c functions as the wiring BL described in the above embodiment.

  The conductive films 350a to 350c can be formed using any of the above materials that can be used for the conductive films 328a and 328b.

  With the above structure, the semiconductor device described in this embodiment can provide a novel circuit structure. Alternatively, the semiconductor device described in this embodiment can switch an oscillation frequency or provide a circuit configuration capable of realizing it. Alternatively, the semiconductor device described in this embodiment can improve the accuracy of the oscillation frequency or provide a circuit configuration capable of realizing it.

  Note that in the connection between the conductive film 350a and the impurity region 320a, the opening of the insulating film and the conductive film are formed repeatedly; however, the semiconductor device described in this embodiment is not limited thereto. For example, an opening may be formed in the insulating films 317 to 311 at once and the conductive film 350a and the impurity region 320a may be directly connected. The same applies to the other openings of the circuit 104 and the conductive film.

  In the capacitor 108 [1], the conductive film 334 functioning as the second terminal is provided below the conductive film 344a functioning as the first terminal; however, the semiconductor device described in this embodiment is not limited to this. Is not something For example, a conductive film functioning as a second terminal may be provided over the conductive film 344a and the insulating film 316 may be used as a dielectric.

  FIG. 10 illustrates the case where the transistor 105 [1] includes a channel formation region corresponding to the gate electrode 348. However, the transistor 105 [1] may have a multi-gate structure in which a plurality of channel formation regions are included in one active layer by including a plurality of electrically connected gate electrodes. In this embodiment, the transistor 105, the transistor 106, and the transistor 107 do not overlap with each other; however, the semiconductor device described in this embodiment is not limited to this, and the transistor 105, the transistor 106, and the like. Alternatively, the transistor 107 may overlap with the transistor 107. In this embodiment, the channel length direction of the transistor 105 and the channel length directions of the transistors 106 and 107 are parallel to each other; however, the semiconductor device described in this embodiment is limited to this. Instead, the channel length direction of the transistor 105 and the channel length directions of the transistors 106 and 107 may not be parallel to each other.

<About the transistor>
Next, a structural example of the transistor 90 having a channel formation region in an oxide semiconductor film is described.

  FIG. 11 illustrates an example of a structure of the transistor 90 including a channel formation region in an oxide semiconductor film. FIG. 11A shows a top view of the transistor 90. Note that in FIG. 11A, various insulating films are omitted in order to clarify the layout of the transistor 90. 11A is a cross-sectional view taken along one-dot chain line A1-A2 in the top view shown in FIG. 11A, and FIG. 11C is a cross-sectional view taken along one-dot chain line A3-A4.

  As illustrated in FIG. 11, the transistor 90 is electrically connected to the oxide semiconductor film 92b and the oxide semiconductor film 92b which are sequentially stacked over the insulating film 91 formed over the substrate 97. The conductive film 93 and the conductive film 94 functioning as a source electrode or a drain electrode, the oxide semiconductor film 92b, the conductive film 93, the oxide semiconductor film 92c over the conductive film 94, and the function as a gate insulating film. In addition, an insulating film 95 located over the oxide semiconductor film 92c and a conductive film 96 which functions as a gate electrode and overlaps with the oxide semiconductor films 92a to 92c over the insulating film 95 are provided. Have. The substrate 97 may be a glass substrate, a semiconductor substrate, or the like, or an element substrate in which a semiconductor element is formed on a glass substrate or a semiconductor substrate.

  Here, the transistor 90 corresponds to the above-described transistor 105, the insulating film 91 is the insulating film 315, the oxide semiconductor films 92a to 92c are the oxide semiconductor film 340, the conductive film 93, and the conductive film. The film 94 corresponds to the conductive films 344a and 344b, the insulating film 95 corresponds to the gate insulating film 346, and the conductive film 96 corresponds to the gate electrode 348.

  Another example of a specific structure of the transistor 90 is illustrated in FIG. 12A is a top view of the transistor 90. FIG. Note that in FIG. 12A, various insulating films are omitted in order to clarify the layout of the transistor 90. 12B is a cross-sectional view taken along dashed-dotted line A1-A2 in the top view of FIG. 12A, and FIG. 12C is a cross-sectional view taken along dashed-dotted line A3-A4.

  As illustrated in FIG. 12, the transistor 90 includes an oxide semiconductor film 92a to an oxide semiconductor film 92c that are sequentially stacked over the insulating film 91, and the oxide semiconductor film 92c, which is electrically connected to the source electrode or the drain electrode. As the gate electrode, the conductive film 93 and the conductive film 94 having functions as the above, and the gate insulating film 95c serving as the gate insulating film and also over the oxide semiconductor film 92c, the conductive film 93, and the conductive film 94 are provided. And the conductive film 96 which overlaps with the oxide semiconductor films 92a to 92c over the insulating film 95.

  11 and 12 illustrate the structure of the transistor 90 including the stacked oxide semiconductor films 92a to 92c. The oxide semiconductor film included in the transistor 90 is not necessarily formed using a plurality of stacked oxide semiconductor films, and may be formed using a single oxide semiconductor film.

  In the case where the transistor 90 includes a semiconductor film in which the oxide semiconductor films 92a to 92c are sequentially stacked, the oxide semiconductor film 92a and the oxide semiconductor film 92c are formed of the metal element included in the oxide semiconductor film 92b. The energy of the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, 0.15 eV or more, and 2 eV or less, 1 eV or less than that of the oxide semiconductor film 92b. , 0.5 eV or less or 0.4 eV or less, and an oxide film close to a vacuum level. Further, the oxide semiconductor film 92b preferably contains at least indium because carrier mobility is increased.

  In the case where the transistor 90 includes the semiconductor film having the above structure, when an electric field is applied to the semiconductor film by applying a voltage to the gate electrode, a channel region is formed in the oxide semiconductor film 92b having a small energy at the bottom of the conduction band. Is formed. That is, by providing the oxide semiconductor film 92 c between the oxide semiconductor film 92 b and the insulating film 95, a channel region can be formed in the oxide semiconductor film 92 b separated from the insulating film 95. it can.

  In addition, since the oxide semiconductor film 92c includes at least one of metal elements included in the oxide semiconductor film 92b as a constituent element, interface scattering occurs at the interface between the oxide semiconductor film 92b and the oxide semiconductor film 92c. Hateful. Accordingly, since the movement of carriers at the interface is difficult to be inhibited, the field effect mobility of the transistor 90 is increased.

  In addition, when an interface state is formed at the interface between the oxide semiconductor film 92b and the oxide semiconductor film 92a, a channel region is also formed in a region near the interface, so that the threshold voltage of the transistor 90 varies. . However, since the oxide semiconductor film 92a includes at least one metal element included in the oxide semiconductor film 92b as a component, the interface state between the oxide semiconductor film 92b and the oxide semiconductor film 92a is Is difficult to form. Thus, with the above structure, variation in electrical characteristics such as the threshold voltage of the transistor 90 can be reduced.

  In addition, it is preferable to stack a plurality of oxide semiconductor films so that an interface state that inhibits the flow of carriers is not formed at the interface of each film due to the presence of impurities between the oxide semiconductor films. . If impurities exist between the stacked oxide semiconductor films, the continuity of the energy at the bottom of the conduction band between the oxide semiconductor films is lost, and carriers are trapped or re-entered near the interface. This is because the bonds disappear. By reducing the impurities between the films, a plurality of oxide semiconductor films having at least one metal as a main component together are simply stacked rather than simply stacked (here, the energy at the lower end of the conduction band is particularly high in each film). A state of having a U-shaped well structure that continuously changes between them).

In order to form a continuous bond, it is necessary to use a multi-chamber type film forming apparatus (sputtering apparatus) provided with a load lock chamber to continuously laminate each film without exposure to the atmosphere. Each chamber in the sputtering apparatus is evacuated (5 × 10 ⁻⁷ Pa to 1 ×) using an adsorption-type evacuation pump such as a cryopump so as to remove as much water as possible from the oxide semiconductor. It is preferable to be up to about 10 ⁻⁴ Pa. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that gas does not flow backward from the exhaust system into the chamber.

In order to obtain a high-purity intrinsic oxide semiconductor, it is important not only to evacuate each chamber to a high vacuum but also to increase the purity of a gas used for sputtering. The dew point of oxygen gas or argon gas used as the gas is −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower, and the oxide semiconductor film is made highly purified by purifying the gas used. It is possible to prevent moisture and the like from being taken into the body as much as possible. Specifically, when the oxide semiconductor film 92b is an In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), a target used to form the oxide semiconductor film 92b In the case where the atomic ratio of the metal element is In: M: Zn = x ₁ : y ₁ : z _{1 ,} x ₁ / y ₁ is 1/3 or more and 6 or less, further 1 or more and 6 or less, z ₁ / y ₁ is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less. Note that when z ₁ / y ₁ is greater than or equal to 1 and less than or equal to 6, a CAAC-OS film is easily formed as the oxide semiconductor film 92b. Typical examples of the atomic ratio of the target metal element include In: M: Zn = 1: 1: 1, In: M: Zn = 3: 1: 2.

Specifically, when the oxide semiconductor film 92a and the oxide semiconductor film 92c are In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), the oxide semiconductor film 92a and the oxide semiconductor film 92a are oxidized. In the target used for forming the physical semiconductor film 92c, if the atomic ratio of metal elements is In: M: Zn = x ₂ : y ₂ : z _{2 ,} x ₂ / y ₂ <x ₁ / y ₁ In addition, z ₂ / y ₂ is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less. Note that by setting z ₂ / y ₂ to 1 to 6, a CAAC-OS film can be easily formed as the oxide semiconductor film 92a and the oxide semiconductor film 92c. As typical examples of the atomic ratio of the target metal element, In: M: Zn = 1: 3: 2, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 6, In: M: Zn = 1: 3: 8 and the like.

  Note that the thickness of the oxide semiconductor film 92a and the oxide semiconductor film 92c is 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the oxide semiconductor film 92b is 3 nm to 200 nm, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm.

  In the three-layer semiconductor film, the oxide semiconductor film 92a to the oxide semiconductor film 92c can be either amorphous or crystalline. Note that the oxide semiconductor film 92b is preferably crystalline because the oxide semiconductor film 92b in which the channel region is formed is crystalline, so that stable electrical characteristics can be imparted to the transistor 90. .

  Note that the channel formation region means a region of the semiconductor film of the transistor 90 that overlaps with the gate electrode and is sandwiched between the source electrode and the drain electrode. The channel region refers to a region where current mainly flows in the channel formation region.

  For example, in the case where an In—Ga—Zn oxide film formed by a sputtering method is used as the oxide semiconductor film 92a and the oxide semiconductor film 92c, the oxide semiconductor film 92a and the oxide semiconductor film 92c are formed using In. A target that is -Ga-Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]) can be used. The film forming conditions may be, for example, 30 sccm of argon gas and 15 sccm of oxygen gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

  In the case where the oxide semiconductor film 92b is a CAAC-OS film, the oxide semiconductor film 92b is formed using an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio] ]) Is preferably used. The film forming conditions may be, for example, an argon gas of 30 sccm and an oxygen gas of 15 sccm as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 300 ° C., and a DC power of 0.5 kW.

  Note that the oxide semiconductor films 92a to 92c can be formed by a sputtering method, but may be formed by another method, for example, a thermal CVD method. As an example of the thermal CVD method, an MOCVD (Metal Organic Chemical Deposition) method or an ALD (Atomic Layer Deposition) method may be used.

  Note that an oxide semiconductor purified by reduction of impurities such as moisture or hydrogen which serves as an electron donor (donor) and oxygen vacancies are reduced because there are few carrier generation sources. , I-type (intrinsic semiconductor) or i-type. Therefore, a transistor including a channel formation region in a highly purified oxide semiconductor film has extremely low off-state current and high reliability. A transistor in which a channel formation region is formed in the oxide semiconductor film tends to have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

By reducing the impurity element, the carrier density in the highly purified oxide semiconductor film is reduced. The carrier density in the film is, for example, 1 × 10 ¹⁷ pieces / cm ³ or less, or 1 × 10 ¹⁵ pieces / cm ³ or less, or 1 × 10 ¹³ pieces / cm ³ or less, or 8 × 10 ¹¹ pieces / cm ^3. The following can be used. More preferably, the carrier density is less than 8 × 10 ¹¹ pieces / cm ^3, less than 1 × 10 ¹¹ pieces / cm ³ , and further preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × 10 ⁻⁹ pieces / cm ^3. This can be done.

Specifically, it can be proved by various experiments that the off-state current of a transistor including a channel formation region in a highly purified oxide semiconductor film is small. For example, even in an element having a channel width of 1 × 10 ⁶ μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, It is possible to obtain characteristics that are below the measurement limit, that is, 1 × 10 ⁻¹³ A or less. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. In addition, off-state current was measured using a circuit in which a capacitor and a transistor were connected and charge flowing into or out of the capacitor was controlled by the transistor. In this measurement, a highly purified oxide semiconductor film was used for a channel formation region of the transistor, and the off-state current of the transistor was measured from the change in charge amount per unit time of the capacitor. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off current of several tens of yA / μm can be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for a channel formation region has significantly lower off-state current than a transistor using crystalline silicon.

  Note that in the case where an oxide semiconductor film is used as the semiconductor film, the oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In addition, it is preferable that gallium (Ga) be included in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide semiconductor. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable that zirconium (Zr) is included as a stabilizer.

  Among oxide semiconductors, In-Ga-Zn oxide, In-Sn-Zn oxide, and the like are different from silicon carbide, gallium nitride, or gallium oxide, transistors having excellent electrical characteristics can be formed by a sputtering method or a wet method. There is an advantage that it can be manufactured and is excellent in mass productivity. Further, unlike silicon carbide, gallium nitride, or gallium oxide, the In—Ga—Zn oxide can form a transistor with excellent electrical characteristics over a glass substrate. In addition, it is possible to cope with an increase in the size of the substrate.

  As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be included.

  For example, as an oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In -Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also expressed as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al -Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Ce -Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn Oxide, In-Er-Zn oxide, In- m-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide can be used.

  Note that for example, an In—Ga—Zn oxide means an oxide containing In, Ga, and Zn, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be included. An In—Ga—Zn oxide has sufficiently high resistance in the absence of an electric field and can have a sufficiently small off-state current, and has high mobility.

  For example, high mobility can be obtained relatively easily with an In—Sn—Zn oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using the In—Ga—Zn oxide.

  In the transistor 90, depending on the conductive material used for the source electrode and the drain electrode, the metal in the source electrode and the drain electrode might extract oxygen from the oxide semiconductor film. In this case, a region in contact with the source electrode and the drain electrode in the oxide semiconductor film is n-type due to formation of oxygen vacancies. Since the n-type region functions as a source region or a drain region, contact resistance between the oxide semiconductor film and the source and drain electrodes can be reduced. Thus, by forming the n-type region, the mobility and on-state current of the transistor 90 can be increased, whereby high-speed operation of the semiconductor device using the transistor 90 can be realized.

  Note that extraction of oxygen by a metal in the source electrode and the drain electrode can occur when the source electrode and the drain electrode are formed by a sputtering method or the like, and can also occur by a heat treatment performed after the source electrode and the drain electrode are formed. . In addition, the n-type region is more easily formed by using a conductive material that is easily bonded to oxygen for the source electrode and the drain electrode. Examples of the conductive material include Al, Cr, Cu, Ta, Ti, Mo, and W.

  In the case where a semiconductor film including a plurality of stacked oxide semiconductor films is used for the transistor 90, the mobility of the transistor 90 indicates that the n-type region reaches the oxide semiconductor film 92b serving as a channel region. Further, it is preferable for increasing the on-current and realizing high-speed operation of the semiconductor device.

The insulating film 91 is preferably an insulating film having a function of supplying part of the oxygen to the oxide semiconductor films 92a to 92c by heating. The insulating film 91 preferably has few defects. Typically, the density of a spin having g = 2.001 derived from a dangling bond of silicon obtained by ESR measurement is 1 × 10 ¹⁸ spins / It is preferable that it is cm ³ or less.

  The insulating film 91 is preferably an oxide because it has a function of supplying part of the oxygen to the oxide semiconductor films 92a to 92c by heating, for example, aluminum oxide, magnesium oxide, or silicon oxide. Silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and the like can be used. The insulating film 91 can be formed by a plasma CVD (Chemical Vapor Deposition) method, a sputtering method, or the like.

  Note that in this specification, oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Point to.

  11 and 12 includes an end portion of the oxide semiconductor film 92b where a channel region is formed, that is, an end portion that does not overlap with the conductive film 93 and the conductive film 94, in other words, the conductive film 93. In addition, the conductive film 96 overlaps with an end portion located in a region different from the region where the conductive film 94 is located. When the end portion of the oxide semiconductor film 92b is exposed to plasma by etching for forming the end portion, chlorine radicals, fluorine radicals, and the like generated from the etching gas are formed with metal elements included in the oxide semiconductor. Easy to combine. Therefore, oxygen vacancies are formed in the end portion of the oxide semiconductor film because oxygen bonded to the metal element is easily released, so that it is considered that the oxide semiconductor film is likely to be n-type. However, in the transistor 90 illustrated in FIGS. 11 and 12, since the conductive film 96 overlaps with an end portion of the oxide semiconductor film 92b that does not overlap with the conductive films 93 and 94, the potential of the conductive film 96 is controlled. Thus, the electric field applied to the end can be controlled. Thus, the current flowing between the conductive film 93 and the conductive film 94 through the end portion of the oxide semiconductor film 92 b can be controlled by the potential applied to the conductive film 96. Such a structure of the transistor 90 is referred to as a Surrounded Channel (S-Channel) structure.

  Specifically, in the case of the S-Channel structure, when a potential at which the transistor 90 is turned off is applied to the conductive film 96, an off-current that flows between the conductive film 93 and the conductive film 94 through the end portion is reduced. It can be kept small. Therefore, in the transistor 90, the channel length is shortened in order to obtain a large on-state current. As a result, even if the length between the conductive film 93 and the conductive film 94 at the end portion of the oxide semiconductor film 92b is shortened, the transistor 90 off-current can be kept small. Therefore, by shortening the channel length, the transistor 90 can obtain a large on-state current when turned on, and can keep the off-state current small when turned off.

Specifically, in the case of the S-Channel structure, when a potential at which the transistor 90 is turned on is applied to the conductive film 96, a current that flows between the conductive film 93 and the conductive film 94 through the end portion. Can be increased. The current contributes to increase in field effect mobility and on-current of the transistor 90. In addition, since the end portion of the oxide semiconductor film 92b and the conductive film 96 overlap with each other, a region where carriers flow in the oxide semiconductor film 92b is not only near the interface of the oxide semiconductor film 92b close to the insulating film 95. Since carriers flow in a wide range of the oxide semiconductor film 92b, the amount of carrier movement in the transistor 90 increases. As a result, the on-state current of the transistor 90 is increased and the field effect mobility is increased. Typically, the field effect mobility is 10 cm ² / V · s or more, and further 20 cm ² / V · s or more. Note that the field-effect mobility here is not an approximate value of mobility as a physical property value of the oxide semiconductor film but an index of current driving force in the saturation region of the transistor and is an apparent field-effect mobility. .

  Hereinafter, the structure of the oxide semiconductor film is described.

  An oxide semiconductor film is classified roughly into a single crystal oxide semiconductor film and a non-single crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, or the like.

  An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal component. An oxide semiconductor film which has no crystal part even in a minute region and has a completely amorphous structure as a whole is typical.

  The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Therefore, the microcrystalline oxide semiconductor film has higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, a microcrystalline oxide semiconductor film has a feature that the density of defect states is lower than that of an amorphous oxide semiconductor film.

  The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts are large enough to fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. The CAAC-OS film is characterized by having a lower density of defect states than a microcrystalline oxide semiconductor film. When the CAAC-OS film is observed with a transmission electron microscope (TEM), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

  When the CAAC-OS film is observed by TEM (cross-sectional TEM observation) from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

  In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

  On the other hand, when the CAAC-OS film is observed by TEM (planar TEM observation) from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

  From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

  From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

  Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

  Further, the crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the region near the top surface can have a higher degree of crystallinity than the region near the formation surface. is there. In addition, in the case where an impurity is added to the CAAC-OS film, the crystallinity of a region to which the impurity is added changes, and a region having a different degree of crystallinity may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

  In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

  Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

  In order to form the CAAC-OS film, the following conditions are preferably applied.

  By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) existing in the treatment chamber may be reduced. Further, the impurity concentration in the deposition gas may be reduced. Specifically, a deposition gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

  Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. When the substrate heating temperature at the time of film formation is increased, when the flat or pellet-like sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

  In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the deposition gas is 30% by volume or more, preferably 100% by volume.

  As an example of the target, an In—Ga—Zn oxide target is described below.

In-Ga-Zn which is polycrystalline by mixing InO _X powder, GaO _Y powder and ZnO _Z powder at a predetermined molar ratio, and after heat treatment at a temperature of 1000 ° C to 1500 ° C. An oxide target is used. X, Y, and Z are arbitrary positive numbers. Here, the predetermined mole number ratio is, for example, 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 for InO _X powder, GaO _Y powder, and ZnO _Z powder. : 2: 3, 2: 1: 3 or 3: 1: 2. In addition, what is necessary is just to change suitably the kind of powder, and the mol number ratio to mix with the target to produce. In particular, a CAAC-OS film formed using a target with a molar ratio of In, Ga, Zn of 2: 1: 3 has a ratio of a region where a CAAC-OS diffraction pattern is observed in a certain range (CAAC The frequency characteristics (f characteristics) of a transistor having a channel formation region in the CAAC-OS film can be increased.

Note that an alkali metal is an impurity because it is not an element included in an oxide semiconductor. Alkaline earth metal is also an impurity when it is not an element constituting an oxide semiconductor. In particular, Na in the alkali metal diffuses into the insulating film and becomes Na ⁺ when the insulating film in contact with the oxide semiconductor film is an oxide. In the oxide semiconductor film, Na breaks or interrupts the bond between the metal constituting the oxide semiconductor and oxygen. As a result, for example, the transistor is deteriorated in electrical characteristics, such as being normally on due to the shift of the threshold voltage in the negative direction, and a decrease in mobility. In addition, the characteristics vary. Specifically, the measured value of Na concentration by secondary ion mass spectrometry is 5 × 10 ¹⁶ / cm ³ or less, preferably 1 × 10 ¹⁶ / cm ³ or less, more preferably 1 × 10 ¹⁵ / cm ³ or less. Good. Similarly, the measured value of the Li concentration is 5 × 10 ¹⁵ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less. Similarly, the measured value of the K concentration is 5 × 10 ¹⁵ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less.

In addition, in the case where a metal oxide containing indium is used, silicon or carbon whose binding energy to oxygen is higher than that of indium may cut the bond between indium and oxygen, thereby forming an oxygen vacancy. Therefore, when silicon or carbon is mixed in the oxide semiconductor film, the electrical characteristics of the transistor are likely to deteriorate as in the case of alkali metal or alkaline earth metal. Therefore, it is desirable that the concentration of silicon or carbon in the oxide semiconductor film be low. Specifically, the measured value of C concentration or the measured value of Si concentration by secondary ion mass spectrometry is preferably 1 × 10 ¹⁸ / cm ³ or less. With the above structure, deterioration of electrical characteristics of the transistor can be prevented, and reliability of the semiconductor device can be improved.

  Further, heat treatment may be performed in order to further reduce impurities such as moisture or hydrogen contained in the oxide semiconductor film so that the oxide semiconductor film is highly purified.

  For example, the amount of moisture when measured using a dew point meter under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or ultra-dry air (CRDS (cavity ring down laser spectroscopy) method) The oxide semiconductor film is subjected to heat treatment in an atmosphere of 20 ppm (−55 ° C. in terms of dew point) or less, preferably 1 ppm or less, preferably 10 ppb or less. Note that the oxidizing atmosphere refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone, or oxygen nitride. Further, the inert atmosphere refers to an atmosphere filled with nitrogen or a rare gas, in which the oxidizing gas is less than 10 ppm.

  Note that after heat treatment in an inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Note that heat treatment may be performed at any time after the oxide semiconductor film is formed. For example, heat treatment may be performed after the selective etching of the oxide semiconductor film.

  The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C. The processing time is within 24 hours.

  For the heat treatment, an electric furnace, an RTA (Rapid Thermal Annealing) apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

<Modification Example 1 of Cross-sectional Structure of Semiconductor Device>
FIG. 13 illustrates an example of a cross-sectional structure corresponding to the transistor 105 and the transistor 106 illustrated in FIG. The transistor 22 corresponds to the transistor 105, and the transistor 23 corresponds to the transistor 106. Note that a region indicated by a broken line A1-A2 indicates a structure in the channel length direction of the transistor 22 and the transistor 23, and a region indicated by a broken line A3-A4 indicates a structure in the channel width direction of the transistor 22 and the transistor 23. Yes. Note that in one embodiment of the present invention, the channel length direction of the transistor 22 and the channel length direction of the transistor 23 do not necessarily match.

  Note that the channel length direction of a transistor means a direction in which carriers move between a source (source region or source electrode) and a drain (drain region or drain electrode), and the channel width direction is in a plane parallel to the substrate. Means a direction perpendicular to the channel length direction.

  FIG. 13 illustrates the case where the transistor 22 having a channel formation region in an oxide semiconductor film is formed over the transistor 23 having a channel formation region in a single crystal silicon substrate.

  The transistor 23 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium that is amorphous, microcrystalline, polycrystalline, or single crystal. Alternatively, the transistor 23 may include a channel formation region in the oxide semiconductor film or the oxide semiconductor substrate. In the case where all the transistors have a channel formation region in an oxide semiconductor film or an oxide semiconductor substrate, the transistor 22 may not be stacked over the transistor 23. The transistor 22 and the transistor 23 are the same layer. It may be formed.

  In the case where the transistor 23 is formed using a silicon thin film, amorphous silicon produced by a vapor deposition method such as a plasma CVD method or a sputtering method, or amorphous silicon is formed on the thin film by a process such as laser annealing. Crystallized polycrystalline silicon, single crystal silicon in which hydrogen ions or the like are implanted into a single crystal silicon wafer and a surface layer portion is peeled off can be used.

  As the substrate 400 over which the transistor 23 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, or the like can be used. FIG. 13 illustrates the case where a single crystal silicon substrate is used as the substrate 400.

  The transistor 23 is electrically isolated by an element isolation method. As the element isolation method, a trench isolation method or the like can be used. FIG. 13 illustrates a case where the transistor 23 is electrically isolated using a trench isolation method. Specifically, in FIG. 13, an insulating material containing silicon oxide or the like is embedded in a trench formed in the substrate 400 by etching or the like, and then the insulating material is partially removed by etching or the like. The case where the transistor 23 is isolated by the element isolation region 401 and electrically isolated is illustrated.

  In addition, an impurity region 402 and an impurity region 403 of the transistor 23 and a channel formation region 404 sandwiched between the impurity region 402 and the impurity region 403 are provided on the convex portion of the substrate 400 that exists in a region other than the trench. . Further, the transistor 23 includes an insulating film 405 that covers the channel formation region 404 and a gate electrode 406 that overlaps with the channel formation region 404 with the insulating film 405 interposed therebetween.

  In the transistor 23, the side and upper portions of the protrusions in the channel formation region 404 overlap with the gate electrode 406 with the insulating film 405 interposed therebetween, so that a wide range including the side and upper portions of the channel formation region 404 is obtained. A career flows. Therefore, the amount of carrier movement in the transistor 23 can be increased while keeping the occupied area of the transistor 23 on the substrate small. As a result, the transistor 23 has an increased on-current and an increased field effect mobility. In particular, when the length in the channel width direction (channel width) of the convex portion in the channel formation region 404 is W and the film thickness of the convex portion in the channel formation region 404 is T, this corresponds to the ratio of the film thickness T to the channel width W. When the aspect ratio is high, the carrier flows in a wider range, so that the on-state current of the transistor 23 can be increased and the field-effect mobility can be further increased.

  Note that in the case of the transistor 23 using a bulk semiconductor substrate, the aspect ratio is preferably 0.5 or more, and more preferably 1 or more.

  An insulating film 411 is provided over the transistor 23. An opening is formed in the insulating film 411. In the opening, an impurity region 402, a conductive film 412 and a conductive film 413 electrically connected to the impurity region 403, and a conductive film 414 electrically connected to the gate electrode 406, Is formed.

  The conductive film 412 is electrically connected to the conductive film 416 formed over the insulating film 411, and the conductive film 413 is electrically connected to the conductive film 417 formed over the insulating film 411. The conductive film 414 is electrically connected to the conductive film 418 formed over the insulating film 411.

  An insulating film 420 is provided over the conductive films 416 to 418. An insulating film 421 having a blocking effect for preventing diffusion of oxygen, hydrogen, and water is provided over the insulating film 420. The insulating film 421 has a higher blocking effect as the density is higher and denser, and as the insulating film 421 is chemically stable with fewer dangling bonds. As the insulating film 421 having a blocking effect for preventing diffusion of oxygen, hydrogen, and water, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like is used. be able to. As the insulating film 421 having a blocking effect for preventing diffusion of hydrogen and water, for example, silicon nitride, silicon nitride oxide, or the like can be used.

  An insulating film 422 is provided over the insulating film 421, and the transistor 22 is provided over the insulating film 422.

  The transistor 22 includes a semiconductor film 430 including an oxide semiconductor over the insulating film 422, a conductive film 432 and a conductive film 433 that are electrically connected to the semiconductor film 430 and function as a source electrode or a drain electrode, a semiconductor film A gate insulating film 431 covering 430 and a gate electrode 434 which overlaps with the semiconductor film 430 with the gate insulating film 431 interposed therebetween. Note that an opening is provided in the insulating films 420 to 422, and the conductive film 433 is connected to the conductive film 418 in the opening.

  Note that in FIG. 13, the transistor 22 only needs to include the gate electrode 434 at least on one side of the semiconductor film 430, but further includes a gate electrode overlapping with the semiconductor film 430 with the insulating film 422 interposed therebetween. May be.

  In the case where the transistor 22 includes a pair of gate electrodes, a signal for controlling a conduction state or a non-conduction state is supplied to one gate electrode, and a potential is supplied to the other gate electrode from another wiring. It may be in a state of being. In this case, a pair of gate electrodes may be given the same potential, or a fixed potential such as a ground potential may be given only to the other gate electrode. By controlling the level of the potential applied to the other gate electrode, the threshold voltage of the transistor can be controlled.

  In general, the potential (voltage) is a relative value, and the value is determined by the relative magnitude from the reference potential. Therefore, even when “ground”, “GND”, “ground”, and the like are described, the potential is not necessarily 0 volts. For example, “ground” or “GND” may be defined with reference to the lowest potential in the circuit. Alternatively, “ground” or “GND” may be defined with reference to an intermediate potential in the circuit. In that case, a positive potential and a negative potential are defined based on the potential.

  Here, in the case where a certain transistor T includes a pair of gates with a semiconductor film interposed therebetween, a signal A may be applied to one gate and a fixed potential Vb may be applied to the other gate. .

  The signal A is a signal for controlling a conduction state or a non-conduction state, for example. The signal A may be a digital signal that takes two kinds of potentials, that is, the potential V1 or the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential. The signal A may be an analog signal.

  The fixed potential Vb is a potential for controlling the threshold voltage VthA of the transistor T, for example. The fixed potential Vb may be the potential V1 or the potential V2. In this case, there is no need to separately provide a potential generation circuit for generating the fixed potential Vb, which is preferable. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. In some cases, the threshold voltage VthA can be increased by lowering the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of the circuit including the transistor T can be reduced in some cases. For example, the fixed potential Vb may be set lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is VDD may be improved, and the operation speed of the circuit including the transistor T may be improved. For example, the fixed potential Vb may be higher than the low power supply potential.

  Further, the signal A may be supplied to one gate of the transistor T, and the signal B may be supplied to the other gate. The signal B is a signal for controlling the conduction state or non-conduction state of the transistor T, for example. The signal B may be a digital signal that takes two kinds of potentials, that is, the potential V3 or the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

  When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-state current of the transistor T may be improved and the operation speed of the circuit including the transistor T may be improved. At this time, the potential V1 of the signal A may be different from the potential V3 of the signal B. Further, the potential V2 of the signal A may be different from the potential V4 of the signal B. For example, when the gate insulating film corresponding to the gate to which the signal B is input is thicker than the gate insulating film corresponding to the gate to which the signal A is input, the potential amplitude (V3 to V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conduction state or non-conduction state of the transistor T may be almost the same.

  When both the signal A and the signal B are digital signals, the signal B may be a signal having a digital value different from that of the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized. For example, when the transistor T is an n-channel transistor, the transistor A is in a conductive state only when the signal A is the potential V1 and the signal B is the potential V3, or the signal A is the potential V2 and the signal B In the case where the transistor is non-conductive only when the potential is V4, the function of a NAND circuit, a NOR circuit, or the like may be realized with one transistor. The signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal having a different potential between a period in which a circuit including the transistor T is operating and a period in which the circuit is not operating. The signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not be switched as frequently as the signal A.

  When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant. An analog signal or the like may be used. In this case, the on-state current of the transistor T may be improved and the operation speed of the circuit including the transistor T may be improved. The signal B may be an analog signal different from the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized.

  The signal A may be a digital signal and the signal B may be an analog signal. The signal A may be an analog signal and the signal B may be a digital signal.

  Further, the fixed potential Va may be applied to one gate of the transistor T, and the fixed potential Vb may be applied to the other gate. When a fixed potential is applied to both gates of the transistor T, the transistor T may function as an element equivalent to a resistance element. For example, in the case where the transistor T is an n-channel transistor, the effective resistance of the transistor may be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb. By making both the fixed potential Va and the fixed potential Vb higher (lower), an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.

  FIG. 13 illustrates the case where the transistor 22 has a single gate structure having a channel formation region corresponding to the gate electrode 434. However, the transistor 22 may have a multi-gate structure in which a plurality of channel formation regions are included in one active layer by including a plurality of electrically connected gate electrodes.

  As illustrated in FIG. 13, the transistor 22 exemplifies a case where the semiconductor film 430 includes oxide semiconductor films 430 a to 430 c which are sequentially stacked over the insulating film 422. Note that in one embodiment of the present invention, the semiconductor film 430 included in the transistor 22 may be a single metal oxide film.

<Modification Example 2 of Cross-sectional Structure of Semiconductor Device>
FIG. 14 illustrates an example of a cross-sectional structure corresponding to the transistor 105 and the transistor 106 illustrated in FIG.

  Note that FIG. 14 illustrates the case where the transistor 22 having a channel formation region in an oxide semiconductor film is formed over the transistor 23 having a channel formation region in a single crystal silicon substrate. Note that the transistor 22 corresponds to the transistor 105, and the transistor 23 corresponds to the transistor 106.

  The transistor 23 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium that is amorphous, microcrystalline, polycrystalline, or single crystal. Alternatively, the transistor 23 may include a channel formation region in the oxide semiconductor film or the oxide semiconductor substrate. In the case where all the transistors have a channel formation region in an oxide semiconductor film or an oxide semiconductor substrate, the transistor 22 may not be stacked over the transistor 23. The transistor 22 and the transistor 23 are the same layer. It may be formed.

  In the case where the transistor 23 is formed using a silicon thin film, amorphous silicon produced by a vapor deposition method such as a plasma CVD method or a sputtering method, or amorphous silicon is formed on the thin film by a process such as laser annealing. Crystallized polycrystalline silicon, single crystal silicon in which hydrogen ions or the like are implanted into a single crystal silicon wafer and a surface layer portion is peeled off can be used.

  As the semiconductor substrate 601 over which the transistor 23 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, or the like can be used. FIG. 14 illustrates the case where a single crystal silicon substrate is used as the semiconductor substrate 601.

  The transistor 23 is electrically isolated by an element isolation method. As an element isolation method, a selective oxidation method (LOCOS method: Local Oxidation of Silicon method), a trench isolation method (STI method: Shallow Trench Isolation), or the like can be used. FIG. 14 illustrates a case where the transistor 23 is electrically isolated using a trench isolation method. Specifically, in FIG. 14, after a trench is formed in the semiconductor substrate 601 by etching or the like, the transistor 23 is isolated by element isolation by an element isolation region 610 formed by burying an insulator containing silicon oxide or the like in the trench. The case where it isolate | separates electrically is illustrated.

  An insulating film 611 is provided over the transistor 23. An opening is formed in the insulating film 611. In the opening, a conductive film 625 and a conductive film 626 that are electrically connected to a source and a drain of the transistor 23, respectively, and a conductive film 627 that is electrically connected to the gate of the transistor 23, Is formed.

  The conductive film 625 is electrically connected to the conductive film 634 formed over the insulating film 611, and the conductive film 626 is electrically connected to the conductive film 635 formed over the insulating film 611. The conductive film 627 is electrically connected to the conductive film 636 formed over the insulating film 611.

  An insulating film 612 is formed over the conductive films 634 to 636. An opening is formed in the insulating film 612, and a conductive film 637 electrically connected to the conductive film 636 is formed in the opening. The conductive film 637 is electrically connected to the conductive film 651 formed over the insulating film 612.

  In addition, an insulating film 613 is formed over the conductive film 651. An opening is formed in the insulating film 613, and a conductive film 652 electrically connected to the conductive film 651 is formed in the opening. The conductive film 652 is electrically connected to the conductive film 653 formed over the insulating film 613. A conductive film 644 is formed over the insulating film 613.

  An insulating film 661 is formed over the conductive films 653 and 644. In FIG. 14, the transistor 22 is formed over the insulating film 661.

  The transistor 22 includes a semiconductor film 701 including an oxide semiconductor over the insulating film 661, a conductive film 721 and a conductive film 722 functioning as a source or a drain over the semiconductor film 701, a semiconductor film 701, a conductive film 721, and a conductive film. A gate insulating film 662 over the film 722 and a gate electrode 731 which is located over the gate insulating film 662 and overlaps with the semiconductor film 701 between the conductive film 721 and the conductive film 722 are provided. Note that the conductive film 722 is electrically connected to the conductive film 653 in an opening provided in the insulating film 661.

  In the transistor 22, the region 710 exists between the region overlapping the conductive film 721 and the region overlapping the gate electrode 731 in the semiconductor film 701. In the transistor 22, the region 711 exists between the region overlapping the conductive film 722 and the region overlapping the gate electrode 731 in the semiconductor film 701. In the regions 710 and 711, a rare gas such as argon, an impurity imparting p-type conductivity to the semiconductor film 701, or an n-type conductivity type is used for the conductive film 721, the conductive film 722, and the gate electrode 731 as a mask. By adding an impurity imparted to the semiconductor film 701, the resistivity of the regions 710 and 711 can be lower than that of the region overlapping with the gate electrode 731 in the semiconductor film 701.

  An insulating film 663 is provided over the transistor 22.

  Note that in FIG. 14, the transistor 22 only needs to have at least one gate electrode 731 on one side of the semiconductor film 701, but the transistor 22 has a pair of gate electrodes existing with the semiconductor film 701 interposed therebetween. May be.

  In the case where the transistor 22 includes a pair of gate electrodes present with the semiconductor film 701 interposed therebetween, a signal for controlling a conduction state or a non-conduction state is supplied to one gate electrode, and the other gate The electrode may be in a state where a potential is applied from another wiring. In this case, a pair of gate electrodes may be given the same potential, or a fixed potential such as a ground potential may be given only to the other gate electrode. By controlling the level of the potential applied to the other gate electrode, the threshold voltage of the transistor can be controlled.

  FIG. 14 illustrates the case where the transistor 22 has a single gate structure including a channel formation region corresponding to the gate electrode 731. However, the transistor 22 may have a multi-gate structure in which a plurality of channel formation regions are included in one active layer by including a plurality of electrically connected gate electrodes.

  This embodiment can be implemented in appropriate combination with the configurations disclosed in this specification and the like of other embodiments.

(Embodiment 4)
<Examples of electronic devices>
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type display (head-mounted display), navigation system, sound playback device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, medical equipment Etc. Specific examples of these electronic devices are shown in FIGS.

  FIG. 15A illustrates a portable game machine including a housing 5001, a housing 5002, a display portion 5003, a display portion 5004, a microphone 5005, a speaker 5006, operation keys 5007, a stylus 5008, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a portable game machine. Note that although the portable game machine illustrated in FIG. 15A includes two display portions 5003 and 5004, the number of display portions included in the portable game device is not limited thereto.

  FIG. 15B illustrates a portable information terminal which includes a first housing 5601, a second housing 5602, a first display portion 5603, a second display portion 5604, a connection portion 5605, operation keys 5606, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a portable information terminal. The first display portion 5603 is provided in the first housing 5601 and the second display portion 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connection portion 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection portion 5605. is there. The video on the first display portion 5603 may be switched according to the angle between the first housing 5601 and the second housing 5602 in the connection portion 5605. Further, a display device to which a function as a position input device is added to at least one of the first display portion 5603 and the second display portion 5604 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

  FIG. 15C illustrates a laptop personal computer, which includes a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a notebook personal computer.

  FIG. 15D illustrates an electric refrigerator-freezer, which includes a housing 5301, a refrigerator door 5302, a refrigerator door 5303, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of an electric refrigerator-freezer.

  FIG. 15E illustrates a video camera, which includes a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a connection portion 5806, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a video camera. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection portion 5806. is there. The video on the display portion 5803 may be switched in accordance with the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806.

  FIG. 15F illustrates an automobile, which includes a car body 5101, wheels 5102, a dashboard 5103, lights 5104, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of an automobile.

  Note that in this specification and the like, in the case where X and Y are explicitly described as being connected, X and Y are electrically connected and X and Y are functionally connected. The case where they are connected and the case where X and Y are directly connected are included. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and includes things other than the connection relation shown in the figure or text.

  Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do.

  Note that when X and Y are explicitly described as being electrically connected, when X and Y are electrically connected (that is, another element between X and Y). Or when X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And a case where X and Y are directly connected (that is, a case where another element or another circuit is not connected between X and Y). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

  Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

  For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

  In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

  Note that the content (may be a part of content) described in one embodiment is different from the content (may be a part of content) described in the embodiment and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part thereof) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

  In addition, about the content which is not prescribed | regulated in the drawing and text in a specification, the one aspect | mode of the invention which prescribed | regulated removing the content can be comprised. Or, when a numerical value range indicated by an upper limit value and a lower limit value is described for a certain value, the range is unified by arbitrarily narrowing the range or by removing one point in the range. One aspect of the invention excluding a part can be defined. Thus, for example, it can be defined that the prior art does not fall within the technical scope of one embodiment of the present invention.

  As a specific example, a circuit diagram using the first to fifth transistors in a certain circuit is described. In that case, it can be specified as an invention that the circuit does not include the sixth transistor. Alternatively, it can be specified that the circuit does not include a capacitor. Furthermore, the invention can be configured by specifying that the circuit does not have the sixth transistor having a specific connection structure. Alternatively, the invention can be configured by specifying that the circuit does not include a capacitor having a specific connection structure. For example, the invention can be defined as having no sixth transistor whose gate is connected to the gate of the third transistor. Alternatively, for example, it can be specified that the first electrode does not include a capacitor connected to the gate of the third transistor.

  As another specific example, a certain value is described as, for example, “It is preferable that a certain voltage is 3 V or more and 10 V or less”. In that case, for example, one embodiment of the invention can be defined as excluding the case where a certain voltage is −2 V or higher and 1 V or lower. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where a certain voltage is 13 V or higher. Note that, for example, the invention can be specified such that the voltage is 5 V or more and 8 V or less. In addition, for example, it is also possible to prescribe | regulate invention that the voltage is about 9V. Note that, for example, the voltage is 3 V or more and 10 V or less, but the invention can be specified except for the case where the voltage is 9 V. Note that even if a value is described as “preferably in such a range”, “preferably satisfying these”, or the like, the value is not limited to the description. That is, even if it is described as “preferred” or “preferred”, the description is not necessarily limited thereto.

  As another specific example, it is assumed that a certain value is described as, for example, “a certain voltage is preferably 10 V”. In that case, for example, one embodiment of the invention can be defined as excluding the case where a certain voltage is −2 V or higher and 1 V or lower. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where a certain voltage is 13 V or higher.

  As another specific example, it is assumed that the property of a certain substance is described as, for example, “a certain film is an insulating film”. In that case, for example, one embodiment of the invention can be defined as excluding the case where the insulating film is an organic insulating film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the insulating film is an inorganic insulating film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the film is a conductive film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the film is a semiconductor film.

  As another specific example, it is assumed that a certain laminated structure is described as “a film is provided between the A film and the B film”, for example. In that case, for example, the invention can be defined as excluding the case where the film is a laminated film of four or more layers. Alternatively, for example, the invention can be defined as excluding the case where a conductive film is provided between the A film and the film.

  Note that in this specification and the like, a person skilled in the art can connect all terminals of an active element (a transistor, a diode, etc.), a passive element (a capacitor element, a resistance element, etc.) without specifying connection destinations. Thus, it may be possible to constitute an aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when there are a plurality of cases where the terminal is connected, it is not necessary to limit the terminal connection to a specific location. Therefore, it is possible to constitute one embodiment of the present invention by specifying connection destinations of only some terminals of active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.). There are cases.

  Note that in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.

  Note that in this specification and the like, a part of the drawings or texts described in one embodiment can be extracted to constitute one embodiment of the present invention. Therefore, when a figure or a sentence describing a certain part is described, the content of the extracted part of the figure or the sentence is also disclosed as one aspect of the invention and may constitute one aspect of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitance elements, resistance elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operating methods, manufacturing methods It is possible to extract one part of a drawing or a sentence on which one or more of the above are described and constitute one embodiment of the invention. For example, from a circuit diagram having N (N is an integer) circuit elements (transistors, capacitors, etc.), M (M is an integer, M <N) circuit elements (transistors, capacitors) Etc.) can be extracted to constitute one embodiment of the invention. As another example, M (M is an integer and M <N) layers are extracted from a cross-sectional view including N layers (N is an integer) to form one embodiment of the invention. It is possible to do. As another example, M elements (M is an integer and M <N) are extracted from a flowchart including N elements (N is an integer) to form one aspect of the invention. It is possible to do. As another example, a part of the elements is arbitrarily extracted from the sentence “A has B, C, D, E, or F”. "A has E and F", "A has C, E and F", or "A has B, C, D and E" It is possible to constitute one aspect of the invention.

  Note that in this specification and the like, when at least one specific example is described in a drawing or text described in one embodiment, it is easy for those skilled in the art to derive a superordinate concept of the specific example. To be understood. Therefore, in the case where at least one specific example is described in a drawing or text described in one embodiment, the superordinate concept of the specific example is also disclosed as one aspect of the invention. Aspects can be configured. One embodiment of the invention is clear.

  Note that in this specification and the like, at least the contents shown in the drawings (may be part of the drawings) are disclosed as one embodiment of the invention, and can constitute one embodiment of the invention It is. Therefore, if a certain content is described in the figure, even if it is not described using sentences, the content is disclosed as one aspect of the invention and may constitute one aspect of the invention. Is possible. Similarly, a drawing obtained by extracting a part of the drawing is also disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. And it can be said that one aspect of the invention is clear.

  In this example, a result of manufacturing and evaluating a voltage-controlled oscillator (VCO) according to one embodiment of the present invention will be described. The circuit configuration of the VCO according to this example was manufactured using the circuit configuration of the apparatus shown in FIGS. 2 and 3 in the above embodiment. In the VCO according to this embodiment, circuits 101 [1] to 101 [n] are set to n = 101, circuits 104 [1] to 104 [m] are set to m = 2, and m = 8. And were prepared in two types.

  The VCO according to this embodiment includes circuits 101 [1] to 101 [101], and the circuits 101 [1] to 101 [101] are connected in a ring shape. Specifically, each of the circuits 101 [1] to 101 [100] has an output terminal connected to an input terminal of the next-stage circuit. The output terminal of the circuit 101 [101] is connected to the input terminal of the circuit 101 [1]. The output terminal of the circuit 101 [51] is also connected to the terminal OUT. A signal generated by the oscillation of the VCO is output from the terminal OUT.

  Each of the circuits 101 [1] to 101 [101] includes a circuit 102 and an inverter 103. In the circuit 102, the terminal A is connected to the output terminal of the inverter 103, and the terminal B of the circuit 102 is connected to the input terminal of the inverter 103 in the next stage. That is, 101 inverters 103 are connected in a ring shape to constitute an inverter ring. A circuit 102 is connected between the inverters 103. The circuit 102 is connected to the wiring BL, the wirings CONTEXT [1] to CONTEXT [m], and the wirings WL [1] to WL [m].

In FIG. 3, the second region 112a includes circuits 102 [1] to 102 [51], and the fourth region 112b includes circuits 102 [52] to 102 [101]. The third region 113b includes an inverter 103 [i ₁ ] (i ₁ is an even number of 2 to 50). The first region 113a includes an inverter 103 [i ₂ ] (i ₂ is an odd number from 1 to 51) and an inverter 103 [i ₃ ] (i ₃ is an even number from 52 to 100). The fifth region 113c is configured by the inverter 103 [i ₄ ] (i ₄ is an odd number of 53 or more and 101 or less).

Here, the inverter 103, the ground potential GND as a low power supply potential, applying a potential _{V RO} as the high power supply potential. The wiring BL is the ground potential GND as a low power supply potential, applying a potential _{V DATA} as the high power supply potential. In the following, a signal input from the wiring BL may be referred to as AVD (analog voltage data). The wiring WL [1] to WL [m] is the electric potential _{V SS} as the low power supply potential, applying a potential _{V DATA} as the high power supply potential. The wirings CONTEXT [1] to CONTEXT [m] supply the ground potential GND as a low power supply potential and the potential V _CONTEXT as a high power supply potential.

  The circuit 102 includes circuits 104 [1] to 104 [m]. In each of the circuits 104 [1] to 104 [m], the terminal C is connected to the terminal A of the circuit 102, and the terminal D of the circuits 104 [1] to 104 [m] is connected to the terminal B of the circuit 102. Each of the circuits 104 [1] to [m] corresponds to one of the wiring BL, the wiring CONTEXT [1] to CONTEXT [m], and the wiring WL [1] to WL [m]. Connected to one wiring. A corresponding one of the wirings WL [1] to WL [m] is the wiring WL [j] in the circuit 104 [j] (j is any one of 1 to m). Further, the corresponding one of the wirings CONTEXT [1] to CONTEXT [m] is the wiring CONTEXT [j] in the circuit 104 [j].

  Each of the circuits 104 [1] to 104 [m] includes a transistor 105, a transistor 106, a transistor 107, and a capacitor 108. The first terminal of the transistor 105 is connected to the wiring BL, the second terminal of the transistor 105 is connected to the gate of the transistor 106, and the gate of the transistor 105 corresponds to one of the wirings WL [1] to WL [m]. Connected to book wiring. A first terminal of the transistor 106 is connected to the terminal C. The first terminal of the transistor 107 is connected to the second terminal of the transistor 106, the second terminal is connected to the terminal D of the transistor 107, and the gate of the transistor 107 is the wiring CONTEXT [1] to CONTEXT [m]. It is connected to one corresponding wiring. A first terminal of the capacitor 108 is connected to the gate of the transistor 106, and a second terminal of the capacitor 108 is connected to a wiring to which a predetermined potential is supplied.

  The transistor 105 has a channel length of 1 μm and a channel width of 4 μm, and the transistors 106 and 107 have a channel length of 0.5 μm and a channel width of 16 μm. In addition, the transistor 106 and the transistor 107 use silicon for a channel formation region.

The transistor 105 uses a CAAC-OS film that is an In—Ga—Zn oxide in a channel formation region. Accordingly, the off-state current of the transistor 105 is extremely small, and leakage of electric charge stored in the capacitor 108 can be reduced. Further, when the transistor 105 turned off, by a non-conducting state by applying a low voltage V _SS from the ground potential GND to the gate of the transistor 105, and further reduce the off-current of the transistor 105, a capacitor 108 This improves the charge retention characteristics.

Further, the transistor 105 has a back gate, and the threshold value of the transistor 105 can be controlled by changing the voltage V _{BG of the} back gate.

  Note that the transistor 106 has a gate capacitance of 16 fF and a storage capacitance of 2 fF, and the combined capacitance of the gate capacitance and the storage capacitance of the entire node SN is 18 fF.

  Next, FIG. 16 shows a photograph of a VCO chip configured with m = 2. FIG. 17 shows a layout diagram of a part of the VCO chip shown in FIG. The VCO shown in FIG. 16 includes a first region 113a, a second region 112a, a third region 113b, a fourth region 112b, and a fifth region 113c, and a sixth region not shown in FIG. A region 114a, a seventh region 114b, and an eighth region 115 are included.

  The sixth region 114a and the seventh region 114b include a wiring BL, a buffer for applying a potential to the wiring BL, and wiring around the buffer. The eighth region 115 includes wirings WL [1] and WL [2], wirings CONTEXT [1] and CONTEXT [2], a buffer for applying a potential to these wirings, and wiring around the buffers. It is.

  The planar layout illustrated in FIG. 17 includes an inverter 103 [1] included in the first region 113a, a circuit 104 [1-1], a circuit 104 [1-2], and a circuit 104 included in the second region 112a. [2-1], the circuit 104 [2-2], and the inverter 103 [2] included in the third region 113b are illustrated. Here, the circuit 104 [1-1] and the circuit 104 [1-2] indicate the circuit 104 [1] and the circuit 104 [2] included in the circuit 102 [1]. The circuits 104 [2-1] and 104 [2-2] refer to the circuits 104 [1] and 104 [2] included in the circuit 102 [2]. Note that the circuit 104 [1-1] and the circuit 104 [1-2] in the planar layout illustrated in FIG. 17 substantially correspond to the layout range illustrated in FIGS. 9A and 9B.

As shown in the above embodiment in FIG. 9 (B), the in circuit 104 [1-1] and the circuit 104 [1-2], the distance between the openings _{C 1} and the opening _{C 2 a 2} regarded as -a _1, the distance between the openings _{D 1} and the opening portion _{D 2} can be regarded as _b 1 -b _2. As shown in the plane layout shown in FIG. 17, the relationship is a ₂ −a ₁ = b ₁ −b ₂ also in the VCO according to the present embodiment.

That is, even in the VCO according to the present embodiment, the distance between the openings C ₁ and the opening C ₂ are equal distance and schematic between openings D ₁ and the opening portion D _2. Thereby, the wiring resistance between the terminal A and the terminal B of the circuit 102 can be made substantially equal regardless of the selection of the wiring path of the circuit 104.

  Further, as shown by the circuits 101 [1] and 101 [2] in FIG. 3, the planar layout shown in FIG. 17 is provided with the odd-numbered circuits 101 and the even-numbered circuits 101 in pairs. . Specifically, the odd-numbered stage circuit 102 (circuit 104 [1-1] and circuit 104 [1-2]) and the even-numbered stage circuit 102 (circuit 104 [2-1] and circuit 104 [2-2]). ) Are provided adjacent to each other in the row direction, and an odd number of inverters 103 (inverter 103 [1]) are provided adjacent to the lower side in the column direction for this group of circuits. An even-numbered inverter 103 (inverter 103 [2]) is provided adjacently. As a result, the space corresponding to the width in the row direction of the odd-numbered circuit 102 and the even-numbered circuit 102 can be used for the odd-numbered inverter 103 and the even-numbered inverter 103, respectively. Thus, the channel width of the transistors constituting the inverter 103 can be increased while suppressing an increase in the area occupied by the inverter 103.

FIG. 18A and FIG. 18B show the results of evaluating the oscillation frequency of the output with respect to the potential V _DATA (AVD) input from the wiring BL for the m = 2 VCO. In FIG. 18A, the horizontal axis represents potential V _DATA [V], and the vertical axis represents output oscillation frequency [MHz] on a linear scale. In FIG. 18B, the horizontal axis represents the potential V _DATA [V], and the vertical axis represents the output oscillation frequency [MHz] on a log scale.

The oscillation frequency was measured under three conditions of potential V _RO = 1.0V, 1.2V and 1.5V. Here, only the circuit 104 [1] is selected. For other conditions, V _CONTEXT = 3.0 V, V _BG = 0 V, V _SS = −0.2 V, and the writing time was 1.0 ms.

18A and 18B show that the oscillation frequency can be controlled simply by changing the AVD. Under the condition of V _RO = 1.5 V, the oscillation frequency is 197 mHz or more and 9.65 MHz or less in the range of potential V _DATA = 1.0 to 3.0 V, and it has a variable oscillation frequency band exceeding 7 digits. all right.

Note that the rate of change of the oscillation frequency differs with respect to the change of AVD. For example, when V _DATA is 2.5 V to 3.0 V, the oscillation frequency is 0.06 decades / 100 mV, and when V _DATA is 1.0 V to 1.5 V, the oscillation frequency is 1.24 decades / 100 mV. This is because when V _DATA is 2.5 V or more and 3.0 V or less, the conductivity of the transistor 106 is relatively high, and the delay due to the inverter 103 becomes dominant, and the influence of the change rate of the delay due to the transistor 106 on the change in AVD. Because it is small. On the other hand, when V _DATA is 1.0 V or more and 1.5 V or less, the conductivity of the transistor 106 is relatively low, the delay due to the transistor 106 becomes dominant, and the AVD dependence of the oscillation frequency is large.

In the region where the AVD is high, the delay due to the inverter 103 becomes dominant, so that the amount of change in the oscillation frequency when the potential _VRO is changed is large. The average increase rate of the oscillation frequency when V _DATA is 1.0 V or more and 1.5 V or less is 0.82 decades / 100 mV and 1.10 decades / 100 mV, respectively, when V _RO = 1.0 V, 1.2 V, and 1.5 V. , 1.24 decades / 100 mV. Therefore, an example in which the drive voltage of the inverter 103 is set high in an application where a wide frequency band is required, and the drive voltage of the inverter 103 is set low in an application in which small frequency control is required can be given.

Next, power consumption at each point illustrated in FIGS. 18A and 18B is illustrated in FIG. In FIG. 19, the horizontal axis represents potential V _DATA [V], and the vertical axis represents power consumption [mW].

Under each condition, it can be seen that the dependence of power consumption on V _RO and V _DATA is roughly correlated with the dependence of the oscillation frequency on V _RO and V _DATA shown in FIG. Thus, taking into account the power consumption and the oscillation frequency of interest, it is effective to set the V _RO and V _DATA. In addition, when V _DATA becomes relatively small with respect to V _RO , a voltage drop occurs through the circuit 104, an intermediate potential is applied to the inverter at the next stage, and there is a region where power efficiency is deteriorated.

Next, FIG. 20 shows changes in the oscillation frequency over time when V _DATA = 2.5 V is stored in the circuit 104 [1] and the VCO is oscillated at V _RO = 1.5 V. In FIG. 20, the horizontal axis represents elapsed time [hour], and the vertical axis represents oscillation frequency [MHz].

FIG. 20 shows the measurement results under two conditions of V _SS = 0V and −0.2V. In the initial state, the oscillation frequency was 9.10 MHz in both conditions, but under the condition of V _SS = 0V, the oscillation frequency attenuated as time passed, and the oscillation frequency was about 7.7% after 5 hours. The oscillation frequency decreased rapidly after that.

On the other hand, under the condition of V _SS = −0.2 V, there was almost no decrease in the oscillation frequency with time. The oscillation frequency after 24 hours was 9.02MH _Z, only 0.87% did not decrease. In correspondence with the graph of FIG. 18A, when V _DATA decreases uniformly, the attenuation of V _DATA after 24 hours is estimated to be about 30 mV.

Here, when the time is t (s), the storage capacitor C (F), and the voltage change amount ΔV (V), the leakage current I _leak is expressed by the following equation (2).

Since t = 86400 (s), C = 18 (fF), and ΔV = 0.03 V, the leakage current I _leak = 6E-21 (A) is estimated from the equation (2). Therefore, it can be seen that AVD can be retained for a long period of time by performing extremely low frequency refresh. In the following evaluation, the condition where the attenuation of the oscillation frequency after 24 hours was less than 1%, that is, V _SS = −0.2 V was set.

Next, FIG. 21A and FIG. 21B show changes in the spectrum of the oscillation frequency when the VCO is oscillated at V _RO = 1.5V. In FIGS. 21A and 21B, the horizontal axis represents the oscillation frequency [MHz], and the vertical axis represents the output [dBm].

FIG. 21A is a graph when AVD is set to 2.5V. The three spectra shown in FIG. 21A are a spectrum with 0 min immediately after applying V _DATA to the node SN through the wiring BL, a spectrum after 90 min, and a spectrum after 180 min.

FIG. 21B is a graph when AVD is set to 2.0V. The three spectra shown in FIG. 21B are a spectrum with 0 min immediately after applying V _DATA to the node SN through the wiring BL, a spectrum after 90 min, and a spectrum after 180 min.

  From FIG. 21A, when AVD = 2.5V, the peak frequency in the spectrum of 0 min is 9.10 MHz, and the peak frequency after the elapse of 180 min is 9.07 MHz. That is, the oscillation frequency is attenuated by 0.34%. On the other hand, from FIG. 21B, when AVD = 2.0 V, the peak frequency in the 0 min spectrum is 6.63 MHz, and the peak frequency when 180 min elapses is 6.58 MHz. That is, the oscillation frequency is attenuated by 0.74%.

Thus, it was found that, under the condition of V _SS = −0.2 V, the amount of change in the oscillation frequency is very small regardless of AVD, that is, the data retention characteristic of AVD is very good.

  Furthermore, the FOM (figure of merit) at t = 0 min when AVD was set to 2.5 V was calculated from the spectrum of FIG.

  Here, Phn is phase noise, Fc is a center frequency, and P is power consumption.

  Table 1 shows the FOM of this example and the FOMs of comparative example 1 and comparative example 2 of the ring oscillator type VCO. Comparative Example 1 is described in Reference 1 (S. B. Andand and B. Razavi, “A CMOS clock recovery circuit for 2.5-Gb / s NRZ data,” IEEE. J. Solid-State Circuits, v. 36. No. 3, pp. 432-439, Mar. 2001., Comparative Example 2 is Reference 2 (C. Zhai et al., “An N-path Filter Enhanced Low Phase Noise Ring VCO,” in Proc. VLSIs Cis. VLSI Cis. Symp., 2014, pp. 187-188.).

  As shown in Table 1, the VCO shown in this example has the same or better performance than the FOM of other ring oscillator type VCOs.

The VCO shown in this embodiment can hold the analog potential at the node SN and can maintain the oscillation frequency even when the power supply is restarted. FIGS. 22A and 22B show waveform diagrams obtained at the terminal OUT when restarting from a power-off state when V _{DATA is set} to 2.5 V as an example. Here, the evaluation was performed under the conditions of V _RO = 1.5 V, V _SS = −0.2 V, and V _BG = 0V. Note that FIG. 22B is an enlarged view of the vicinity of the restart in FIG.

  From the waveform diagrams shown in FIGS. 22A and 22B, it was found that oscillation was resumed in 100 ns or less when restarted from the power-off state at time (α + 1.0) μs. In FIG. 22A, α is 1 hour. That is, from FIGS. 22A and 22B, it was found that good oscillation was resumed even after 1 hour had elapsed.

  As described above, when the VCO according to this embodiment is applied to the PLL, the power to the constituent circuits other than the VCO can be turned off during a period other than the low-frequency refresh operation required for maintaining the oscillation frequency. Therefore, the PLL to which the VCO according to the present embodiment is applied can suppress power consumption.

Further, when the VCO according to the present embodiment is applied to the PLL, V _DATA for outputting the previous oscillation frequency can be held even when restarting from the power-off state. Therefore, an instantaneous restart can be performed.

The VCO shown in this embodiment sets different analog potential V _DATA for each of the circuits 104 [1] to 104 [m], and switches the selection of the circuits 104 [1] to 104 [m]. The oscillation frequency can be changed in a short time. In FIG. 23, V _RO = 1.5 V, V _DATA = 1.8 V is set in the circuit 104 [1], V _DATA = 2.5 V is set in the circuit 104 [2], and the circuits 104 [1] and 104 [ 2] is a waveform diagram obtained at the terminal OUT of the VCO when switching to [2].

  In FIG. 23, the circuit 104 [1] is selected in a period in which the time t is 0 μsec or more and less than 1.0 μsec, and a signal having an oscillation frequency of 4.0 MHz according to 1.8V AVD is output. When the selected circuit is changed to the circuit 104 [2] at t = 1.0 μsec, the oscillation frequency of the output signal instantaneously changes to 9.1 MHz.

  Thus, from the waveform diagram shown in FIG. 23, it was found that the VCO according to this example can switch the oscillation frequency in 100 ns or less.

As a result of evaluating the output oscillation frequency with respect to the potential V _DATA (AVD) input from the wiring BL by selecting the circuit 104 [1] and the circuit 104 [2] for the VCO of m = 2 shown in this embodiment. Is shown in FIG. In FIG. 24, the horizontal axis represents the potential V _DATA [V], and the vertical axis represents the output oscillation frequency [MHz].

The oscillation frequency was measured under three conditions of potential V _RO = 1.0V, 1.2V and 1.5V. For other conditions, V _CONTEXT = 2.5 V, V _BG = 0 V, V _SS = −0.2 V, and the writing time was 1.0 ms.

As shown in FIG. 24, for any condition of potential V _RO = 1.0V, 1.2V, and 1.5V, if the AVD input in the circuit 104 [1] and the circuit 104 [2] is the same, it is output. The oscillation frequency is almost the same. That is, in the VCO shown in this embodiment, the oscillation frequency is the same regardless of which of the circuit 104 [1] and the circuit 104 [2] is selected.

  From the above, it can be seen that in the VCO shown in this embodiment, the wiring length can be made substantially uniform regardless of the circuit 104 to be selected, and the occurrence of signal delay due to the difference in the circuit 104 to be selected can be prevented. It was done. Thus, in the semiconductor device according to one embodiment of the present invention, the oscillation frequency corresponding to specific data can be made approximately equal, so that the accuracy of the oscillation frequency can be improved.

Next, in a VCO with m = 8, V _DATA = 2.5V is set in the circuits 104 [1] to 104 [8], and the number of circuits 104 to be selected is 1, 2, 3, 4 and oscillates. The frequency was measured. Here, the evaluation was performed under the conditions of V _RO = 3.0 V, V _SS = −0.2 V, and V _BG = 0V. FIG. 25 shows a graph of the relationship between the number of circuits 104 to be selected and the oscillation frequency.

  The oscillation frequency when one circuit 104 is selected is 6.97 MHz, whereas the number of circuits 104 to be selected is 2, 3, and 4, so that the oscillation frequency is 9.93 MHz, 10.80 MHz, 11 Increase to 10 MHz. This is because increasing the number of circuits 104 to be selected improves the conductivity of the circuit 102 and reduces the delay. That is, the oscillation frequency can be controlled by the number of circuits 104 to be selected.

  If the number of circuits 104 to be selected is increased and the conductivity is improved, the contribution of the delay time in the inverter is relatively increased at the oscillation frequency of the VCO. Therefore, as the number of circuits 104 to be selected is increased, the increase rate of the oscillation frequency of the VCO with respect to the increase in the number of circuits 104 to be selected is lowered.

  When a VCO having a plurality of analog memory sets is used, each circuit 104 can hold different AVDs. Therefore, it is possible to finely control a wider oscillation frequency band by performing digital control for changing the number of circuits 104 to be selected and analog control for changing the value of AVD.

22 transistor 23 transistor 90 transistor 91 insulating film 92a oxide semiconductor film 92b oxide semiconductor film 92c oxide semiconductor film 93 conductive film 94 conductive film 95 insulating film 96 conductive film 97 substrate 101 circuit 102 circuit 103 inverter 104 circuit 105 transistor 106 transistor 107 Transistor 108 Capacitor 112a Region 112b Region 113a Region 113b Region 113c Region 114a Region 114b Region 115 Region 201 Phase comparator 202 Loop filter 203 Voltage controlled oscillator 204 Frequency divider 300 Substrate 310 Insulating film 311 Insulating film 311 Insulating film 313 Insulating film 314 Insulating film 315 Insulating film 316 Insulating film 317 Insulating film 320 Semiconductor film 320a Impurity region 320b Impurity region 320c Impurity region 320d Impurity region 3 20e Impurity region 320f Channel formation region 320g Channel formation region 322a Gate insulation film 322b Gate insulation film 324a Gate electrode 324b Gate electrode 326a Side wall insulation film 326b Side wall insulation film 328a Conductive film 328b Conductive film 328c Conductive film 330a Conductive film 330b Conductive film 330c conductive film 332 conductive film 334 conductive film 336 conductive film 340 oxide semiconductor film 340a oxide semiconductor film 340c oxide semiconductor film 342a conductive film 342b conductive film 344a conductive film 344b conductive film 346 gate insulating film 348 gate electrode 350a conductive film 350b Conductive film 350c Conductive film 400 Substrate 401 Element isolation region 402 Impurity region 403 Impurity region 404 Channel formation region 405 Insulating film 406 Gate electrode 411 Insulating film 412 Conductive film 413 Conductive film 414 Conductive film 416 Conductive film 417 Conductive film 418 Conductive film 420 Insulating film 421 Insulating film 422 Insulating film 430 Semiconductor film 430a Oxide semiconductor film 430c Oxide semiconductor film 431 Gate insulating film 432 Conductive film 433 Conductive film 434 Gate electrode 601 Semiconductor substrate 610 Element isolation region 611 Insulating film 612 Insulating film 613 Insulating film 625 Conductive film 626 Conductive film 627 Conductive film 634 Conductive film 635 Conductive film 636 Conductive film 637 Conductive film 644 Conductive film 651 Conductive film 652 Conductive film 653 Conductive Film 661 Insulating film 662 Gate insulating film 663 Insulating film 701 Semiconductor film 710 Region 711 Region 721 Conductive film 722 Conductive film 731 Gate electrode 5001 Case 5002 Case 5003 Display portion 5004 Display portion 5005 Microphone 5006 Speaker 5007 Control Construction key 5008 Stylus 5101 Car body 5102 Wheel 5103 Dashboard 5104 Light 5301 Housing 5302 Refrigeration room door 5303 Freezer compartment door 5401 Housing 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 Housing 5602 Housing 5603 Display unit 5604 Display unit 5605 Connection portion 5606 Operation key 5801 Case 5802 Case 5803 Display portion 5804 Operation key 5805 Lens 5806 Connection portion

Claims (8)

Having an oscillation circuit,
The oscillation circuit includes first to n-th (n is an odd number of 3 or more) inverters, a first circuit, and a second circuit.
A first terminal of the first circuit is electrically connected to an output terminal of the i-th inverter (i is any one of 1 to n-1);
A second terminal of the first circuit is electrically connected to an input terminal of the i + 1th inverter;
A first terminal of the second circuit is electrically connected to an output terminal of the i-th inverter;
A second terminal of the second circuit is electrically connected to an input terminal of the i + 1th inverter;
A wiring path between the output terminal of the i-th inverter and the first terminal of the first circuit, and between the second terminal of the first circuit and the input terminal of the i + 1-th inverter. The sum of the length of the wiring path and
A wiring path between the output terminal of the i-th inverter and the first terminal of the second circuit, and between the second terminal of the second circuit and the input terminal of the i + 1-th inverter. A semiconductor device characterized in that a sum of lengths of wiring paths is substantially equal. In claim 1,
An insulating film on at least a part of the first circuit and the second circuit;
On the insulating film, a first wiring electrically connected to an output terminal of the i-th inverter and a second wiring electrically connected to an input terminal of the i + 1-th inverter are provided. ,
The first wiring is electrically connected to a first terminal of the first circuit through a first opening provided in the insulating film, and a second wiring provided in the insulating film. Electrically connected to the first terminal of the second circuit through the opening,
The second wiring is electrically connected to a second terminal of the first circuit through a third opening provided in the insulating film, and a fourth wiring provided in the insulating film. Electrically connected to the second terminal of the second circuit through the opening;
A distance between the first opening and the second opening is approximately equal to a distance between the third opening and the fourth opening. In claim 1 or claim 2,
A first region in which the j-th inverter (j is an odd number from 1 to n) is provided;
A second region in which the first circuit and the second circuit are provided;
A third region provided with the k-th inverter (k is an even number not less than 2 and not more than n-1),
The semiconductor device, wherein the second region is located between the first region and the third region. In any one of Claims 1 thru | or 3,
The first circuit has a function of storing first data;
The first circuit makes the first terminal and the second terminal non-conductive, or sets a resistance value between the first terminal and the second terminal to a value based on the first data. Has a function to switch between
The second circuit has a function of storing second data;
The second circuit makes the first terminal and the second terminal non-conductive, or sets a resistance value between the first terminal and the second terminal to a value based on the second data. A semiconductor device having a function of switching whether or not to perform. In any one of Claims 1 thru | or 4,
The semiconductor device, wherein the first data and the second data are analog potentials. In any one of Claims 1 thru | or 5,
The first circuit includes a first transistor and a first capacitor,
The second circuit includes a second transistor and a second capacitor,
The first data is input to the first capacitor through the first transistor,
The second data is input to the second capacitor through the second transistor,
The first transistor includes an oxide semiconductor in a channel formation region,
The semiconductor device, wherein the second transistor includes an oxide semiconductor in a channel formation region. In any one of Claims 1 thru | or 6,
The first circuit includes a third transistor and a fourth transistor,
The second circuit includes a fifth transistor and a sixth transistor,
The third transistor and the fourth transistor are electrically connected in series between a first terminal of the first circuit and a second terminal of the first circuit,
The fifth transistor and the sixth transistor are electrically connected in series between a first terminal of the second circuit and a second terminal of the second circuit;
The resistance value between the source and drain of the third transistor has a value based on the first data,
The fourth transistor has a function of controlling conduction or non-conduction between the first terminal of the first circuit and the second terminal of the first circuit;
The resistance value between the source and the drain of the fifth transistor has a value based on the second data,
The sixth transistor has a function of controlling conduction or non-conduction between a first terminal of the second circuit and a second terminal of the second circuit. In any one of Claims 1 thru | or 7,
Having a PLL,
The PLL includes the oscillation circuit, a frequency divider, a phase comparator, and a loop filter.