JP2016085337A - Semiconductor device, semiconductor storage device, and reliability test of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device mounted with a random number generator which can easily and efficiently perform a reliability test of the random number generator.SOLUTION: A memory controller 11 has a self-test processing unit 22 that performs a reliability test of a random number generator 12. The self-test processing unit 22 inputs a predetermined control signal D7 to the random number generator 12 so as to cause the random number generator 12 to generate a random number value D8, and inspects the irreproducibility of the random number D8 generated by the random number generator 12.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, a semiconductor memory device, and a semiconductor device reliability test method.

  The random number generator is a cryptographic technique used for various purposes in many security systems.

  The random number generated by the random number generator is used for encryption algorithm key information or an authentication code for mutual authentication between devices, and is highly confidential information closely related to the security strength of the system. is there.

  Therefore, the random number generated by the random number generator is required to have high randomness, and when the semiconductor device mounted with the random number generator is shipped, it is evaluated whether the random number generator can generate the requested level of random numbers. Usually, a random number test is performed.

  Patent Documents 1 and 2 below disclose a technique for evaluating whether or not the appearance frequency of “0” or “1” is within an allowable range with respect to the random number generated by the random number generator. Yes.

JP-T-2005-517998 International Publication No. WO2005 / 124537

  As a general random number evaluation method, a statistical test method such as “NIST Special Publication 800-22” or “DIEHARD” has been proposed. However, in a random number test performed at the time of shipment of a semiconductor device on which a random number generator is mounted, if a complex random number evaluation using such a statistical test method is performed, the processing load of the tester device increases and the test load increases. The required time becomes longer, and as a result, the test cost of the shipping test increases.

  The present invention has been made in view of such circumstances, and a semiconductor device capable of easily and efficiently executing a reliability test of a random number generator for a semiconductor device on which a random number generator is mounted, An object of the present invention is to obtain a semiconductor memory device and a semiconductor device reliability test method.

  A semiconductor device according to a first aspect of the present invention includes a random number generator that generates a random number, and a memory controller connected to the random number generator, wherein the memory controller is a reliability test of the random number generator. The self-test processing unit inputs a predetermined control signal to the random number generator to cause the random number generator to generate a random value, and the random number generator generates the self-test processing unit. It is characterized by checking the non-reproducibility of random values.

  According to the semiconductor device of the first aspect, the self-test processing unit causes the random number generator to generate a random value by inputting a predetermined control signal to the random number generator, and the random number generated by the random number generator is generated. Check for reproducibility. By performing the self test by the self test processing unit, it becomes possible to easily and efficiently execute the reliability test of the random number generator. Further, by limiting the reliability test of the random number generator to the inspection of the non-reproducibility of the random number value, it becomes possible to facilitate the test and reduce the test cost. It is particularly effective to apply the present invention to an apparatus in which the uniformity of random numbers is ensured by a processing block different from the random number generator.

  The semiconductor device according to the second aspect of the present invention is the semiconductor device according to the first aspect, and further includes a storage unit (a memory array, an internal register of a memory controller, a RAM, or the like), and the self-test processing unit includes: The random number value generated by the random number generator is stored in the storage unit, and the non-reproducibility of the random number value generated by the random number generator is checked based on the random number value read from the storage unit. It is what.

  According to the semiconductor device of the second aspect, the self-test processing unit stores the random value generated by the random number generator in the storage unit, and the random number generator generates the random number value read from the storage unit Check the reproducibility of random values. By storing the random number value generated in the past by the random number generator in the storage unit, the self-test processing unit reproduces random number sticking, periodicity, bias, etc. based on the random value read from the storage unit It becomes possible to check the impossibility.

  The semiconductor device according to a third aspect of the present invention is the semiconductor device according to the second aspect, in particular, the number of times information specifying the number of times the random number generator generates a random number value is received by the semiconductor device from an external device. The self-test processing unit extracts the number-of-times information from the test command, and causes the random number generator to sequentially generate a plurality of random number values based on the number-of-times information. Is.

  According to the semiconductor device of the third aspect, the self-test processing unit extracts the number information from the test command, and causes the random number generator to sequentially generate a plurality of random number values based on the number information. As a result, a plurality of random number values generated in order by the random number generator can be stored in the storage unit, and the self-test processing unit reads out the plurality of random number values from the storage unit, thereby checking the reproducibility of the random number value. It becomes possible to do. Also, by including the number information in the test command, the number information can be easily changed by an external device.

  The semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the second aspect, in particular, the number information specifying the number of times that the random number generator generates a random number value is stored in a predetermined manner in the semiconductor device. The self-test processing unit reads out the number information from the storage unit, and causes the random number generator to sequentially generate a plurality of random number values based on the number information. is there.

  According to the semiconductor device of the fourth aspect, the number-of-times information is stored in the predetermined storage unit in the semiconductor device, and the self-test processing unit stores the number-of-times information in the random number generator based on the number-of-times information read from the storage unit. Generate multiple random values in order. As a result, a plurality of random number values generated in order by the random number generator can be stored in the storage unit, and the self-test processing unit reads out the plurality of random number values from the storage unit, thereby checking the reproducibility of the random number value. It becomes possible to do.

  In a semiconductor device according to a fifth aspect of the present invention, in particular, in the semiconductor device according to the third or fourth aspect, the self-test processing unit starts an inspection of a random value when the number-of-times information is input. When the inspection is completed, the inspection result is transmitted to the external device.

  According to the semiconductor device of the fifth aspect, the self-test processing unit starts the inspection of the random number value when the number-of-times information is input, and transmits the inspection result to the external device when the inspection is completed. Therefore, with respect to the reliability test of the random number generator, the test pattern creation processing by the external device and the collation processing with the expected value are not required, and the processing load on the external device can be reduced.

  The semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, in particular, the self-test processing unit performs the random number value non-reproducibility test as described above. It is characterized by checking whether or not the same random number value is continuously generated by the random number generator.

  According to the semiconductor device of the sixth aspect, the self-test processing unit checks whether or not the same random number value is continuously generated by the random number generator as a check of the reproducibility of the random number value. As a result, it is possible to easily check whether the random number is stuck.

  The semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, in which the self-test processing unit performs the reproducibility test of the random value as It is characterized by checking whether or not the same random number value is included in a plurality of random number values generated by the random number generator.

  According to the semiconductor device of the seventh aspect, the self-test processing unit includes the same random number value among the plurality of random number values generated by the random number generator as a test of the non-reproducibility of the random number value. Inspect whether or not As a result, it is possible to easily check whether the random number has periodicity.

  The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to any one of the first to seventh aspects, in particular, the self-test processing unit is configured as the random number value non-reproducibility test as described above. It is characterized by checking whether or not the appearance ratio of “0” or “1” in the random value generated by the random number generator is within a predetermined allowable range.

  According to the semiconductor device of the eighth aspect, the self-test processing unit has an appearance ratio of “0” or “1” in the random number value generated by the random number generator as a test of the non-reproducibility of the random number value. Inspect whether it is within a predetermined tolerance. As a result, it is possible to easily check whether each bit of the random number is biased by “0” or “1”.

  A semiconductor memory device according to a ninth aspect of the present invention includes a random number generator that generates a random number, a memory controller connected to the random number generator, and a storage unit, and the memory controller generates the random number. A self-test processing unit that executes a reliability test of the generator, the self-test processing unit causing the random number generator to generate a random value by inputting a predetermined control signal to the random number generator, and the random number The random number value generated by the generator is stored in the storage unit, and the non-reproducibility of the random number value generated by the random number generator is checked based on the random number value read from the storage unit It is.

  According to the semiconductor memory device of the ninth aspect, the self-test processing unit causes the random number generator to generate a random value by inputting a predetermined control signal to the random number generator, and the random number value generated by the random number generator Is stored in a storage unit (a memory array, an internal register of a memory controller, a RAM, or the like), and the reproducibility of the random number value generated by the random number generator is checked based on the random number value read from the storage unit. By performing the self test by the self test processing unit, it becomes possible to easily and efficiently execute the reliability test of the random number generator. Further, by storing the random number value generated in the past by the random number generator in the storage unit, the self-test processing unit can attach the random number, the periodicity, the bias, or the like based on the random value read from the storage unit. It becomes possible to inspect the non-reproducibility of. Further, by limiting the reliability test of the random number generator to the inspection of the non-reproducibility of the random number value, it becomes possible to facilitate the test and reduce the test cost. It is particularly effective to apply the present invention to an apparatus in which the uniformity of random numbers is ensured by a processing block different from the random number generator.

  According to a tenth aspect of the present invention, there is provided a reliability test method for a semiconductor device comprising: a random number generator that generates a random number; and a self-test processing unit that performs a reliability test of the random number generator. (A) causing the self-test processing unit to input a predetermined control signal to the random number generator to cause the random number generator to generate a random value; and (B) the self-test. The processing unit includes a step of checking the non-reproducibility of the random number value generated by the random number generator.

  According to the reliability test method for a semiconductor device according to the tenth aspect, the self-test processing unit causes the random number generator to generate a random value by inputting a predetermined control signal to the random number generator, and the random number generator Check the reproducibility of the generated random value. By performing the self test by the self test processing unit, it becomes possible to easily and efficiently execute the reliability test of the random number generator. Further, by limiting the reliability test of the random number generator to the inspection of the non-reproducibility of the random number value, it becomes possible to facilitate the test and reduce the test cost. It is particularly effective to apply the present invention to an apparatus in which the uniformity of random numbers is ensured by a processing block different from the random number generator.

  According to the present invention, it becomes possible to easily and efficiently execute a reliability test of a random number generator for a storage device in which the random number generator is mounted.

It is a figure which shows the condition which is implementing the shipping test for the semiconductor memory device which concerns on embodiment of this invention. It is a figure which shows the structure of a semiconductor memory device. It is a figure which shows the memory area of a memory array. 3 is a flowchart showing a flow of a reliability test process for a semiconductor memory device. It is a flowchart which shows the flow of the process which a memory controller performs in a memory test. It is a flowchart which shows the flow of the process which a memory controller performs in a random number test. It is a flowchart which shows the flow of the process which a memory controller performs in a random number test. It is a flowchart which shows the flow of the process which a memory controller performs in a random number test.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the element which attached | subjected the same code | symbol in different drawing shall show the same or corresponding element.

  FIG. 1 is a diagram showing a situation in which a shipping test is performed on a semiconductor memory device (semiconductor device) 1 according to an embodiment of the present invention. By connecting a plurality of semiconductor memory devices 1 to one tester device 2, a reliability test is simultaneously performed on the plurality of semiconductor memory devices 1. The semiconductor memory device 1 is, for example, a memory card that can be detachably connected to a host device. Alternatively, any storage device such as an optical disk or a magnetic disk can be used instead of the memory card. Instead of the tester device 2, the reliability test of the semiconductor memory device 1 can be performed using an arbitrary external device such as a simple tester or a host device having a test function.

  FIG. 2 is a diagram showing a configuration of the semiconductor memory device 1. The semiconductor memory device 1 includes a memory controller 11, a random number generator 12 that generates a true random number using an indeterminate circuit, and a memory array 13 that uses a NAND flash memory or the like.

  As shown in the connection relationship of FIG. 2, the memory controller 11 includes an encryption / decryption processing unit 21, a self test processing unit 22, a register 23, and selectors 24 to 26.

  FIG. 3 is a diagram showing a memory area of the memory array 13. The memory array 13 has a content data storage area R1 for storing content data and a test data storage area R2 for storing test data.

  FIG. 4 is a flowchart showing a flow of reliability test processing for the semiconductor memory device 1. First, in step SP11, the tester apparatus 2 executes a reliability test of the memory array 13 (hereinafter referred to as “memory test”). When the memory test is completed, the tester apparatus 2 next executes a reliability test (hereinafter referred to as “random number test”) of the random number generator 12 in step SP12. Thus, for the semiconductor memory device 1, the memory test and the random number test are executed separately in time series. Note that the execution order of the memory test and the random number test may be opposite to the example shown in FIG.

<Reliability test of memory array>
FIG. 5 is a flowchart showing a flow of processing executed by the memory controller 11 in the memory test. When executing a memory test in the shipping test, first, the tester apparatus 2 generates a predetermined fixed random number value to be used by the encryption / decryption processing unit 21 in the memory test, and then generates a test pattern and its expected value. Next, the tester apparatus 2 stores the fixed random number value in a dedicated test command (hereinafter referred to as “memory test command”) for instructing execution of the memory test, and then transmits the memory test command to a known test mode encryption code. Encrypt using an algorithm. Then, the encrypted memory test command is transmitted to the semiconductor memory device 1 as data D1. Note that encryption of the memory test command may be omitted.

  With reference to FIG. 5, first, in step SP <b> 21, the memory controller 11 receives the encrypted memory test command transmitted from the tester apparatus 2. The received encrypted memory test command is decrypted by the encryption / decryption processing unit 21 using the test mode encryption algorithm. The encryption / decryption processing unit 21 outputs the decrypted memory test command as data D2.

  Next, in step SP22, the memory controller 11 recognizes from the command ID that the memory test command has been received from the tester device 2, and thereby switches the input terminals of the selectors 24-26 to the “0” side in FIG.

  Next, in step SP23, the memory controller 11 extracts the fixed random value from the memory test command output from the encryption / decryption processing unit 21 in step SP21.

  Next, in step SP24, the memory controller 11 inputs the fixed random value extracted in step SP23 to the register 23 as data D3. As a result, the fixed random number value is stored in the register 23.

  Next, in step SP25, the memory controller 11 inputs the fixed random number value stored in the register 23 to the encryption / decryption processing unit 21 via the selector 24. As a result, the memory controller 11 initializes the encryption / decryption processing unit 21 with the fixed random number value.

  Next, in step SP26, the memory controller 11 notifies the tester apparatus 2 that the initialization of the encryption / decryption processing unit 21 has been completed as a return value for the memory test command.

  Next, in step SP27, the memory controller 11 executes a reliability test of the memory array 13 using the test pattern generated by the tester device 2. For example, the tester device 2 transmits an encrypted test pattern encrypted using the fixed random number value to the semiconductor memory device 1. The memory controller 11 uses the encryption / decryption processing unit 21 to decrypt the encrypted test pattern received from the tester apparatus 2 using the fixed random number value. Next, the memory controller 11 inputs the address included in the decoded test pattern to the memory array 13 through the selector 26 as data D4. Next, the memory controller 11 inputs the data D5 read from the memory array 13 to the encryption / decryption processing unit 21 via the selector 25. Next, the memory controller 11 transmits the encrypted data to the tester device 2 by encrypting the data D5 by the encryption / decryption processing unit 21 using the fixed random number value.

  The tester device 2 decrypts the encrypted data received from the semiconductor memory device 1 using the fixed random number value. Then, the reliability of the memory array 13 is evaluated by collating the value of the decrypted data with the expected value of the test pattern generated above.

  In the above description, the example in which the fixed random number value is included in the memory test command and transmitted from the tester device 2 to the semiconductor memory device 1 has been described. However, the present invention is not limited to this example. For example, the fixed random number value may be stored in advance in an arbitrary storage unit (memory array 13, RAM, ROM, register, or the like) in the semiconductor memory device 1. In this case, the memory controller 11 receives the memory test command from the tester device 2, reads the fixed random value from the storage unit, and stores the fixed random value in the register 23.

<Reliability test of random number generator (first example: evaluation of sticking of random number)>
FIG. 6 is a flowchart showing a flow of processing executed by the memory controller 11 in the random number test. When a random number test is executed in the shipping test, first, the tester device 2 generates number information for designating the number of times of random number acquisition from the random number generator 12. Next, the tester apparatus 2 stores the number-of-times information in a dedicated test command (hereinafter referred to as “random number test command”) for instructing execution of a random number test, and then uses the random number test command as a known test mode cryptographic algorithm. Encrypt using. Then, the encrypted random number test command is transmitted to the semiconductor memory device 1 as data D1. Note that encryption of the random number test command may be omitted.

  With reference to FIG. 6, first in step SP31, the memory controller 11 receives the encrypted random number test command transmitted from the tester apparatus 2. The received encrypted random number test command is decrypted by the encryption / decryption processing unit 21 using the test mode encryption algorithm. The encryption / decryption processing unit 21 outputs the decrypted random number test command as data D2.

  Next, in step SP32, the memory controller 11 recognizes that the random number test command has been received from the tester device 2 by the command ID, thereby switching the input terminals of the selectors 24 to 26 to the “1” side in FIG.

  Next, in step SP33, the memory controller 11 extracts the number-of-times information from the random number test command output from the encryption / decryption processing unit 21 in step SP31.

  Next, in step SP34, the memory controller 11 inputs the number-of-times information extracted in step SP33 to the self-test processing unit 22 as data D6. As a result, the number of acquisitions of the random number value from the random number generator 12 is designated to the self-test processing unit 22.

  Next, in step SP35, the memory controller 11 inputs a control signal D7 for instructing the random number generator 12 to generate a random number value from the self-test processing unit 22 to the random number generator 12. The random number generator 12 generates a random value D8 when the control signal D7 is input. Next, the memory controller 11 inputs the random number value D <b> 8 output from the random number generator 12 to the self test processing unit 22.

  Next, in step SP36, the memory controller 11 inputs the address D9 in the test data storage area R2 for storing the random value D8 from the self test processing unit 22 to the memory array 13 via the selector 26. In addition, the memory controller 11 inputs the random value D8 acquired in step SP35 from the self-test processing unit 22 to the memory array 13. As a result, the random value D8 acquired in step SP35 is stored at the designated address in the test data storage area R2.

  Next, in step SP <b> 37, the memory controller 11 reads the random number value D <b> 8 that was generated one time before and stored in the memory array 13 from the memory array 13 to the self-test processing unit 22. Next, the memory controller 11 obtains the latest random number value D8 (hereinafter referred to as “new random number value”) acquired in step SP35, and the previous random number value D8 read from the memory array 13 (hereinafter referred to as “old random number value”). Are compared by the self-test processing unit 22.

  If the result of determination in step SP37 is that the new random number value D8 and the old random number value D8 are the same, then in step SP39, the memory controller 11 continuously generates the same random number value by the random number generator 12. The test result indicating that this is the case (that is, the test result indicating that sticking of random numbers has occurred) is input from the self-test processing unit 22 to the encryption / decryption processing unit 21 via the selector 25 as data D10. Next, the memory controller 11 encrypts the inspection result using the test mode encryption algorithm by the encryption / decryption processing unit 21, and transmits the result to the tester device 2. The tester device 2 decrypts the encrypted inspection result received from the semiconductor memory device 1 by using the test mode encryption algorithm, so that the reliability of the random number generator 12 (in this case, the sticking of the random number is suppressed). Evaluate).

  If the result of determination in step SP37 is that the new random number value D8 and the old random number value D8 are not the same, then in step SP39, the memory controller 11 has acquired the random number value D8 for the number of times specified by the number information. Is determined by the self-test processing unit 22.

  If acquisition of the random number D8 for the specified number of times has not been completed, the memory controller 11 repeatedly executes the processing after step SP35.

  On the other hand, when acquisition of the random number value D8 for the specified number of times is completed, in step SP39, the memory controller 11 then uses the self-test processing unit 22 as the data D10 as an inspection result indicating that no random number sticking has occurred. To the encryption / decryption processing unit 21 via the selector 25. Next, the memory controller 11 encrypts the inspection result using the test mode encryption algorithm by the encryption / decryption processing unit 21, and transmits the result to the tester device 2. The tester device 2 decrypts the encrypted inspection result received from the semiconductor memory device 1 by using the test mode encryption algorithm, so that the reliability of the random number generator 12 (in this case, the sticking of the random number is suppressed). Evaluate what has not happened.

  In the above description, the number information is included in the random number test command and transmitted from the tester device 2 to the semiconductor memory device 1. However, the present invention is not limited to this example. For example, the number information may be stored in advance in an arbitrary storage unit (memory array 13, RAM, ROM, register, or the like) in the semiconductor memory device 1. In this case, the memory controller 11 receives the random number test command from the tester device 2, thereby reading the number information from the storage unit and inputting it to the self-test processing unit 22. The same applies to second and third examples described later.

  In the above description, the example in which the old random number value D8 is stored in the test data storage area R2 of the memory array 13 has been described. However, the present invention is not limited to this example. The old random value D8 may be stored in an internal register of the memory controller 11 or a RAM. The same applies to second and third examples described later.

<Reliability test of random number generator (second example: evaluation of periodicity of random number)>
FIG. 7 is a flowchart showing a flow of processing executed by the memory controller 11 in the random number test. When a random number test is executed in the shipping test, first, the tester device 2 generates number information for designating the number of times of random number acquisition from the random number generator 12. Next, after storing the number-of-times information in the random number test command, the tester device 2 encrypts the random number test command using a known test mode encryption algorithm. Then, the encrypted random number test command is transmitted to the semiconductor memory device 1 as data D1. Note that encryption of the random number test command may be omitted.

  With reference to FIG. 7, first, in step SP51, the memory controller 11 receives the encrypted random number test command transmitted from the tester apparatus 2. The received encrypted random number test command is decrypted by the encryption / decryption processing unit 21 using the test mode encryption algorithm. The encryption / decryption processing unit 21 outputs the decrypted random number test command as data D2.

  Next, in step SP52, the memory controller 11 recognizes that the random number test command has been received from the tester device 2 based on the command ID, thereby switching the input terminals of the selectors 24 to 26 to the “1” side in FIG.

  Next, in step SP53, the memory controller 11 extracts the number-of-times information from the random number test command output from the encryption / decryption processing unit 21 in step SP51.

  Next, in step SP54, the memory controller 11 inputs the number-of-times information extracted in step SP53 to the self-test processing unit 22 as data D6. As a result, the number of acquisitions of the random number value from the random number generator 12 is designated to the self-test processing unit 22.

  Next, in step SP55, the memory controller 11 inputs a control signal D7 for instructing the random number generator 12 to generate a random number value from the self-test processing unit 22 to the random number generator 12. The random number generator 12 generates a random value D8 when the control signal D7 is input. Next, the memory controller 11 inputs the random number value D <b> 8 output from the random number generator 12 to the self test processing unit 22.

  Next, in step SP56, the memory controller 11 inputs the address D9 in the test data storage area R2 for storing the random value D8 from the self test processing unit 22 to the memory array 13 via the selector 26. In addition, the memory controller 11 inputs the random value D8 acquired in step SP55 from the self-test processing unit 22 to the memory array 13. As a result, the random value D8 acquired in step SP55 is stored at the designated address in the test data storage area R2.

  Next, in step SP57, the memory controller 11 reads all random number values D8 stored in the memory array 13 at that time from the memory array 13 to the self-test processing unit 22. Next, the memory controller 11 acquires the latest random number value D8 (hereinafter referred to as “new random value”) acquired in step SP55 and the existing random number value D8 read from the memory array 13 (hereinafter referred to as “existing random number value”). Are compared by the self-test processing unit 22.

  If the result of determination in step SP57 is that the new random number value D8 is the same as any of the existing random number values D8, then in step SP59, the memory controller 11 uses the random number generator 12 to generate the same random number value in duplicate. A test result indicating that the random number has been generated (that is, a test result indicating that a random periodicity has occurred) is input from the self-test processing unit 22 to the encryption / decryption processing unit 21 via the selector 25 as data D10. Next, the memory controller 11 encrypts the inspection result using the test mode encryption algorithm by the encryption / decryption processing unit 21, and transmits the result to the tester device 2. The tester device 2 decrypts the encrypted inspection result received from the semiconductor memory device 1 using the test mode encryption algorithm, thereby improving the reliability of the random number generator 12 (in this case, the periodicity of the random number). Is evaluated).

  If the result of determination in step SP57 is that the new random number value D8 is not the same as all existing random number values D8, then in step SP58, the memory controller 11 acquires random number values D8 for the number of times specified by the number information. The self-test processing unit 22 determines whether or not it has been performed.

  If acquisition of the random number D8 for the specified number of times has not been completed, the memory controller 11 repeatedly executes the processing from step SP55.

  On the other hand, when acquisition of the random number D8 for the specified number of times is completed, in step SP59, the memory controller 11 then uses the self-test processing unit as the data D10 as an inspection result indicating that random number periodicity has not occurred. 22 to the encryption / decryption processing unit 21 via the selector 25. Next, the memory controller 11 encrypts the inspection result using the test mode encryption algorithm by the encryption / decryption processing unit 21, and transmits the result to the tester device 2. The tester device 2 decrypts the encrypted inspection result received from the semiconductor memory device 1 using the test mode encryption algorithm, thereby improving the reliability of the random number generator 12 (in this case, the periodicity of the random number). Is not occurring).

<Reliability test of random number generator (third example: evaluation of random number bias)>
FIG. 8 is a flowchart showing a flow of processing executed by the memory controller 11 in the random number test. When a random number test is executed in the shipping test, first, the tester device 2 generates number information for designating the number of times of random number acquisition from the random number generator 12. Next, after storing the number-of-times information in the random number test command, the tester device 2 encrypts the random number test command using a known test mode encryption algorithm. Then, the encrypted random number test command is transmitted to the semiconductor memory device 1 as data D1. Note that encryption of the random number test command may be omitted.

  Referring to FIG. 8, first, in step SP <b> 71, the memory controller 11 receives the encrypted random number test command transmitted from the tester apparatus 2. The received encrypted random number test command is decrypted by the encryption / decryption processing unit 21 using the test mode encryption algorithm. The encryption / decryption processing unit 21 outputs the decrypted random number test command as data D2.

  Next, in step SP72, the memory controller 11 switches the input terminals of the selectors 24 to 26 to the “1” side in FIG. 2 by recognizing from the command ID that the random number test command has been received from the tester device 2.

  Next, in step SP73, the memory controller 11 extracts the number-of-times information from the random number test command output from the encryption / decryption processing unit 21 in step SP71.

  Next, in step SP74, the memory controller 11 inputs the number-of-times information extracted in step SP73 to the self-test processing unit 22 as data D6. As a result, the number of acquisitions of the random number value from the random number generator 12 is designated to the self-test processing unit 22.

  Next, in step SP75, the memory controller 11 inputs a control signal D7 for instructing the random number generator 12 to generate a random number value from the self-test processing unit 22 to the random number generator 12. The random number generator 12 generates a random value D8 when the control signal D7 is input. Next, the memory controller 11 inputs the random number value D <b> 8 output from the random number generator 12 to the self test processing unit 22.

  Next, in step SP76, the memory controller 11 inputs the address D9 in the test data storage area R2 for storing the random value D8 from the self test processing unit 22 to the memory array 13 via the selector 26. In addition, the memory controller 11 inputs the random value D8 acquired in step SP75 from the self-test processing unit 22 to the memory array 13. Thereby, the random value D8 acquired in step SP75 is stored in the designated address in the test data storage area R2.

  Next, in step SP77, the memory controller 11 determines whether or not the random number value D8 for the number of times specified by the number information is acquired by the self-test processing unit 22.

  If acquisition of the random number D8 for the specified number of times has not been completed, the memory controller 11 repeatedly executes the processing after step SP75.

  On the other hand, when acquisition of the random number D8 for the designated number of times is completed, in step SP78, the memory controller 11 next performs self-test processing on all random numbers D8 stored in the memory array 13 from the memory array 13. Read to unit 22. Next, the memory controller 11 uses the self-test processing unit 22 to check whether or not each bit of the random value D8 is biased with “0” or “1”. For example, when the bit length of each random value D8 is 128 bits and the specified number of times is 64, the self-test processing unit 22 counts the number of “0” or “1” out of the total 128 × 64 bits. However, if it is within the allowable range of “50 × 64” or more and within “70 × 64”, it is determined that there is no bias, and if it is outside the allowable range, it is determined that there is bias.

  Next, in step SP79, the memory controller 11 inputs a test result indicating whether or not random number bias has occurred to the encryption / decryption processing unit 21 from the self-test processing unit 22 via the selector 25 as data D10. Next, the memory controller 11 encrypts the inspection result using the test mode encryption algorithm by the encryption / decryption processing unit 21, and transmits the result to the tester device 2. The tester device 2 decrypts the encrypted inspection result received from the semiconductor memory device 1 by using the test mode encryption algorithm, so that the reliability of the random number generator 12 (in this case, the bias of the random number is increased). Evaluate whether or not it has occurred.

  In the above description, the example in which the specified number of random values D8 are stored in the test data storage area R2 of the memory array 13 has been described, but the present invention is not limited to this example. By counting the number of bits of “0” or “1” with the random number value D8 stored in the internal register of the memory controller 11, and accumulating the count value each time a new random number value D8 is generated, the memory array The storage of the random value D8 in 13 may be omitted.

  The first to third examples relating to the reliability test of the random number generator 12 can be applied in any combination.

<Summary>
According to the semiconductor memory device (semiconductor device) 1 according to the present embodiment, the memory controller 11 receives only a memory test command from the tester device 2, so that only the memory array 13 of the memory array 13 and the random number generator 12 is received. A reliability test (memory test) is performed on the memory array 13 and a random number test command is received from the tester device 2, so that the reliability test is performed only on the random number generator 12 among the memory array 13 and the random number generator 12. (Random number test) is executed. In this way, the reliability test of the memory array 13 that does not depend on the random number value of the true random number and the reliability test of the random number generator 12 that depends on the random number value of the true random number are separated and executed. It is possible to simultaneously perform a reliability test on a plurality of semiconductor memory devices 1 using the tester device 2. As a result, the semiconductor memory device 1 on which the random number generator 12 for generating the true random number is mounted can also realize a simultaneous reliability test for a plurality of semiconductor memory devices 1, thereby improving the productivity of the shipping test. Is possible.

  Further, according to the semiconductor memory device 1 according to the present embodiment, when executing the reliability test of the memory array 13, the memory controller 11 replaces the genuine random number generated by the random number generator 12 with a predetermined fixed number. The random number value is input to the encryption / decryption processing unit 21, and the encryption / decryption processing unit 21 encrypts and transmits a signal (command and data) transmitted / received to / from the tester device 2 based on the fixed random number value. Decrypt. In this way, when a reliability test of the memory array 13 is executed by using a predetermined fixed random value instead of the true random number, the encryption / decryption processing unit 21 performs random number generation when executing the reliability test of the memory array 13. It does not depend on the true random number generated by the device 12. As a result, since a common expected value can be used by setting a common fixed random number value for a plurality of semiconductor memory devices 1, the reliability test of the memory array 13 for the plurality of semiconductor memory devices 1 is simultaneously performed. It becomes possible to do.

  Further, according to the semiconductor memory device 1 according to the present embodiment, the memory controller 11 extracts a fixed random value from the memory test command (first test command) received from the tester device 2, and registers the fixed random value in the register. 23. By using the fixed random number value stored in the register 23, the encryption / decryption processing unit 21 can execute encryption and decryption processing independent of the true random number generated by the random number generator 12. . In addition, by including a fixed random value in the memory test command, the tester device 2 can easily change the fixed random value.

  Further, according to the semiconductor memory device 1 according to the present embodiment, the fixed random number value is stored in the predetermined storage unit in the semiconductor memory device 1, and the memory controller 11 reads the fixed random number value read from the storage unit. Is stored in the register 23. By using the fixed random number value stored in the register 23, the encryption / decryption processing unit 21 can execute encryption and decryption processing independent of the true random number generated by the random number generator 12. .

  Further, according to the semiconductor memory device 1 according to the present embodiment, the self-test processing unit 22 causes the random number generator 12 to generate the random value D8 by inputting the predetermined control signal D7 to the random number generator 12, and The reproducibility of the random value D8 generated by the random number generator 12 is checked. By performing a self test by the self test processing unit 22, it is possible to easily and efficiently execute a reliability test of the random number generator 12.

  In a general random number test, it is necessary to check whether the generated random number satisfies both non-reproducibility and uniformity. Cost increases. In the semiconductor memory device 1 according to the present embodiment, the reliability test of the random number generator 12 is limited to the inspection of the reproducibility of the random number value, thereby facilitating the test and reducing the test cost. It becomes possible. On the other hand, since the uniformity test is not performed in the reliability test of the random number generator 12, the present invention is applied to an apparatus in which the uniformity of random numbers is ensured by a processing block different from the random number generator. It is particularly effective to do this. In the semiconductor memory device 1 according to the present embodiment, the uniformity of random numbers is ensured by the encryption algorithm in the encryption / decryption processing unit 21, so that the reliability test of the random number generator 12 can check the inability to reproduce random numbers. It can be limited to.

  Further, according to the semiconductor memory device 1 according to the present embodiment, the self-test processing unit 22 stores the random number value D8 generated by the random number generator 12 (memory array 13, internal register of the memory controller 11, or RAM). The random number value D8 generated by the random number generator 12 is inspected based on the random value D8 stored in the storage unit and read from the storage unit. By storing the random number value D8 generated in the past by the random number generator 12 in the storage unit, the self-test processing unit 22 is based on the random number value D8 read from the storage unit, sticking of random numbers, periodicity, or It becomes possible to inspect non-reproducibility such as bias.

  Further, according to the semiconductor memory device 1 according to the present embodiment, the self-test processing unit 22 extracts the number information from the random number test command (second test command), and sends it to the random number generator 12 based on the number information. A plurality of random values D8 are generated in order. As a result, a plurality of random number values D8 sequentially generated by the random number generator 12 can be stored in the storage unit, and the self-test processing unit 22 reads the plurality of random number values D8 from the storage unit, thereby reproducing the random number values. It becomes possible to check the impossibility. Also, by including the number information in the random number test command, the number information can be easily changed by the tester device 2.

  In addition, according to the semiconductor memory device 1 according to the present embodiment, the number-of-times information is stored in a predetermined storage unit (memory array 13, RAM, ROM, register, or the like) in the semiconductor memory device 1, and the self-test The processing unit 22 causes the random number generator 12 to generate a plurality of random number values D8 in order based on the number-of-times information read from the storage unit. As a result, a plurality of random number values D8 sequentially generated by the random number generator 12 can be stored in the storage unit, and the self-test processing unit 22 reads the plurality of random number values D8 from the storage unit, thereby reproducing the random number values. It becomes possible to check the impossibility.

  Further, according to the semiconductor memory device 1 according to the present embodiment, the self-test processing unit 22 starts the inspection of the random value D8 when the number-of-times information is input, and when the inspection is completed, the inspection result (data D10) ) To the tester device 2. Accordingly, with respect to the reliability test of the random number generator 12, test pattern creation processing by the tester device 2 and collation processing with an expected value are not required, so that the processing load on the tester device 2 can be reduced.

  Moreover, according to the semiconductor memory device 1 according to the present embodiment, the self-test processing unit 22 determines whether the same random number value is continuously generated by the random number generator 12 as an inspection of the reproducibility of the random number value. Check for no. As a result, it is possible to easily check whether the random number is stuck.

  Further, according to the semiconductor memory device 1 according to the present embodiment, the self-test processing unit 22 includes, among the plurality of random number values generated by the random number generator 12, as a test for the non-reproducibility of the random number value. Check whether the same random value is included. As a result, it is possible to easily check whether the random number has periodicity.

  Further, according to the semiconductor memory device 1 according to the present embodiment, the self-test processing unit 22 checks “0” or “0” in the random number value generated by the random number generator 12 as a check of the reproducibility of the random number value. It is checked whether the appearance ratio of “1” is within a predetermined allowable range. As a result, it is possible to easily check whether each bit of the random number is biased by “0” or “1”.

  Further, according to the semiconductor memory device 1 according to the present embodiment, the random number value D8 generated by the random number generator 12 is stored in the memory array 13. Therefore, since it is not necessary to prepare a large-capacity register or RAM for storing a plurality of random number values D8 generated by the random number generator 12 inside or outside the memory controller 11, the circuit scale can be reduced. Become.

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Tester device 11 Memory controller 12 Random number generator 13 Memory array 21 Encryption / decryption processing part 22 Self-test processing part 23 Register 24-26 Selector

Claims (10)

A random number generator for generating random numbers;
A memory controller connected to the random number generator;
With
The memory controller has a self-test processing unit that performs a reliability test of the random number generator,
The self-test processing unit
By inputting a predetermined control signal to the random number generator, the random number generator generates a random value,
A semiconductor device that inspects the reproducibility of a random number value generated by the random number generator. A storage unit;
The self-test processing unit
Storing the random value generated by the random number generator in the storage unit;
The semiconductor device according to claim 1, wherein non-reproducibility of the random number value generated by the random number generator is inspected based on the random value read from the storage unit. The number of times information specifying the number of times the random number generator generates a random number value is included in a test command received by the semiconductor device from an external device,
The semiconductor device according to claim 2, wherein the self-test processing unit extracts the number-of-times information from a test command, and causes the random number generator to sequentially generate a plurality of random number values based on the number-of-times information. Number-of-times information designating the number of times the random number generator generates a random number value is stored in a predetermined storage unit in the semiconductor device,
The semiconductor device according to claim 2, wherein the self-test processing unit reads the number-of-times information from the storage unit, and causes the random number generator to sequentially generate a plurality of random number values based on the number-of-times information.   5. The semiconductor device according to claim 3, wherein the self-test processing unit starts an inspection of a random value by inputting the number-of-times information, and transmits the inspection result to an external device when the inspection is completed.   The self-test processing unit inspects whether or not the same random number value is continuously generated by the random number generator as an inspection of the reproducibility of the random number value. A semiconductor device according to 1.   The self-test processing unit inspects whether or not the same random number value is included in a plurality of random number values generated by the random number generator, as a check of the reproducibility of the random number value. Item 7. The semiconductor device according to any one of Items 1 to 6.   The self-test processing unit checks whether or not the appearance ratio of “0” or “1” in the random number value generated by the random number generator is within a predetermined allowable range, as a check of the reproducibility of the random value. The semiconductor device according to claim 1, wherein the semiconductor device is inspected. A random number generator for generating random numbers;
A memory controller connected to the random number generator;
A storage unit;
With
The memory controller has a self-test processing unit that performs a reliability test of the random number generator,
The self-test processing unit
By inputting a predetermined control signal to the random number generator, the random number generator generates a random value,
Storing the random value generated by the random number generator in the storage unit;
A semiconductor memory device that inspects the reproducibility of a random number value generated by the random number generator based on a random number value read from the storage unit. A semiconductor device reliability test method comprising: a random number generator that generates a random number; and a self-test processing unit that executes a reliability test of the random number generator,
(A) causing the self-test processing unit to input a predetermined control signal to the random number generator to cause the random number generator to generate a random value;
(B) the self-test processing unit inspecting the non-reproducibility of the random number value generated by the random number generator;
A semiconductor device reliability test method comprising:

Images