JP2016032049A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2016032049A JP2016032049A JP2014154312A JP2014154312A JP2016032049A JP 2016032049 A JP2016032049 A JP 2016032049A JP 2014154312 A JP2014154312 A JP 2014154312A JP 2014154312 A JP2014154312 A JP 2014154312A JP 2016032049 A JP2016032049 A JP 2016032049A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 268
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000004806 packaging method and process Methods 0.000 claims abstract description 92
- 238000009423 ventilation Methods 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims description 76
- 238000012856 packing Methods 0.000 claims description 48
- 238000003825 pressing Methods 0.000 claims description 26
- XOFYZVNMUHMLCC-ZPOLXVRWSA-N prednisone Chemical compound O=C1C=C[C@]2(C)[C@H]3C(=O)C[C@](C)([C@@](CC4)(O)C(=O)CO)[C@@H]4[C@@H]3CCC2=C1 XOFYZVNMUHMLCC-ZPOLXVRWSA-N 0.000 claims description 23
- 239000000853 adhesive Substances 0.000 claims description 19
- 230000001070 adhesive effect Effects 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 13
- 230000001681 protective effect Effects 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 8
- 239000002390 adhesive tape Substances 0.000 claims description 7
- 239000013256 coordination polymer Substances 0.000 abstract description 101
- 238000009461 vacuum packaging Methods 0.000 abstract description 12
- 235000012431 wafers Nutrition 0.000 description 148
- 239000007789 gas Substances 0.000 description 43
- 239000000463 material Substances 0.000 description 32
- 102100035233 Furin Human genes 0.000 description 31
- 101001022148 Homo sapiens Furin Proteins 0.000 description 31
- 101000701936 Homo sapiens Signal peptidase complex subunit 1 Proteins 0.000 description 31
- 238000012986 modification Methods 0.000 description 21
- 230000004048 modification Effects 0.000 description 21
- 101000601394 Homo sapiens Neuroendocrine convertase 2 Proteins 0.000 description 18
- 102100037732 Neuroendocrine convertase 2 Human genes 0.000 description 18
- 101100311249 Schizosaccharomyces pombe (strain 972 / ATCC 24843) stg1 gene Proteins 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 11
- 101150002258 HDR1 gene Proteins 0.000 description 10
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 101001128694 Homo sapiens Neuroendocrine convertase 1 Proteins 0.000 description 8
- 101000828971 Homo sapiens Signal peptidase complex subunit 3 Proteins 0.000 description 8
- 101001046426 Homo sapiens cGMP-dependent protein kinase 1 Proteins 0.000 description 8
- 101000979222 Hydra vulgaris PC3-like endoprotease variant A Proteins 0.000 description 8
- 101000979221 Hydra vulgaris PC3-like endoprotease variant B Proteins 0.000 description 8
- 102100032132 Neuroendocrine convertase 1 Human genes 0.000 description 8
- 102100022422 cGMP-dependent protein kinase 1 Human genes 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000007689 inspection Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 101100070271 Oryza sativa subsp. japonica HDR3 gene Proteins 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/67346—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67356—Closed carriers specially adapted for containing chips, dies or ICs
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67376—Closed carriers characterised by sealing arrangements
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/6735—Closed carriers
- H01L21/67389—Closed carriers characterised by atmosphere control
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/4809—Loop shape
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract
Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
<半導体パッケージ>
まず、本実施の形態の半導体パッケージ(半導体装置)PKG1の概要構成について、図1および図2を用いて説明する。本実施の形態の半導体パッケージPKG1は、配線基板2、および配線基板2上に搭載された半導体チップ(半導体装置)CPを備えている。図1は本実施の形態の半導体パッケージ(半導体装置)の上面図である。また、図2は、図1のA−A線に沿った断面図である。なお、図1および図2では、半導体チップCPの主面CPt側に形成された複数のイメージセンサ素子(受光素子)の配置領域を見やすくするため、イメージセンサ素子の配置領域を二点鎖線で囲み、符号LSEを付して示している。
次に、図1および図2を用いて説明した半導体パッケージPKG1の製造工程について説明する。なお、本実施の形態では、図1に示す半導体チップCPを製造する工程(ウエハ工程)と、半導体パッケージを組み立てる工程(組立工程)と、を互いに異なる場所で行う実施態様について説明する。この場合、ウエハ工程を実施した後、完成した半導体チップを梱包し、搬送する必要がある。図3は、図1および図2を用いて説明した半導体パッケージの製造工程の概要を示す説明図である。
図3に示すウエハ工程では、ウエハ準備工程として、例えばシリコン(Si)などの半導体材料からなる基板である、半導体ウエハWH(図4参照)を準備する。図4は、図3に示すウエハ準備工程で準備する半導体ウエハの回路形成面側の平面図である。なお、ウエハ準備工程で準備する半導体ウエハWHは、複数のデバイス領域DVpを有するが、各デバイス領域DVpの境界に、目視可能な線が形成されていなくても良い。図4では、複数のデバイス領域DVpが存在することを明示的にしめすため、デバイス領域DVpの境界、すなわち、ダイシングラインDCpに二点鎖線を付している。
次に、図3に示す組立工程について説明する。図15は、図3に示す包装開封工程で、梱包袋の密封状態を開封する様子を模式的に示す説明図である。また、図16は、図10に示す梱包ケースが有する通気経路を模式的に示す平面図である。また、図17は、図11に示す梱包ケースが有する通気経路を模式的に示す平面図である。
例えば、上記実施の形態では、半導体チップの例として、平面視において、主面CPt側にイメージセンサ素子LSEが形成された半導体チップCPを例示的に取り上げた。イメージセンサ素子LSEが形成されている場合、イメージセンサ素子LSEが損傷すると、半導体チップCPの特性低下の原因になるので、特に上記実施の形態で説明した方法が有効である。しかし、主面CPt側にイメージセンサ素子LSEなどが形成されていない半導体チップに適用しても良い。例えば、半導体チップの主面CPtが保護膜に覆われている場合でも、図1に示す複数のパッドPDは保護膜から露出させる必要がある。この場合、パッドPDが損傷すると、半導体チップの電気的特性が低下する原因になる。
また、上記実施の形態では、図12に示すようにリング押さえ部HDR1のリングRGと接触する面、すなわち、リング押さえ面HDR1bが平坦な面となっている実施態様について説明した。しかし、変形例として、図18に示すリング押さえ部HDR3のリング押さえ面HDR3bのように複数の突起部BPを有する凹凸面であっても良い。リング押さえ部HDR3のように複数の突起部BPをリングRGの上面RGtと接触させてリングRGを押さえる構造の場合、隣り合う突起部BPの間の隙間が、凹部DM1に連通する通気経路として機能する。この場合、図10に示すような通気経路VTR1を設けられていない場合でも、包装開封工程において、空間SPC1内に気体GS2を流入させることができる。
また、上記実施の形態では、複数の半導体チップCPの主面CPtが露出した状態でソーンウエハSWを梱包ケースSP内に収容する実施態様について説明した。しかし、図19に示す変形例のように、複数の半導体チップCPの主面CPtを覆う保護テープMTをソーンウエハSWの上面SWt側に貼り付けても良い。この場合、複数の半導体チップCPの主面CPtが保護テープMTにより覆われるので、さらに損傷し難くなる。
また、上記実施の形態では、半導体パッケージの例として、半導体チップCPを基材である配線基板2上に搭載した半導体パッケージを例示的に取り上げて説明した。しかし、半導体パッケージの構造には種々の変形例がある。例えば、基材としてチップ搭載部の隣に、複数のリードが形成されたリードフレームを用いた半導体パッケージであっても良い。
また、上記実施の形態で説明した技術思想の要旨を逸脱しない範囲内において、変形例同士を組み合わせて適用することができる。
2b 下面(第2面、実装面)
2BF 端子(ボンディングリード、ボンディングフィンガ、半導体チップ接続用端子)
2LD ランド(端子、実装端子)
2s 側面
2t 上面(第1面、チップ搭載面)
2W 配線
ADf 粘着面(接着面、上面)
BP 突起部(凹凸部)
BW ワイヤ(導電性部材)
CFt 回路形成面
CG カバー部材
CP 半導体チップ(半導体装置)
CPb 主面(裏面、下面)
CPs 側面
CPt 主面(表面、上面)
CR クリーンルーム
DB ブレード(ダイシングブレード)
DCp ダイシングライン(スクライブ領域)
DM1 凹部(第1凹部)
DM2 凹部(第2凹部)
DM3 凹部(第3凹部)
DT ダイシングテープ(粘着シート、粘着テープ)
DTb 下面
DVp デバイス領域
GS1、GS2 気体
HDR1、HDR3、HDRh リング押さえ部
HDR1b、HDR3b リング押さえ面
HS シール装置
LSE 複数のイメージセンサ素子(受光素子)
MT 保護テープ
PD パッド(ボンディングパッド、チップ電極)
PKG1 半導体パッケージ(半導体装置)
RG リング
RGb 下面
RGt 上面
SB 半田ボール(半田材、外部端子、電極、外部電極)
SBG 梱包袋
SP、SPh1 梱包ケース
SP1 蓋部(第1ケース部)
SP2 本体部(第2ケース部)
SPC1、SPC2、SPC3 空間
STG1、STG2 支持部
SW ソーンウエハ(半導体装置)
SWb 下面
SWpkg 包装体(半導体装置)
SWt 上面
VC 真空チャンバ
VP 真空ポンプ
VTR1 通気経路(第1通気経路)
VTR2 通気経路(第2通気経路)
WH 半導体ウエハ
Claims (11)
- (a)第1主面と、前記第1主面と反対側の面である第2主面を有する基板を準備し、前記基板の前記第1主面上に複数の半導体素子を形成することにより半導体ウエハを形成する工程と、
(b)粘着テープが貼り付けられた環状のリングを準備する工程と、
(c)前記半導体ウエハの前記第2主面と前記リングの環内に位置する前記粘着テープの粘着面とが対向するように、前記粘着テープ上に前記半導体ウエハを貼り付ける工程と、
(d)前記半導体ウエハを切断することにより、複数の半導体チップに分割し、前記複数の半導体チップが前記粘着テープに貼り付いた状態で前記リングに保持される、ソーンウエハを作成する工程と、
(e)前記(d)工程の後、前記ソーンウエハの前記複数の半導体チップが貼り付けられた第1面を覆う第1ケース部と、前記ソーンウエハの前記第1面の反対側の第2面を覆う第2ケース部と、を有する梱包ケース内に前記ソーンウエハを収納して前記リングを固定する工程と、
(f)前記(e)工程の後、梱包袋内に前記梱包ケースを収納する工程と、
(g)前記(f)工程の後、前記梱包袋内の気体を吸気することにより、前記梱包ケース内を減圧する工程と、を有し、
前記第1ケース部は、前記(e)工程で、前記複数の半導体チップを覆う第1凹部、および上記第1凹部に連通し、前記梱包ケースの外部空間に接続される第1通気経路を有し、
前記第2ケース部は、前記(e)工程で、前記ソーンウエハの前記第2面を覆う第2凹部を有し、
前記(g)工程では、前記第1通気経路を介して、前記梱包ケース内の気体を排出する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1ケース部は、前記第1凹部の外側において、前記ソーンウエハの前記リングの前記第1面を押圧して前記リングを固定するリング押さえ部を有し、
平面視において、前記第1通気経路は、前記リングの内側の空間と前記リングの外側の空間とを連通する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1ケース部は、前記第1凹部の周囲を囲むように設けられ、前記ソーンウエハの前記リングの前記第1面を押圧して前記リングを固定するリング押さえ部を有し、
平面視において、前記第1通気経路は、前記リング押さえ部の一部を貫通するように、前記第1凹部内の空間と前記リング押さえ部の外側の空間とを連通する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第2ケース部は、前記第2凹部に連通し、前記梱包ケースの外部空間に接続される第2通気経路を有し、
前記(g)工程では、前記第2通気経路を介して、前記第2凹部内の気体を排出する、半導体装置の製造方法。 - 請求項4に記載の半導体装置の製造方法において、
前記第1通気経路および前記第2通気経路は、互いに接続される、半導体装置の製造方法。 - 請求項4に記載の半導体装置の製造方法において、
前記第2通気経路は、前記ソーンウエハの前記リングの外縁部と前記第2凹部の壁面との間に生じる隙間を含む、半導体装置の製造方法。 - 請求項4に記載の半導体装置の製造方法において、
前記(e)工程において、前記第1凹部と前記ソーンウエハの前記第1面により形成される第1空間の容積は、前記(e)工程において、前記第2凹部と前記ソーンウエハの前記第2面により形成される前記第2凹部の容積よりも大きい、半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記複数の半導体チップのそれぞれは、前記第1主面側に形成されたイメージセンサ素子を有する、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記(d)工程の後、前記(e)工程の前に、前記複数の半導体チップを覆うように保護テープを前記ソーンウエハ上に貼り付ける工程を有する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
(h)前記(g)工程の後、前記梱包袋を開封することにより、前記梱包ケース内の圧力を上昇させる工程と、
(i)前記(h)工程の後、前記ソーンウエハを前記梱包ケースから取り出す工程と、をさらに有する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記梱包ケースの外部空間と前記第1凹部内の第1空間とを接続する前記第1通気経路中には、前記第1通気経路の断面積が局所的に大きくなる空間が設けられる、半導体装置の製造方法。
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Also Published As
Publication number | Publication date |
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US9837466B2 (en) | 2017-12-05 |
US20160204010A1 (en) | 2016-07-14 |
US20160035787A1 (en) | 2016-02-04 |
CN105321879B (zh) | 2020-11-13 |
US9324763B2 (en) | 2016-04-26 |
TW201618220A (zh) | 2016-05-16 |
KR20160014536A (ko) | 2016-02-11 |
JP6310803B2 (ja) | 2018-04-11 |
CN105321879A (zh) | 2016-02-10 |
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