JP2016029864A - Transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a transmission circuit used in a communication system using magnetic coupling to communicate at a higher data rate than the self-resonant frequency of an inductor using only one inductor.SOLUTION: A transmission circuit according to the present invention is a transmission circuit for transmitting data to an insulated other semiconductor chip by driving an inductor. The transmission circuit includes a driving circuit that receives transmission data with a higher data rate than the self-resonant frequency of the inductor and outputs a transmission signal to drive the inductor at the data rate of the transmission data.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a transmission circuit, and more particularly to a transmission circuit that transmits a signal via a transformer.

  In recent years, communication means using magnetic coupling by a transformer has been frequently used as one of close proximity communications. However, in the communication means using magnetic coupling, the transformer is constituted by coils, and each coil is constituted by an inductor. Then, distortion occurs in the pulse waveform used for transmission / reception due to the self-resonance of the inductor. Therefore, in the communication means using magnetic coupling, the pulse transmission interval (referred to as data rate) is limited to about 1/3 times the self-resonant frequency of the inductor.

  However, there is a demand for improvement in communication speed even in close proximity communication. Therefore, non-patent documents 1 to 5 disclose techniques for increasing the communication speed in a communication system using magnetic coupling. In Non-Patent Document 1, a plurality of transformers are provided to parallelize transmission / reception signals, thereby improving the communication speed.

N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, “A 1 Tb / s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link ”, IEEE Journal of Solid-State Circuits, vol. 42, 2007, pp. 111-122. N. Miura, D. Mizoguchi, M. Inoue, T. Sakurai, and T. Kuroda, “A 195-Gb / s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package ”, IEEE Journal of Solid-State Circuits, vol. 41, 2006, p. 23. N. Miura, D. Mizoguchi, T. Sakurai, and T. Kuroda, “Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect”, IEEE Journal of Solid-State Circuits, vol. 40, 2005, p. 829. S. Kawai, H. Ishikuro, and T. Kuroda, “A 2.5 Gb / s / ch 4PAM inductive-coupling transceiver for non-contact memory card”, 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010, pp. 264-265. N. Miura, Y. kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, and T. Kuroda, “A hign-speed inductive-coupling link with burst transmission”, IEEE Journal of Solid-State Circuits, vol. 44 , no. 3, pp. 947-955, 2009.

  However, the transformer has a large circuit area or mounting area. For this reason, when Non-Patent Documents 1 to 5 are used, a plurality of transformers must be provided, which hinders downsizing of the device or reduction in cost.

  One aspect of a transmission circuit according to the present invention is a transmission circuit that transmits data by driving an inductor to generate electromagnetic induction, and receives transmission data having a data rate higher than a self-resonance frequency of the inductor. And a drive circuit for outputting a transmission signal for driving the inductor at a data rate of the transmission data.

  One aspect of a receiving circuit according to the present invention is a receiving circuit that receives a transmission signal generated by electromagnetic induction of an inductor, and determines a logical level of transmission data from the reception signal at a data rate higher than a self-resonance frequency of the inductor. And a discrimination circuit for outputting the received data.

  One aspect of a communication system according to the present invention includes a transmission path including a first inductor and a second inductor that are electromagnetically coupled, and a drive circuit that drives the first inductor based on input transmission data. A discriminating circuit for generating received data based on a received signal input via the second inductor, wherein the driving circuit and the discriminating circuit are self-resonant frequencies of the first and second inductors. The transmission data is transmitted at a higher data rate.

  In the transmission circuit, the reception circuit, and the communication system having these according to the present invention, signals are transmitted and received at a data rate higher than the self-transmission frequency of the inductor. Thereby, in the transmission circuit, the reception circuit, and the communication system having these according to the present invention, it is possible to improve the communication speed of communication processing performed through one transformer.

  According to the transmission circuit, the reception circuit, and the communication system having these according to the present invention, it is possible to realize proximity communication with a high data rate with a small circuit area or mounting area.

1 is a block diagram of a communication system according to the present invention. It is the schematic of the inductor formed on a chip | tip in the communication system of FIG. FIG. 3 is a diagram illustrating an example of a waveform of a transmission signal of the transmission circuit according to the first exemplary embodiment. It is a graph of the frequency characteristic of the transmission circuit concerning a comparative example. 3 is a graph of frequency characteristics of the transmission circuit according to the first exemplary embodiment; 1 is a block diagram of a drive circuit according to a first exemplary embodiment; FIG. 3 is a conceptual diagram illustrating a processing principle of a transmission signal correction unit according to the first exemplary embodiment. 1 is a block diagram of a drive circuit according to a first exemplary embodiment; 1 is a block diagram of a data delay circuit according to a first exemplary embodiment; 1 is a block diagram of a multiplexer according to a first exemplary embodiment. FIG. 3 is a block diagram of a transmission signal output circuit according to the first exemplary embodiment; It is a figure which shows the waveform of the transmission signal when not performing a correction process, and a received signal. It is a figure which shows the waveform of the transmission signal at the time of performing the correction process by FIR type | mold equalization process, and a received signal. It is a figure which shows the eye pattern of the received signal when not performing a correction process. It is a figure which shows the eye pattern of the received signal at the time of performing the correction process by FIR type | mold equalization process. FIG. 6 is a block diagram of a drive circuit according to a second exemplary embodiment. FIG. 6 is a diagram for explaining a precoder according to a second embodiment; FIG. 4 is a block diagram of a drive circuit according to a third exemplary embodiment. 10 is a graph showing transition of mean square error in correction coefficient adjustment processing in the drive circuit according to the third exemplary embodiment; 12 is a graph showing a transition of correction coefficients in a correction coefficient adjustment process in the drive circuit according to the third embodiment. FIG. 6 is a block diagram of a drive circuit according to a fourth exemplary embodiment. FIG. 10 is a block diagram of a determination circuit according to a fifth embodiment; FIG. 10 is a conceptual diagram of a processing principle of a reception signal correction unit according to a fifth embodiment; FIG. 10 is a block diagram of a discrimination circuit according to a sixth embodiment. It is a conceptual diagram of the processing principle of the received signal correction | amendment part concerning Embodiment 6. FIG. 10 is a waveform diagram showing waveform correction processing in decision feedback equalization processing according to the sixth exemplary embodiment; It is a figure which shows the eye pattern of the received signal when not performing a correction process. It is a figure which shows the eye pattern of the received signal at the time of performing the correction process by the decision feedback type | mold equalization process. FIG. 10 is a block diagram of a discrimination circuit according to a seventh embodiment. FIG. 10 is a block diagram of a communication system according to an eighth embodiment. FIG. 9 is an equivalent circuit diagram of an inductor according to an eighth embodiment. It is a block diagram which shows the example of mounting of the transmission circuit concerning other embodiment, and a receiving circuit. It is a block diagram which shows the example of mounting of the transmission circuit concerning other embodiment, and a receiving circuit.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. First, a communication system according to the present invention will be described. FIG. 1 is a block diagram of a communication system according to the present invention. As shown in FIG. 1, the communication system according to the present invention includes a transformer, a transmission circuit, and a reception circuit. Further, FIG. 1 shows a processing circuit A that provides transmission data to the transmission circuit and a processing circuit B that receives reception data output from the reception circuit and performs predetermined processing. The communication system according to the present invention performs communication between a transmission circuit and a reception circuit formed on an electrically insulated semiconductor substrate by a transformer using a coil constituted by inductors L1 and L2. . That is, this transformer constitutes a transmission path from the transmission circuit to the reception circuit.

  The transmission circuit has a drive circuit DRV. Then, the drive circuit DRV drives the inductor to cause electromagnetic induction in the inductor. The drive circuit DRV receives transmission data having a data rate higher than the self-resonance frequency of the inductor, and outputs a transmission signal that drives the inductor L1 at the data rate of the transmission data. Further, the processing circuit A outputs transmission data to the drive circuit DRV at a data rate higher than the resonance frequency of the inductor L1.

  The reception circuit has a determination circuit DET. Then, the determination circuit DET determines the logical level of the transmission data from the reception signal at a data rate higher than the self-resonance frequency of the inductor, and outputs the reception data. Then, the processing circuit B performs a predetermined process based on the reception data output from the determination circuit DET.

  In the example shown in FIG. 1, the transmission circuit and the reception circuit are formed on separate semiconductor substrates. Moreover, a transformer is comprised by the inductors L1 and L2. In the example shown in FIG. 1, the inductor L1 is formed on the same semiconductor substrate as the drive circuit DRV, and the inductor L2 is formed on the same substrate as the determination circuit DET. A schematic diagram of the configuration of the inductor formed on the semiconductor substrate in this way is shown in FIG. As shown in FIG. 2, the inductor formed on the semiconductor substrate is formed by polygonal wiring, and is connected to the power supply terminal VDD in the vicinity of the midpoint thereof. Further, terminals EM1 and EM2 to which the drive circuit DRV or the determination circuit DET is connected are formed at both ends of the wiring constituting the inductor. In the following description, an example in which an inductor is operated by a differential signal will be described. However, the present invention can also be applied to a case where the inductor is driven by a single end signal.

  In a conventional communication system using magnetic coupling, the data rate of transmission data is limited by the self-resonant frequency of the inductor constituting the transformer. However, the communication system according to the present invention is characterized in that communication is performed at a data rate higher than the self-resonance frequency of the inductor while using magnetic coupling for signal transmission.

  Therefore, the transmission circuit of the communication system according to the present invention receives transmission data having a data rate higher than the self-resonance frequency of the inductor, and outputs a transmission signal that drives the inductor at the data rate of the transmission data. The receiving circuit determines the logical level of the transmission data from the reception signal at a data rate higher than the self-resonance frequency of the inductor, and outputs the reception data.

  Next, the relationship between the data rate Rb of transmission data in the communication system using magnetic coupling and the reception signals generated at both ends of the inductor L2 on the reception side due to the transmission data will be described. FIG. 3 shows a waveform diagram of transmission data and a reception signal corresponding to the transmission data in a communication system using magnetic coupling. As shown in FIG. 3, in the communication system, value 1 or value 0 is handled as one data symbol. The data symbol transmission interval is the data rate Rb. In FIG. 3, the transmission interval of data symbols is the data rate Rb, and the waveform of the transmission signal has a larger negative amplitude for transmission data with a value of 1, and a positive side for transmission data with a value of 0. The amplitude of becomes larger. The received signal has an amplitude corresponding to the front edge of the transmission data, but it takes a predetermined time until the amplitude converges. This predetermined time is determined by the resonance frequency of the inductors L1 and L2.

  In the conventional communication system, the data rate Rb is limited to 1/3 or less of the resonance frequency of the inductors L1 and L2 in order to prevent interference between data symbols due to distortion of the received signal waveform caused by self-resonance of the inductors L1 and L2. There was a need to do. Here, a graph showing the relationship between the data rate Rb and the resonant frequencies of the inductors L1 and L2 in the conventional communication system is shown in FIG. As shown in FIG. 4, in the conventional communication system, it was necessary to set the data rate Rb to 1/3 or less of the resonance frequency of the inductors L1 and L2 in order to prevent interference between data symbols.

  On the other hand, FIG. 5 shows a graph showing the relationship between the data rate Rb and the resonant frequencies of the inductors L1 and L2 in the communication system according to the present invention. As shown in FIG. 5, in the communication system according to the present invention, the data rate Rb is set higher than the resonance frequency of the inductors L1 and L2.

  In the communication system according to the present invention, a transmission signal is output to a single transformer at a data rate higher than the resonance frequency of the inductors L1 and L2. High-speed communication can be performed without being limited by the resonance frequency.

  It is also possible to increase the communication speed by increasing the self-resonance frequency by reducing the diameter of the inductor constituting the transformer. However, in this case, there is a problem that the communication distance is shortened. However, in the communication system according to the present invention, the communication speed can be improved without being limited by the self-resonant frequency of the inductor even if the diameter of the inductor is set sufficiently large to ensure the communication distance. In other words, by using the communication system according to the present invention, it is possible to reduce the number of inductors while forming inductors with an inductor diameter that secures a sufficient communication distance, so high-speed communication with a small circuit area or mounting area. Can be realized.

  In the communication system according to the present invention, since signals are transmitted and received at a data rate higher than the self-resonant frequency of the inductor, there is a risk of interference between data symbols. Therefore, in the communication system according to the present invention, interference between data symbols is prevented by performing correction processing on a signal used for transmission / reception in at least one of the transmission circuit and the reception circuit. In the communication system according to the present invention, the correction process may be performed by either the transmission circuit or the reception circuit. In the first embodiment, the case where the correction process is performed on the transmission side will be described.

  First, in the first embodiment, a case where correction processing is performed by the drive circuit DRV provided on the transmission circuit side will be described. FIG. 6 is a block diagram of the drive circuit DRV1 according to the first embodiment. As shown in FIG. 6, the drive circuit DRV1 includes a transmission signal correction unit 1 and a drive unit 2.

  The transmission signal correction unit 1 receives the transmission data DIN, corrects the waveform distortion caused by the self-resonance of the inductors L1 and L2 with respect to the transmission data DIN, and outputs the corrected transmission data to the driving unit 2. Output to. The transmission signal correction unit 1 performs the correction process at a speed corresponding to the data rate of the transmission data DIN. The correction process performed in the transmission signal correction unit 1 corrects the transmission data DIN to be transmitted using n pieces of transmission data DIN transmitted n (n is an integer) cycles before the transmission data DIN to be transmitted. Done in More specifically, the transmission signal correction unit 1 includes an equalization coefficient holding circuit 11 and an FIR type filter circuit. In the FIR type filter circuit, correction processing (for example, equalization processing is performed by the function of the FIR type filter, and therefore, in the following description, the FIR type filter circuit is referred to as FIR type equalize circuit 12. The equalization coefficient holding circuit 11 is The equalizer coefficient used in the FIR type equalizer circuit 12 is held in the first embodiment, and the equalizer coefficient is set in advance in the first embodiment.

  The drive unit 2 drives the inductor L1 based on the transmission data MT corrected by the transmission signal correction unit 1. In the first embodiment, the driving unit 2 drives the inductor L1 with a differential signal.

  Subsequently, the equalization process performed in the transmission signal correction unit 1 will be specifically described. FIG. 7 shows the principle of the equalization process performed by the transmission signal correction unit 1. In FIG. 7, a specific circuit is shown for each process necessary for the equalization process in order to explain the operation principle of the equalization process. As shown in FIG. 7, equalization processing performed by the transmission signal correction unit 1 according to the first embodiment can be realized by delay circuits 311 to 31n, multipliers 320 to 32n, and an adder 33.

  Delay circuits 311 to 31n are cascade-connected. Then, the delay circuits 311 to 31n delay the transmission data DIN by a time corresponding to the period of the data rate. Then, the delay circuits 311 to 31n transmit the delayed transmission data DIN to the delay circuit at the next stage. Multiplier 320 multiplies input transmission data DIN and equalization coefficient C0, and outputs a multiplication result. The multipliers 321 to 32n multiply the transmission data DIN output from the delay circuits 311 to 31n and the equalization coefficients C1 to Cn, respectively, and output the multiplication results. The adder 33 adds the multiplication results output from the multipliers 320 to 32n, and generates corrected transmission data MT.

  That is, in the equalization process, the transmission data DIN is delayed and the transmission data DIN for n cycles is parallelized. Then, equalization coefficients C0 to Cn are multiplied according to the transmission order of the parallel transmission data DIN. Then, n transmission data DIN obtained by multiplying equalization coefficients C0 to Cn are added to obtain corrected transmission data MT.

  The drive circuit DRV1 according to the first embodiment receives the transmission data DIN as a digital signal and drives the inductor L1 with a current. Therefore, the drive circuit DRV1 needs to output a current corresponding to a value given by a digital signal. Therefore, in the drive circuit DRV1, the equalization processing function and the drive function of the inductor L1 are realized by a circuit in which the transmission signal correction unit 1 and the drive unit 2 are mixed. FIG. 8 shows a block diagram of the drive circuit DRV1 according to the first embodiment.

  As shown in FIG. 8, the drive circuit DRV1 includes a data delay circuit 40, multiplexers 411 to 415, and transmission signal output circuits 421 to 425. The drive circuit DRV1 shown in FIG. 8 is an example having four stages of delay circuits shown in FIG. In the first embodiment, it is assumed that transmission data obtained by parallelizing transmission data to be serially transmitted with a bit width of 4 bits is input to the data delay circuit 40. The data delay circuit 40 receives the clock signal CLKa and generates delay data DLY1 to DLY5 obtained by delaying the transmission data DIN at the timing of the clock signal CLKa. The clock signal CLKa has a frequency that is ¼ of the data rate of the transmission data DIN. The delay data DLY1 to DLY5 are 4-bit signals. The data delay circuit 40 realizes a function corresponding to the delay circuits 311 to 31n in FIG.

  The multiplexer 411 to 415 receives one corresponding signal among the delay data DLY1 to DLY5. The multiplexers 411 to 415 receive the clock signal CLKa and the clock signal CLKb. The clock signal CLKb has a frequency that is ½ of the data rate of the transmission data DIN. The multiplexers 411 to 415 take in the delay data DLY1 to DLY5 with the clock signal CLKa, and output the data constituting the delay data bit by bit according to the clock signal CLKb. Note that the multiplexers 411 to 415 output 1-bit data as differential signals.

  The transmission signal output circuits 421 to 425 drive the inductor L1 according to the data output from the multiplexers 411 to 415. The current control signals W1 to W5 are input to the transmission signal output circuits 421 to 425. Each of the current control signals W1 to W5 is a 5-bit signal and adjusts the driving capability of the transmission signal output circuits 421 to 425. The current control signals W1 to W5 are signals having values corresponding to the equalization coefficients C0 to C4. The outputs of the transmission signal output circuits 421 to 425 output differential signals. Further, the output terminals of the transmission signal output circuits 421 to 425 are connected to output terminals having the same polarity at different nodes. In the transmission signal output circuits 421 to 425, the inductor L1 is connected between the positive output terminal and the negative output terminal.

  That is, the transmission signal output circuits 421 to 425 realize the function of the multiplier shown in FIG. Further, the function of the adder of FIG. 7 is realized by connecting the output nodes of the transmission signal output circuits 421 to 425 to each other.

  Next, a specific circuit of the data delay circuit 40 will be described. A block diagram of the data delay circuit 40 is shown in FIG. As shown in FIG. 9, the data delay circuit 40 includes flip-flops 51 to 58. The flip-flops 51 to 58 update the value input to the input terminal D in synchronization with the clock signal CLKa and output it from the output terminal Q. In the example shown in FIG. 9, the symbols Q1 to Q8 are attached to the signals output from the flip-flops 51 to 58. As shown in FIG. 9, the flip-flops 55 to 58 hold the values of the transmission data DIN [1] to DIN [4]. The flip-flops 51 to 54 hold the values of the signals Q5 to Q8 output from the flip-flops 55 to 58. That is, the signal Q1 is transmission data transmitted first in time. The signals Q2 to Q8 are data transmitted following the signal Q1. With this configuration, when the signal Q5 is transmission data to be transmitted, the transmission data of the signals Q1 to Q4 is used for correction. When the signal Q6 is transmission data to be transmitted, the transmission data of the signals Q2 to Q5 is used for correction. When the signal Q7 is transmission data to be transmitted, the transmission data of the signals Q3 to Q6 is used for correction. When the signal Q8 is transmission data to be transmitted, the transmission data of the signals Q4 to Q7 is used for correction.

  Subsequently, specific circuits of the multiplexers 411 to 415 will be described. Since the multiplexers 411 to 415 have the same configuration, the multiplexer 411 will be described here. A block diagram of the multiplexer 411 is shown in FIG. As illustrated in FIG. 10, the multiplexer 411 includes flip-flops 60 to 62, 64 to 66 and 68 to 70, selectors 63, 67 and 71, and an inverter 72. Then, transmission data Q5 to Q8 are given to the multiplexer 411 as the delay data DLY1.

  The flip-flop 60 updates the value held by the value given as the transmission data Q5 based on the clock signal CLKa. The flip-flop 61 updates the value held with the value given as the transmission data Q6 based on the clock signal CLKa. The flip-flop 62 updates the value held by the value of the transmission data Q6 held by the flip-flop 61 based on the falling edge of the clock signal CLKa. The selector 63 outputs one of the value held in the flip-flop 60 and the value held in the flip-flop 62 in accordance with the logic level of the clock signal CLKa. That is, the selector 63 sequentially outputs the transmission data Q5 and Q6 according to the logic level of the clock signal CLKa.

  The flip-flop 64 updates the value held by the value given as the transmission data Q7 based on the clock signal CLKa. The flip-flop 65 updates the value held by the value given as the transmission data Q8 based on the clock signal CLKa. The flip-flop 66 updates the value held by the value of the transmission data Q8 held by the flip-flop 65 based on the falling edge of the clock signal CLKa. The selector 67 outputs either one of the value held in the flip-flop 64 and the value held in the flip-flop 66 according to the logic level of the clock signal CLKa. That is, the selector 67 sequentially outputs the transmission data Q7 and Q8 according to the logic level of the clock signal CLKa.

  The flip-flop 68 updates the values held in order with the values of the transmission data Q5 and Q6 output from the selector 63 based on the clock signal CLKb. The flip-flop 69 updates the values held in order with the values of the transmission data Q7 and Q8 output from the selector 67 based on the clock signal CLKb. The flip-flop 70 updates the values held in order with the values of the transmission data Q7 and Q8 held by the flip-flop 69 based on the falling edge of the clock signal CLKb. The selector 71 outputs either the value held in the flip-flop 68 or the value held in the flip-flop 71 according to the logic level of the clock signal CLKb. That is, the selector 71 sequentially outputs transmission data Q5 to Q8 at the data rate of the transmission data DIN.

  The inverter 72 outputs an inverted signal of transmission data output from the selector 71. Data output from the selector 71 is applied to the normal input terminal of the transmission signal output circuit 421 as the drive signal I +. The data output from the inverter 72 is given to the inverting input terminal of the transmission signal output circuit 421 as the drive signal I−.

  Subsequently, specific circuits of the transmission signal output circuits 421 to 425 will be described. Since the transmission signal output circuits 421 to 425 have the same configuration, only the transmission signal output circuit 421 will be described here. A circuit diagram of the transmission signal output circuit 421 is shown in FIG. As illustrated in FIG. 11, the transmission signal output circuit 421 includes a differential amplification unit 80 and a variable current source 81.

  The differential amplifier 80 has a differential pair composed of transistors MN1 and MN2. The gate of the transistor MN1 is an inverting input terminal of the transmission signal output circuit 421, and receives the drive signal I−. The drain of the transistor MN1 is connected to the normal output terminal OUT +. The gate of the transistor MN2 is a normal input terminal of the transmission signal output circuit 421, and the drive signal I + is input thereto. The drain of the transistor MN2 is connected to the inverting output terminal OUT−. The sources of the transistors MN1 and MN2 are connected in common, and an operating current is supplied from a variable current source.

  The variable current source 81 outputs an operating current that is a fifth power of 2 from 1 to 31 times according to the value of the current control signal W1. This operating current is output as a drive current via the differential amplifier 80. The variable current source 81 includes transistors MN3 to MN12. The transistors MN8 to MN12 have the reference voltage Vref1 input to their gates. The transistors MN8 to MN12 have the same gate length but a gate width that is an integral multiple. For example, the transistor MN8 has a gate width of 1 (reference gate width) and outputs a current (reference current) of 1 time. The transistor MN9 has a gate width twice that of the transistor MN8 and outputs a current that is twice the reference current. The transistor MN10 has a gate width four times that of the transistor MN8 and outputs a current that is four times the reference current. The transistor MN11 has a gate width that is eight times that of the transistor MN8 and outputs a current that is eight times the reference current. The transistor MN12 has a gate width that is 16 times that of the transistor MN8 and outputs a current that is 16 times the reference current. The sources of the transistors MN8 to MN12 are each connected to the ground terminal.

  The transistors MN3 to MN7 function as switches that switch which of the transistors MN8 to MN12 is enabled. The transistor MN3 is provided corresponding to the transistor MN8, and is switched on and off according to the current control signal W1 [0]. The transistor MN4 is provided corresponding to the transistor MN9, and is switched on and off according to the current control signal W1 [1]. The transistor MN5 is provided corresponding to the transistor MN10 and is switched on and off according to the current control signal W1 [2]. The transistor MN6 is provided corresponding to the transistor MN11, and is switched on and off according to the current control signal W1 [3]. The transistor MN7 is provided corresponding to the transistor MN12, and is switched on and off according to the current control signal W1 [4]. The drains of the transistors MN <b> 3 to MN <b> 7 are connected in common and supply an operating current to the differential amplifier 80.

  In other words, the transmission signal output circuits 421 to 425 adjust the operating current applied to the differential amplifier 80 according to the values of the current control signals W1 [0] to W1 [4], so that the equalization coefficient and the transmission data DIN Multiply The transmission signal output circuits 421 to 425 each output a drive current, and add the multiplication values by adding the drive currents at the output node.

  Next, the drive current output from the drive circuit DRV1 and the reception signal generated in the inductor L2 provided on the reception side will be described. Hereinafter, a case where the value of the drive current and the reception signal changes to 010 as the transmission data DIN will be described as an example.

  First, FIG. 12 shows the relationship between the drive current and the received signal when the correction process is not performed in the drive circuit DRV1 according to the first embodiment. As shown in FIG. 12, when correction is not performed, time TM1 is required until the amplitude of the received signal generated according to the drive current pulse generated corresponding to the transmission data of value 1 converges. In FIG. 12, the current pulse width corresponds to the time required for 1-bit transmission data. In the example shown in FIG. 12, the time TM1 is longer than the 1-bit width. Furthermore, in the example shown in FIG. 12, it can be seen that the maximum amplitude Vp on the positive side of the received signal is smaller than the maximum amplitude Vn on the negative side.

  On the other hand, FIG. 13 shows the relationship between the drive current and the received signal when the correction process is performed in the drive circuit DRV1 according to the first embodiment. As shown in FIG. 13, when correction is performed, time TM2 is required until the amplitude of the received signal generated in response to the drive current pulse generated corresponding to the transmission data of value 1 converges. In FIG. 13, the correction process makes the width of the current pulse corresponding to the transmission data of value 1 larger than the time required for 1-bit transmission data. On the other hand, in the example shown in FIG. 13, the relationship between the 1-bit width and the time TM2 is approximately three times the 1-bit width. Furthermore, in the example shown in FIG. 13, it can be seen that the maximum amplitude Vp on the positive side of the received signal is substantially the same as the maximum amplitude Vn on the negative side. That is, by performing the correction process, the received signal waveform generated according to the transmission data of value 1 converges in a shorter time and becomes a received signal of 0, 1, -1, 0. A signal such as this received signal is called a dicode signal.

  Next, the effect of the correction process will be described using the eye pattern of the received signal. FIG. 14 shows an eye pattern of the received signal when the correction process is not performed. FIG. 15 shows an eye pattern of the received signal when correction processing is performed. The eye patterns in FIGS. 14 and 15 are those of the received signal generated at one end of the inductor L2 provided on the receiving circuit side.

  In FIG. 14, it can be seen that the eye pattern is broken due to waveform distortion. It is difficult to discriminate such a signal with a discrimination circuit. On the other hand, in FIG. 15, the distortion of the waveform is corrected to form a large eye pattern, and it can be seen that it is easy to determine the signal level of the received signal. As shown in FIG. 15, by performing the correction process of the drive circuit DRV1 according to the first embodiment, the binary transmission data becomes a ternary reception signal of 0, 1, and -1. For example, transmission data subsequent to -1, 1, -1, -1 are received signals of 0, 1, -1, 0.

  From the above description, in the drive circuit DRV1 according to the first embodiment, the time required for convergence of the received signal is shortened by performing the correction process by the FIR type equalization process. This correction process is performed at the data rate of the transmission data. Thereby, in the drive circuit DRV1 according to the first embodiment, even when transmission data is transmitted at a data rate higher than the self-resonance frequency of the inductors L1 and L2, interference between continuous transmission data is prevented, and the reception circuit Erroneous reception can be prevented.

  In addition, since the driving circuit DRV1 according to the first embodiment uses a clock signal having a frequency lower than the data rate of transmission data when performing the correction process, it is possible to reduce power consumption required for the correction process.

Embodiment 2
In the second embodiment, a drive circuit DRV2 that is a modification of the drive circuit DRV1 according to the first embodiment will be described. FIG. 16 is a block diagram of the drive circuit DRV2 according to the second embodiment. As shown in FIG. 16, the drive circuit DRV2 is obtained by adding a precoder 3 to the drive circuit DRV1.

  The precoder 3 is provided before the correction unit 1, modulates the transmission data DIN 0, and outputs the modulated transmission data DIN 1 to the correction unit 1. The transmission data DIN reaches the determination circuit DET1 with a predetermined transfer function determined by the correction unit 1, the drive unit 2, the inductors L1, L2, and the like. The precoder 3 modulates the transmission data DIN0 with a transfer function that cancels a predetermined transfer function to generate transmission data DIN1.

Here, a specific example of the precoder 3 will be described. FIG. 17 is a block diagram for explaining the configuration of the precoder 3. In the example shown in FIG. 17, the transmission data DIN0 is modulated by the precoder 3 and becomes reception data DOUT via the correction unit 1, the drive unit 2, the inductors L1 and L2, the reception signal correction unit 4, and the determination unit 5. In the example of FIG. 17, the correction unit 1, the drive unit 2, the inductors L1 and L2, and the reception signal correction unit 4 are signal transmission units. And let the transfer function of this signal transmission part be 1-D. Note that D indicates a delay corresponding to a 1-bit width. Further, the transfer function of the discriminator 5 is assumed to be mod2 (residue of 2). The precoder 3 shown in FIG. 17 has a transfer function of the expression (1) in order to cancel the transfer function 1-D of the signal transfer unit and the transfer function of the determination unit 5.

  The precoder 3 includes an exclusive OR circuit 90, a flip-flop 91, and an inverter 92. The exclusive OR circuit 90 outputs an exclusive OR operation result of the transmission data DIN0 and the inverted signal of the modulated transmission data DIN1. The flip-flop 91 updates the hold value with the output value of the exclusive OR circuit 90 based on the clock signal having the same frequency as the data rate. Further, the output value of the flip-flop 91 becomes the transmission data DIN1 after modulation. The inverter 92 inverts the modulated transmission data DIN1 and supplies the inverted transmission data DIN1 to the exclusive OR circuit 90.

  In the example illustrated in FIG. 17, an example of the determination unit 5 is illustrated. The determination unit 5 includes comparators 93 and 94 and an exclusive OR circuit 95. The reference voltage + Vref2 is input to the inverting input terminal of the comparator 93, and the reception signal MR corrected by the reception signal correction unit 4 is input to the normal rotation input terminal. The reception signal MR corrected by the reception signal correction unit 4 is input to the normal input terminal of the comparator 94, and the reference voltage -Vref2 is input to the inverting input terminal. The output signal of the comparators 93 and 94 is input to the exclusive OR circuit 95. With such a configuration, the determination unit 5 functions as a circuit that determines a remainder of 2 with respect to a ternary signal of 1, 0, and −1.

  In the drive circuit DRV2 according to the second embodiment, the precoder 3 is provided to cancel the transfer functions of the signal transfer unit and the determination unit. Thus, the received data can be generated with a simple circuit by canceling the transfer function of the signal transfer path. Further, the correlation between the reception data DOUT and the transmission data DIN1 can be increased by canceling the transfer function of the signal transmission path.

Embodiment 3
In the third embodiment, a modified example of the drive circuit DRV1 according to the first embodiment will be described. FIG. 18 shows a block diagram of the drive circuit DRV3 according to the third embodiment. As shown in FIG. 18, the drive circuit DRV3 according to the third embodiment is obtained by adding an equalization coefficient adjustment circuit 6 to the drive circuit DRV1 according to the first embodiment.

  The equalization coefficient adjustment circuit 6 adjusts a correction coefficient (for example, equalization coefficient) used in the FIR type equalization process in the transmission signal correction unit 1 based on the output waveform of the drive unit 2 and the transmission data DIN. In the example shown in FIG. 18, the equalization coefficient adjustment circuit 6 receives the drive waveform of the inductor L1 output as a differential signal and the transmission data DIN, and uses the equalization coefficient holding unit 11 to calculate the adjusted equalization coefficient calculated therefrom. Output to.

Here, a specific adjustment process of the equalization coefficient adjustment circuit 6 will be described. The equalization coefficient adjustment circuit 6 adjusts the equalization coefficient so as to minimize the mean square error between the value of the transmission data DIN and the transmission data on the transmission circuit side obtained from the drive waveform of the inductor L1. More specifically, the mean square error is reduced by iteratively calculating the following formulas (2) to (4) at the data rate. Equations (2) to (4) are for performing equalization processing using three pieces of transmission data DIN.
d = sign [x (n), x (n-1), x (n-2)] (2)
error = sign (DIN (n) −DOUT (n)) (3)
w (n + 1) = w (n) + μ * error * d (4)
In the equation (2), d is a variable, x is a sign of transmission data DIN, and n is a transmission order of transmission data. In the expression (2), the sign of the three transmission data DIN is a variable d. In equation (3), a difference error between the nth transmission data DIN and the nth reception data DOUT output from the reception circuit is calculated. In equation (4), the multiplication value of the variable d, the difference error and the coefficient adjustment unit μ is subtracted from the equalization coefficient w (n) after n iterations, thereby obtaining an equalization coefficient after n + 1 iterations and To do. Such a calculation method is referred to as a sign least square error method.

  FIG. 19 shows the transition by the iterative calculation of the mean square error calculated by the sign least square error method. As shown in FIG. 19, by repeating the iterative calculation by the code least square error method, the mean square error between the transmission data DIN and the reception data DOUT corresponding to the transmission data DIN is reduced. FIG. 20 shows transitions of the equalization coefficients W1 to W5 when the calculations of the expressions (2) to (4) are repeatedly performed. As shown in FIG. 20, the equalization coefficients W1 to W5 converge to a predetermined value.

  From the above description, by providing the equalization coefficient adjusting circuit 6, the equalization coefficient can be set without calculating in advance. Further, the equalization coefficient adjustment circuit 6 can appropriately change the equalization coefficient even when it is necessary to change the equalization coefficient in accordance with the state of the communication system.

Embodiment 4
In the fourth embodiment, an equalization coefficient adjustment circuit 6a as a modification of the equalization coefficient adjustment circuit 6 according to the third embodiment will be described. FIG. 21 shows a block diagram of the drive circuit DRV4 having the equalization coefficient adjustment circuit 6a. As shown in FIG. 21, the equalization coefficient adjusting circuit 6a receives a waveform of a reception signal generated in the inductor L2 instead of the output waveform of the drive circuit. Even in such a configuration, since the transmission data DOUT can be reproduced, the equalization coefficient adjustment circuit 6a can perform the same operation as the equalization coefficient adjustment circuit 6.

  The signal input from the receiving circuit side may be performed via a wireless interface or via a wired interface.

  The configuration of the fourth embodiment is particularly effective when the delay between the inductors L1 and L2 is small or when the equalization coefficient update rate is slow. Further, since the equalization coefficient adjustment circuit 6a performs the adjustment process of the equalization coefficient based on the signal generated on the receiving circuit side, it is possible to perform adjustment with higher accuracy.

Embodiment 5
In the fifth embodiment, an example in which the transmission waveform is corrected on the receiving circuit side will be described. More specifically, in the fifth embodiment, correction processing is performed in the determination circuit DET1 of the reception circuit. A block diagram of the discrimination circuit DET1 is shown in FIG. As illustrated in FIG. 22, the determination circuit DET1 includes a reception signal correction unit 4 and a determination unit 5.

  The reception signal correction unit 4 corrects the waveform distortion caused by the self-resonance of the inductors L1 and L2 in the reception signal, and generates a corrected reception signal. The speed at which the reception signal correction unit 4 performs the correction process is a speed corresponding to the data rate of the transmission data DIN. The correction processing performed by the reception signal correction unit 4 corrects the reception signal based on the reception signals for n cycles received n cycles before the reception signal. More specifically, the reception signal correction unit 4 includes an equalization coefficient holding circuit 101 and an FIR filter circuit. In the FIR type filter circuit, correction processing (for example, equalization processing is performed by the function of the FIR type filter, and therefore, in the following description, the FIR type filter circuit is referred to as FIR type equalize circuit 102. The equalization coefficient holding circuit 101 is , And holds the equalization coefficient used in the FIR type equalization circuit 102. In the fifth embodiment, this equalization coefficient is set in advance.

  The determination unit 5 determines the logical level of the transmission data DIN based on the corrected reception signal and generates reception data DOUT.

  Subsequently, the equalization process performed in the reception signal correction unit 4 will be specifically described. FIG. 23 shows a processing principle of equalization processing performed by the reception signal correction unit 4. In FIG. 23, in order to explain the operation principle of the equalization process, a specific circuit is shown for each process necessary for the equalization process. As shown in FIG. 23, the equalization processing performed by the received signal correction unit 4 according to the fifth embodiment can be realized by delay circuits 1111 to 111n, multipliers 1120 to 112n, and an adder 113.

  Delay circuits 1111 to 111n are cascade-connected. The delay circuits 1111 to 111n delay the received signal by a time corresponding to the data rate period. Then, the delay circuits 1111 to 111n transmit the delayed reception signal to the next-stage delay circuit. Multiplier 1120 multiplies the input received signal by equalization coefficient C0 and outputs the multiplication result. Multipliers 1121 to 112n multiply the reception signals output from delay circuits 1111 to 111n and equalization coefficients C1 to Cn, respectively, and output the multiplication results. The adder 113 adds the multiplication results output from the multipliers 1120 to 112n to generate a corrected received signal MR.

  That is, in the equalization process, the reception signal is delayed and the reception signals for n cycles are parallelized. Then, equalization coefficients C0 to Cn are multiplied according to the reception order of the parallel received signals. Then, n received signals obtained by multiplying equalization coefficients C0 to Cn are added to obtain a corrected received signal MR.

  The determination circuit DET1 according to the fifth embodiment receives the reception signal as an analog signal and determines the logical level of the transmission data DIN. Therefore, the determination circuit DET1 constitutes the reception signal correction unit 4 by an analog circuit. Specifically, the delay circuit is realized by a resistor and a capacitor, for example. The multiplier can be an amplifier whose output capability varies according to the equalization coefficient. Furthermore, the adder can be realized by connecting the outputs of the multipliers at one node.

  By using the FIR type equalize circuit, the distortion of the received signal can be corrected as in the first embodiment. Therefore, by providing the FIR type equalize circuit 102 in the receiving circuit, it is possible to shorten the time until the amplitude of the received signal MR after correction converges, as in the first embodiment. Further, by using the FIR type equalize circuit, interference between continuous data can be suppressed.

Embodiment 6
In the sixth embodiment, another form of the received signal correction unit 4 of the fifth embodiment will be described. In the sixth embodiment, a reception signal correction unit 7 is provided instead of the reception signal correction unit 4. Then, the reception signal correction unit 7 performs correction processing using a decision feedback equalization circuit. Therefore, the reception signal correction unit 7 includes an equalization coefficient holding circuit 121 and a decision feedback type equalization circuit 122. The equalization coefficient holding circuit 121 holds an equalization coefficient used in the decision feedback type equalization circuit 122.

  The decision feedback equalization circuit 122 corrects the received signal using n received data DOUT received n cycles before the received signal and outputs a corrected received signal MR. That is, the decision feedback equalization circuit 122 corrects the received signal based on n pieces of received data received n cycles before the received signal.

  Subsequently, the equalization process performed by the reception signal correction unit 7 will be specifically described. FIG. 25 shows the principle of the equalization process performed by the reception signal correction unit 7. In FIG. 25, in order to explain the operation principle of the equalization process, a specific circuit is shown for each process necessary for the equalization process. As shown in FIG. 25, the equalization process performed by the reception signal correction unit 7 according to the sixth embodiment can be realized by delay circuits 1311 to 131n, multipliers 1320 to 132n, and adders 133 and 134.

  The delay circuits 1311 to 131n are cascade-connected. Then, the delay circuits 1311 to 131n delay the reception data DOUT by a time corresponding to the data rate period. The delay circuits 1311 to 131n transmit the delayed reception data DOUT to the delay circuit at the next stage. Multiplier 1320 multiplies the input received signal by equalization coefficient C0 and outputs the multiplication result. Multipliers 1321 to 132n multiply the reception data output from delay circuits 1311 to 131n and equalization coefficients C1 to Cn, respectively, and output the multiplication results. The adder 133 adds the multiplication results output from the multipliers 1320 to 132n and outputs a correction signal. The adder 134 adds the correction signal and the reception signal to generate a corrected reception signal MR.

  That is, in the decision feedback equalization process, the reception data DOUT is delayed and the reception signals for n cycles are parallelized. Then, equalization coefficients C0 to Cn are multiplied in accordance with the reception order of the parallel received data DOUT. Subsequently, n received data DOUT obtained by multiplying the equalization coefficients C0 to Cn are added to generate a correction signal. Then, the corrected received signal MR is obtained by adding the corrected signal and the received signal.

  The determination circuit DET2 according to the sixth embodiment generates a correction value using the reception data DOUT output as a digital signal. Therefore, the configurations of the delay circuit, the multiplier, the adder, and the like excluding the adder 134 can use the same configuration as that of the first embodiment (for example, the configuration of FIG. 8).

  Next, an outline of waveform correction by equalization processing by the decision feedback type equalize circuit 122 will be described. FIG. 26 shows a waveform diagram of the reception signal, correction signal, and reception signal MR after correction by the decision feedback equalization circuit 122. As shown in FIG. 26, in the example according to the sixth embodiment, the received signal is not a dicode signal. The correction signal is generated as a rectangular wave corresponding to the peak excluding the first peak of the received signal. Then, by adding the received signal and the correction signal, the corrected received signal MR is suppressed in peak amplitude except for the first peak. Therefore, the logical level of the reception data DOUT can be determined by determining the reception signal at the timing T2 when the first peak occurs. In the example shown in FIG. 26, at the timing T2, the signal level of the received signal exceeds the determination threshold voltage, whereas at other timings, the signal level of all the received signals is almost the same as the signal level at the time of no signal. It is the same.

  Next, the effect of the correction process will be described using the eye pattern of the received signal. FIG. 27 shows an eye pattern of the received signal when the correction process is not performed. FIG. 28 shows an eye pattern of a received signal when correction processing is performed using the decision feedback equalization circuit 122. Note that the eye patterns in FIGS. 27 and 28 are those of the received signal input to the determination unit 5.

  In FIG. 27, it can be seen that the eye pattern is broken due to waveform distortion. It is difficult to discriminate such a signal with a discrimination circuit. On the other hand, in FIG. 28, the distortion of the waveform is corrected to form a large eye pattern, which makes it easy to determine the signal level of the received signal. As shown in FIG. 28, when correction is performed by the decision feedback equalization circuit 122, the received signal MR after correction is a binary signal.

  From the above description, even when the decision feedback type equalize circuit 122 is used, the waveform distortion of the received signal can be corrected and the convergence of the amplitude of the received signal can be accelerated. Thereby, like other embodiments, interference between continuous transmission data can be prevented, and high-speed communication can be realized without being restricted by the self-resonance frequency by the inductors L1 and L2.

Embodiment 7
In the seventh embodiment, a modification of the determination circuit DET2 according to the sixth embodiment will be described. FIG. 29 shows a block diagram of the determination circuit DET3 according to the seventh embodiment. As illustrated in FIG. 29, the determination circuit DET3 according to the seventh embodiment is obtained by adding an equalization coefficient adjustment circuit 8 to the determination circuit DET1 according to the sixth embodiment.

  The equalization coefficient adjustment circuit 8 outputs the correction coefficient (for example, equalization coefficient) used in the determination feedback type equalization processing in the received signal correction unit 7 and the reception data DOUT output from the determination unit 5 and the determination feedback type equalization circuit 122. Adjustment is made based on the waveform of the received signal MR after correction.

Here, a specific adjustment process of the equalization coefficient adjustment circuit 8 will be described. The equalization coefficient adjustment circuit 8 adjusts the equalization coefficient so as to minimize the mean square error between the reception data obtained from the corrected waveform of the reception signal MR and the reception data DOUT. More specifically, the mean square error is reduced by iteratively calculating the following formulas (5) to (7) at the data rate. Equations (5) to (7) are for performing equalization processing using three pieces of received data DOUT.
d = sign [y (n), y (n-1), y (n-2)] (5)
error = sign (DOUT (n) −MR (n)) (6)
w (n + 1) = w (n) + μ * error * d (7)
In equation (5), d is a variable, y is a sign of received data DOUT, and n is a reception order of received data. In the equation (5), the sign of the three received data DOUT is a variable d. In the equation (6), a difference error between the nth received signal MR and the nth received data DOUT is calculated. In equation (7), the equalization coefficient after n + 1 iterations is obtained by subtracting the multiplication value of the variable d, the difference error and the coefficient adjustment unit μ from the equalization coefficient w (n) after n iterations. And Such a calculation method is referred to as a sign least square error method.

  From the above description, by providing the equalization coefficient adjusting circuit 8, the equalization coefficient can be set without calculating in advance. Further, the equalization coefficient adjustment circuit 8 can appropriately change the equalization coefficient even when it is necessary to change the equalization coefficient in accordance with the state of the communication system.

Embodiment 8
In the eighth embodiment, another form of the inductors L1 and L2 will be described. Accordingly, FIG. 30 shows a block diagram of a communication system showing another form of the inductors L1 and L2. As shown in FIG. 30, the inductors L <b> 1 and L <b> 2 according to the eighth embodiment are not formed in a loop shape like the inductors according to the other embodiments but are formed by wires with open ends. FIG. 31 shows an equivalent circuit diagram of the inductors L1 and L2 when the inductor is formed in such a shape.

  As shown in FIG. 31, in the equivalent circuit of the inductors L1 and L2 according to the eighth embodiment, the inductor L and the wiring resistance R are connected in series, and the parasitic capacitance C is connected between the ground power supply and the wiring resistance. The The inductors L1 and L2 form a magnetic coupling having a coupling coefficient M by being close to each other. In this way, the inductors L1 and L2 only need to have a shape or form that enables wireless communication by magnetic coupling.

Other Embodiments In other embodiments, a mounting form of the transmission circuit and the reception circuit according to the above embodiment will be described. FIG. 32 shows an example in which a transmission circuit and a reception circuit are mounted on different printed circuit boards.

  In the example shown in FIG. 32, the transmission circuit and the processing circuit A are mounted on the printed circuit board PB1. Further, the wiring that forms the inductor L1 is formed on the printed circuit board PB1. Then, the transmission circuit drives the inductor L1. A receiving circuit and a processing circuit B are mounted on the printed circuit board PB2. Further, the wiring that constitutes the inductor L2 is formed on the printed circuit board PB2. And a receiving circuit receives a received signal via this inductor L2.

  That is, in the example shown in FIG. 32, the transmission circuit and the reception circuit are insulated by being formed on different semiconductor substrates. The inductors L1 and L2 are mounted as external components on the transmission circuit and the reception circuit.

  Such an implementation can be used as an interface between a semiconductor storage device such as a flash memory and a processing device using the semiconductor storage device, for example. In this implementation, a semiconductor memory device such as a flash memory is formed on one of the processing circuits A and B, and a personal computer or the like is formed on the other of the processing circuits A and B.

  Further, by providing a plurality of transformers, transmission circuits, and reception circuits formed by inductors, a plurality of signal transmission paths can be formed by the plurality of inductors. By configuring the interface in this way, for example, an interface having a plurality of terminals currently used can be replaced with a wireless interface. Here, in the transmission circuit and the reception circuit according to the present invention, since the data rate is not limited by the self-resonance frequency of the inductor, the data rate of the conventional interface and the data rate of the wireless interface via the inductor can be easily adapted. Can do. That is, the interface can be wireless while maintaining the conventional interface specifications.

  The mounting form shown in FIG. 32 can also be used for a mobile terminal such as a mobile phone. For example, by providing a printed circuit board PB1 on which a transmitting circuit is mounted on a mobile phone and providing a printed circuit board PB2 on which a receiving circuit is mounted on another terminal, an interface between the mobile terminal and another device is formed. Can do.

  FIG. 33 shows an implementation example of the transmission circuit and the reception circuit when the transmission circuit and the reception circuit operate with different power supply voltages. As shown in FIG. 33, when the power supply voltages of the transmission circuit and the reception circuit are different, it is generally preferable to insulate the transmission circuit and the reception circuit. When circuits operating with different power supply voltages are connected without insulation, problems such as reverse current flow may occur due to the voltage difference between the power supply voltages. This insulation method includes a method of forming the transmission circuit and the reception circuit in separate semiconductor devices and a method of forming the transmission circuit and the reception circuit in separate regions insulated from each other on the same semiconductor chip. There is a problem that signals cannot be transmitted only by simple connection between circuits that are insulated from each other. In such a case, communication between circuits can be performed by using a wireless interface using an inductor. Further, in the transmission circuit and the reception circuit according to the present invention, since the data rate is not limited by the inductor, the communication speed between the circuits insulated from each other can be increased.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the precoder and the equalize correction circuit are applicable to all the embodiments.

  As described above, a case has been shown in which communication is performed such that the data rate Rb that is the reciprocal of the pulse transmission interval is higher than the self-resonance frequency of the inductor L1 and the inductor L2. It is desirable that the inductors L1 and L2 have substantially the same self-resonant frequency. However, when the inductors L1 and L2 have different self-resonant frequencies, the received waveform is defined by the self-resonant frequency of L2, so that the data rate to be transmitted / received should be higher than the self-resonant frequency of L2.

DRV, DRV1 to DRV4 drive circuit DET, DET1 to DET3 discrimination circuit L1, L2 Inductor 1 Transmission signal correction unit 2 Drive unit 3 Precoder 4, 7 Reception signal correction unit 5 Discrimination unit 6, 6a, 8 Equalization coefficient adjustment circuit 11, 101 Equalization coefficient holding circuit 12, 102 FIR type equalization circuits 311 to 31n, 1311 to 131n Delay circuits 320 to 32n, 1320 to 132n Multipliers 33, 133, 134 Adder 40 Data delay circuits 411 to 415 Multiplexers 421 to 425 Transmission signal output Circuits 51-58, 60-62, 64-66, 68-70 Flip-flops 63, 67, 71 Selector 72 Inverter 80 Differential amplifier 81 Variable current source MN1-MN12 Transistor

Claims (6)

A transmission circuit that drives an inductor to generate electromagnetic induction and transmits data,
A drive circuit that receives transmission data at a data rate higher than the self-resonant frequency of the inductor and outputs a transmission signal that drives the inductor at a data rate of the transmission data;
The drive is performed by modulating the transmission data with a transfer function that cancels a transfer function from a received signal to a determination circuit that generates transmission data in a semiconductor chip different from the semiconductor chip in which the drive circuit is formed from the input of the drive circuit A precoder circuit that outputs to the circuit;
A transmission circuit. The drive circuit is
A drive unit for driving the inductor;
Receiving the transmission data, correcting the waveform distortion caused by self-resonance of the inductor with respect to the transmission data, and transmitting the corrected transmission data to the drive unit;
The transmission circuit according to claim 1, comprising:   The transmission circuit according to claim 2, wherein the transmission signal correction unit corrects a waveform distortion caused by self-resonance of the inductor at a processing speed corresponding to the data rate.   The transmission circuit according to claim 3, wherein the transmission signal correction unit corrects the transmission data by FIR filter processing.   The correction coefficient used in the FIR filter processing in the transmission signal correction unit is based on the output waveform of the drive circuit or a reception signal waveform on a semiconductor chip different from the semiconductor chip on which the drive circuit is formed and the transmission data. The transmission circuit according to claim 4, further comprising a coefficient adjustment circuit for adjustment.   The transmission circuit according to claim 1, wherein the inductor is formed on the same semiconductor substrate as the drive circuit.