JP2015203831A - Display drive circuit and display driver ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust slew rates of all source amplifiers to be uniform to each other even if the chip size of a display driver IC is increased and thereby make the luminance characteristics of a display panel within lines equal to each other.SOLUTION: A display driver IC includes: a plurality of source amplifiers; a plurality of gradation level selection circuits supplying input level to the respective source amplifiers; a gradation level generation circuit supplying gradation level to the gradation level selection circuit through a gradation line; and a bias control circuit adjusting bias current of the source amplifier. The bias control circuit adjusts the bias current of each source amplifier based on the wiring length of the gradation line to the gradation level selection circuit corresponding to the source amplifier from the gradation level generation circuit. The bias current of each source amplifier is adjusted so as to cancel a difference between gradation line level restoration times due to wiring resistance of the gradation line, and a slew rate of each source amplifier is adjusted to be uniform among all the source amplifiers.

Description

  The present invention relates to a display drive circuit and a display driver IC (Integrated Circuit), and can be suitably used particularly for a display drive circuit and a display driver IC connected to a high-definition display panel.

  In display driver ICs that are connected to a display panel and drive the source electrode, the load on the source electrode increases with the increase in resolution and definition of the display panel, and the number of source output channels also increases. A display panel such as a liquid crystal display (LCD) panel includes a plurality of scanning electrodes (also called gate electrodes) and a plurality of signal electrodes (also called source electrodes), and a pixel capacitance (liquid crystal capacitance) at the intersection. Prepare. The display resolution is the number of pixels, and is defined by the product of the number of lines (number of gate electrodes) and the number of pixels per line (corresponding to the number of source electrodes). Since the display driver IC is mounted on one side of the display panel, as the number of lines (the number of gate electrodes) increases, the wiring length to the far-end pixel capacitance increases and the wiring resistance increases. Further, the difference in wiring resistance between the pixel capacitors at the far end and near end becomes large. Due to such a background, in the display driver IC, the load on the source electrode is increased as the display panel has higher resolution and higher definition.

  Patent Document 1 discloses a capacitive load drive circuit that is suitable for a source electrode drive circuit (source amplifier) of such a display driver IC and can reduce power consumption while maintaining drive capability. Yes. In the source electrode drive circuit, the slew rate is adjusted based on the distance (arrangement) to the capacitive load to be driven.

JP 2008-139697 A

  As a result of examination of the patent document 1 by the present inventors, it has been found that there are the following new problems.

  In Patent Document 1, the wiring resistance from the source electrode driving circuit (source amplifier) to the load capacitance (pixel capacitance) on the display panel is considered, but the wiring resistance inside the display driver IC is not considered. . In the display driver IC, a large number of source electrode drive circuits (source amplifiers) are arranged along the side where the terminals connected to the source electrodes of the display panel are arranged. The source amplifier selects one gradation voltage from a plurality of supplied gradation voltages based on image data or generates an intermediate gradation voltage from a plurality of gradation voltages, and drives the connected source electrode Output analog voltage. At this time, as the chip size increases, intra-chip wiring such as gradation lines for supplying gradation voltages to each source amplifier becomes longer. As the wiring becomes longer, the resistance of the gradation line and power supply line becomes higher, and there is a difference in the recovery time from the gradation line level and the recovery time from the power supply drop in the near-end and far-end source amplifiers from each supply circuit. I found it to happen. Along with this, there is a difference between the slew rate of the source amplifier arranged on the near-end side from the gradation line supply circuit and the slew rate of the source amplifier arranged on the far-end side, resulting in the luminance characteristics of the display panel. It has been found that there is a risk of causing variations.

  An object of the present invention is to adjust the slew rate of all the source amplifiers to be equal even when the chip size of the display driver IC is increased, and to align the luminance characteristics within the line of the display panel.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, according to an embodiment of the present invention, a plurality of source amplifiers, a plurality of gradation level selection circuits that respectively supply input levels, and a gradation level that is supplied to the gradation level selection circuit by gradation lines. A display driving circuit or a display driver IC including a tone level generation circuit and a bias control circuit that adjusts the bias current of the source amplifier. The bias control circuit adjusts the bias current of each source amplifier based on the wiring length of the gradation line from the gradation level generation circuit to the gradation level selection circuit corresponding to the source amplifier. The bias current of each source amplifier is adjusted so as to cancel the difference in the gradation line level recovery time due to the wiring resistance of the gradation line, and the slew rate of each source amplifier is made equal for all the source amplifiers. Adjusted to

  The effect obtained by the one embodiment will be briefly described as follows.

  That is, even when the chip size of the display driver IC is increased, it is possible to adjust the slew rate of all the source amplifiers to be equal, and to align the luminance characteristics within the line of the display panel. In this application, the term “equal” in terms of slew rate does not mean that it is mathematically strictly equal, but includes a deviation within a range in which the difference in luminance characteristics within the line of the display panel is not visually recognized. Means equal. Further, the term “adjustment to be equal” means that adjustment is performed in a direction that makes equality, and does not require that the result is equal.

FIG. 1 is a block diagram illustrating a configuration example of an electronic device in which a display driving circuit (display driver IC) according to the present invention is mounted. FIG. 2 is a block diagram illustrating a configuration example of a display driving circuit (display driver IC). FIG. 3 is an explanatory diagram schematically showing an example of the layout of the display drive circuit (display driver IC). FIG. 4 is a circuit diagram showing a configuration example of the source amplifier bias control circuit. FIG. 5 is a circuit diagram showing a configuration example of the source amplifier. FIG. 6 is an explanatory diagram schematically showing an embodiment of the layout of the display drive circuit (display driver IC). FIG. 7 is a circuit diagram illustrating a configuration example of the source amplifier block according to the first embodiment. FIG. 8 is a circuit diagram illustrating a configuration example of the source amplifier block according to the second and third embodiments. FIG. 9 is a circuit diagram illustrating a configuration example of the source amplifier bias control circuit according to the second embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of the source amplifier bias control circuit according to the third embodiment. FIG. 11 is an explanatory diagram schematically illustrating an example of the arrangement of the source amplifier blocks and the wiring from the source amplifier bias control circuit according to the second and third embodiments. FIG. 12 is a graph showing a bias current distribution in the layout (placement / wiring) shown in FIG. FIG. 13 is an explanatory diagram schematically illustrating another example of the arrangement of the source amplifier blocks and the wiring from the source amplifier bias control circuit according to the second and third embodiments. FIG. 14 is a graph showing a bias current distribution in the layout (placement / wiring) shown in FIG. FIG. 15 is an explanatory diagram for explaining the problems found by the inventors of the present application and the effects of the present invention.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Source amplifier whose bias is controlled based on the wiring length of the gradation line>
A representative embodiment disclosed in the present application includes a plurality of source amplifiers (4_1 to 4_n), a plurality of gradation level selection circuits (5_1 to 5_n) for supplying input levels to the source amplifiers, A display drive circuit comprising a gradation level generation circuit (13) for supplying gradation levels to the gradation level selection circuit by means of gradation lines, and a bias control circuit (14) for adjusting bias currents of the plurality of source amplifiers. (1), which is configured as follows. The bias control circuit adjusts the bias currents of the plurality of source amplifiers based on the wiring length of the gradation line from the gradation level generation circuit to the gradation level selection circuit corresponding to the source amplifier.

  As a result, even when the chip size of the display driver IC (1) is increased, the slew rate of all the source amplifiers (4_1 to 4_n) is adjusted to be equal, and the line in the display panel (2) is adjusted. Brightness characteristics can be aligned. The bias current of each source amplifier is controlled so as to cancel the difference in the gradation line level recovery time caused by the wiring length (wiring resistance) of the gradation line from the gradation level generation circuit (13) to each source amplifier. This is because the slew rate of all the source amplifiers can be adjusted to be equal.

[2] <Adjust bias current for each block>
In Item 1, the plurality of source amplifiers are divided into a plurality of groups (L1 to L4, R1 to R4) based on the wiring lengths of the gradation lines, and the bias control circuit includes a source for each group. Adjust the bias current of the amplifier.

  Thereby, the bias control circuit is simplified, and the size of the circuit added for controlling the bias of the source amplifier and the area of the added wiring can be suppressed.

[3] <Bias current supply wiring short-circuited between blocks>
In item 2, the bias current control lines supplied from the bias control circuit to the groups of the plurality of source amplifiers are short-circuited at the boundary between adjacent groups.

  This eliminates the discontinuity of the bias current between adjacent blocks.

[4] <Adjusting current gain on the source amplifier bias control signal receiving side>
In Item 1, the bias control circuit forms a current mirror with the plurality of source amplifiers, and the current amplification factors of the current mirrors of the plurality of source amplifiers can be adjusted.

  As a result, the number of bias control lines from the bias control circuit to the plurality of source amplifiers becomes the same as the conventional one, and an increase for carrying out the present invention can be suppressed.

[5] <Register for adjusting bias current amplification factor of source amplifier>
In Item 4, the plurality of source amplifiers are divided into a plurality of groups (L1 to L4, R1 to R4) based on the wiring length of the gradation lines, and the bias control circuit is configured to It has registers (21_L1 to 21_L4, 21_R1 to 21_R4) that can set the current amplification factor of the current mirror.

  As a result, the bias control circuit is simplified as in the item 2, and the scale of the circuit added for controlling the bias of the source amplifier and the area of the added wiring can be suppressed, and the source of each group The bias current of the amplifier is controlled for each block (group) by a digital value set in the register.

[6] <Bias control circuit for each block>
In Item 2, the bias control circuit includes a bias supply circuit (31_L1 to 31_L4, 31_R1 to 31_R4) for controlling bias currents of the plurality of source amplifiers for each group, and the bias current of the source amplifier is set for each group. Can be adjusted to.

  As a result, the number of bias control lines from the bias control circuit to the plurality of source amplifiers is increased as compared with the item 2, but the source amplifier itself is the same as the conventional one, and the circuit scale of the source amplifier for carrying out the present invention is increased. The increase can be suppressed.

[7] <Bias control circuit for each block (shared reference current source)>
In Item 6, the bias control circuit includes one reference current source (30) and the bias supply circuits (31_L1 to 31_L4, 31_R1 to 31_R4) corresponding to each group, and the bias supply circuit Each constitute a current mirror with the reference current source, and the current mirror can be adjusted in current amplification factor for each group.

  This provides a simple bias control circuit. The current amplification factor of the bias supply circuit corresponding to each block (group) is set by, for example, registers (22_L1 to 22_L4, 22_R1 to 22_R4) provided for each block (group).

[8] <Bias control circuit for each block (individual reference current source)>
In Item 6, the bias control circuit includes the bias supply circuit (31_L1 to 31_L4, 31_R1 to 31_R4) corresponding to each group and a plurality of reference current sources (30_L1 to 30_L4, 30_R1 to 30_R4) corresponding to each group. Each of the bias supply circuits forms a current mirror with the reference current source, and the reference current source can have a current value adjusted for each group.

  This provides a simple bias control circuit. The current value of the reference current source of the bias supply circuit corresponding to each block (group) is set by, for example, registers (23_L1 to 23_L4, 23_R1 to 23_R4) provided for each block (group).

[9] <Bias current supply wiring short-circuited between blocks>
Item 6, Item 7 or Item 8, wherein bias current control lines (BIP11-14, BIN11-14) supplied from the bias control circuit to the groups of the plurality of source amplifiers are boundaries between adjacent groups. Is short-circuited.

  Thereby, similarly to the item 3, the discontinuity of the bias current between the adjacent blocks (groups) is eliminated.

[10] <Display driver IC>
In any one of Items 1 to 9, the display driving circuit is formed on a single semiconductor substrate.

  Thereby, a display driver IC including the display driving circuit of the present invention can be provided.

[11] <Layout>
In item 10, the plurality of source amplifiers and the plurality of gradation level selection circuits are arranged in a longitudinal direction of the semiconductor substrate, and the gradation level generation circuit and the bias control circuit are respectively connected to the plurality of source amplifiers. And the plurality of gradation level selection circuits are arranged approximately at the center in the longitudinal direction.

  Thereby, the wiring length of the gradation line can be suppressed to about ½ of the width in the longitudinal direction (left and right direction) where a plurality of gradation level selection circuits are arranged. The bias currents of the plurality of source amplifiers are controlled symmetrically, or when there is left-right asymmetry, they are controlled independently so that the slew rate of the source amplifiers is symmetrical. Can do. Here, “center” and “right / left symmetry” do not mean mathematically exact “center” and “left / right symmetry”, but allow errors based on industrial specifications. The industrial specification at this time is defined on the basis of, for example, the degree to which the luminance of an image displayed on the display panel cannot visually recognize the luminance difference between the left and right for the user viewing the image.

[12] <Display driver IC for controlling bias current of source amplifier based on wiring length of gradation line>
A representative embodiment disclosed in the present application includes a plurality of source amplifiers (4_1 to 4_n), a plurality of gradation level selection circuits (5_1 to 5_n) for supplying input levels to the source amplifiers, A display driver IC comprising a gradation level generation circuit (13) for supplying gradation levels to the gradation level selection circuit by gradation lines, and a bias control circuit (14) for adjusting bias currents of the plurality of source amplifiers. (1), which is configured as follows.

  The plurality of source amplifiers and the plurality of gradation level selection circuits are arranged in a longitudinal direction, the gradation lines are wired in the longitudinal direction from the gradation level generation circuit, and the plurality of gradation level generation circuits are Are connected to the gradation lines. The bias control circuit adjusts the bias currents of the plurality of source amplifiers based on the wiring length of the gradation line from the gradation level generation circuit to the gradation level selection circuit corresponding to the source amplifier.

  As a result, even when the chip size of the display driver IC (1) is increased, the slew rate of all the source amplifiers (4_1 to 4_n) is adjusted to be equal, and the line in the display panel (2) is adjusted. Brightness characteristics can be aligned. The bias current of each source amplifier is controlled so as to cancel the difference in the gradation line level recovery time caused by the wiring length (wiring resistance) of the gradation line from the gradation level generation circuit (13) to each source amplifier. This is because the slew rate of all the source amplifiers can be adjusted to be equal.

[13] <Adjust bias current for each block>
In Item 12, the plurality of source amplifiers and the plurality of gradation level selection circuits are divided into a plurality of regions (L1 to L4, R1 to R4), and the bias control circuit is provided for each region. Adjust the bias current.

  Thereby, the bias control circuit is simplified, and the size of the circuit added for controlling the bias of the source amplifier and the area of the added wiring can be suppressed.

[14] <Bias current supply wiring short-circuited between blocks>
In item 13, the bias current control lines supplied from the bias control circuit to the source amplifiers in the respective regions are short-circuited at the boundaries between the adjacent regions.

  This eliminates the discontinuity of the bias current between adjacent blocks (regions).

[15] <Adjusting current gain on the source amplifier bias control signal receiving side>
In Item 12, the bias control circuit forms a current mirror with the plurality of source amplifiers, and the current amplification factor of the current mirror can be adjusted for each of the plurality of source amplifiers.

  As a result, the number of bias control lines from the bias control circuit to the plurality of source amplifiers becomes the same as the conventional one, and an increase for carrying out the present invention can be suppressed.

[16] <Register for adjusting bias current amplification factor of source amplifier>
In item 15, the plurality of source amplifiers and the plurality of gradation level selection circuits are divided into a plurality of regions (L1 to L4, R1 to R4), and the bias control circuit is configured to generate the current for each region. It has registers (21_L1 to 21_L4, 21_R1 to 21_R4) that can set the current amplification factor of the mirror.

  As a result, the bias control circuit is simplified similarly to the item 13, and the scale of the circuit added to control the bias of the source amplifier and the area of the added wiring can be suppressed, and each block (region) is controlled. ) Source amplifier bias current is controlled for each block (area) by a digital value set in the register.

[17] <Bias control circuit for each block>
In Item 13, the bias control circuit includes bias supply circuits (31_L1 to 31_L4, 31_R1 to 31_R4) for controlling bias currents of the plurality of source amplifiers for each region, and the bias current of the source amplifier is for each region. Can be adjusted to.

  As a result, the number of bias control lines from the bias control circuit to the plurality of source amplifiers is increased as compared with the item 13, but the source amplifier itself is the same as the conventional one, and the circuit scale of the source amplifier for carrying out the present invention is increased. The increase can be suppressed.

[18] <Bias control circuit for each block (shared reference current source)>
In Item 17, the bias control circuit includes one reference current source (30) and the bias supply circuits (31_L1 to 31_L4, 31_R1 to 31_R4) for supplying a bias current to the source amplifiers in the respective regions. The bias supply circuit forms a current mirror with the reference current source, and the current mirror can be adjusted in current amplification factor for each region.

  This provides a simple bias control circuit. The current amplification factor of the bias supply circuit corresponding to each block (area) is set by, for example, registers (22_L1 to 22_L4, 22_R1 to 22_R4) provided for each block (area).

[19] <Bias control circuit for each block (individual reference current source)>
In Item 17, the bias control circuit includes a bias supply circuit (31_L1 to 31_L4, 31_R1 to 31_R4) that supplies a bias current to the source amplifier in each region, and a plurality of reference current sources (30_L1 to 30_L4) corresponding thereto. 30_R1 to 30_R4), and each of the bias supply circuits forms a current mirror with the reference current source, and the current value of each of the reference current sources can be adjusted for each region.

  This provides a simple bias control circuit. The current value of the reference current source of the bias supply circuit corresponding to each block (area) is set by, for example, registers (23_L1 to 23_L4, 23_R1 to 23_R4) provided for each block (area).

[20] <Bias current supply wiring is short-circuited between blocks>
In the item 17, the item 18 or the item 19, the control line for the bias current supplied from the bias control circuit to the source amplifier in each region is short-circuited at a boundary between adjacent regions.

  Thereby, similarly to the item 14, the discontinuity of the bias current between the adjacent blocks (regions) is eliminated.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 is a block diagram illustrating a configuration example of an electronic device 100 in which a display driving circuit (display driver IC) 1 according to the present invention is mounted. The electronic device 100 is an example of an electronic device according to the present invention, and constitutes a part of a portable terminal such as a PDA (Personal Digital Assistant) or a mobile phone, and includes a display panel 2, a display drive circuit (display driver IC) 1. And a host processor 3. In the electronic device 100, image data supplied from the host processor 3 is displayed on the display panel 2 by the display drive circuit (display driver IC) 1.

  Electronic device 100 may further include a touch panel, a touch panel controller, a sub processor for touch detection, and the like. At this time, the display drive circuit 1 and the touch panel controller, or further, the sub processor or the host processor 3 are formed on a single semiconductor chip, or mounted in one package as, for example, a multichip module, and thus one semiconductor device. May be formed. Further, the display panel 2 and the touch panel may be mounted so as to overlap each other, and may be an in-cell configuration in which they are manufactured as an integral unit or an on-cell configuration in which they are manufactured separately and stacked. The host processor 3 generates image data, and the display drive circuit (display driver IC) 1 performs display control for displaying the image data received from the host processor 3 on the display panel 2. Further, the host processor 3 acquires position coordinate data when a touch event (touch) occurs from the sub-processor, and provides the position coordinate data on the display panel 2 and the display drive circuit (display driver IC) 1 for display. The input by the operation of the touch panel may be analyzed based on the relationship with the displayed screen. Furthermore, the electronic device 100 is configured as, for example, a portable terminal by incorporating or connecting a communication control unit, an image processing unit, an audio processing unit, and other accelerators to the host processor 3.

  On the display panel 2, gate lines G1 to Gm as scan electrodes formed in the horizontal direction and source lines S1 to Sn as signal electrodes formed in the vertical direction are arranged, and display cells are arranged at the intersections. Be placed. The display cell includes a transfer gate Tr having a gate terminal connected to a gate line and a source terminal connected to a source line, a drain terminal of the transfer gate Tr, and a common voltage Vcom as illustrated in a region surrounded by a broken line in the drawing. A pixel capacitor C such as a liquid crystal formed between them is formed. The structure of the transfer gate Tr is symmetric, and the relationship between the drain terminal and the source terminal described above may be reversed. The gate lines G <b> 1 to Gm that are scan electrodes are scan-driven by a gate drive circuit 15 formed in the display panel 2. The circuit elements constituting the gate drive circuit 15 are configured by using, for example, thin film transistors (TFTs) formed on the glass substrate of the display panel 2. At this time, the gate drive circuit 15 is called a gate in panel (GIP). A signal Gctl for controlling the gate drive circuit (GIP) 15 is supplied from the display drive circuit (display driver IC) 1. For example, when the gate drive circuit (GIP) 15 is configured by a shift register, the supplied signal Gctl includes a clock for the shift operation, a start flag, a signal for enabling / disabling the shift direction and the shift operation, and the like. Is included. A signal having a gradation level corresponding to the luminance to be displayed is applied from the display drive circuit (display driver IC) 1 directly or via a demultiplexer to the source lines S1 to Sn as signal electrodes. The pixel capacitors C of the line selected by the above are charged in parallel. When the display panel 2 is a liquid crystal display panel, the magnitude of the polarization of the liquid crystal is determined by the magnitude of the electric field formed by the charge held in the pixel capacitor C, and the amount of transmitted light, that is, the luminance of the pixel is determined. The pixel capacitor C holds the charge and displays the same luminance until the same line is selected in the next frame and a new display level is charged. Driving the scanning electrode and the signal electrode as described above in order to transfer the charge corresponding to the display level to the pixel capacitor C is referred to as display driving and includes a display driving period (also referred to as a display period for short). Means a period during which display driving is performed. The configuration of the display panel 2 is not limited to the illustrated example and is arbitrary. For example, instead of providing the gate drive circuit 15, the gate lines G <b> 1 to Gm can be directly driven by the display drive circuit (display driver IC) 1.

  FIG. 2 is a block diagram illustrating a configuration example of the display drive circuit (display driver IC) 1. The display driving circuit 1 includes a host interface 9, a control unit 8, a frame memory 7, a line latch 6, a source amplifier block 40, a source amplifier bias control circuit 14, a gradation level generation circuit 13, and gate control. The signal drive circuit 12 and the power supply circuit 11 are included.

  The display driving circuit 1 is connected to the host processor 3 via the host interface 9, receives control commands, transmits / receives various parameters, receives image data to be displayed on the display panel 2 at a high speed, and generates vertical synchronization signals. Timing information such as (Vsync) and horizontal synchronization signal (Hsync) is also received. The host interface 9 may be an interface compliant with MIPI-DSI (Mobile Industry Processor Interface Display Serial Interface), which is one of standard communication interfaces of display devices, for example. The control unit 8 includes a command register (not shown) for holding control commands and parameters received from the host processor 3 and a parameter register (not shown). Based on the command register, the operation of each circuit, for example, from the gate control signal drive circuit 12 is performed. The operation of outputting the control signal Gctl of the gate drive circuit 15 is controlled. The control unit 8 writes image data received from the host processor 3 via the host interface 9 in the frame memory 7. The frame memory 7 is composed of, for example, an SRAM (Static Random Access Memory). Image data for one line is read from the frame memory 7 to the line latch 6, and the line latch 6 supplies the image data for one line to the source amplifier block 40 in parallel. The source amplifier block 40 includes source amplifiers 4_1 to 4_n for driving the source lines S1 to Sn and gradation level selection circuits 5_1 to 5_n for inputting gradation levels to the respective source amplifiers. The gradation level selection circuits 5_1 to 5_n are supplied with multi-gradation analog gradation voltages from the gradation level generation circuit 13. Each of the gradation level selection circuits 5_1 to 5_n selects one gradation level corresponding to the image data input from the line latch 6 from the supplied multi-gradation analog gradation voltages, or A plurality of gradation levels are selected, intermediate gradation levels are generated therefrom, and supplied to the connected source amplifiers 4_1 to 4_n. As illustrated in FIG. 2, the source amplifiers 4_1 to 4_n are voltage follower amplifiers configured by operational amplifiers. The source amplifiers 4_1 to 4_n are signal electrodes of the connected display panel 2 by amplifying a supplied gradation level. A certain source wiring S1 to Sn is driven. A bias voltage is supplied from the source amplifier bias control circuit 14 to the source amplifiers 4_1 to 4_n.

  The power supply circuit 11 includes a step-up circuit, a step-down circuit, a stabilization circuit (regulator), and the like, and is used in each circuit in the display drive circuit (display driver IC) 1 from the power supply VDD / VSS supplied from the outside. Generate and supply internal power. The internal power supply is brought to a low impedance by a power amplifier not explicitly shown in FIG.

  The above-described display drive circuit (display driver IC) 1 has been described with respect to the configuration example in which the frame memory 7 is incorporated. However, a configuration in which the frame memory is not incorporated may be employed. In the configuration example in which the frame memory 7 is built in, when the image to be displayed is a still image, the still image of one frame is held in the frame memory 7 and repeatedly read and displayed, thereby displaying the host during the period in which the still image is displayed. Transfer of image data from the processor 3 can be omitted. On the other hand, a configuration without a built-in frame memory requires a small chip area and reduces costs.

  FIG. 3 is an explanatory diagram schematically showing an example of the layout of the display drive circuit (display driver IC) 1. Although not shown, the display drive circuit (display driver IC) 1 includes terminals (pads) for driving the source wirings S1 to Sn of the display panel 2, and therefore, in the direction in which the terminals are arranged, in FIG. The chip is long in the lateral direction (this is called the long side direction). The source amplifier block 40 is arranged, for example, divided into left and right, and the source amplifier bias control circuit 14 is arranged at the center thereof. Similarly, the gradation level generation circuit 13 is also arranged approximately at the center, and gradation lines are wired on the left and right. Although not shown, the gradation lines are further wired to the gradation level selection circuits 5_1 to 5_n included in the source amplifier block 40. A power amplifier that supplies power to the source amplifiers 4_1 to 4_n is also disposed near the source amplifier bias control circuit 14. The gradation level generation circuit 13, the source amplifier bias control circuit 14, and the power supply amplifier are arranged in the center in the long side direction, and the gradation line, the bias wiring, and the power supply wiring are wired to the left and right, respectively. Compared with the case where the wiring is arranged at one end in the side direction, the wiring length can be reduced to approximately ½.

  FIG. 4 is a circuit diagram showing a configuration example of the source amplifier bias control circuit 14. The source amplifier bias control circuit 14 includes a reference current source 30 and a bias supply circuit 31. The reference current source 30 is composed of a current source 300 and an N-channel MOSFET (MN0), and the bias supply circuit 31 is composed of two N-channel MOSFETs, MN9 and MN10, and two P-channel MOSFETs, MP9 and MP10. Is done. A current mirror is configured by MN0 and MN9, and by making the size of MN9 variable, the current value defined by the current source 300 is amplified in accordance with the ratio of the sizes (transconductance) of MN0 and MN9 to supply a bias. This is supplied to the circuit 31. The bias supply circuit 31 also has a current mirror composed of MP9 and MP10, and bias voltages on the P channel side and the N channel side are respectively applied to the differential stage of the source amplifier 4 and the like to be described later by bias lines BIP1 and BIN1. Supply.

  FIG. 5 is a circuit diagram illustrating a configuration example of the source amplifier 4. The source amplifier 4 is an operational amplifier including a differential stage, an intermediate stage, and an output stage, and an output Vout is fed back to one of the differential inputs to constitute a voltage follower amplifier. The differential stage is composed of three P-channel MOSFETs, MP1 to MP3, and three N-channel MOSFETs, MN1 to MN3. Bias lines BIP1 and BIN1 are connected to MP1 and MN1, respectively, and a current mirror is formed between MP9 and NN10 of the source amplifier bias control circuit 14, and functions as a tail current source for supplying a bias current to the source amplifier 4. . Feedback from Vout is connected to the gate terminals of MP2 and MN2, which are one differential input, and Vin is input to the gate terminals of MP3 and MN3, which are the other differential inputs. The intermediate stage is composed of four P-channel MOSFETs, MP4 to MP7, and four N-channel MOSFETs, MN4 to MN7. The two rails, MP4, MP6, MN6, and MN4, and MP5, MP7, MN7, and MN5, are configured to flow currents of the same current value to the differential stage. According to the difference between the two inputs Vin and Vout, a differential voltage is generated and output to the output stage by the current input from the differential stage and the current drawn to the differential stage. MP6 and MN6 and MP7 and MN7 are not shown in the input to the gate terminals, but these gate terminals are fixed at a constant voltage, for example, and MP6 and MN6 and MP7 and MN7 function as load resistors, respectively. It is configured as follows. The output stage includes one P-channel MOSFET, MP8, one N-channel MOSFET, MN8, and feedback capacitors Cp and Cn connected between the respective drain terminals and gate terminals. The differential voltage input from the intermediate stage is current-amplified and Vout is output.

  FIG. 6 is an explanatory view schematically showing an embodiment of the layout of the display drive circuit (display driver IC) 1. Although the layout is the same as that shown in FIG. 3, the source amplifier block 40 is divided into four blocks (areas) L1 to L4 and R1 to R4 on the left and right sides. Although the number of divisions is arbitrary, each block (region) is divided based on the wiring length of the gradation line, the bias wiring, and the power supply wiring. The source amplifier bias control circuit 14 is configured to be able to adjust the bias current of the source amplifier 4 for each block (region). The bias current of the source amplifier 4 for each block (area) cancels the difference in the gradation line level return time caused by the wiring length (wiring resistance) of the gradation line from the gradation level generation circuit 13 to each source amplifier. The slew rate of all source amplifiers is adjusted to be equal. When a difference occurs in the slew rate of the source amplifier due to the wiring length (wiring resistance) of the power supply wiring, the bias current of the source amplifier 4 for each block (region) is controlled so that this difference is canceled out. The Instead of the bias current of the source amplifier, the slew rate may be adjusted to be equal by another method.

  As a result, even when the chip size of the display driver circuit (display driver IC) 1 increases, the slew rate of all the source amplifiers 4_1 to 4_n is adjusted to be uniform, and the luminance within the line of the display panel 2 is adjusted. The characteristics can be aligned.

  FIG. 15 is an explanatory diagram for explaining the problems found by the inventors of the present application and the effects of the present invention. The horizontal axis represents time, and in the vertical axis direction, data, gradation lines, power lines of the source amplifier 4, input and output waveforms are schematically shown in order from the top. The data is a digital signal supplied from the line latch 6 to the gradation level selection circuit 5. A gradation line is an analog gradation level signal supplied from the gradation level generation circuit 13 to each gradation level selection circuit 5, and one line that changes from the non-selected state to the selected state by the gradation level selection circuit 5. The voltage levels of the gradation lines are shown. The voltage of the gradation line is originally kept constant, but the load fluctuates when the gradation level selection circuit 5 changes from the non-selected state to the selected state as the data changes at time t1. Therefore, the voltage temporarily decreases. The load is capacitive, and the magnitude of the voltage drop and the time to return vary depending on the magnitude of the wiring resistance of the gradation line. At the near end of the gradation level generation circuit 13, the wiring resistance is minimum and thus the voltage drop and the recovery time are minimum. However, at the far end, the wiring resistance is maximum and the voltage drop and the recovery time are also maximum. The same applies to the power supply line of the source amplifier 4. Although the power supply voltage is originally maintained at a constant value, since the source amplifier 4 operates as data changes, the operating current increases transiently and the power supply voltage temporarily decreases. The magnitude of the power supply voltage drop and the recovery time depend on the wiring resistance of the power supply line. At the near end of the power amplifier that supplies power to the source amplifier 4, the wiring resistance is minimum, so the voltage drop and recovery time are minimum. At the far end, the wiring resistance is maximum, so the voltage drop and recovery time are also maximum. It becomes. The input of the source amplifier 4 is affected by the temporary voltage drop of the gradation line, and the output of the source amplifier 4 is further affected by the temporary voltage drop of the power supply line, resulting in variations in the slew rate. The slew rate is maximum at the near end of the gradation level generation circuit 13 and the power amplifier, and is minimum at the far end. Along with this, the settling time is short at the near end and long at the far end, so that there is a possibility that the required specification t2 of the settling time cannot be satisfied at the far end.

  On the other hand, in the present invention, the bias current on the near end side is decreased and the bias current on the far end side is increased, so that the slew rates of all the source amplifiers 4_1 to 4_n are adjusted in a substantially uniform direction. can do. As a result, even when the size of the display drive circuit (display driver IC) 1 in the longitudinal direction increases, the slew rate of all the source amplifiers is adjusted to be uniform, and the luminance characteristics within the line of the display panel are adjusted. Can be aligned. In addition, the power consumption of the source amplifier on the near end side can be reduced, and a sufficient margin can be secured on the far end side to satisfy the specifications for the settling time.

  Here, in the embodiment shown in FIG. 6, the source amplifier block 40 is divided into four blocks (regions) L1 to L4 and R1 to R4 on the left and right sides, and the bias current of the source amplifier 4 for each block (region). Is controlled. Since the control is performed in units of divided blocks (areas), the slew rate cannot be adjusted and uniformized among the plurality of source amplifiers 4 included in the block (area). However, as described above, it is sufficient if the luminance characteristics within the lines of the display panel can be made uniform, and it is sufficient that the slew rates of all the source amplifiers are adjusted to be equal, and as a result, equal There is no need to be. By increasing the number of divisions, it is possible to achieve a more accurate (with less deviation) equality, while the overhead for the circuit and layout for that purpose becomes large, which is a so-called trade-off relationship. In this application, the terms “equal” and “uniform” with respect to slew rate do not mean exactly equal, but mean equal, including deviations within a range that takes into account the trade-offs described above.

  As a method of adjusting the slew rate of the source amplifier, there are a method of changing circuit constants and a method of changing operating conditions. In the present application, as one of the methods for changing the operating condition, a method for adjusting the bias will be described in detail below. Instead of the method of adjusting the bias, a method of changing circuit constants or a method of changing other operating conditions may be employed.

  FIG. 7 is a circuit diagram illustrating a configuration example of the source amplifier block 40 according to the first embodiment. Only four blocks (regions) R1 to R4 on the right side of the source amplifier block 40 are shown, and bias current adjusting registers 21_R1 to 21_R4 are provided corresponding to the respective blocks (regions). Registers 21_L1 to 21_L4 are provided corresponding to the left four blocks (areas) L1 to L4 (not shown). The registers 21_R1 to 21_R4 and 21_L1 to 21_L4 are not necessarily provided in the source amplifier block 40, and may be provided in another circuit block, for example, the control unit 8. Each block (area) includes a plurality of source amplifiers 4, but due to space limitations, FIG. 7 shows only the differential stages of the two source amplifiers included in the block (area) R1, The intermediate stage, the output stage, and other source amplifiers are omitted.

  Compared with the source amplifier shown in FIG. 5, the source amplifier 4 shown in FIG. 7 functions as a tail current source in the differential stage, and replaces MP1 and MN1 in FIG. MP1a, MP1b, MP1c, MP1sa, MP1sb and MP1sc, six N-channel MOSFETs, MN1a, MN1b, MN1c, MN1sa, MN1sb and MN1sc are provided. The configurations of the intermediate stage and the output stage are the same as those in FIG. BIP1 is input to MP1a, MP1b, and MP1c, and constitutes a current mirror with MP9 of the source amplifier bias control circuit 14 (see FIG. 4), and the respective sizes Wpa / Lpa, Wpb / Lpb, and Wpc / Lpc are set. Accordingly, it functions as a current source having a current value proportional to the current flowing through MP9. Wpa and Lpa are the gate width and gate length of MP1a, respectively. As the size, the expression “Wpa / Lpa” is a notation that is commonly used because the mutual conductance gm of MP1a is proportional to Wpa / Lpa. The same applies to other MOSFETs including other drawings cited in (1).

  MP1sa, MP1sb, and MP1sc are connected to MP1a, MP1b, and MP1c, respectively, and function as switches. Which of MP1a, MP1b, and MP1c that functions as a current source is connected to MP2 and MP3 is controlled by a control signal supplied from the R1 register 21_R1. Assuming that the control signals supplied from the R1 register 21_R1 are bpa, bpb, and bpc, and take the value “1” when asserted and the value “0” when negated, the P channel of the source amplifier 4 The bias current on the side is defined by the following proportionality constant with respect to the current flowing through the MP9 of the source amplifier bias control circuit 14.

bpa × Wpa / Lpa + bpb × Wpb / Lpb + bpc × Wpc / Lpc
Also on the N channel side, the functions of the six N channel MOSFETs, MN1a, MN1b, MN1c, MN1sa, MN1sb, and MN1sc are the same as those of the above P channel side, and the bias current on the N channel side of the source amplifier 4 is The current flowing in MN10 of the source amplifier bias control circuit 14 is defined by the following proportionality constant.

bna × Wna / Lna + bnb × Wnb / Lnb + bnc × Wnc / Lnc
In the source amplifiers 4 included in the eight blocks (areas) R1 to R4 and L1 to L4 constituting the source amplifier block 40, BIP1 and BIN1 supplied from the source amplifier bias control circuit 14 are commonly supplied to all blocks. However, the bias current is independently adjusted for each block (area) by the values set in the registers 21_R1 to 21_R4 and 21_L1 to 21_L4 corresponding to the respective blocks (areas). In the example shown in FIG. 7, the P channel and the N channel are adjusted by the control value of 3 bits each, and the bias current is controlled in the remaining 7 gradations except when all switches are turned off from 8 gradations. . Thereby, it is not necessary to change the source amplifier bias control circuit 14 from the circuit shown in FIG. 4, and the bias current of the source amplifier 4 is changed for each block (region) without increasing the number of wirings of BIP1 and BIN1. It can be controlled independently. Note that the control value of the bias current is 3 bits is merely an example, and the number of bits can be arbitrarily changed.

[Embodiment 2]
FIG. 8 is a circuit diagram illustrating a configuration example of the source amplifier block 40 according to the second and third embodiments. As in FIG. 7, only the four blocks (regions) R1 to R4 on the right side of the source amplifier block 40 are shown, only the differential stage of one source amplifier 4 in the block (region) R1 is shown, The output stage and other source amplifiers are omitted. In the source amplifier block 40 of FIG. 7, the bias lines BIP1 and BIN1 are commonly connected to all the source amplifiers. However, in the source amplifier block 40 of FIG. Corresponding to R4, independent bias lines BIP11 to BIP14 and BIN11 to BIN14 are connected. Each source amplifier 4 has the same circuit configuration as that of the source amplifier 4 shown in FIG.

  FIG. 9 is a circuit diagram illustrating a configuration example of the source amplifier bias control circuit 14 according to the second embodiment. Unlike the source amplifier bias control circuit 14 shown in FIG. 4, it is constituted by one reference current source 30 and bias supply circuits 31_R1 to 31_R4 and registers 22_R1 to 22_R4 respectively corresponding to the blocks (regions) R1 to R4. The The bias supply circuits 31_L1 to 31_L4 and the registers 22_L1 to 22_L4 corresponding to the blocks (areas) L1 to L4 are not illustrated. Each of the bias supply circuits 31_R1 to 31_R4 is configured by the same circuit, and only 31_R1 is illustrated as a representative. The bias supply circuit 31_R1 includes six N-channel MOSFETs, MN9a, MN9b, MN9c, MN9sa, MN9sb, and MN9sc, instead of the MN9 of the bias supply circuit 31 shown in FIG. The gate terminals of MN9a, MN9b, and MN9c are connected to the wiring from the drain terminal and the gate terminal of MN0 of the reference current source 30 to form a current mirror with MN0. MN9a, MN9b, and MN9c have their respective sizes Wna. / Lna, Wnb / Lnb, and Wnc / Lnc function as a current source having a current value proportional to the current flowing through MP9. MN9sa, MN9sb, and MN9sc are connected to MN9a, MN9b, and MN9c, respectively, and function as switches. Which of the MN9a, MN9b, and MN9c that functions as a current source is connected to the MP9 is controlled by a control signal supplied from the R1 register 22_R1. If the control signal supplied from the R1 register 22_R1 is bna, bnb, bnc, and takes the value “1” when asserted and takes the value “0” when negated, the source defined by the BIP11 The bias current of the amplifier 4 is defined by the following proportionality constant with respect to the current flowing through MN0 of the reference current source 30.

bna × Wna / Lna + bnb × Wnb / Lnb + bnc × Wnc / Lnc
Since the current flowing through MP10 and MN10 is also mirrored, the bias current of the source amplifier 4 defined by BIN11 is the same. The bias current of the source amplifier 4 is adjusted by a 3-bit control value, and is controlled with the remaining 7 gradations except when all switches are turned off from 8 gradations.

  Since the registers 22_R1 to 22_R4, the bias supply circuits 31_R1 to 31_R4, and the bias lines BIP11 to BIP14 and BIN11 to BIN14 are provided corresponding to the blocks (areas) R1 to R4, the blocks (areas) R1 to R4 are provided. The bias current of the source amplifier 4 can be controlled independently for each block (region).

  Thereby, also in the second embodiment, in the source amplifier block 40, the bias current of the source amplifier 4 in the block (region) on the near end side from the gradation level generation circuit 13 is reduced and the bias current on the far end side is increased. As a result, the slew rates of all the source amplifiers 4_1 to 4_n can be adjusted to be approximately equal. Therefore, even when the size of the display drive circuit (display driver IC) 1 in the longitudinal direction increases, the slew rate of all the source amplifiers is adjusted to be uniform, and the luminance characteristics in the lines of the display panel are made uniform. be able to.

  In the first embodiment described with reference to FIG. 7, transistors are added to all the source amplifiers 4_1 to 4_n. However, in this embodiment, although the number of bias lines is increased, elements are added to the source amplifier 4. It is not necessary, and the number of transistors added as a whole can be reduced.

  The registers 22_R1 to 22_R4 and the registers 22_L1 to 22_L4 (not shown) may be provided in the source amplifier bias control circuit 14, or may be provided in another circuit block, for example, the control unit 8. In addition, the control values stored in the registers 22_R1 to 22_R4 are described as 3 bits only as an example, and the number of bits can be arbitrarily changed.

  FIG. 11 is an explanatory diagram schematically illustrating an example of the arrangement of the blocks (regions) R1 to R4 on the right side of the source amplifier block 40 and the wiring of the bias lines BIN11 to BIN14 from the source amplifier bias control circuit 14 according to the second embodiment. It is. The wiring of the bias lines BIP11 to BIP14 on the P channel side is the same as the wiring of the bias lines BIN11 to BIN14 shown in the drawing, but is not shown. The blocks (regions) L1 to L4 on the left side of the source amplifier block 40 are the same as those shown on the right side, but are not shown. Resistors R111 to R114, R122 to R124, R133 to R134, and R144 schematically indicate wiring resistances of the bias lines BIN11 to BIN14. Although it is actually a distributed constant, it is shown as a lumped constant resistance. The values of the resistors R111 to R114 are the same values determined by the wiring length corresponding to the width in the longitudinal direction of the block (region) R1. Similarly, the values of the resistors RR122 to R124, R133 to R134, and R144 have the same value determined by the wiring length corresponding to the width in the longitudinal direction of the blocks (regions) R2, R3, and R4. The wiring resistances of BIN11 to BIN14 are R111 only, R112 + R122, R113 + R123 + R133, and R114 + R124 + R134 + R144, respectively. The wiring resistance is smaller at the near end and larger at the far end.

  FIG. 12 is a graph showing a bias current distribution in the layout (placement / wiring) shown in FIG. The horizontal axis represents the distance from the source amplifier bias control circuit 14, and the vertical axis schematically shows the value of the bias current of the source amplifier 4. When the bias current has the same value for all the source amplifiers 4_1 to 4_n, the slew rate of the source amplifier 4 is gradually increased from the block (area) R1 closer to the gradation level generation circuit 13 toward the block (area) R4 that is sequentially farther away. Will decline. In order to offset this and obtain a substantially uniform slew rate, the bias current is set so as to increase from the closest block (region) R1 toward the farther block (region) R4.

  As a result, the slew rates of all the source amplifiers 4_1 to 4_n can be adjusted in a direction that is substantially uniform.

  FIG. 13 schematically shows another example of the arrangement of the blocks (regions) R1 to R4 on the right side of the source amplifier block 40 and the wiring of the bias lines BIN11 to BIN14 from the source amplifier bias control circuit 14 in the second embodiment. It is explanatory drawing. The left blocks (areas) L1 to L4 and the bias lines BIP11 to BIP14 are omitted in the same manner as in FIG. Bias line BIN12 is connected to BIN11 near the boundary between blocks (regions) R1 and R2, bias line BIN13 is connected to each other near the boundary between BIN11 and blocks (region) R2 and R3, and bias line BIN14 is connected to BIN11 and block (region). Region) It is different from FIG. 11 in that it is connected to each other in the vicinity of the boundary between R3 and R4.

  FIG. 14 is a graph showing a bias current distribution in the layout (placement / wiring) shown in FIG. As in FIG. 12, the horizontal axis represents the distance from the source amplifier bias control circuit 14, and the vertical axis schematically represents the value of the bias current of the source amplifier 4. In order to cancel out the decrease in the slew rate of the source amplifier 4 from the near end to the far end and to make it almost equal, the bias current is directed from the near block (region) R1 to the far block (region) R4 in order. Set to be larger. Since the bias current set in each block (region) R1 to R4 is set for each block (region), as shown in FIG. 12, it takes the same value in the same block and becomes stepped. It becomes discontinuous at the boundary of (region). However, as shown in FIG. 13, by short-circuiting the bias line in the vicinity of the block (region) boundary, the bias current that actually flows through the source amplifier 4 can be continuous even at the block (region) boundary.

  Thereby, it is possible to prevent the slew rate of the source amplifier 4 from changing discontinuously at the block (region) boundary. There is a risk of discontinuity in luminance characteristics due to discontinuity of the slew rate of the source amplifier 4 in adjacent pixels in the line of the display panel 2 corresponding to the block (area) boundary, but this is prevented. can do.

[Embodiment 3]
FIG. 10 is a circuit diagram illustrating a configuration example of the source amplifier bias control circuit 14 according to the third embodiment. Unlike the source amplifier bias control circuit 14 shown in FIG. 9, four source amplifier bias control circuits 14_R1 each composed of reference current sources 30_R1 to 30_R4 and bias supply circuits 31_R1 to 31_R4 and corresponding to the blocks (regions) R1 to R4. To 14_R4 and registers 23_R1 to 23_R4. The source amplifier bias control circuits 14_L1 to 14_L4 and the registers 23_L1 to 23_L4 corresponding to the blocks (areas) L1 to L4 are not shown. The four source amplifier bias control circuits 14_R1 to 14_R4 are composed of the same circuit, and only 14_R1 is shown as a representative. The reference current source 30_R1 includes three current sources 300a, 300b, and 300c, three P-channel MOSFETs, MP0sa, MP0sb, and MP0sc, instead of the current source 300 of the reference current source 30 shown in FIG. Is provided. The three P-channel MOSFETs, MP0sa, MP0sb, and MP0sc function as switches, and the total current value of the current sources 300a, 300b, and 300c selected by being turned on is supplied to the bias supply circuit 31_R1 by the reference current source 30_R1 The value of the bias current of the source amplifier 4 in the block (region) R1 is defined by this reference value. In other words, the three P-channel MOSFETs, MP0sa, MP0sb, and MP0sc are on / off controlled by the value stored in the register 23_R1, and the bias current value of the source amplifier 4 in the block (region) R1 is adjusted. .

  As a result, even when the source amplifier bias control circuit 14 shown in the third embodiment is used, the bias current of the source amplifier 4 in the block (region) on the near end side from the gradation level generation circuit 13 in the source amplifier block 40 is changed. By reducing the bias current on the far end side and increasing the bias current, the slew rates of all the source amplifiers 4_1 to 4_n can be adjusted in a direction that is substantially uniform. Therefore, even when the size of the display drive circuit (display driver IC) 1 in the longitudinal direction increases, the slew rate of all the source amplifiers is adjusted to be uniform, and the luminance characteristics in the lines of the display panel are made uniform. be able to.

  The control values stored in the registers 23_R1 to 23_R4 are described as three bits only as an example, and the number of bits can be arbitrarily changed.

  Also in the third embodiment, as shown in FIG. 11, each block (region) of the source amplifier block 40 is arranged, and the bias lines BIN11 to BIN14 and BIP11 to BIP14 are wired from the source amplifier bias control circuit 14. be able to. In this case, the bias current in each source amplifier has a distribution similar to that shown in FIG. When the bias lines BIN11 to BIN14 and BIP11 to BIP14 are changed as shown in FIG. 13 from the source amplifier bias control circuit 14, the bias current in each source amplifier has a distribution similar to that shown in FIG. The same effects as those described in the second embodiment can be obtained.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the method for controlling the bias current has been described as a method for equalizing the slew rate of the source amplifier. However, the method may be changed to a method for controlling the circuit constants of the source amplifier with a switch or a method for adjusting with an analog signal. . The operational amplifier constituting the source amplifier can be changed to an operational amplifier of another circuit system, for example, a tail current source provided only in one of the P channel and the N channel.

1. Display drive circuit (display driver IC)
2 Display Panel 3 Host Processor 4 Source Amplifier 5 Gradation Level Selection Circuit 40 Source Amplifier Block 6 Line Latch 7 Frame Memory 8 Control Unit 9 Host Interface 11 Power Supply Circuit 12 Gate Control Signal Drive Circuit 13 Gradation Level Generation Circuit 14 Source Amplifier Bias Control circuit 15 Gate-in panel (GIP)
21, 22, 23 Register 30 Reference current source 300 Current source 31 Bias supply circuit 100 Electronic equipment MN0 to MN10, MN1a to MN1c, MN9a to MN9c N-channel MOSFET
MN1sa to MN1sc, MN9sa to MN9sc N-channel MOSFET (switch MOS)
MP1-MP10, MP1a-MP1c P-channel MOSFET
MP0sa to MP0sc, MP1sa to MP1sc P-channel MOSFET (switch MOS)
Tr transfer gate C pixel capacitance Cn, Cp feedback capacitance R111 to R144 Wiring resistance R1 to R4, L1 to L4 Each block (area) of the source amplifier block

Claims (20)

A plurality of source amplifiers, a plurality of gradation level selection circuits for supplying an input level to each of the source amplifiers, a gradation level generation circuit for supplying gradation levels to the gradation level selection circuit by a gradation line, A bias control circuit for adjusting a bias current of the plurality of source amplifiers,
The bias control circuit adjusts bias currents of the plurality of source amplifiers based on a wiring length of a gradation line from the gradation level generation circuit to a gradation level selection circuit corresponding to the source amplifier. Driving circuit.   The plurality of source amplifiers according to claim 1, wherein the plurality of source amplifiers are divided into a plurality of groups based on a wiring length of the gradation line, and the bias control circuit adjusts a bias current of the source amplifier for each of the groups. Display drive circuit.   3. The display drive circuit according to claim 2, wherein control lines for bias current supplied from the bias control circuit to the groups of the plurality of source amplifiers are short-circuited at the boundary between adjacent groups.   The display according to claim 1, wherein the bias control circuit forms a current mirror with the plurality of source amplifiers, and the plurality of source amplifiers can each adjust a current amplification factor of the current mirror. Driving circuit.   5. The plurality of source amplifiers according to claim 4, wherein the plurality of source amplifiers are divided into a plurality of groups based on a wiring length of the gradation line, and the bias control circuit sets a current amplification factor of the current mirror for each group. A display driver circuit having a possible register.   The bias control circuit according to claim 2, wherein the bias control circuit includes a bias supply circuit that controls a bias current of the plurality of source amplifiers for each group, and the bias current of the source amplifier can be adjusted for each group. Display drive circuit.   7. The bias control circuit according to claim 6, wherein the bias control circuit includes one reference current source and the bias supply circuit corresponding to each group, and each of the bias supply circuits is connected to the reference current source. A display driving circuit which constitutes a current mirror, and the current mirror can be adjusted in current amplification factor for each group.   7. The bias control circuit according to claim 6, wherein the bias control circuit includes the bias supply circuit corresponding to each group and a plurality of reference current sources corresponding to each group, and each of the bias supply circuits is connected to the reference current source. A display drive circuit that forms a current mirror between the reference current sources, and a current value of each of the reference current sources can be adjusted for each group.   7. The display drive circuit according to claim 6, wherein a control line for bias current supplied from the bias control circuit to each group of the plurality of source amplifiers is short-circuited at a boundary between adjacent groups.   The display drive circuit according to claim 1, formed on a single semiconductor substrate.   11. The plurality of source amplifiers and the plurality of gradation level selection circuits are arranged in a longitudinal direction of the semiconductor substrate, and the gradation level generation circuit and the bias control circuit are respectively connected to the plurality of sources. A display driving circuit arranged at an approximate center in the longitudinal direction in which an amplifier and the plurality of gradation level selection circuits are arranged. A plurality of source amplifiers, a plurality of gradation level selection circuits for supplying an input level to each of the source amplifiers, a gradation level generation circuit for supplying gradation levels to the gradation level selection circuit by a gradation line, A bias control circuit for adjusting a bias current of the plurality of source amplifiers,
The plurality of source amplifiers and the plurality of gradation level selection circuits are arranged in a longitudinal direction, the gradation lines are wired in the longitudinal direction from the gradation level generation circuit, and the plurality of gradation level generation circuits are , Connected to the gradation lines,
The bias control circuit adjusts bias currents of the plurality of source amplifiers based on a wiring length of a gradation line from the gradation level generation circuit to a gradation level selection circuit corresponding to the source amplifier. Driver IC.   13. The display according to claim 12, wherein the plurality of source amplifiers and the plurality of gradation level selection circuits are arranged in a plurality of regions, and the bias control circuit adjusts a bias current of the source amplifier for each of the regions. Driver IC.   14. The display driver IC according to claim 13, wherein a control line for bias current supplied from the bias control circuit to the source amplifier in each region is short-circuited at a boundary between adjacent regions.   13. The display according to claim 12, wherein the bias control circuit forms a current mirror with the plurality of source amplifiers, and each of the plurality of source amplifiers can adjust a current amplification factor of the current mirror. Driver IC.   16. The plurality of source amplifiers and the plurality of gradation level selection circuits according to claim 15 are arranged in a plurality of regions, and the bias control circuit can set a current amplification factor of the current mirror for each region. Display driver IC having a simple register.   14. The bias control circuit according to claim 13, wherein the bias control circuit includes a bias supply circuit that controls bias currents of the plurality of source amplifiers for each region, and the bias current of the source amplifier can be adjusted for each region. Display driver IC.   18. The bias control circuit according to claim 17, wherein the bias control circuit includes one reference current source and the bias supply circuit that supplies a bias current to a source amplifier in each region, and each of the bias supply circuits includes the reference current source. A display driver IC which forms a current mirror with a current source, and the current mirror can adjust a current amplification factor for each region.   The bias control circuit according to claim 17, wherein the bias control circuit includes a bias supply circuit that supplies a bias current to a source amplifier in each region, and a plurality of reference current sources corresponding to the bias supply circuits. A display driver IC that forms a current mirror with the reference current source, and the reference current source can have a current value adjusted for each region.   18. The display driver IC according to claim 17, wherein a control line for bias current supplied from the bias control circuit to the source amplifier in each region is short-circuited at a boundary between adjacent regions.

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