JP2015142359A - Electronic apparatus with programmable logic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic apparatus with a PLD capable of preventing rewrite of configuration data of the PLD from being disabled.SOLUTION: The electronic apparatus includes a plurality of programmable logic circuit devices 11 and 12 and a versatile bus 50. The programmable logic circuit device configures a logic circuit on the basis of circuit configuration data. The versatile bus transmits rewrite data for rewriting the circuit configuration data to each of the plurality of programmable logic circuit devices. The programmable logic circuit devices include conversion circuits 1 and 2 each for converting the rewrite data acquired from the versatile bus into a rewrite signal for rewriting into the circuit configuration data. The circuit configuration data of one programmable logic circuit device are rewritten by the rewrite signal generated by conversion circuits of other programmable logic circuit device.

Description

  The present invention relates to an electronic apparatus having a programmable logic circuit device.

  A programmable logic circuit device (hereinafter also referred to as PLD) is different from a logic circuit device that cannot be changed once a logic circuit inside the device is determined, such as ASIC (Application Specific Integrated Circuit), A logic circuit device capable of repeatedly changing a circuit.

  In recent PLDs, a user can edit a configuration of a desired logic circuit on a terminal such as a personal computer, read information on the configuration of the logic circuit as configuration data, and configure a logic circuit inside the device. It is becoming. As such PLDs, for example, CPLD (Complex Programmable Logic Device), FPGA (Field Programmable Gate Array) and the like are generally known.

  In general, configuration data read into the CPLD is stored in an internal flash memory, and the same data is maintained until it is rewritten even when the power is turned off. On the other hand, in many FPGAs, the read configuration data is stored in an internal static RAM (Random Access Memory). Therefore, when the power is turned off, the configuration data stored in the static RAM is not maintained. Usually, in such an FPGA, a flash memory for loading configuration data into an internal static RAM is often separately connected when activated.

  CPLDs and FPGAs typically include a JTAG (Joint Test Action Group) port for rewriting configuration data. The JTAG port is a standard that was originally used for inspection of integrated circuits and substrates, but in recent years it is used not only for inspection purposes but also as a means for accessing CPLDs and FPGAs such as rewriting configuration data.

  When rewriting the configuration data of the CPLD, the rewrite data is received from the outside of the board on which the CPLD is mounted, and the received rewrite data is converted into a signal for inputting to the JTAG port of the CPLD (hereinafter referred to as a JTAG signal). There is a need to. For this reason, a circuit for converting the received rewrite data into a JTAG signal (hereinafter referred to as a JTAG conversion circuit) is generally mounted on the substrate. Then, the JTAG signal generated by the JTAG conversion circuit is transmitted to the CPLD through a dedicated signal line.

  For example, Patent Document 1 below discloses a serial bus system for rewriting configuration data of a plurality of flash memories respectively connected to a plurality of FPGAs as an example using such a conventional technique. The reason why a plurality of FPGAs are used as in the technique disclosed in Patent Document 1 is as follows, for example. In recent years, large-scale PLDs have been manufactured with the advancement of semiconductor technology, but large-scale PLDs are still expensive. Therefore, when a large-scale logic circuit is configured using PLDs, This is because it is cheaper to use a plurality of small-scale PLDs.

  The serial bus system disclosed in Patent Document 1 includes a dedicated CPU (Central Processing Unit) and a dedicated FPGA for rewriting configuration data of a plurality of flash memories respectively connected to a plurality of FPGAs. The dedicated CPU receives data from an external interface through serial communication, and the dedicated FPGA functions as a JTAG conversion circuit to generate a JTAG signal based on the data, and to the JTAG ports of the plurality of FPGAs through dedicated signal lines. To transmit.

  However, in the serial bus system of Patent Document 1, since the JTAG signal is transmitted to the JTAG ports of a plurality of FPGAs through a dedicated signal line, the rewrite data transmission means is limited to one. For this reason, for example, when the JTAG signal cannot be transmitted to the JTAG ports of the plurality of FPGAs for some reason such as a failure of the JTAG conversion circuit, there is no other means for transmitting the rewrite data to the JTAG ports of the plurality of FPGAs. As a result, there is a problem that the configuration data of the plurality of FPGAs cannot be rewritten.

JP 2010-1113630 A

  The present invention has been made in view of the above problems. Accordingly, an object of the present invention is to provide an electronic device including a PLD that can prevent the configuration data of the PLD from being rewritten.

  The above object of the present invention is achieved by the following.

  (1) A plurality of programmable logic circuit devices constituting a logic circuit based on circuit configuration data, and rewrite data for rewriting the circuit configuration data for each of the plurality of programmable logic circuit devices Each programmable logic circuit device includes a conversion circuit that converts rewrite data acquired from the general-purpose bus into a rewrite signal for rewriting circuit configuration data. An electronic apparatus in which circuit configuration data of a programmable logic circuit device is rewritten by a rewrite signal generated by a conversion circuit of another programmable logic circuit device.

  (2) The system further includes a system on chip for acquiring the rewrite data and controlling the general-purpose bus, and the rewrite data from the general-purpose bus is transmitted to the plurality of programmable logic circuit devices via the system on-chip. The electronic device according to (1), wherein

  (3) A storage unit for storing the acquired rewrite data is further included, and when the circuit configuration data of the programmable logic circuit device is rewritten, the rewrite data is read from the storage unit to the system-on-chip, The electronic apparatus according to (2), wherein the rewrite data is transmitted to the programmable logic circuit device via a bus.

  (4) Rewrite data from the general-purpose bus is transmitted to the plurality of programmable logic circuit devices via an external interface connected to the general-purpose bus. Electronic equipment.

  (5) The system-on-chip further includes an order control unit that performs control for rewriting circuit configuration data of the plurality of programmable logic circuit devices in a predetermined order. The electronic device according to any one of 4).

  (6) The system-on-chip further includes a verification unit that performs verification of rewritten data written in the programmable logic circuit device, according to any one of (2) to (5), The electronic device described.

  (7) The electronic device according to any one of (1) to (6), further including a switching unit configured to connect or disconnect each programmable logic circuit device and the general-purpose bus. apparatus.

  (8) When the circuit configuration data of one programmable logic circuit device is being rewritten, the switching unit separates the other programmable logic circuit device from the general-purpose bus. ) Electronic device.

  (9) The circuit configuration for each of the first to Nth programmable logic circuit devices configuring the logic circuit based on the circuit configuration data, and the first to Nth programmable logic circuit devices. A general-purpose bus for transmitting rewrite data for rewriting data, wherein the first to Nth programmable logic circuit devices rewrite the rewrite data acquired from the general-purpose bus to rewrite circuit configuration data. A conversion circuit for converting to a rewrite signal is provided, and circuit configuration data of the nth (n <N) programmable logic circuit device is rewritten by a rewrite signal generated by the conversion circuit of the (n + 1) th programmable logic circuit device. Circuit configuration data of the Nth programmable logic circuit device is stored in the first programmable logic circuit device. Rewritten by scan rewrite signal generated by the conversion circuit of the electronic device.

  (10) The electronic apparatus according to (9), further comprising an order control unit that performs control for rewriting circuit configuration data of the first to Nth programmable logic circuit devices in a predetermined order. apparatus.

  (11) The electronic device according to (10), wherein the sequence control unit is provided in the system-on-chip.

  According to the present invention, since the rewrite data can be transmitted to the PLD via the general-purpose bus, the rewrite data transmission means is not limited to one. Therefore, it is possible to prevent the PLD circuit configuration data from being rewritten.

It is a schematic block diagram which shows the structure of the controller as an electronic apparatus provided with PLD of one Embodiment of this invention. It is a figure for demonstrating the rewriting procedure from the system on chip in one Embodiment of this invention. It is a figure following FIG. 2A. It is a figure following FIG. 2B. It is a figure for demonstrating the rewriting procedure from the external interface in one Embodiment of this invention. It is a figure following FIG. 2D. It is a figure for demonstrating the modification of one Embodiment of this invention.

  Hereinafter, an embodiment of a controller as an electronic apparatus including the PLD of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same members.

(Embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of a controller as an electronic apparatus including a PLD according to the present embodiment. As shown in FIG. 1, the controller 100 of this embodiment includes first and second CPLDs 11 and 12, a system-on-chip (hereinafter referred to as SoC) 20, a memory device 30, first and second switches 41, 42 and a general-purpose bus 50 on a predetermined board.

  In the present embodiment, a case where a CPLD is used as a programmable logic circuit device (PLD) will be described as an example. However, the configuration may be such that an FPGA is used instead of the CPLD and a flash memory is additionally provided for storing configuration data (circuit configuration data) that is information indicating the configuration of the logic circuit.

  The first and second CPLDs 11 and 12 function as a PLD and configure a user's desired logic circuit based on configuration data stored in an internal flash memory.

  In the present embodiment, the first and second CPLDs 11 and 12 convert the rewrite data (parallel data) into rewrite signals (for example, JTAG serial signals) for rewriting the CPLD configuration data. Conversion circuits 1 and 2. As will be described later, the first and second conversion circuits 1 and 2 do not rewrite the configuration data of their own CPLD in which the first and second conversion circuits 1 and 2 are configured. Used to rewrite CPLD configuration data.

  In the present embodiment, the controller 100 can be a printer controller, for example. In this case, the first and second CPLDs 11 and 12 can be provided with functions such as power control, reset control, and interrupt control, for example, according to the contents of the configuration data. Therefore, in the present embodiment, the configuration data of the first and second CPLDs 11 and 12 includes a configuration corresponding to the above function performed by each CPLD and a configuration of each of the first and second conversion circuits 1 and 2. Can be included. The rewriting of the configuration data is executed including the configuration corresponding to the function and the configurations of the first and second conversion circuits 1 and 2. Therefore, if there is no particular change in the configuration of the first and second conversion circuits 1 and 2, the configuration portion of the first and second conversion circuits 1 and 2 is rewritten to the same configuration as the previous time. .

  In the present embodiment, the first and second CPLDs 11 and 12 each include a JTAG terminal, a general-purpose input / output terminal, a general-purpose output terminal, and output terminals of the first and second conversion circuits 1 and 2. The JTAG terminal of the first CPLD 11 is connected to the output terminal of the second conversion circuit 2 of the second CPLD 12, and the JTAG terminal of the second CPLD 12 is the output terminal of the first conversion circuit 1 of the first CPLD 11. It is connected to the. The general purpose input / output terminals of the first and second CPLDs 11 and 12 are connected to the general purpose bus 50 via the first and second switches 41 and 42, respectively. The general-purpose output terminal of the first CPLD 11 is connected to the control terminal of the second switch 42, and the general-purpose output terminal of the second CPLD 12 is connected to the control terminal of the first switch 41.

  The SoC 20 controls reception of rewrite data and a general-purpose bus. The SoC 20 includes a communication interface (not shown), and receives rewrite data through a communication unit 200 such as a LAN (Local Area Network) or a USB (Universal Serial Bus). The SoC 20 includes a general-purpose bus controller (not shown). The SoC 20 is connected to the first and second CPLDs 11 and 12 via the switches 41 and 42 via the general-purpose bus 50.

  The memory device 30 stores the rewrite data received by the SoC 20 as a storage unit. The memory device 30 has a RAM and is connected to the general-purpose bus 50.

  Each of the first and second switches 41 and 42 has a control terminal, and connects or disconnects the first and second CPLDs 11 and 12 and the general-purpose bus 50 according to the state of the control terminal. Switch. The first and second switches 41 and 42 function as a switching unit.

  The general-purpose bus 50 is a bidirectional bus for connecting the first and second CPLDs 11 and 12, the SoC 20, the memory 30 and the external interface 300 to each other. In this embodiment, as will be described later, the general-purpose bus 50 is used when rewriting the CPLD configuration data. The general-purpose bus 50 transmits rewrite data for rewriting configuration data to each of the first and second CPLDs 11 and 12.

  The external interface 300 is an interface for communicating between the general-purpose bus 50 and a module outside the controller 100. The controller 100 of this embodiment can communicate with the external interface 300 without going through the SoC 20. The external interface 300 is connected when rewriting the configuration data of the first and second CPLDs 11 and 12, and may not be connected at other times.

  Next, rewriting of CPLD configuration data in the controller of the present embodiment will be described with reference to FIGS. 2A to 2E. 2A to 2C are diagrams for explaining a rewriting procedure from the SoC in the present embodiment, and FIGS. 2D and 2E are diagrams for explaining a rewriting procedure from the external interface in the present embodiment. In the present embodiment, there are two methods: a method of rewriting data by inputting rewrite data from the SoC 20 and a method of rewriting data by inputting rewrite data from the external interface 300.

<Rewrite procedure from SoC>
First, rewriting from the SoC 20 will be described. As shown in FIG. 2A, the SoC 20 receives rewrite data from the communication unit 200 (LAN, USB, etc.). The memory device 30 stores the rewrite data (see “memory access route” indicated by a broken line). In the present embodiment, the rewrite data of the first and second CPLDs 11 and 12 are received and stored in the memory device 30. After receiving the rewrite data, rewriting of the configuration data is started.

  When rewriting the configuration data of the second CPLD 12, as shown in FIG. 2B, the rewrite data is read from the memory device 30 to the first CPLD 11 via the general-purpose bus 50 while reading the rewrite data of the second CPLD 12 to the SoC 20. Send. At that time, the second CPLD 12 turns on the first switch 41 and the first CPLD 11 turns off the second switch 42 (“memory access route” and “second CPLD rewrite route shown by broken lines”). ). The reason why the second switch 42 is turned off is that the general-purpose input / output terminal is indefinite while the configuration data of the second CPLD 12 is rewritten.

  Next, after the transmission of the rewrite data of the second CPLD 12 is completed, the SoC 20 performs a read process of the rewrite data of the second CPLD 12 from the first CPLD 11 via the general-purpose bus 50. The SoC 20 functions as a verification unit, and verifies the rewritten data of the second CPLD 12 using the rewritten data read from the memory device 30 to the SoC 20 (hereinafter referred to as “verify”). As a result of the verification, when the rewritten data includes an error, a measure such as retransmission of the rewritten data is taken. The first CPLD 11 keeps the second switch 42 off (see “second CPLD rewrite route” indicated by a broken line).

  Next, as shown in FIG. 2C, after the SoC 20 completes the verification of the rewrite data of the second CPLD 12, the first CPLD 11 turns on the second switch. The rewrite data is transmitted to the second CPLD 12 via the general-purpose bus 50 while reading the rewrite data of the first CPLD 11 from the memory device 30 to the SoC 20. At that time, the second CPLD 12 turns off the first switch 41 (see “memory access route” and “first CPLD rewrite route” indicated by broken lines).

  Next, after completing the transmission of the rewrite data of the first CPLD 11, the SoC 20 performs a read process of the rewrite data of the first CPLD 11 from the second CPLD 12 via the general-purpose bus 50. The SoC 20 performs verification of the rewrite data of the first CPLD 11 by using the rewrite data read from the memory device 30 to the SoC 20. The second CPLD 12 keeps the first switch 41 off (see “first CPLD rewrite route” indicated by a broken line). After the SoC 20 completes the verification of the rewrite data of the first CPLD 11, the second CPLD 12 turns on the first switch 41. And the rewriting from SoC20 is complete | finished.

<Rewrite procedure from external interface>
Next, rewriting from the external interface 300 will be described. As shown in FIG. 2D, when rewriting the configuration data of the second CPLD 12, the external interface 300 transmits the rewrite data of the second CPLD 12 to the first CPLD 11 via the general-purpose bus 50. At this time, the second CPLD 12 turns on the first switch 41, and the first CPLD 11 turns off the second switch 42 (see “second CPLD rewrite route” indicated by a broken line). .

  Next, as shown in FIG. 2E, when the configuration data of the first CPLD 11 is rewritten, the first CPLD 11 turns on the second switch 42 after receiving the rewrite data of the second CPLD 12. The external interface 300 continues to transmit the rewrite data of the first CPLD 11 to the second CPLD 12 via the general-purpose bus 50. At that time, the second CPLD 12 turns off the first switch 41 (see “first CPLD rewrite route” indicated by a broken line). The second CPLD 12 turns on the first switch 41 after receiving the rewrite data of the first CPLD 11. Then, rewriting from the external interface 300 ends.

  In the present embodiment, since the verify function is not provided in the external interface 300, the rewrite data is not verified after the rewrite from the external interface 300. However, the external interface 300 may have a verify function. In this case, the rewritten data can be verified.

  As described above, in this embodiment, rewrite data of one PLD is transmitted to another PLD via the general-purpose bus 50, and the rewrite data is converted into a rewrite signal by a conversion circuit configured in the other PLD. Rewrite the configuration data of the above one PLD.

  Therefore, according to the controller 100 of the present embodiment, the rewrite data can be transmitted to the first and second CPLDs 11 and 12 via the general-purpose bus 50, so the rewrite data transmission means is not limited to one. That is, since the versatility of transmission of rewrite data is improved, it is possible to prevent the CPLD configuration data from being rewritten.

  Further, it is not necessary to provide a dedicated PLD and a dedicated CPU for rewriting configuration data, and the number of pins of the SoC 20 can be reduced as compared with a case where a dedicated PLD and a dedicated CPU are provided.

<Modification>
Next, with reference to FIG. 3, the modification of one Embodiment of this invention is shown. FIG. 3 is a diagram for explaining a modification of the controller in the present embodiment. The controller of this modification is different from the above-described controller in that it includes first to Nth CPLDs and first to Nth switches. The general-purpose bus transmits rewrite data for rewriting configuration data to each of the first to Nth CPLDs.

  The first to Nth CPLDs include first to nth conversion circuits that convert the rewrite data received from the general-purpose bus into rewrite signals for rewriting configuration data.

  The SoC (not shown) includes an order control unit that performs control for rewriting the configuration data of the first to Nth CPLDs in a desired order. The first CPLD has its configuration data rewritten by the rewrite signal generated by the second conversion circuit of the second CPLD, and the second CPLD has the rewrite signal generated by the third conversion circuit of the third CPLD. To rewrite the configuration data. The configuration data of the nth (n <N) CPLD is rewritten by the rewrite signal generated by the (n + 1) th conversion circuit of the (n + 1) th CPLD. The configuration data of the Nth CPLD is rewritten by a rewrite signal generated by the first conversion circuit of the first CPLD.

  As described above, in the embodiment, the electronic device including the PLD of the present invention has been described. However, it goes without saying that the present invention can be appropriately added, modified, and omitted by those skilled in the art within the scope of the technical idea.

  For example, in the above-described embodiment, the printer controller has been described as an example of the electronic device including the PLD. However, the electronic device including the PLD of the present invention is not limited to the printer controller, and can be applied to various electronic devices including the PLD.

1 1st conversion circuit,
2 second conversion circuit;
11 first CPLD,
12 second CPLD,
20 SoC,
30 memory devices,
41 first switch,
41 second switch,
50 General-purpose bus,
100 controllers,
200 Communication Department,
300 External interface.

Claims (11)

A plurality of programmable logic circuit devices that configure the logic circuit based on the circuit configuration data;
A general-purpose bus for transmitting rewrite data for rewriting the circuit configuration data to each of the plurality of programmable logic circuit devices;
Each of the programmable logic device is
A conversion circuit that converts rewrite data acquired from the general-purpose bus into a rewrite signal for rewriting circuit configuration data,
An electronic apparatus in which circuit configuration data of one programmable logic circuit device is rewritten by a rewrite signal generated by a conversion circuit of another programmable logic circuit device. Further comprising a system-on-chip for acquiring the rewrite data and controlling the general-purpose bus;
2. The electronic apparatus according to claim 1, wherein the rewrite data from the general-purpose bus is transmitted to the plurality of programmable logic circuit devices via the system-on-chip. A storage unit for storing the acquired rewrite data;
When rewriting the circuit configuration data of the programmable logic circuit device, the rewrite data is transmitted to the programmable logic circuit device via the general-purpose bus while reading the rewrite data from the storage unit to the system-on-chip. The electronic device according to claim 2. The rewrite data from the general-purpose bus is
The electronic apparatus according to claim 1, wherein the electronic apparatus is transmitted to the plurality of programmable logic circuit devices via an external interface connected to the general-purpose bus. The system on chip is:
5. The electronic apparatus according to claim 2, further comprising an order control unit that performs control to rewrite circuit configuration data of the plurality of programmable logic circuit devices in a predetermined order. 6. . The system on chip is:
The electronic apparatus according to claim 2, further comprising a verification unit configured to verify rewritten data written in the programmable logic circuit device.   The electronic apparatus according to claim 1, further comprising a switching unit that connects or disconnects each of the programmable logic circuit devices and the general-purpose bus. The switching unit is
8. The electronic apparatus according to claim 7, wherein when the circuit configuration data of one programmable logic circuit device is rewritten, the other programmable logic circuit device is separated from the general-purpose bus. First to Nth programmable logic circuit devices that configure a logic circuit based on circuit configuration data;
A general-purpose bus for transmitting rewrite data for rewriting the circuit configuration data to each of the first to Nth programmable logic circuit devices;
The first to Nth programmable logic circuit devices are:
A conversion circuit that converts rewrite data acquired from the general-purpose bus into a rewrite signal for rewriting circuit configuration data,
The circuit configuration data of the nth (n <N) programmable logic circuit device is:
Rewritten by a rewrite signal generated by the conversion circuit of the (n + 1) th programmable logic circuit device;
The circuit configuration data of the Nth programmable logic circuit device is:
An electronic device rewritten by a rewrite signal generated by a conversion circuit of a first programmable logic circuit device.   The electronic apparatus according to claim 9, further comprising an order control unit that performs control for rewriting circuit configuration data of the first to Nth programmable logic circuit devices in a predetermined order.   The electronic device according to claim 10, wherein the sequence control unit is provided in the system-on-chip.