JP2015135933A - Multilayer wiring board and manufacturing method thereof - Google Patents

Multilayer wiring board and manufacturing method thereof Download PDF

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JP2015135933A
JP2015135933A JP2014018895A JP2014018895A JP2015135933A JP 2015135933 A JP2015135933 A JP 2015135933A JP 2014018895 A JP2014018895 A JP 2014018895A JP 2014018895 A JP2014018895 A JP 2014018895A JP 2015135933 A JP2015135933 A JP 2015135933A
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wiring board
multilayer wiring
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conduction path
electrical conduction
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英徳 林田
Hidenori Hayashida
英徳 林田
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Abstract

PROBLEM TO BE SOLVED: To solve the problem that, in an inorganic multilayer board, circuit disconnection and insulation layer breakage or warpage may also easily occur in addition to a conduction defect of upper and lower conductive layers and it is necessary to remedy a high defect rate that may reach 30 to 40%.SOLUTION: A multilayer wiring board has a structure where conductive layers 1 are electrically connected with each other by an electrical conduction path 4 embedded into an insulation layer 3 that is positioned on the conductive layer 1, deeply to the side face thereof and penetrating the insulation layer 3 held between the upper and lower conductive layers 1. The three-dimensional structure of the multilayer wiring board is divided into thin layers by horizontal cross sections to generate 3D data. The multilayer wiring board is formed by printing, hardening and laminating the thin layers by a 3D printer using the 3D data. The electrical connection between the electrical conduction path 4 penetrating the insulation layer 3 and the conductive layer positioned at an upper side of the upper and lower positioning conductive layers 1 is formed by projecting the electrical conduction path 4 higher than a surface of the insulation layer 3 and bonding a protruding part of the electrical conduction path 4 while covering it with the conductive layer positioned at the upper side.

Description

本発明は多層配線板とその製造方法に係わり、更に詳しくは、3Dプリンターを使用して製造した多層配線板とその製造方法に関するものである。  The present invention relates to a multilayer wiring board and a manufacturing method thereof, and more particularly to a multilayer wiring board manufactured using a 3D printer and a manufacturing method thereof.

従来の多層配線板の種類として有機系(MLPCB)、無機系(LTCC)、及び有機系と無機系を混合したハイブリッド系がある。
これら従来の多層配線板は、いずれも大量生産方式であり、使用する設備等に多額の投資が必要である上に、更に、その製造工程は複雑で、高度な技術を必要とし、高価な薬品を使用する必要があった。そのために、製造コストが極めて高くなり、大量生産方式でしか、製造コストを低減できない根源的な問題点を内包している。
従って試作や少量生産にはコスト的に適用できない生産方式である。
Conventional types of multilayer wiring boards include organic (MLPCB), inorganic (LTCC), and hybrid systems in which organic and inorganic systems are mixed.
These conventional multilayer wiring boards are all mass-produced, and require a large investment in the equipment to be used. Furthermore, the manufacturing process is complicated, requires advanced technology, and is expensive. Had to be used. For this reason, the manufacturing cost becomes extremely high, and the fundamental problem that the manufacturing cost can be reduced only by the mass production method is included.
Therefore, this is a production method that cannot be applied to trial production and small-scale production.

従来の作製工程は、無機系、有機系、いずれにも共通して、絶縁層の形成、絶縁層表面に導電層形成、導電層に対するフォトリソ、エッチングによる配線回路形成、上下の配線回路を電気的に導通させるために、この絶縁層表面から下の配線回路まで、直径数十μmの極微細穴を明け、この穴にメッキ等の方法で導電体を充填して下の配線回路と電気的に導通させる方法であるので、下の配線回路と穴に充填した導電体を完全に電気的に接続させるのは極めて難しい方法である。
このため上下の導電層の導通不良による不良率は、10%にも達する。特に無機系多層基板では、上下の導電層の導通不良のほか、回路の断線、絶縁層のワレやソリも発生しやすく、不良率が30〜40%にも達している。
Conventional manufacturing processes are common to both inorganic and organic systems. Formation of an insulating layer, formation of a conductive layer on the surface of the insulating layer, photolithography for the conductive layer, wiring circuit formation by etching, and upper and lower wiring circuits are electrically connected In order to make it conductive, an extremely fine hole with a diameter of several tens of μm is formed from the surface of the insulating layer to the lower wiring circuit, and a conductive material is filled in the hole by a method such as plating to electrically connect with the lower wiring circuit. Since it is a conduction method, it is extremely difficult to completely electrically connect the lower wiring circuit and the conductor filled in the hole.
For this reason, the failure rate due to conduction failure between the upper and lower conductive layers reaches 10%. In particular, in the inorganic multilayer substrate, in addition to the conduction failure of the upper and lower conductive layers, circuit disconnection, cracking and warping of the insulating layer are likely to occur, and the defect rate reaches 30 to 40%.

また更に従来の製造工程は、前記したいずれの工程も、薬剤や副資材、水等を多量消費するために、地球環境保護の観点からも早急に改善すべき問題点を有している。  Furthermore, the conventional manufacturing process has a problem that should be improved immediately from the viewpoint of protecting the global environment because any of the above-described processes consumes a large amount of chemicals, auxiliary materials, water, and the like.

また更に製作に1〜3か月を要し、結果的には製作費が高価になり、日本では国際競争力が無くなり、生産会社の海外移転や、海外外注の原因になっている。  Furthermore, it takes 1 to 3 months for production. As a result, the production cost becomes high, and international competitiveness is lost in Japan, causing production companies to move overseas and outsource.

一方、従来の複雑な作製方法を改良すべく、工程を簡略化、短縮化した方法も開発されたが、現在に至るまで大幅な普及には至っていない。
その代表的なものとして、パナソニック社のALIVH(特許文献1)、大日本印刷社のB2it(特許文献2)等がある。
これらの手法は、絶縁層と配線回路を一層ずつ積み上げ、その都度、絶縁層を挟む上下の配線回路間で電気的導通を取るために、各絶縁層毎に、レーザー加工や感光性樹脂を用いるフォトリソ法等で、直径100μm程度の穴を明ける方法である。
これらの手法は、一層ずつを積み上げて、その都度、ビィア(貫通孔)を形成し、メッキや導電性ペーストで電気的導通を取り、回路形成を行ってゆくため、層数が増えれば、増えるほど、リードタイムや作製コストがかかり、不良率もより高くなる欠点があり、普及しなかった。
On the other hand, in order to improve the conventional complicated manufacturing method, a method in which the process is simplified and shortened has been developed. However, it has not yet been widely spread.
Representative examples include ALIVH (Patent Document 1) of Panasonic Corporation and B2it (Patent Document 2) of Dai Nippon Printing Co., Ltd.
In these methods, an insulating layer and a wiring circuit are stacked one layer at a time, and each time an insulating layer is sandwiched between the upper and lower wiring circuits, laser processing or photosensitive resin is used for each insulating layer. In this method, a hole having a diameter of about 100 μm is formed by a photolithography method or the like.
These methods are stacked one by one, and each time a via (through hole) is formed, electrical conduction is achieved with plating or conductive paste, and circuit formation is performed, so the number of layers increases as the number of layers increases However, it has the disadvantages of increasing the lead time and manufacturing cost, and increasing the defect rate, and it has not spread.

特開2013−89745JP2013-89745A 特開2010−67835JP 2010-67835 A

本発明はかかる問題点に鑑みてなされたもので、その目的は、多層配線板において、多品種少量生産でも、短期間で安価に製造でき、かつ配線回路の断線、上下の絶縁層間の導通不良等の問題を解決して不良率を大幅に低減できる多層配線板の新規な構造とその製造方法を提供することにある。  The present invention has been made in view of such problems, and its purpose is to produce a multilayer wiring board at a low cost in a short period of time even in low-volume production of various products, and disconnection of a wiring circuit, poor conduction between upper and lower insulating layers. It is an object of the present invention to provide a novel structure of a multilayer wiring board and a method for manufacturing the same that can solve the above-mentioned problems and greatly reduce the defect rate.

本発明者は、上記課題に関して鋭意研究を行い、従来の多層基板の製法、すなわちエッチングによる回路形成、フォトリソ、穴あけ、穴埋め等の手法は用いずに、直接、3Dプリンターで多層基板を製造することを試みた結果、下記の知見を得た。
すなわち、微細な回路や突起やパッドが従来のフォトリソ法で製作されたものと同程度の正確さで出来ること、たとえばラインとラインの間、R/Sは10μm程度の精度が得られ、かつ回路薄層や絶縁薄層の積層と同時に硬化、焼結できることが判った。そして更に、従来の製法と同等以上の性能を備えた多層基板を製造でき、更に従来製法の最大の欠点であった製品不良率の高さを劇的に改良できることが判った。
本発明は以上の知見を基になされたものであり、本発明の上記課題は、下記の手段で解決することが出来る。
なお本明細書で導電層とは、配線回路、および配線回路と電気的に連結されたパッドおよびバンプ等を意味するものである。
The present inventor conducts earnest research on the above-mentioned problems, and directly manufactures a multilayer substrate with a 3D printer without using a conventional multilayer substrate manufacturing method, i.e., circuit formation by etching, photolithography, drilling, hole filling, etc. As a result, the following knowledge was obtained.
That is, fine circuits, protrusions and pads can be made with the same accuracy as those manufactured by the conventional photolithography method. For example, R / S can be obtained with an accuracy of about 10 μm between lines, and the circuit It was found that it can be cured and sintered simultaneously with the lamination of thin layers and insulating thin layers. Furthermore, it was found that a multilayer substrate having performance equal to or better than that of the conventional manufacturing method can be manufactured, and further, the high product defect rate, which was the biggest drawback of the conventional manufacturing method, can be dramatically improved.
This invention is made | formed based on the above knowledge, The said subject of this invention can be solved by the following means.
In this specification, the conductive layer means a wiring circuit, pads and bumps electrically connected to the wiring circuit, and the like.

すなわち、
導電層と絶縁層が、複数層、交互に積層、接合されて形成されてなる多層配線板であって、該導電層は、該導電層の上に位置する絶縁層に側面まで埋入されてなると共に、上下に位置する導電層は、該上下の導電層に挟まれた絶縁層を貫通する電気的導通路で、互いに電気的に接続されてなる構造の多層配線板であって、
該多層配線板の立体構造を水平断面で薄層に分割して3Dデータ化して、該3Dデータを用いて、該薄層を3Dプリンターで印刷、硬化、積層させて形成することで、
従来の製作方法と比べて、エッチングによる回路形成、フォトリソソグラフィ、穴あけ、穴埋め等の工程が省略でき、しかも短期間に製品を製造できる。また高価な設備、高度な技術、高純度の薬品、部材が不要で、内部配線密度も従来の数倍の密度のものが製作でき、積層する層数も10〜50層の超多層のプリント配線板(MLPCB)が製作できることを見出した。
That is,
A multilayer wiring board in which a conductive layer and an insulating layer are formed by alternately laminating and bonding a plurality of layers, and the conductive layer is embedded in the insulating layer located on the conductive layer to the side surface. The upper and lower conductive layers are multi-layer wiring boards having a structure in which they are electrically connected to each other through an electrical conduction path that penetrates the insulating layer sandwiched between the upper and lower conductive layers,
The three-dimensional structure of the multilayer wiring board is divided into thin layers in a horizontal section to form 3D data, and using the 3D data, the thin layer is printed, cured, and laminated by a 3D printer,
Compared with conventional manufacturing methods, processes such as circuit formation by etching, photolithography, drilling, and hole filling can be omitted, and a product can be manufactured in a short time. In addition, expensive equipment, advanced technology, high-purity chemicals, and materials are not required, and the internal wiring density can be several times higher than the conventional density, and the number of layers to be stacked is super multi-layer printed wiring with 10 to 50 layers. It has been found that a board (MLPCB) can be produced.

そして、更に、前記絶縁層を貫通する電気的導通路と、前記上下に位置する導電層の上位に位置する導電層との電気的接続は、該電気的導通路を、該絶縁層表面よりも上に突出させ、該電気的導通路の突出部を、該上位に位置する導電層で包覆して接合してなる構造にすることで、
導電層と電気的導通路の接触不良に伴う電気的導通不良が原因の不良率を著しく低減させることが出来ることを見出した。
そして更に、前記電気的導通路と、前記上下に位置する導電層の下位に位置する導電層との電気的接続は、該電気的導通路を、導電層表面に直接印刷して、硬化させることで、強度の高い接合がなされ、確実に電気的接続が達成できる。
従って本発明の電気的導通路の上下端は、前記した構造によって上下の導電層と信頼性の高い電気的接続が達成でき、電気的導通不良が原因の不良率を著しく低減させることが出来ることを見出した。
Further, the electrical connection between the electrical conduction path penetrating the insulating layer and the conductive layer located above the conductive layer located above and below is such that the electrical conduction path is closer to the surface of the insulation layer. By projecting upward, the projecting portion of the electrical conduction path is covered with the conductive layer positioned above and joined to form a structure,
It has been found that the failure rate due to poor electrical conduction due to poor contact between the conductive layer and the electrical conduction path can be significantly reduced.
Furthermore, the electrical connection between the electrical conduction path and the conductive layer located below the conductive layer located above and below is performed by printing the electrical conduction path directly on the surface of the conductive layer and curing it. As a result, high-strength bonding is achieved, and electrical connection can be reliably achieved.
Therefore, the upper and lower ends of the electrical conduction path of the present invention can achieve a reliable electrical connection with the upper and lower conductive layers by the above-described structure, and can significantly reduce the failure rate due to electrical conduction failure. I found.

そして、前記導電層と、導電層を挟む上下二層の上の絶縁層と、上の絶縁層を貫通する電気的導通路を形成するに際して、前記導電層と電気的導通路を先に硬化させて、強度を発現させた後に、上の絶縁層を硬化させることで、絶縁層のインキの硬化時の収縮ストレス等で、電気的導通路に亀裂等が発生して導通不良が発生する確率も極めて低くなり、上下の配線回路間の電気的導通不良や配線回路の断線が原因の不良率を著しく低減させることが出来ることを見出した。
本発明は以上の知見を元になされたものである。
Then, when forming the conductive layer, the insulating layer on the upper and lower layers sandwiching the conductive layer, and the electric conduction path penetrating the upper insulating layer, the conductive layer and the electric conduction path are first cured. In addition, after the strength is developed, the upper insulating layer is cured, so that there is a possibility that a crack or the like occurs in the electrical conduction path due to shrinkage stress at the time of curing of the ink of the insulating layer and a conduction failure occurs. It has been found that the failure rate can be significantly reduced and the failure rate due to poor electrical continuity between the upper and lower wiring circuits and the disconnection of the wiring circuits can be significantly reduced.
The present invention has been made based on the above findings.

なお前記電気的導通路の下部は導電層の上に印刷して形成するが、電気的導通路と導電層の硬化順序は、同時であっても良いし、あるいは電気的導通路が先、あるいは導電層が先、いずれでもよい。硬化の順番が原因で導電層および電気的導通路に欠陥が発生することはない。  The lower part of the electrical conduction path is formed by printing on the conductive layer, but the curing sequence of the electrical conduction path and the conductive layer may be simultaneous, or the electrical conduction path is first, or The conductive layer may be either first. Defects do not occur in the conductive layer and the electrical conduction path due to the order of curing.

本明細書請求項2の「包覆」とは、電気的導通路の、少なくとも突出した先端面を導電層が包んで被覆する状態を意味するものである。従って突出した電気的導通路の側面は、全周あるいは一部が電気的導通路に接触して接合されることになる。また電気的導通路の突出端面は、導電層で包まれて被覆されるので、電気的導通路を絶縁層から突出させる高さは、必然的に導電層の高さ未満の高さに制限されることになる。  The term “covering” in claim 2 of the present specification means a state in which the conductive layer wraps and covers at least the protruding end surface of the electrical conduction path. Therefore, the side surface of the protruding electrical conduction path is joined in contact with the entire circumference or part of the electrical conduction path. In addition, since the protruding end surface of the electrical conduction path is wrapped and covered with the conductive layer, the height at which the electrical conduction path protrudes from the insulating layer is necessarily limited to a height less than the height of the conductive layer. Will be.

本明細書において、「硬化」とは、本発明多層配線板の製造に使用する印刷用インキが有機材料、無機材料を問わず、また硬化手段を問わず、たとえば加熱硬化、反応硬化、光硬化、焼結硬化、その他の硬化手段を問わず、硬化させて強度と接合性を発現させることを意味するものである。従って有機材料の接着、無機材料の焼結、いずれをも包含するものである。  In this specification, “curing” means that the printing ink used for the production of the multilayer wiring board of the present invention is an organic material, an inorganic material, and a curing means, for example, heat curing, reaction curing, photocuring. It means that the resin is cured to exhibit strength and bondability regardless of whether it is sintered and cured or other curing means. Therefore, it includes both adhesion of organic materials and sintering of inorganic materials.

本発明方法を実施するためには、先ず多層配線板の配線やパッドの設計情報を3D−CADに取り込み、この多層配線板の立体構造を水平断面で薄層に分割して3Dデータ化して、この3Dデータを用いて、薄層を3Dプリンターで印刷、硬化、積層して3次元積層構造を形成する。  In order to carry out the method of the present invention, first, the design information of the wiring and pads of the multilayer wiring board is taken into 3D-CAD, the three-dimensional structure of this multilayer wiring board is divided into thin layers in a horizontal section, and converted into 3D data, Using this 3D data, a thin layer is printed, cured and laminated by a 3D printer to form a three-dimensional laminated structure.

3Dプリンターで印刷して積層する1層当たりの薄層厚さには特別な制約はないが、薄いほど多層基板を軽薄にできるので、絶縁性と導電性に支障がなければ、より薄い方が好ましい。
絶縁層では、たとえばエポキシ樹脂では20〜100μm程度である。
導電層では、2〜100μm程度である。
There are no special restrictions on the thickness of each layer that is printed and stacked with a 3D printer, but the thinner the multilayer substrate, the thinner the thinner, so long as there is no problem with insulation and conductivity. preferable.
In the insulating layer, for example, an epoxy resin has a thickness of about 20 to 100 μm.
In a conductive layer, it is about 2-100 micrometers.

電気的導通路の形状に特別な制約はないが、突起状の形状が最も好適である。
突起は中空形状、中実形状、いずれでも構わないが、中実形状が印刷によって最も作りやすい形状である。
There is no particular restriction on the shape of the electrical conduction path, but a protruding shape is most preferable.
The protrusion may be a hollow shape or a solid shape, but the solid shape is the most easily formed by printing.

多層基板の製造を始めるときのスタート材の選択に特別な制約はない。
銅張樹脂基板を用いても良いし、あるいは通常の樹脂基板を使用しても良い。
あるいはスタート材は使用せずに、最初から3Dブリンターを用いてスタートしても良い。
There are no particular restrictions on the choice of starting material when starting production of a multilayer substrate.
A copper-clad resin substrate may be used, or a normal resin substrate may be used.
Or you may start using a 3D printer from the beginning, without using a starting material.

銅張樹脂基板を使用する時は、先ず最初は、銅層をエッチングして配線回路(本発明では導電層と表示)を形成する。
配線回路の表面に、上層との導通用の電気的導通路を3Dプリンター用のインクを用いて印刷する。
通常の樹脂基板を使用する時は、樹脂基板に配線回路を、そして配線回路の上に、上層との導通用の電気的導通路を3Dプリンター用のインクを用いて印刷する。
When using a copper-clad resin substrate, first, the copper layer is etched to form a wiring circuit (in the present invention, indicated as a conductive layer).
An electrical conduction path for conduction with the upper layer is printed on the surface of the wiring circuit using ink for a 3D printer.
When a normal resin substrate is used, a wiring circuit is printed on the resin substrate, and an electrical conduction path for conduction with the upper layer is printed on the wiring circuit using ink for a 3D printer.

印刷した電気的導通路や配線回路は、レーザー等を用いて局所照射して、加熱硬化させる。
次に、配線回路を包み隠すように絶縁用の樹脂を印刷する。
絶縁用樹脂の印刷厚さは、配線回路の厚さを越える厚さにして配線回路を絶縁用樹脂の中に埋入し、かつ電気的導通路の高さ未満にして、電気的導通路の先端が絶縁層から突出するようにする。そして突出高さは、配線回路の厚さ未満の高さにする。
The printed electrical conduction path and wiring circuit are locally irradiated using a laser or the like, and are cured by heating.
Next, an insulating resin is printed so as to cover the wiring circuit.
The printed thickness of the insulating resin should be greater than the thickness of the wiring circuit so that the wiring circuit is embedded in the insulating resin and less than the height of the electrical conduction path. The tip should protrude from the insulating layer. The protruding height is set to a height less than the thickness of the wiring circuit.

3Dプリンターの印刷方法に特別な制約はない。いかなる印刷法でも適宜選択できる。たとえばインクジェット法、プロジェクション法、熱溶融積層法、粉末焼成法、光造形法を適宜選択できる。  There are no particular restrictions on the printing method of the 3D printer. Any printing method can be selected as appropriate. For example, an ink jet method, a projection method, a hot melt lamination method, a powder firing method, and an optical modeling method can be appropriately selected.

次にレーザー照射等を行って、エポキシ樹脂を硬化させる。  Next, laser irradiation or the like is performed to cure the epoxy resin.

次に前述と同様に、絶縁層に、配線回路および上層との導通用の電気的導通路を形成する。  Next, in the same manner as described above, an electrical conduction path for conduction between the wiring circuit and the upper layer is formed in the insulating layer.

配線回路と電気的導通路のみにレーザー照射等により導通用のインクを焼き付ける。
以後の工程は、前記した同じ工程を繰り返して、逐次積層してゆく。
Conductive ink is baked on the wiring circuit and the electrical conduction path only by laser irradiation or the like.
In the subsequent steps, the same steps described above are repeated, and the layers are sequentially stacked.

絶縁層の最表面には、ワイヤーボンディング(W/B)用のパッドや面実装用(SMD)のパッドやフリップチップ実装用のバンプ(突起)を作成し、その後メッキを行う。なお本明細書では、これらパッドやバンプはいずれも導電層と表現している。  On the outermost surface of the insulating layer, a wire bonding (W / B) pad, a surface mounting (SMD) pad, and a flip chip mounting bump (protrusion) are formed, and then plated. In this specification, these pads and bumps are all expressed as conductive layers.

従来技術では、配線と配線の幅(R/S)は100μm以下では製作上困難であった。本発明ではR/Sが10μm以下でも作成可能であり、高密度の配線板を製作できる。  In the prior art, it was difficult to manufacture wiring and wiring width (R / S) of 100 μm or less. In the present invention, it can be produced even if R / S is 10 μm or less, and a high-density wiring board can be produced.

又本発明では、重要な技術は3Dプリンターで配線回路や電気的導通路、および絶縁層を容易に印刷できることが重要であり、そのためにはインクの組成が極めて重要になる。  In the present invention, an important technique is that a 3D printer can easily print a wiring circuit, an electrical conduction path, and an insulating layer, and for this purpose, the composition of the ink is extremely important.

必要条件として、絶縁用樹脂(インク)と導通用の樹脂(インク)との接着力が強いこと、かつまた導通用のインクは、レーザー等の加熱硬化後、電気導電性が高いことである。
導通用のインキとして最も好ましいものは、Sn−Ag−Cuのサブミクロンから2〜3μmの粒径のものを、セルロース系の増粘剤(ベヒクル)混合して、練り合わせたものが好ましい。
レーザー加熱後、完全燃焼し、カーボンやその他の有機物の残渣が残らないような配合にする必要がある。
又印刷性も重要であり、本発明では3Dプリンターで印刷した配線回路の精度は幅2〜10μm、回路断面は直方体に印刷できる。ちなみに従来法のスクリーン印刷法やフォトリソ−エッチング法での断面は、台形状や逆台形、オーバーハング状、キノコ状になるために断線等の重大な事故を引き起こしている。
As a necessary condition, the adhesive strength between the insulating resin (ink) and the conductive resin (ink) is strong, and the conductive ink has high electrical conductivity after heat curing with a laser or the like.
The most preferable ink for conduction is preferably a mixture of Sn-Ag-Cu submicron particles having a particle size of 2 to 3 μm mixed with a cellulose-based thickener (vehicle) and kneaded.
After laser heating, it is necessary to formulate it so that it burns completely and no carbon or other organic residue remains.
Printability is also important. In the present invention, the accuracy of the wiring circuit printed by the 3D printer is 2 to 10 μm in width, and the circuit cross section can be printed in a rectangular parallelepiped. Incidentally, the cross section of the conventional screen printing method or photolithographic etching method has a trapezoidal shape, an inverted trapezoidal shape, an overhang shape, or a mushroom shape, causing a serious accident such as disconnection.

配線板の回路および上下層間の電気的導通路に用いる金属材料として、Cu,Ag,Sn、Au,Pt,Pd,Ni,W,Mo,Mn,Bi,Pb,Al,In,Sb,Ti,Co、Cr等の金属の単体及びこれらの2種以上の合金より適宜選択出来る。  As a metal material used for the circuit of the wiring board and the electrical conduction path between the upper and lower layers, Cu, Ag, Sn, Au, Pt, Pd, Ni, W, Mo, Mn, Bi, Pb, Al, In, Sb, Ti, It can be appropriately selected from simple metals such as Co and Cr and two or more kinds of these alloys.

導電性インキの選択の基本は、どういう機能、特性を有する基板を作成するかによって決定される。
たとえばPCB(樹脂製プリント基板)の場合、樹脂の耐熱性等の関係上あまり高融点のものは好ましくない。
こんにちは局所的にレーザー照射の技術が開発され、従来のように全体的に加熱する方法に比べると使用できる金属粉末の種類は多くなった。
これらの金属の微粉を吹付け、レーザーで融解、焼結する方法も可能であるが、好ましいのは、これらの金属の微粉をいくつかの薬品と混合して、3Dプリンターで印刷しやすい形態に加工する方法が好ましい。
従来のスクリーン印刷で用いられているクリーム半田の技術を改良して、インクジェット法で印刷することにより導電層(配線回路、パッド、バンプ)や電気的導通路を形成できる。
The basis for selecting the conductive ink is determined by the function and characteristics of the substrate to be created.
For example, in the case of a PCB (resin printed circuit board), a resin having a very high melting point is not preferable due to the heat resistance of the resin.
Hi, laser irradiation technology has been developed locally, and the number of types of metal powder that can be used is increased compared to the conventional heating method.
Although these metal fine powders can be sprayed, melted and sintered by laser, it is preferable to mix these metal fine powders with some chemicals to make it easy to print with a 3D printer. A processing method is preferred.
Conductive layers (wiring circuits, pads, bumps) and electrical conduction paths can be formed by improving the cream solder technology used in conventional screen printing and printing by the ink jet method.

セラミックス配線板に用いる導電性インクは、LTCCの場合は、Cu,Ag,Ni、Co、Ag−Pdペーストインキが好ましい。
高温焼成タイプのHTCCは、W,Mo−Mnペーストインキが好ましい。
In the case of LTCC, the conductive ink used for the ceramic wiring board is preferably Cu, Ag, Ni, Co, or Ag—Pd paste ink.
The high-temperature firing type HTCC is preferably W, Mo-Mn paste ink.

次に絶縁用の樹脂として、PCBの場合は、従来のエポキシ系、フェノール系、PET、フッ素樹脂系、ABS、ウレタン、ポリカーボネート、アラミド樹脂、ABS、ウレタン、ポリカーボネート、アラミド樹脂等が好ましい。  Next, in the case of PCB as the insulating resin, conventional epoxy, phenol, PET, fluororesin, ABS, urethane, polycarbonate, aramid resin, ABS, urethane, polycarbonate, aramid resin and the like are preferable.

使用形態として、これらの微粉末を静電塗装のように吹付けて、加熱、融解、硬化させる方法も可能であるが、2〜50μmの均一な膜厚を作成するのは難しい。
本発明は、これらの樹脂を3Dプリンターで印刷しやすい液状で使用する方法が、膜厚の管理や作業性が高い。
As a form of use, a method of spraying these fine powders like electrostatic coating to heat, melt, and harden is possible, but it is difficult to create a uniform film thickness of 2 to 50 μm.
In the present invention, the method of using these resins in a liquid form that can be easily printed by a 3D printer has high film thickness management and workability.

セラミックス配線板の作製に用いる絶縁層の材質は、アルミナ基板の場合は、Al、AlN基板ではAlN、Si系基板の揚合、Siを主成分として、その他にガラス質や無機の酸化物を添加して、かつ3Dプリンターで印刷しやすい形状にする。セルロース系の増粘剤や界面活性剤を添加して用いる。The material of the insulating layer used for the production of the ceramic wiring board is Al 2 O 3 for the alumina substrate, AlN for the AlN substrate, Si 3 N 4 based substrate, Si 3 N 4 as the main component, and others Add a glassy or inorganic oxide and make it easy to print with a 3D printer. Cellulose thickeners and surfactants are added for use.

又回路や上下導通用の導電性材料として、W,Mo−Mn,Cu,Ni、Co、Ag,Ag−Pd、ペーストを用いることが出来る。  Moreover, W, Mo-Mn, Cu, Ni, Co, Ag, Ag-Pd, and a paste can be used as a conductive material for circuits and vertical conduction.

インクジェット方式で印刷して、レーザー照射で局所加熱することにより、配線回路や電気的導通路を形成する。  A wiring circuit or an electrical conduction path is formed by printing by an inkjet method and locally heating by laser irradiation.

本発明で印刷し、硬化された表面のパットやバンプは、そのままではW/BやSMDは使用できにくいために、メッキを施した方が良い。
メッキしたパット等に電子部品をはんだ付けするための半田は、Sn−Ag−Cu,Sn,Sn−Ag−Cu−Bi等のクリーム半田や半田ボールを用いることが出来る。
一方、W/B用のパットやバンプには、Ni/Au,Ni/Pd/Au等のメッキを施した方が良い。
The pads and bumps on the surface printed and cured according to the present invention cannot be used with W / B or SMD as they are, so it is better to perform plating.
As solder for soldering an electronic component to a plated pad or the like, cream solder such as Sn-Ag-Cu, Sn, Sn-Ag-Cu-Bi, or a solder ball can be used.
On the other hand, it is better to apply plating of Ni / Au, Ni / Pd / Au, etc. to the pads and bumps for W / B.

今日、Au線からCu線にPdメッキを施したワイヤーを用いてW/Bを行う方式に変わりつつある。
下地のパットやバンプ上には、Ni/Au,Ni/Pd/Auのやや厚いメッキを行う。メッキ方法は、導通が取れれば電気メッキが好ましい。導通が取れない場合は、無電解のNi,Pd,Auをする。
Today, a method of performing W / B using a wire obtained by performing Pd plating on a Cu wire from an Au wire is changing.
A slightly thick plating of Ni / Au and Ni / Pd / Au is performed on the underlying pad or bump. As the plating method, electroplating is preferable as long as conduction is obtained. If continuity cannot be obtained, electroless Ni, Pd, Au is used.

本発明絶縁層間に、必要に応じて電子部品を挿入、実装することが出来る。
本発明多層配線板の層間に存在する導電層と電気的に接続させることで、電子部品の持つ新しい機能を本発明多層配線板に付与することが出来る。
電子部品とは、IC、LSI、抵抗、コンデンサー、アンテナ、バリスター、SAWフィルター等である。
Electronic components can be inserted and mounted between the insulating layers of the present invention as necessary.
By electrically connecting to the conductive layer existing between the layers of the multilayer wiring board of the present invention, a new function of the electronic component can be imparted to the multilayer wiring board of the present invention.
Electronic components include ICs, LSIs, resistors, capacitors, antennas, varistors, SAW filters, and the like.

本発明は下記の効果を有する。
1 従来技術で必要であったフォトリソ、穴あけ、穴埋め、メッキ等の工数を大幅に省略したり、あるいは減らすことが出来る。(生産工程とコストの大幅な削減)
2 高価な設備、高度な技術、高価な薬品、部材、水等の賞を大幅に減らすことが出来、環境に対する負荷を削減できる。(省エネ、省資源)
3 微細で精度の高い多層基板を誰でも簡単に製作できる。
4 多品種、少量生産を短期間で製作でき、カスタマイズドな基盤を提供できる。
5 導通不良、回路断線による不良率を大幅に低減させることが出来る。
6 多層配線板を大幅に軽薄短小化できる。
The present invention has the following effects.
1. Man-hours such as photolithography, drilling, hole filling, plating, etc. required in the prior art can be largely omitted or reduced. (Significant reduction in production process and cost)
2 Awards for expensive equipment, advanced technology, expensive chemicals, components, water, etc. can be greatly reduced, and the burden on the environment can be reduced. (Energy saving and resource saving)
3 Anyone can easily produce a fine and highly accurate multilayer board.
4. Can produce a variety of products and small-scale production in a short period of time and provide a customized base.
5. The failure rate due to continuity failure and circuit disconnection can be greatly reduced.
6 The multilayer wiring board can be significantly reduced in size and thickness.

本発明構造を説明するための模式図である。It is a schematic diagram for demonstrating this invention structure. 本発明構造を説明するための別の模式図である。It is another schematic diagram for demonstrating this invention structure. 本発明構造を説明するための別の模式図である。It is another schematic diagram for demonstrating this invention structure. 包覆構造の別の実施態様を説明する図である。It is a figure explaining another embodiment of a covering structure. 本発明の製造工程を説明する図である。It is a figure explaining the manufacturing process of this invention.

図面によって本発明の構造を説明する。
図1は本発明構造を説明するための模式図である。
図2は本発明構造を説明するための別の模式図である。
図3は本発明構造を説明するための別の模式図である。
The structure of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic view for explaining the structure of the present invention.
FIG. 2 is another schematic diagram for explaining the structure of the present invention.
FIG. 3 is another schematic diagram for explaining the structure of the present invention.

本発明多層基板において、図1に示す絶縁層2(下)と絶縁層3(上)の上下の絶縁層、および絶縁層を挟む上下の導電層1と、導電層を挟む上下の絶縁層、および絶縁層を貫通し、上下の導電層に接合された電気的導通路が存在する組合せからなるものを本発明多層基板の単位構造と表示する。
本発明多層基板は、この単位構造が多重に積重ねられて多層配線板が構築されるものである。
図1では、最下層は絶縁層2(下)であるが、多層配線板の最下層は、絶縁層、導電層、電気的導通路、いずれであっても良い。つまり、最下層が導電層の場合は、図2の構造が本発明多層基板の単位構造となり、電気的導通路が最下層の場合は、図3の構造が単位構造となり、いずれも上下の絶縁層、および絶縁層を挟む上下の導電層1と、導電層を挟む上下の絶縁層、および絶縁層を貫通し、上下の導電層に接合された電気的導通路が存在する組合せからなるものである。なお図3の組合せでは、最下層の電気的導通路4は外に露出するが、後から、ここに導電層(バンプ、パッド)が接合されることになる。
In the multilayer substrate of the present invention, the upper and lower insulating layers of the insulating layer 2 (lower) and the insulating layer 3 (upper) shown in FIG. 1, the upper and lower conductive layers 1 sandwiching the insulating layer, and the upper and lower insulating layers sandwiching the conductive layer, A unit structure of the multilayer substrate of the present invention is indicated by a combination of electrical conduction paths that penetrate through the insulating layer and are joined to the upper and lower conductive layers.
In the multilayer substrate of the present invention, a multilayer wiring board is constructed by stacking multiple unit structures.
In FIG. 1, the lowermost layer is the insulating layer 2 (lower), but the lowermost layer of the multilayer wiring board may be any of an insulating layer, a conductive layer, and an electrical conduction path. That is, when the lowermost layer is a conductive layer, the structure of FIG. 2 becomes the unit structure of the multilayer substrate of the present invention, and when the electrical conduction path is the lowermost layer, the structure of FIG. The upper and lower conductive layers 1 sandwiching the layers and the insulating layer, the upper and lower insulating layers sandwiching the conductive layer, and the combination in which there is an electrical conduction path that penetrates the insulating layer and is joined to the upper and lower conductive layers. is there. In the combination shown in FIG. 3, the lowermost electrical conduction path 4 is exposed to the outside, but a conductive layer (bump, pad) is joined thereto later.

図1の構造は、主に銅張樹脂基板等をスタート材に使用し、得られた多層配線板の中にスタート材が残る場合に得られる構造であり、図2、図3の構造は、主にダミー板をスタート材に使用し、得られた多層配線板からダミー板を剥ぎ取ってしまう場合に得られる構造であり、いずれの場合も本発明に包含されるものである。  The structure of FIG. 1 is a structure obtained when a copper clad resin substrate or the like is mainly used as a start material, and the start material remains in the obtained multilayer wiring board. The structures of FIGS. This is a structure obtained mainly when a dummy plate is used as a starting material, and the dummy plate is peeled off from the obtained multilayer wiring board, and both cases are included in the present invention.

図1〜3に示したように、電気的導通路4は導電層1の上に積層され、導電層1と電気的導通路4は、共に絶縁層に埋入される。そして隣同士の導電層1の間隙も絶縁層3で埋められている。  As shown in FIGS. 1 to 3, the electrical conduction path 4 is laminated on the conductive layer 1, and the conductive layer 1 and the electrical conduction path 4 are both embedded in the insulating layer. The gap between the adjacent conductive layers 1 is also filled with the insulating layer 3.

電気的導通路4の高さは、絶縁層の高さよりも高くなるように設計されているので、絶縁層に埋入されても、絶縁層を貫通して外に突出する構造になっている。
更に、絶縁層3の上に導電層1が積層され、絶縁層3から外に突出した電気的導通路4を導電層1が包覆する構造になっている。従って電気的導通路4の突出高さは、導電層1の高さ(厚さ)未満の高さになる。
Since the height of the electrical conduction path 4 is designed to be higher than the height of the insulating layer, even if embedded in the insulating layer, it has a structure that penetrates the insulating layer and protrudes outside. .
Further, the conductive layer 1 is laminated on the insulating layer 3, and the conductive layer 1 covers the electrical conduction path 4 protruding outward from the insulating layer 3. Therefore, the protruding height of the electrical conduction path 4 is less than the height (thickness) of the conductive layer 1.

電気的導通路4の上端面が、絶縁層3と同じ高さの場合、絶縁層3を印刷した時、インクが電気的導通路4の上端面に滲んで、電気的導通路4の上端面が、絶縁層で被覆されて、導電層との電気的導通が阻害されて、導通不良を起こすことがある。
電気的導通路4の高さを絶縁層の高さよりも高くするのは、滲みによる導通不良を防ぐことが目的である。また更に、万が一、電気的導通路4の突出部側面に、印刷したインキのセリ上がりが発生した時でも、導電層と導通不良が発生しないように、電気的導通路4の上端面を導電層で包覆させるのである。
本発明は、「電気的導通路4を絶縁層よりも上に突出させること」、そして「電気的導通路4の上端面を導電層で包覆させること」、この2つの手段で、電気的導通路4と導電層の接触、接合を確実にして、導通不良を防止するものである。そして、この2つの手段は、3Dプリンターで薄層を印刷、硬化、積層させて3次元構造体を形成することで初めて可能になるのである。
When the upper end surface of the electrical conduction path 4 is the same height as the insulating layer 3, when the insulating layer 3 is printed, the ink oozes into the upper end surface of the electrical conduction path 4 and the upper end surface of the electrical conduction path 4. However, it may be covered with an insulating layer, and electrical conduction with the conductive layer may be hindered, resulting in poor conduction.
The purpose of making the height of the electrical conduction path 4 higher than the height of the insulating layer is to prevent conduction failure due to bleeding. Furthermore, in the unlikely event that printed ink swells on the side surface of the protruding portion of the electrical conduction path 4, the upper end surface of the electrical conduction path 4 is connected to the conductive layer so as not to cause poor conduction with the conductive layer. It is covered with.
In the present invention, the electric conduction path 4 protrudes above the insulating layer, and the upper end surface of the electric conduction path 4 is covered with the conductive layer. This ensures contact and bonding between the conduction path 4 and the conductive layer, and prevents conduction failure. These two means can be realized only by forming a three-dimensional structure by printing, curing and laminating thin layers with a 3D printer.

図1〜3の電気的導通路4を包覆する構造は、電気的導通路4の上端面全面と、突出した側面周囲の一部を包み込む構造であるが、図4の包覆構造は、突出した面、全面を埋め込んで包覆するものである。
本発明は、図1および図4の包覆構造、いずれを選択しても良い。電気的導通路4の形状、突出部の表面積等を勘案して、適宜、いずれかを選択すればよい。
The structure for covering the electrical conduction path 4 in FIGS. 1 to 3 is a structure for wrapping the entire upper end surface of the electrical conduction path 4 and a part of the periphery of the protruding side surface. The protruding surface and the entire surface are embedded and covered.
In the present invention, any of the covering structures shown in FIGS. 1 and 4 may be selected. Any one may be selected as appropriate in consideration of the shape of the electrical conduction path 4, the surface area of the protruding portion, and the like.

図5で、本発明の製造工程を説明する。
図5は、図1に示した単位構造の多層配線板を製造する場合の説明図である。
図2、図3の単位構造の場合の製造工程も、最下層が導電層あるいは電気的導通層に入れ替わるだけで、絶縁層、導電層、電気的導通路を積層する順序は同じであり、最終的な構造は基本的には同じになるので、図5の場合の説明で代表させる。
The manufacturing process of the present invention will be described with reference to FIG.
FIG. 5 is an explanatory diagram in the case of manufacturing the multilayer wiring board having the unit structure shown in FIG.
The manufacturing process in the case of the unit structure of FIG. 2 and FIG. 3 also has the same order of stacking the insulating layer, the conductive layer, and the electrical conduction path, except that the lowermost layer is replaced with a conductive layer or an electrical conduction layer. Since the basic structure is basically the same, it will be represented in the description of FIG.

本発明多層配線板は、図3の第1〜第3工程までで単位構造が出来上がる。
本発明多層配線板は、この単位構造を何十組も積重ねて形成されるものである。
各工程について詳述する。
第1工程
予め硬化処理された絶縁層表面に3Dプリンターで導電層が印刷され、導電層の表面に電気的導通路が印刷される。
第2工程の前に導電層と電気的導通路が硬化処理される。
硬化処理される順序は、どちらが先でも、あるいは同時でもよい。
In the multilayer wiring board of the present invention, the unit structure is completed in the first to third steps of FIG.
The multilayer wiring board of the present invention is formed by stacking dozens of the unit structures.
Each step will be described in detail.
1st process A conductive layer is printed with a 3D printer on the surface of the insulating layer that has been previously cured, and an electrical conduction path is printed on the surface of the conductive layer.
Prior to the second step, the conductive layer and the electrical conduction path are cured.
The order of the curing treatment may be either first or simultaneous.

第2工程
硬化処理された導電層と電気的導通路の上を、3Dプリンターを用いて、絶縁性インキで印刷する。この時、絶縁性インキが電気的導通路の上部を覆わないように印刷する。また導電層間の隙間にもインクを充填する。
印刷した絶縁層インクを硬化処理する。
硬化処理の際、絶縁層インキには収縮が起こるが、電気的導通路と導電層は、すでに硬化処理されているので、この収縮ストレスで、電気的導通路に亀裂、あるいは導電層(配線回路)に断線が発生して導通不良が発生する確率は極めて低くなり、上下の配線回路間の電気的導通不良や配線回路の断線が原因の不良率を著しく低減させることが出来る。
「導電層と電気的導通路の印刷層を先に硬化させ、後から絶縁層の印刷層を硬化させる」、本発明多層基板の製造方法の最大の特徴は、ここにある。
Second Step The printed conductive layer and the electrical conduction path are printed with an insulating ink using a 3D printer. At this time, printing is performed so that the insulating ink does not cover the upper part of the electrical conduction path. Also, ink is filled in the gap between the conductive layers.
The printed insulating layer ink is cured.
During the curing process, shrinkage occurs in the insulating layer ink. However, since the electrical conduction path and the conductive layer are already cured, the shrinkage stress causes cracks in the electrical conduction path or the conductive layer (wiring circuit). The probability of occurrence of a conduction failure due to disconnection is extremely low, and the failure rate due to an electrical conduction failure between the upper and lower wiring circuits and a disconnection of the wiring circuit can be significantly reduced.
This is the greatest feature of the method for producing the multilayer substrate of the present invention, “the printed layer of the conductive layer and the electrical conduction path are cured first, and the printed layer of the insulating layer is cured later”.

第3工程
絶縁層に突出した電気的導通路を包覆する構造で導電層を印刷して、硬化させる。
以上、第1〜3の工程で、本発明多層配線板の単位構造が形成される。
3rd process A conductive layer is printed and hardened by the structure which covers the electrical conduction path which protruded to the insulating layer.
As described above, the unit structure of the multilayer wiring board of the present invention is formed in the first to third steps.

実施例によって本発明を説明する。
なお本実施例は、本発明の趣旨をよりよく理解させるために具体的に説明するものであり、本発明がこれのみに限定されるものでないことはもちろんである。
The examples illustrate the invention.
In addition, a present Example is concretely demonstrated in order to make the meaning of this invention understand better, and of course, this invention is not limited only to this.

実施例1
多層配線板の製作(MLPCB)
製作方法を、以下に具体的に述べるが、本実施例のみが本発明を限定するものではないことは勿論である。
Example 1
Production of multilayer wiring boards (MLPCB)
A manufacturing method will be specifically described below, but it is needless to say that only the present embodiment does not limit the present invention.

3Dデータの作成
3D−CADで作成した三次元内部配線を有する基板の設計情報をもとに3Dデータを作成し、3Dプリンターに入力した。
なお3Dプリンターにはシーメット社の装置を用いた。
多層配線板の立体構造を水平断面で薄層に分割する時、3Dプリンターで印刷する一回印刷ごとの絶縁層、配線回路の薄層の印刷厚さは、絶縁層は15μm、配線回路は、20μmにし、絶縁層、配線回路の薄層は、共に一回の印刷で形成できる厚さとした。
上層との導通に用いる電気的導通路は、絶縁層(15μm厚さ)から外に突出させることが必要であるので、高さは20μmとした。つまり絶縁層から5μm突出させ、20μm厚さの配線回路に、突出部が埋入される高さにした。
Creation of 3D data 3D data was created based on the design information of the substrate having the three-dimensional internal wiring created by 3D-CAD, and input to the 3D printer.
In addition, the apparatus of Simet was used for 3D printer.
When the three-dimensional structure of the multilayer wiring board is divided into thin layers in a horizontal section, the insulating layer for each printing printed by a 3D printer, the printed thickness of the thin layer of the wiring circuit is 15 μm for the insulating layer, The thickness was set to 20 μm, and both the insulating layer and the thin layer of the wiring circuit had a thickness that could be formed by a single printing.
Since the electrical conduction path used for conduction with the upper layer needs to protrude outward from the insulating layer (15 μm thickness), the height was set to 20 μm. In other words, the height of the protrusion was embedded in the wiring circuit having a thickness of 20 μm by protruding 5 μm from the insulating layer.

本実施例の多層配線板の単位構造は、図1に示す構造を採用した。そして製造工程は、図5に示す工程を採用した。The unit structure of the multilayer wiring board of the present example employs the structure shown in FIG. And the manufacturing process employ | adopted the process shown in FIG.

スタート材には市販のA4サイズの両面銅張樹脂基板を用い、本実施例では片面のみを使って逐次積層を実施することとした。As the starting material, a commercially available A4 size double-sided copper-clad resin substrate was used, and in this example, only one side was used for sequential lamination.

まず銅張基板の銅層をエッチングすることで、樹脂基板表面に、内部配線銅回路、および上層との導通に用いるための円柱状の銅突起を立設するためのパッドを形成した。
本例では、樹脂基板が、図5の工程1図の絶縁層(硬化)に相当する。
なお本実施例の内部配線銅回路およびパッドは、本明細書では導電層と総称している。円柱状の銅突起は、本明細書の電気的導通路である。
内部配線銅回路の幅は20μm、厚さは20μm、内部配線間の隙間(R/S)は20μm、円柱状銅突起は、直径20μm、高さ20μmとした。
次に内部配線銅回路および突起形成用のパッド上に、直径20μm、高さ20μm、隣接する銅突起との距離を20μmとして、上層の内部配線銅回路との電気導通用の円柱形の突起を形成した。
下記の工程で形成した。
First, the copper layer of the copper-clad substrate was etched to form a pad for standing a cylindrical copper protrusion for use in conduction with the internal wiring copper circuit and the upper layer on the surface of the resin substrate.
In this example, the resin substrate corresponds to the insulating layer (cured) in step 1 of FIG.
Note that the internal wiring copper circuit and the pad of this embodiment are collectively referred to as a conductive layer in this specification. The cylindrical copper protrusion is an electrical conduction path in the present specification.
The width of the internal wiring copper circuit was 20 μm, the thickness was 20 μm, the gap (R / S) between the internal wirings was 20 μm, and the cylindrical copper protrusion had a diameter of 20 μm and a height of 20 μm.
Next, on the internal wiring copper circuit and the pad for forming the protrusion, a cylindrical protrusion for electrical conduction with the upper internal wiring copper circuit is formed with a diameter of 20 μm, a height of 20 μm, and a distance from the adjacent copper protrusion of 20 μm. Formed.
It formed in the following process.

導電性インク(※1)を使用して、3Dプリンターで前記パッドの表面に突起を立設した。
次にレーザーで突起部分のみを局所加熱して、硬化させた。インクに含まれているベヒクル(粘着剤)成分は完全に消失させた。
硬化後の突起の導電率(比抵抗)は、1.780×10−6Ω・cmであった。
純銅の導電率(比抵抗)は1.724×10−6Ω・cm−1であり、本発明突起の硬化後の導電率(比抵抗)は、純銅とほぼ同じであった。
Using conductive ink (* 1), a protrusion was erected on the surface of the pad with a 3D printer.
Next, only the protrusions were locally heated with a laser and cured. The vehicle (adhesive) component contained in the ink was completely lost.
The conductivity (specific resistance) of the protrusion after curing was 1.780 × 10 −6 Ω · cm.
The conductivity (specific resistance) of pure copper was 1.724 × 10 −6 Ω · cm −1 , and the conductivity (specific resistance) after curing of the projections of the present invention was almost the same as that of pure copper.

なお前記導電性インクの組成は、下記のとおりである。
※1の組成:市販の銅ペースト(フジクラ化成社製品)にフェノール樹脂を混合した組成。
The composition of the conductive ink is as follows.
* 1 Composition: Composition in which phenol resin is mixed with commercially available copper paste (product of Fujikura Kasei Co., Ltd.).

その後、前記銅突起以外の所に、3Dプリンターを用いて、エポキシ樹脂、ガラス粉、ベヒクルから調合された3Dプリンター用の絶縁性インキ(※2)を均一印刷した。その時、絶縁性印刷インキが突起の上部を覆わないように印刷した。絶縁性印刷インキの印刷厚さ15μm、突起の高さ20μmとし、段差を5μmに設計して印刷した。Thereafter, an insulating ink (* 2) for 3D printer prepared from epoxy resin, glass powder, and vehicle was uniformly printed using a 3D printer at a place other than the copper protrusion. At that time, printing was performed so that the insulating printing ink did not cover the top of the protrusion. Insulating printing ink was printed with a printing thickness of 15 μm, a protrusion height of 20 μm, and a step of 5 μm.

なお※2のインクの組成は、下記のとおりである。
※2の組成:エポキシ樹脂70%、1〜3μm粒径のガラス粉20%、ブチルセルソルブ(ブチセロ)10%等を混合した組成。
The ink composition of * 2 is as follows.
* 2 Composition: Composition in which 70% epoxy resin, 20% glass powder having a particle diameter of 1 to 3 μm, 10% butyl cellosolve (buticello), etc. are mixed.

レーザーを照射して絶縁性インキの印刷層を硬化させた。The printed layer of insulating ink was cured by irradiating a laser.

次に、前記絶縁層(絶縁性インキの印刷層)の表面に、導電性インキ(※1の組成)を用いて、幅20μm、厚さは20μm、内部配線間の隙間(R/S)は20μm、の内部配線銅回路を印刷した。
前記絶縁層の表面に5μm突出した突起上に、導電性インキが被るように印刷し、突起と回路の導通が、確実に取れるように印刷し、その後、印刷された回路部のみをレーザーで加熱、硬化させた。
Next, on the surface of the insulating layer (printing layer of insulating ink), using conductive ink (* 1 composition), the width is 20 μm, the thickness is 20 μm, and the gap (R / S) between the internal wirings is A 20 μm internal wiring copper circuit was printed.
On the surface of the insulating layer, printing is performed so that the conductive ink is covered on the protrusion protruding 5 μm, and printing is performed so that the connection between the protrusion and the circuit is ensured, and then only the printed circuit part is heated with a laser. And cured.

外に露出した内部配線表面上に、上層との導通用の円柱状の突起を、導電性インキ(※1)を使用して、3Dプリンターで立設した。
突起の直径20μm、高さ20μmを印刷した。
On the surface of the internal wiring exposed to the outside, a cylindrical projection for conduction with the upper layer was erected with a 3D printer using conductive ink (* 1).
A protrusion having a diameter of 20 μm and a height of 20 μm was printed.

レーザーを用いて突起のみを局所加熱して硬化させた。Only the protrusions were locally heated using a laser and cured.

以後の工程は、前記した一連の工程を繰り返して、逐次積層して、20層の内部配線を有する超多層のプリント配線板(MLPCB)を作製した。In the subsequent steps, the above-described series of steps were repeated and sequentially laminated to produce a super multilayer printed wiring board (MLPCB) having 20 layers of internal wiring.

表層(最外層)には種々の電子部品を実装するためのパッド、突起(バンプ)を3Dプリンターで印刷して硬化させた。
印刷インキには前記※1と同じ導電性インキを用いた。
On the surface layer (outermost layer), pads and protrusions (bumps) for mounting various electronic components were printed with a 3D printer and cured.
The same conductive ink as the above * 1 was used as the printing ink.

ワイヤーボンディング(W/B)や表面実装(SMD)のために、表層のパッド、突起(バンプ)にメッキを行った。For the wire bonding (W / B) and surface mounting (SMD), the surface layer pads and protrusions (bumps) were plated.

W/B用のパッドおよび半田付けのためのパッド上に、2種類のメッキ(Ni/Auメッキ、Ni/Pd/Auメッキ)を行った。Two types of plating (Ni / Au plating and Ni / Pd / Au plating) were performed on the pad for W / B and the pad for soldering.

W/B用及び半田付けのためのパッドのメッキ工程
1.銅ペースト(導電性インキ)で形成した銅回路、銅突起(バンプ)の酸化物や残存する不純物を除去するために、
硫酸20g/L、クエン酸10g/L、界面活性剤0.1g/Lからなる酸性脱脂材に50℃で3分間浸漬した。
銅の酸化物等が除去され、赤い銅色が現れ、水はじきが無くなった。
1. Pad plating process for W / B and soldering To remove copper circuit, copper protrusion (bump) oxide and remaining impurities formed with copper paste (conductive ink)
It was immersed in an acidic degreasing material composed of 20 g / L sulfuric acid, 10 g / L citric acid, and 0.1 g / L surfactant for 3 minutes at 50 ° C.
Copper oxides were removed, a red copper color appeared, and water repelling disappeared.

2.Na 10g/L、硫酸 10gからなるエッチング液で、30℃で3分間浸漬し、いわゆるソフトエッチングを行った。2. So-called soft etching was performed by immersing in an etching solution composed of 10 g / L of Na 2 S 2 O 8 and 10 g of sulfuric acid at 30 ° C. for 3 minutes.

3.銅表面に生成したCuOを除くために硫酸20g/Lで、30℃で2分浸漬処理した。3. In order to remove CuO produced on the copper surface, immersion treatment was performed at 30 ° C. for 2 minutes with 20 g / L of sulfuric acid.

4.PdCL 0.1g/L、硫酸5g/LからなるPd活性液に、20℃、2分間浸漬した。4). It was immersed in a Pd active solution composed of PdCL 2 0.1 g / L and sulfuric acid 5 g / L at 20 ° C. for 2 minutes.

5.NiSO 30g/L、NaHPO 20g/L、クエン酸 30g/L、pH4.5、浴温85℃で、20分間メッキした。Cu回路、突起部のみにNiが4μmメッキされた。5. Plating was performed for 20 minutes at 30 g / L of NiSO 4, 20 g / L of NaH 2 PO 2 , 30 g / L of citric acid, pH 4.5, and a bath temperature of 85 ° C. Only the Cu circuit and the protrusions were plated with 4 μm of Ni.

6.KAu(CN) 1g/L、クエン酸 10g/L、pH4.5、浴温90℃、で10分メッキした。
Ni上にAuが0.04μmメッキされた。
6). Plating was performed for 10 minutes at KAu (CN) 2 1 g / L, citric acid 10 g / L, pH 4.5, and bath temperature 90 ° C.
Au was plated to 0.04 μm on Ni.

7.このNi/Auメッキされたパットや突起(バンプ)に電子部品を実装した。
Ni/Auメッキされた基板を用いて、パットに対するW/B強度および半田接合強度を測定した。
結果を表1に示す。
7). Electronic parts were mounted on the Ni / Au plated pads and protrusions (bumps).
Using a Ni / Au plated substrate, W / B strength and solder joint strength with respect to the pad were measured.
The results are shown in Table 1.

Figure 2015135933
W/B強度の測定は、30個のテストピースを用いて、20gの力でワイヤーを引張って、何個、パッド部から剥がれたかで評価した。
表中、分子の数字は、30個のテストピース中の剥がれた数を表す。
Figure 2015135933
The measurement of W / B strength was evaluated by using 30 test pieces, pulling the wire with a force of 20 g, and how many pieces were peeled from the pad portion.
In the table, the number of molecules represents the number of peeled pieces in 30 test pieces.

W/B強度および半田接合強度も従来法とほぼ同程度であった。The W / B strength and solder joint strength were almost the same as those of the conventional method.

Ni/Pd/Auメッキ工程
無電解Niメッキが終了した基板を、PdCl 2g/L、エチレンジアミン20g/L、EDTA 10g/L、ヒドラジン 5g/L、pH9.0からなる無電解Pdメッキ浴に、70℃、5分間、メッキする。
Pdが0.2μmメッキされた。
次に、KAu(CN) 2g/L、クエン酸 10g/L、pH4.5からなるAuメッキ液に、90℃、2分間メッキした。
Auメッキが0.001μmメッキされた。
この基板を用いてW/B、半田接合強度を測定した。
結果を表2に示す。
Ni / Pd / Au plating process The substrate after electroless Ni plating was placed in an electroless Pd plating bath composed of PdCl 2 2 g / L, ethylenediamine 20 g / L, EDTA 10 g / L, hydrazine 5 g / L, pH 9.0, Plate at 70 ° C. for 5 minutes.
Pd was plated by 0.2 μm.
Next, plating was performed at 90 ° C. for 2 minutes on an Au plating solution composed of KAu (CN) 2 2 g / L, citric acid 10 g / L, and pH 4.5.
Au plating was plated by 0.001 μm.
Using this substrate, W / B and solder joint strength were measured.
The results are shown in Table 2.

Figure 2015135933
半田接合強度の測定は、各々のパッドに半田付けをして引張り、パッドから半田が剥がれた時のg数で強度を評価した。数値は30カ所の強度の平均値を示す。
Figure 2015135933
The solder joint strength was measured by soldering each pad and pulling, and the strength was evaluated by the number of grams when the solder peeled off from the pad. A numerical value shows the average value of intensity | strength of 30 places.

W/B強度および半田接合強度も従来法とほぼ同程度であった。The W / B strength and solder joint strength were almost the same as those of the conventional method.

表1、表2の結果から、めっきの種類が変わってもW/B強度および半田接合強度は従来法とほぼ同程度であり、本発明方法で形成した表層のパットは、従来法で形成した表層のパットと、そのメッキ性、密着強度(絶縁層に対する)、強度等の点で、なんら遜色ないことを意味するものである。From the results in Tables 1 and 2, the W / B strength and solder joint strength are almost the same as those of the conventional method even if the type of plating is changed, and the surface layer pad formed by the method of the present invention was formed by the conventional method. This means that the surface pad and its plating properties, adhesion strength (to the insulating layer), strength and the like are comparable.

比較例
以下に記載する従来技術で多層配線基板を作成した。
1.図1と同じ両面銅張基板を用い片面だけを使用した。
2.まず基板全面にエポキシ樹脂ペーストを40μmの高さを目標に塗布(スクリーン印刷)し、加熱で硬化させた。
3.下層の回路と導通を取るために、硬化させたエポキシ樹脂層にレーザーで直径100μmの穴をあけた。(ブラインドビィア)
4.このブラインドビィアを銅メッキで埋めるために以下の工程を経た。
Comparative Example A multilayer wiring board was prepared by the conventional technique described below.
1. The same double-sided copper-clad substrate as in FIG. 1 was used and only one side was used.
2. First, an epoxy resin paste was applied to the entire surface of the substrate with a target of 40 μm height (screen printing) and cured by heating.
3. A hole having a diameter of 100 μm was drilled in the cured epoxy resin layer with a laser in order to establish conduction with the underlying circuit. (Blind Via)
4). In order to fill the blind via with copper plating, the following steps were performed.

5.常法のエッチング、デスミィヤ、無電解銅メッキ、電解銅メッキ(ビィアフィル)、その後、絶縁膜(エポキシ樹脂層)と同一の高さになるように、銅メッキ面を研磨し、ビィアフィルが完了した。
6.絶縁樹脂と銅メッキとの密着強度を得るために樹脂表面を粗化し、センシタイサン、アクチベーター、無電解銅、電解銅メッキを行い、厚さ20μmの銅メッキ層を形成した。
7.フォトリソグラフィーで銅メッキ層をエッチングして、配線回路とパットを形成した。
8.前記(2)と同様の工程で、エポキシ樹脂を塗布、乾燥、硬化させ、前記(3)と同様の工程で、下層との導通を取るための穴をレーザーで穴あけをした。
4、5、6、7、8の工程を繰返し、逐次、積層して積層数を増やした。
積層水が増えるごとに、導通不良の発生が多くなり、積層数は10層が限界であった。
表層には、W/B用のパットや半田付け用のパット、フリップチップ実装用のバンプを形成し、W/B、半田付けをするためにNi/Au、Ni/Pd/Auメッキを行った。
5. Usual etching, desmear, electroless copper plating, electrolytic copper plating (via fill), and then the copper plating surface was polished so as to be the same height as the insulating film (epoxy resin layer), and the via fill was completed.
6). In order to obtain adhesion strength between the insulating resin and the copper plating, the surface of the resin was roughened, and sensity san, activator, electroless copper and electrolytic copper plating were performed to form a copper plating layer having a thickness of 20 μm.
7). The copper plating layer was etched by photolithography to form a wiring circuit and a pad.
8). In the same step as (2), an epoxy resin was applied, dried and cured, and in the same step as (3), a hole for establishing conduction with the lower layer was drilled with a laser.
Steps 4, 5, 6, 7, and 8 were repeated, and the number of layers was increased by sequentially stacking.
As the amount of laminated water increased, the occurrence of poor conduction increased, and the number of laminated layers was limited to ten.
On the surface layer, a pad for W / B, a pad for soldering, and a bump for flip chip mounting were formed, and Ni / Au and Ni / Pd / Au plating were performed for W / B and soldering. .

従来法は、工数が極めて多く、製作に長期間を要した。The conventional method requires a lot of man-hours and takes a long time to manufacture.

同じ配線基板を本実施例で作製した時と、前記比較例で先制した時の、作製可能層数、歩留まり、作成に必要な日数、製造費用について比較した表を、表3に示す。  Table 3 shows a table comparing the number of layers that can be produced, the yield, the number of days required for production, and the production cost when the same wiring board is produced in this example and when the above-mentioned comparative example is preempted.

Figure 2015135933
Figure 2015135933

表3の結果から、本発明は、作製可能層数、歩留まり、作成日数、作製費用等で非常に有利であることが判った。
従来の製作方法と比べ本発明は、エッチングによる回路形成、フォトリソソグラフィ、穴あけ、穴埋め等の工程が省略でき、しかも短期間で確実に良品ができる。また高価な設備、高度な技術、高純度の薬品、部材が不要で、内部配線密度も従来の数倍の密度のものが容易に製作でき、積層する層数も20層の超多層のプリント配線板(MLPCB)が製作でき、電気的導通路や配線回路の断線等が原因の導通不良の発生防止に極めて効果があることが判明した。
From the results shown in Table 3, it was found that the present invention is very advantageous in terms of the number of layers that can be produced, yield, production days, production costs, and the like.
Compared with the conventional manufacturing method, the present invention can omit steps such as circuit formation by etching, photolithography, hole making, hole filling and the like, and can reliably produce a good product in a short period of time. In addition, expensive equipment, advanced technology, high-purity chemicals, and materials are not required, and the internal wiring density can be easily manufactured with several times the density of the conventional wiring. A plate (MLPCB) can be manufactured, and it has been found that it is extremely effective in preventing the occurrence of poor conduction due to disconnection of the electrical conduction path and wiring circuit.

実施例2
微細な内部配線構造を有する三次元内部配線構造からなるアルミナセラミックス製パッケージ(HTCC)の作製
製造工程は以下のとおりである。
Example 2
A manufacturing process of an alumina ceramic package (HTCC) having a three-dimensional internal wiring structure having a fine internal wiring structure is as follows.

1 三次元内部配線を有するセラミックス配線基板の設計情報を3D−CADで作製し、3Dデータを作成し、3Dプリンターに入力した。なお本例で使用した3Dプリンターは米国ストニタシス社のノズルから泥状のものを押し出す方式を用いた。なお本発明で使用する3Dプリンターがこれのみに限定されるものではないことは言うまでもないことである。1 Design information of a ceramic wiring board having three-dimensional internal wiring was prepared by 3D-CAD, 3D data was created, and input to a 3D printer. The 3D printer used in this example used a method of extruding a muddy material from a nozzle of US Sunititas. It goes without saying that the 3D printer used in the present invention is not limited to this.

多層配線板の立体構造を水平断面で薄層に分割する時、3Dプリンターで印刷する一回印刷ごとの絶縁層、配線回路の薄層の印刷厚さは、絶縁層は15μm、配線回路は、20μmにし、絶縁層、配線回路の薄層は、共に一回の印刷で形成できる厚さとした。When the three-dimensional structure of the multilayer wiring board is divided into thin layers in a horizontal section, the insulating layer for each printing printed by a 3D printer, the printed thickness of the thin layer of the wiring circuit is 15 μm for the insulating layer, The thickness was set to 20 μm, and both the insulating layer and the thin layer of the wiring circuit had a thickness that could be formed by a single printing.

2 Alを主成分としてSiO、B、PEG(ポリエチレングリコール)等を混合して作製したグリーンシート上に市販のWペーストを用いて3Dプリンターを用いて配線回路とパッドを印刷した。
配線回路の幅は20μm、配線回路間の間隔は20μm、配線回路の厚さは20μmとした。
2 A wiring circuit and a pad using a 3D printer using a commercially available W paste on a green sheet prepared by mixing SiO 2 , B 2 O 3 , PEG (polyethylene glycol), etc. with Al 2 O 3 as a main component. Printed.
The width of the wiring circuit was 20 μm, the interval between the wiring circuits was 20 μm, and the thickness of the wiring circuit was 20 μm.

3 還元雰囲気(H2+N2)中でレーザーを用いてグリーンシートと配線回路を同時焼結した。3 The green sheet and the wiring circuit were simultaneously sintered using a laser in a reducing atmosphere (H2 + N2).

4 次に上層の配線回路との導通用の柱状の突起(直径20μm、高さ20μm)を前述のWペーストを用いて、焼結した配線回路の表面に3Dプリンターで作製し、突起をレーザーで加熱して焼結した。4 Next, columnar protrusions (diameter 20 μm, height 20 μm) for conduction with the upper layer wiring circuit are produced on the surface of the sintered wiring circuit with a 3D printer using the above-mentioned W paste, and the protrusions are formed with a laser. Sintered by heating.

5 前記2で用いたグリーンシートと同成分の粘土状のAlスラリーを、突起部分には印刷せず、突起の上部を覆わないように印刷して、上下層間の絶縁層を作製した。Alスラリーの印刷厚さ15μm、突起の高さ20μmとし、段差を5μmに設計して印刷した。5 The clay-like Al 2 O 3 slurry having the same component as the green sheet used in 2 above was printed without printing on the protrusions and covering the upper part of the protrusions, and an insulating layer between the upper and lower layers was produced. . The Al 2 O 3 slurry was printed with a printing thickness of 15 μm, a protrusion height of 20 μm, and a step of 5 μm.

6 前記3と同じ条件で、絶縁層をレーザーで焼結した。
7 この時点で下層の配線回路と突起(上下層間導通用の柱)が完全に接合され、導通不良がないか、検査し、問題がないことを確認して次工程へ進んだ。
6 The insulating layer was sintered with laser under the same conditions as 3 above.
7 At this point, the lower layer wiring circuit and the protrusions (upper and lower interlayer conduction pillars) were completely joined, and inspected for continuity defects and confirmed that there were no problems, and proceeded to the next step.

8 焼結された絶縁層に前記2と3の工程を繰り返し、導通チェックし、この工程を繰り返して、逐次積層を繰り返した。8 The above steps 2 and 3 were repeated on the sintered insulating layer to check the continuity, and this step was repeated to repeat the sequential lamination.

9 最外層面には電子部品を搭載するためのパット、W/B用のパットを、Wペーストを用いて3Dプリンターで印刷し、焼結した。
10 公知の方法でW/B、半田付用のパット、バンプにNi/Au、Ni/Pd/Auメッキを行って、多層セラミックスICパッケージを完成させた。
完成した多層基板には、ワレ、ソリ、導通不良もなかった。
本発明方法では、欠陥のない健全なセラミックス多層基板を容易に作成できることが確認できた。
9 On the outermost layer surface, a pad for mounting electronic components and a pad for W / B were printed with a 3D printer using W paste and sintered.
10 W / B, pads for soldering, and bumps were plated with Ni / Au and Ni / Pd / Au by a known method to complete a multilayer ceramic IC package.
The completed multilayer substrate was free from cracks, warpage, and poor conduction.
In the method of the present invention, it was confirmed that a sound ceramic multilayer substrate without defects can be easily produced.

比較例(従来技術による方法)
従来方法は、下記1〜6の工程で製造した。
1 従来技術はグリーンシートにWペーストを用いて、スクリーン印刷法で回路やパッドを形成した。
2 第2層も同様のグリーンシート上に上下導通用の穴をパンチングで穿孔し、Wペーストで回路を印刷し、穿孔部には、Wペーストを埋め込み、上下導通用の柱に用いた。
3 第三層も第二層と同様の工程で形成した。
4 最外層には、W/B用のパッドや半田付け用のパッドをWペーストで印刷した。
5 逐次積層後、多層版を重ね合わせた後に、還元雰囲気で一体焼結した。
6 焼結後、常法通りの方法で、W/Bパッドや半田付けパッドにメッキを行った。
Comparative example (method according to the prior art)
The conventional method was manufactured in the following steps 1-6.
1 In the prior art, circuits and pads were formed by screen printing using W paste on a green sheet.
2 In the second layer, a hole for vertical conduction was punched on the same green sheet by punching, a circuit was printed with W paste, W paste was embedded in the punched portion, and used as a column for vertical conduction.
3 The third layer was formed in the same process as the second layer.
4 On the outermost layer, a W / B pad and a soldering pad were printed with W paste.
5 After successive lamination, the multilayer plates were superposed and then integrally sintered in a reducing atmosphere.
6 After sintering, plating was performed on the W / B pad and the soldering pad by a conventional method.

従来技術の最大の問題点は、グリーンシート焼結時、体積が20〜30%収縮すること、収縮時に、内部配線に用いたWペーストの膨張係数の違いにより、回路が断線したり、上下導通の柱が接触不良を起こしたり、基板のワレやソリが多発して、不良率は30〜40%に達している。
本例では、20個作製して、ソリと導通不良併せて9個、不良が発生した。
一方、本発明では、積層時に逐次、断線、接触不良をチェックできること、また各層積層ごとに焼結を行うので、基板のソリやワレは皆無であり、不良率は、0%であった。
The biggest problem of the prior art is that when the green sheet is sintered, the volume shrinks by 20-30%, and at the time of shrinkage, the circuit breaks due to the difference in the expansion coefficient of the W paste used for the internal wiring, and the vertical conduction The column causes contact failure, and cracks and warpage of the substrate frequently occur, and the defect rate reaches 30 to 40%.
In this example, 20 pieces were produced, and nine defects including warpage and conduction failure occurred.
On the other hand, in the present invention, disconnection and contact failure can be checked sequentially at the time of stacking, and since sintering is performed for each layer stack, there is no warping or cracking of the substrate, and the defect rate is 0%.

実施例3
本発明による製法と従来の製法で、絶縁不良、断線の数を比較して、本発明の優位性を証明する。
すなわち同じ仕様でML−PCBを製作した。
使用した最初の基板は市販の銅張両面基板(A4サイズ)を用いた。
銅板の厚さは、20μm、片面のみ用い、導通テスト用の端子をエッチングで作製した。
上下導通用の突起は、直径20μm、高さ20μm、層数は10層積層した。
突起の数は200箇所作成し、各層の突起を突合せて接合し、一層目の端子(突起)と10層目の端子(突起)間で比抵抗を測定して絶縁性や断線の有無を評価した。
本発明の多層基板は、実施例1の方法で作製した。
従来法の基板は、実施例1の比較例1の手法で作製した。
結果は、表4に示す。
Example 3
The superiority of the present invention is proved by comparing the number of defective insulation and disconnection between the manufacturing method according to the present invention and the conventional manufacturing method.
That is, ML-PCB was manufactured with the same specifications.
The first board used was a commercially available copper-clad double-sided board (A4 size).
The thickness of the copper plate was 20 μm, only one side was used, and a terminal for continuity test was produced by etching.
The vertical conduction protrusions were laminated with a diameter of 20 μm, a height of 20 μm, and 10 layers.
The number of projections is 200, and the projections of each layer are butted and joined, and the specific resistance is measured between the first layer terminals (projections) and the tenth layer terminals (projections) to evaluate the presence or absence of insulation or disconnection. did.
The multilayer substrate of the present invention was produced by the method of Example 1.
A conventional substrate was produced by the method of Comparative Example 1 of Example 1.
The results are shown in Table 4.

Figure 2015135933
導通テストの条件:下層と上層間の抵抗を測定し、200個の突起の平均値を示す。
耐湿サイクルの条件:90〜60%の湿度の中で25℃×10Hr、65℃×14Hrを1サイクルとして、10サイクル繰り返した。
断線:下層と上層間で全く電流が流れない時を断線とみなした。数字は、200箇所測定した時の断線箇所の数。
Figure 2015135933
Conditions for continuity test: The resistance between the lower layer and the upper layer is measured, and the average value of 200 protrusions is shown.
Conditions of moisture resistance cycle: 10 cycles were repeated with 25 ° C. × 10 Hr and 65 ° C. × 14 Hr as one cycle in a humidity of 90-60%.
Disconnection: When no current flows between the lower layer and the upper layer, it was considered as a disconnection. The number is the number of disconnection points when 200 points are measured.

表4の結果より、本発明は、従来法に比較して比抵抗が小さいうえに、断線が皆無であることである。  From the results in Table 4, the present invention has a smaller specific resistance than the conventional method and no disconnection.

従来法では、比抵抗が大きくなり、断線発生率が高くなる原因は下記の理由によると思われる。
すなわち、従来法の製作上の最大の問題点は、穴あけ工程でレーザーを用いて、下層の銅回路に達するまでエポキシ樹脂を焼切る方法である。
この方法では、銅表面に樹脂の燃焼残渣や不完全燃焼した樹脂が固着残存したりする。また穴の周囲は、樹脂が融解し、銅表面に被膜を形成し、次工程のデスミィヤ、エッチング工程で除去出来にくく、又確認も難しい。結局、これらの残存物が残った銅表面に電解あるいは無電解銅メッキを行うために、当然、接触抵抗は大きくなり、断線の頻度も高くなるものと推察できる。
またレーザーで開孔された穴の形状は、台形、逆台形、オーバーハング等、色々な形状になっている。均一な形状になっていないのも、不良率が高くなる原因と思われる。
In the conventional method, the reason why the specific resistance increases and the disconnection rate increases is considered to be as follows.
That is, the biggest problem in manufacturing the conventional method is a method of burning the epoxy resin until it reaches the underlying copper circuit using a laser in the drilling process.
In this method, a resin combustion residue or incompletely burned resin remains on the copper surface. In addition, the resin melts around the hole to form a film on the copper surface, and it is difficult to remove and confirm in the next desmear and etching processes. Eventually, in order to perform electrolysis or electroless copper plating on the copper surface where these residues remain, it can be inferred that the contact resistance naturally increases and the frequency of disconnection also increases.
Moreover, the shape of the hole opened by the laser has various shapes such as a trapezoid, an inverted trapezoid and an overhang. It seems that the reason why the defect rate is high is that the shape is not uniform.

一方、本発明は、上下導通用の突起形成時に、突起の周辺には樹脂(絶縁物)は存在しない。硬化焼成時に樹脂等が突起上に流れ込むことはない。
従って本発明には、断線や絶縁不良を起こす原因が存在しない。
また加速劣化試験(耐湿サイクル試験)の結果から、明らかなように、更に優劣がはっきりする。
加速劣化試験後でも導通不良は皆無、抵抗変化も従来法よりも著しく小さい理由は、本発明の突起は、上層と下層との突起の界面は、突起同士が融着して一体化しているためであると推察できる。
On the other hand, according to the present invention, no resin (insulator) is present around the protrusion when the protrusion for vertical conduction is formed. Resins and the like do not flow onto the protrusions during curing and baking.
Therefore, the present invention has no cause for disconnection or insulation failure.
Further, as is clear from the results of the accelerated deterioration test (humidity cycle test), the superiority and inferiority become clearer.
The reason why there is no conduction failure even after the accelerated deterioration test and the resistance change is remarkably smaller than that of the conventional method is that the protrusions of the present invention are integrated by bonding the protrusions between the upper layer and the lower layer. It can be inferred that

実施例4
本発明による製法と従来の製法で、絶縁不良、断線、基板のソリを比較して、本発明の優位性を証明する。すなわち同じ仕様でHTCCを製作した。
Example 4
The superiority of the present invention is proved by comparing insulation failure, disconnection, and substrate warpage between the manufacturing method according to the present invention and the conventional manufacturing method. That is, HTCC was manufactured with the same specifications.

Al2O3を主成分とする絶縁層の厚さは、30μm、上下導通用の突起は、直径30μm、高さ30μmの円柱状にした。
層数は、10層とした。突起の数は200個作製し、各層の突起を突合せて接合し、下層と上層間の比抵抗を測定して、絶縁不良、断線を測定した。
基板のソリ、ワレは目視で評価した。
本発明の製作は、実施例2の方法と同じ方法で作製した。また従来法は実施例2の比較例の手法で作製した。
結果を表5に示す。
The insulating layer mainly composed of Al2O3 has a thickness of 30 μm, and the vertical conduction protrusions have a cylindrical shape with a diameter of 30 μm and a height of 30 μm.
The number of layers was 10. The number of projections was 200, and the projections of each layer were butted and joined, and the specific resistance between the lower layer and the upper layer was measured to measure insulation failure and disconnection.
The warpage and cracking of the substrate were evaluated visually.
The production of the present invention was produced by the same method as that of Example 2. Further, the conventional method was prepared by the method of the comparative example of Example 2.
The results are shown in Table 5.

Figure 2015135933
導通テストの条件:下層と上層間の抵抗を測定し、200個の突起の平均値を示す。
耐湿サイクルの条件:90〜60%の湿度の中で25℃×10Hr、65℃×14Hrを1サイクルとして、10サイクル繰り返した。
断線:下層と上層間で全く電流が流れない時を断線とみなした。数字は、200箇所測定した時の断線箇所の数。
Figure 2015135933
Conditions for continuity test: The resistance between the lower layer and the upper layer is measured, and the average value of 200 protrusions is shown.
Conditions of moisture resistance cycle: 10 cycles were repeated with 25 ° C. × 10 Hr and 65 ° C. × 14 Hr as one cycle in a humidity of 90-60%.
Disconnection: When no current flows between the lower layer and the upper layer, it was considered as a disconnection. The number is the number of disconnection points when 200 points are measured.

表5の結果より、本発明は加速劣化試験(耐湿サイクル試験)後でも断線は皆無であるが、従来法は、断線発生率が極めて高いことを証明できた。  From the results shown in Table 5, although the present invention has no disconnection even after the accelerated deterioration test (humidity cycle test), it has been proved that the conventional method has an extremely high disconnection rate.

この原因は、下記の理由によると考えられる。
すなわち、従来方法では、一体成形して焼成するので、セラミックス焼成時の宿命として、体積比で30〜40%収縮は避けられず、このことが、内部配線回路の断線、更に上下導通突起の断線や接触不良を引き起こす最大の原因になっている。従って従来製法では、20〜40%の不良率が発生することは避けられないことである。
一方、本発明の製法は、まずグリーンシートにWペーストによる回路形成、突起形成、その後、回路、突起部分のみをレーザーで局所加熱、焼成する。その後、絶縁用セラミックスを印刷し、焼成する方法である。また更に、本発明は一層ずつ焼成、チェックして、積層する方法であるので、もともと、ワレ、ソリ、断線等は発生しない手法である。
The cause is considered to be as follows.
That is, in the conventional method, since it is integrally molded and fired, the shrinkage of 30 to 40% in volume ratio is unavoidable as a fate when firing ceramics. This is due to the disconnection of the internal wiring circuit and the disconnection of the upper and lower conductive protrusions. And the biggest cause of poor contact. Therefore, it is inevitable that a defect rate of 20 to 40% occurs in the conventional manufacturing method.
On the other hand, in the production method of the present invention, circuit formation and protrusion formation are first performed on a green sheet using W paste, and then only the circuit and protrusion portions are locally heated and fired with a laser. Thereafter, the insulating ceramic is printed and fired. Furthermore, since the present invention is a method of firing, checking and laminating one layer at a time, it is originally a technique that does not cause cracks, warpage, disconnection, or the like.

実施例5
市販の銅張樹脂基板は使用せずに、最初から3Dプリンターを用いて両面多層配線板を作製する実施例
1.まず大きさA4サイズ、厚さ2mmのガラス板を用意した。
2.ガラス板の片面のバンプ、パッドになる部分に、実施例1と同じ銅ペーストを用いて、インクジェット方式で、直径20μm、高さ20μmの柱状の突起を300個印刷し、その部分をレーザーで加熱して硬化させた。
この突起は、反対面に多層配線板を積層するときの始点になるバンプやパットとなる。
3.その後、突起以外の所にエポキシ樹脂系の絶縁樹脂を印刷した。
その時、樹脂が突起の上部を覆わないように印刷した。
樹脂の厚さ15μm、突起の高さは20μmとし、段差を5μmに設計して印刷した。
4.樹脂をレーザーで加熱、硬化させた。
5.次に2)と同一の銅ペーストを用いて、幅20μm、高さ20μmの配線回路を樹脂の表面に印刷した。
2)で形成した突起上に銅ペーストが被るように印刷し、突起と回路が、確実に導通が取れるように印刷し、その後、印刷された回路部のみをレーザーを用いて加熱、硬化させた。
6.次に回路部に、上下層間の導通を取るために、直径20μm、高さ20μmの柱状の突起300個を、2)で用いた銅ペーストインクを用いて、回路部表面に印刷した。その後、突起部のみをレーザーで加熱、硬化させた。
7.3)と同様に、柱状の突起以外の部分に、エポキシ樹脂を印刷し、加熱、硬化させた。この場合も突起の上部に樹脂が被さっていないかを、導通テストで確認しながら作業した。
8.6)〜7)の工程を繰り返して、片側20層の多層配線板を作製した。
9.最外表面には、フリップチップ用のバンプ(直径20μm、高さ20μm)を形成し、レーザーで加熱、硬化させた。
10.作成された多層配線板を、150℃で3時間、加熱して、樹脂、回路、突起を十分硬化させた。
11.次に、最初に用いたガラス板を多層配線板から外した。
得られた多層配線板の裏側には、樹脂に埋め込まれた突起の端面が露出した。
この部分は裏面のパッドになる。この裏面のパッド部を起点にして、突起形成、絶縁樹脂の印刷を繰り返して、裏表同一構造で、裏表合計40層の多層配線板を作製し、実施例1の方法で無電解メッキを行った。
12.W/B強度や半田付け強度等も、実施例1と同様の強度が得られ、従来方法で作製されたものと同等であった。
Example 5
Example 1 of producing a double-sided multilayer wiring board using a 3D printer from the beginning without using a commercially available copper-clad resin substrate. First, a glass plate having a size A4 and a thickness of 2 mm was prepared.
2. Using the same copper paste as in Example 1, 300 columnar protrusions with a diameter of 20 μm and a height of 20 μm are printed on the glass bumps and pads on one side using the same copper paste as in Example 1, and the portions are heated with a laser. And cured.
This protrusion serves as a bump or pad that becomes the starting point when the multilayer wiring board is laminated on the opposite surface.
3. Thereafter, an epoxy resin-based insulating resin was printed at a place other than the protrusion.
At that time, printing was performed so that the resin did not cover the top of the protrusion.
The thickness of the resin was 15 μm, the height of the protrusion was 20 μm, and the step was designed to be 5 μm for printing.
4). The resin was heated and cured with a laser.
5. Next, using the same copper paste as in 2), a wiring circuit having a width of 20 μm and a height of 20 μm was printed on the surface of the resin.
Printing was performed so that the copper paste was covered on the protrusion formed in 2), and the protrusion and the circuit were printed so as to ensure conduction, and then only the printed circuit portion was heated and cured using a laser. .
6). Next, 300 columnar protrusions having a diameter of 20 μm and a height of 20 μm were printed on the surface of the circuit portion on the surface of the circuit portion using the copper paste ink used in 2) in order to establish conduction between the upper and lower layers. Thereafter, only the protrusions were heated and cured with a laser.
In the same manner as in 7.3), an epoxy resin was printed on portions other than the columnar protrusions, and heated and cured. In this case as well, the work was performed while confirming whether or not the resin was covered on the upper part of the protrusion by a continuity test.
The steps of 8.6) to 7) were repeated to produce a multilayer wiring board with 20 layers on one side.
9. Bumps for flip chip (diameter 20 μm, height 20 μm) were formed on the outermost surface, and heated and cured with a laser.
10. The produced multilayer wiring board was heated at 150 ° C. for 3 hours to sufficiently cure the resin, circuit, and protrusions.
11. Next, the glass plate used first was removed from the multilayer wiring board.
On the back side of the obtained multilayer wiring board, the end face of the protrusion embedded in the resin was exposed.
This part becomes the back pad. Using the pad portion on the back surface as a starting point, the formation of protrusions and the printing of the insulating resin were repeated to produce a multilayer wiring board with a total of 40 layers on the back and front surfaces, and electroless plating was performed by the method of Example 1. .
12 The W / B strength, soldering strength, and the like were the same as those in Example 1, and were equivalent to those produced by the conventional method.

実施例6
両面、多層配線板の層間に、電子部品(抵抗、コイル等の回路素子)を作り込む実施例
1.大きさA4サイズ、厚さ2mmのガラス板を用意した。
2.ガラス版の片面、バンプ、回路、パッドになる位置に、実施例2に用いた市販のWペーストを用いて、インクジェット方式で、バンプ、回路、パッドを印刷した。
3.還元雰囲気中(H+N)中でレーザーを用いて、W印刷部を加熱、焼結した。
4.次に、上層との導通用の柱状の突起(直径20μm、高さ20μm)を、前記Wペーストを用いて、回路部に立設した。
突起部を前記3)の方法で加熱、焼結した。
突起の数は、20個/2cmとした。
5.実施例2で用いたグリーンシートと同じ成分を突起の上に被らないように、低い高さ(15μm)印刷し、上下層間の絶縁層を形成し、前記3)と同じ工程で焼結した。
6.この時点で、下層の回路と突起が完全に接合し、導通が取れていることを確認した。
7.絶縁層の上に、回路、パッドを、Wペーストを用いて印刷した。
回路やパッドは、突起を通して上下層と導通した構造にした。
前記3)の工程で、パッド、回路を焼結した。
8.次に抵抗を印刷した。
抵抗は、パッドと導通が取れる設計にした。
抵抗の成分は、Ni微粉45質量%、Cr微粉45質量%、SiO5質量%、B5質量%からなるものに、水を加えて粘土状にしたものを3Dプリンターでくし状に印刷し、レーザーで加熱、焼結した。
9.更に回路上に、前記4)と同じ工程で、突起を立てた。
10.前記5)と同じ工程で、絶縁層を形成した。
11.前記7と同じ工程で、パッドや回路を印刷した。
12.次に層間にバリスターを作り込む
13.ZnO+SiC+ZnO−BiOの微粉と水とニトロセルロースを混合し、スラリー状にしたものをインクジェット方式で回路とパッドの間に印刷し、回路と導通できるように設計した。
レーザーを用いて焼結した。
特性をチェックし、性能を確認した。
14.前記9と同じ工程で突起を立て、焼結した。
15.前記5と同じ工程で絶縁層を作製し、焼結した。
16.最表面に実装用のパッド、フリップチップ実装用のバンプを形成し、焼結した。
17.パッドやバンプには、Ni−Auメッキを施した。
18.ガラス基板を外し、反対側にも同じ工程を繰り返し、最外層には、メッキを施した。いわゆる層間に電子部品を実装した両面多層配線板が得られた。
Example 6
Example 1 in which electronic components (circuit elements such as resistors and coils) are formed between both surfaces of a multilayer wiring board. A glass plate having a size of A4 and a thickness of 2 mm was prepared.
2. A bump, a circuit, and a pad were printed by an ink jet method using the commercially available W paste used in Example 2 at a position to become one side of the glass plate, a bump, a circuit, and a pad.
3. The W printing part was heated and sintered using a laser in a reducing atmosphere (H 2 + N 2 ).
4). Next, columnar protrusions (diameter 20 μm, height 20 μm) for conduction with the upper layer were erected on the circuit portion using the W paste.
The protrusion was heated and sintered by the method of 3).
The number of protrusions was 20/2 cm 2 .
5. In order not to cover the same components as the green sheet used in Example 2 on the protrusions, printing was performed at a low height (15 μm), an insulating layer between upper and lower layers was formed, and sintered in the same process as 3) above. .
6). At this point, it was confirmed that the underlying circuit and the protrusions were completely joined and conducted.
7). Circuits and pads were printed on the insulating layer using W paste.
Circuits and pads are structured to be connected to the upper and lower layers through protrusions.
In the step 3), the pad and the circuit were sintered.
8). The resistance was then printed.
The resistor was designed to be conductive with the pad.
The resistance component is composed of 45% by mass of Ni fine powder, 45% by mass of Cr fine powder, 5% by mass of SiO 2, and 5% by mass of B 2 O 3 , and is made into a clay by adding water to form a comb. Printed on, heated and sintered with a laser.
9. Further, protrusions were raised on the circuit in the same process as in 4).
10. An insulating layer was formed in the same step as 5).
11. Pads and circuits were printed in the same process as 7 above.
12 Next, create a varistor between the layers. A fine powder of ZnO + SiC + ZnO—BiO 3 , water, and nitrocellulose were mixed, and a slurry was printed between the circuit and the pad by an inkjet method, and designed to be electrically connected to the circuit.
Sintered using a laser.
The characteristics were checked and the performance was confirmed.
14 Protrusions were raised and sintered in the same process as 9 above.
15. An insulating layer was prepared and sintered in the same process as in 5.
16. A pad for mounting and a bump for flip chip mounting were formed on the outermost surface and sintered.
17. Ni-Au plating was applied to the pads and bumps.
18. The glass substrate was removed and the same process was repeated on the opposite side, and the outermost layer was plated. A double-sided multilayer wiring board having electronic components mounted between so-called layers was obtained.

実施例7
両面、多層配線板の層間に、既成の電子部品(抵抗、コイル等の回路素子)を作り込む実施例
1.大きさA4サイズ、厚さ2mmのガラス板を用意した。
2.ガラス版の片面、バンプ、回路、パッドになる位置に、実施例1に用いた導電性ペーストを用いて、バンプ、回路、パッドを印刷し、レーザーで加熱、硬化させた。
3.実施例1の方法で、絶縁樹脂を印刷した。その際、バンプ、回路、パッドには絶縁樹脂が覆い被らないように印刷し、加熱、硬化した。
4.回路部やパッド部に、直径20μm、高さ20μmの突起を200個立てた。
5.前記3)と同じ方法で、絶縁樹脂を高さ15μmで印刷、硬化させた。その際、突起に絶縁樹脂が覆い被らないように注意して印刷し、加熱、硬化させた。
6.突出した突起に既製のSAWフィルターを半田付けした。
使用した半田は、質量比で、Ag:Cu:Sn=3.0:0.5:96.5の割合で、これらの0.1〜2.0μの微粉を50質量%、ブチルセルソルブ10質量%、メチルセルロース10質量%、水30質量%を良く混和して3Dプリンターで印刷しやすい状態にしたもの。
7.更に別の突起には、市販のセラミックス製の抵抗を接合し、又別の突起には、樹脂上に形成されたアンテナを実装した。
8.残りの突起および絶縁樹脂に覆われていない回路の開口部に、高さ20μm、直径20μmの突起を立てた。
9.前記3)と同じ工程で、絶縁樹脂を印刷した。
10.この操作を繰り返して、片面20層の多層配線基板を作製した。
11.最外層には、半導体や電子部品を実装できるようにバンプやパッドを形成した。
12.得られた多層配線基板から、ガラス基板を外し、反対側にも同じ工程を繰り返し、最外層には、メッキを施した。いわゆる層間に電子部品を実装した両面多層配線板が得られた。
Example 7
Embodiment 1 In which existing electronic parts (circuit elements such as resistors and coils) are formed between both surfaces of a multilayer wiring board. A glass plate having a size of A4 and a thickness of 2 mm was prepared.
2. Bumps, circuits, and pads were printed on the glass plate on one side, bumps, circuits, and pads using the conductive paste used in Example 1, and heated and cured with a laser.
3. Insulating resin was printed by the method of Example 1. At that time, the bumps, circuits, and pads were printed so as not to cover the insulating resin, and were heated and cured.
4). 200 protrusions having a diameter of 20 μm and a height of 20 μm were erected on the circuit portion and the pad portion.
5. The insulating resin was printed and cured at a height of 15 μm by the same method as 3) above. At that time, printing was performed with care so that the insulating resin did not cover the protrusions, and heating and curing were performed.
6). A ready-made SAW filter was soldered to the protruding protrusion.
The used solder is a mass ratio of Ag: Cu: Sn = 3.0: 0.5: 96.5, and 50% by mass of these fine powders of 0.1 to 2.0 μ, butyl cellosolve 10 1% by mass, 10% by mass of methylcellulose, and 30% by mass of water are mixed well to make it easy to print with a 3D printer.
7). Furthermore, a commercially available ceramic resistor was joined to another protrusion, and an antenna formed on a resin was mounted on another protrusion.
8). Protrusions having a height of 20 μm and a diameter of 20 μm were raised at the remaining protrusions and the openings of the circuit not covered with the insulating resin.
9. Insulating resin was printed in the same step as 3).
10. This operation was repeated to produce a multilayer wiring board having 20 layers on one side.
11. On the outermost layer, bumps and pads were formed so that semiconductors and electronic components could be mounted.
12 The glass substrate was removed from the obtained multilayer wiring board, and the same process was repeated on the opposite side, and the outermost layer was plated. A double-sided multilayer wiring board having electronic components mounted between so-called layers was obtained.

実施例6、7によって、下記のことが判明した。
すなわち層間に既製のIC、電子部品を作り込むことにより、基板の厚みを大幅に減らすことが出来、最外層のスペースが広くなり、他の電子部品を実装できる余裕が生まれることが判明した。
本発明は、電子部品の軽薄短小化に多大なる貢献が出来ることが判明した。
Examples 6 and 7 revealed the following.
In other words, it has been found that by making off-the-shelf ICs and electronic components between the layers, the thickness of the substrate can be greatly reduced, the outermost layer space is widened, and there is room for mounting other electronic components.
It has been found that the present invention can make a great contribution to the reduction in the thickness and size of electronic components.

本発明は、半導体が実装される多層基板の多品種少量生産分野で、製造コストの低減と製作に必要な期間の短縮に著しく貢献するものであり、産業上極めて有用な発明である。また電子部品の軽薄短小化に多大な貢献ができるものである。  INDUSTRIAL APPLICABILITY The present invention contributes significantly to the reduction of manufacturing cost and the time required for manufacturing in the field of production of a large variety of multi-layer substrates on which semiconductors are mounted, and is an industrially extremely useful invention. In addition, it can greatly contribute to the miniaturization of electronic parts.

1 導電層 2 絶縁層(下)
3 絶縁層(上) 4 電気的導通路
1 Conductive layer 2 Insulating layer (bottom)
3 Insulating layer (top) 4 Electrical conduction path

Claims (10)

導電層と絶縁層が、複数層、交互に積層、接合されて形成されてなる多層配線板であって、該導電層は、該導電層の上に位置する絶縁層に側面まで埋入されてなると共に、上下に位置する導電層は、該上下の導電層に挟まれた絶縁層を貫通する電気的導通路で、互いに電気的に接続されてなる構造の多層配線板であって、
該多層配線板の立体構造を水平断面で薄層に分割して3Dデータ化して、該3Dデータを用いて、該薄層を3Dプリンターで印刷、硬化、積層させて形成してなることを特徴とする多層配線板。
A multilayer wiring board in which a conductive layer and an insulating layer are formed by alternately laminating and bonding a plurality of layers, and the conductive layer is embedded in the insulating layer located on the conductive layer to the side surface. The upper and lower conductive layers are multi-layer wiring boards having a structure in which they are electrically connected to each other through an electrical conduction path that penetrates the insulating layer sandwiched between the upper and lower conductive layers,
The three-dimensional structure of the multilayer wiring board is divided into thin layers in a horizontal section to form 3D data, and the thin layers are printed, cured and laminated by a 3D printer using the 3D data. A multilayer wiring board.
前記絶縁層を貫通する電気的導通路と、前記上下に位置する導電層の上位に位置する導電層との電気的接続が、該電気的導通路を該絶縁層表面よりも上に突出させ、該電気的導通路の突出部を、該上位に位置する導電層で包覆して接合してなる構造からなることを特徴とする請求項1に記載の多層配線板。  The electrical connection between the electrical conduction path that penetrates the insulating layer and the conductive layer that is located above the conductive layer located above and below makes the electrical conduction path protrude above the surface of the insulation layer, 2. The multilayer wiring board according to claim 1, wherein the protruding portion of the electrical conduction path is covered with a conductive layer positioned above and joined. 前記電気的導通路が、導電性突起構造からなる請求項1〜2のいずれか1項に記載の多層配線板。  The multilayer wiring board according to claim 1, wherein the electrical conduction path has a conductive protrusion structure. 前記導電層と電気的導通路は導電性インクを用いて、前記絶縁薄層は絶縁性インキを用いて、3Dプリンターで印刷した後、硬化させて形成したものである請求項1〜2のいずれか1項に記載の多層配線板。  The conductive layer and the electrical conduction path are formed using a conductive ink, and the insulating thin layer is formed using an insulating ink, printed with a 3D printer, and then cured. 2. The multilayer wiring board according to item 1. 前記導電性インクが、Cu、Ag、Au、Pt、Pd、Ni、Co、Mn、Mo、W、Sn、Pb、Bi、Al、In、Sb、Ti、Crの中から選択された一種あるいは一種以上の成分の合金あるいは混合物を主成分とするものである請求項4に記載の多層配線板。  The conductive ink is one or a kind selected from Cu, Ag, Au, Pt, Pd, Ni, Co, Mn, Mo, W, Sn, Pb, Bi, Al, In, Sb, Ti, and Cr. The multilayer wiring board according to claim 4, wherein the multilayer wiring board is mainly composed of an alloy or a mixture of the above components. 前記絶縁性インクが、有機系絶縁材料の粉末あるいは無機系絶縁材料の粉末あるいは有機系粉末と無機系粉末を混合した絶縁材料を主成分とするものであって、該有機系絶縁材料の粉末は、エポキシ、アラミド、ABS、ポリカーボネート、フェノール、ウレタン、フッ素、ポリアミド、アクリル、RETの中から選択された一種あるいは2種以上の樹脂粉末を混合したものであって、該無機系絶縁材料の粉末は、アルミナ、窒化アルミ、炭化ケイ素、シリカ、酸化硼素、窒化ケイ素、ガラス、ガラス繊維、カーボンナノチューブの中から選択された一種あるいは2種以上のセラミックス粉末を混合したものである請求項4に記載の多層配線板。  The insulating ink is mainly composed of an organic insulating material powder, an inorganic insulating material powder, or an insulating material obtained by mixing an organic powder and an inorganic powder, and the organic insulating material powder is: , Epoxy, aramid, ABS, polycarbonate, phenol, urethane, fluorine, polyamide, acrylic, RET, or a mixture of two or more resin powders, and the inorganic insulating material powder is The ceramic powder according to claim 4, which is a mixture of one or more ceramic powders selected from alumina, aluminum nitride, silicon carbide, silica, boron oxide, silicon nitride, glass, glass fiber, and carbon nanotube. Multilayer wiring board. 請求項1〜6のいずれか1項に記載の多層配線板表面の導電層にメッキが施されてなる多層配線板。  A multilayer wiring board obtained by plating the conductive layer on the surface of the multilayer wiring board according to any one of claims 1 to 6. 請求項1〜7のいずれか1項に記載の多層配線板の表面に電子部品を搭載した多層配線板。  The multilayer wiring board which mounted the electronic component on the surface of the multilayer wiring board of any one of Claims 1-7. 請求項1〜8のいずれか1項に記載の多層配線板の絶縁層の層間に、回路素子あるいは集積回路を実装してなる多層配線板。  A multilayer wiring board comprising a circuit element or an integrated circuit mounted between the insulating layers of the multilayer wiring board according to claim 1. 請求項1〜9のいずれか1項に記載の多層配線板の導電層と、該導電層を挟む上下二層の上の絶縁層と、該上の絶縁層を貫通する電気的導通路を形成するに際して、該導電層と電気的導通路を先に硬化処理した後、該上の絶縁層を硬化処理することを特徴とする多層配線板の製造方法。  A conductive layer of the multilayer wiring board according to any one of claims 1 to 9, an insulating layer on two upper and lower layers sandwiching the conductive layer, and an electrical conduction path penetrating the insulating layer on the upper side are formed. The method for producing a multilayer wiring board is characterized in that the conductive layer and the electrical conduction path are first cured, and then the insulating layer on the conductive layer is cured.
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