JP2015057849A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of performing in a semiconductor device as a three-dimensional device in which a three-dimensional convexoconcave part having side walls and a plane part on an upper portion is formed, uniform doping of a high-concentration impurity with low energy on the side walls and the plane part on the upper portion.SOLUTION: A semiconductor device manufacturing method comprises: a process of preparing a semiconductor substrate 1 serving as a base substrate of the semiconductor device, in which a silicon Fin part 11 which has side walls and a plane part on an upper portion with the side walls and a plane part other than the plane part on the upper part being covered with an insulation layer is formed on a surface of the semiconductor substrate 1 by processing; a process of depositing an impurity thin film containing an impurity atom serving as a donor or an acceptor on the side walls and the planer part on the upper portion of the silicon Fin part as a deposition film so as to be deposited thicker on the plane part on the upper portion and thinner on the side walls; and a process of performing oblique ion implantation from obliquely upward of the deposited film in the silicon Fin part and oblique ion implantation from oblique upward on the opposite side, and introducing the impurity atom by the ion implantation from the inside of the deposited film to inside of the side walls of the silicon Fin and inside of the plane part on the upper part by recoiling of the impurity atom.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for doping impurity atoms into a horizontal plane and a vertical wall of a three-dimensional three-dimensional structure device.

  A Fin (fin or fin) type FET (field effect transistor) will be described with reference to FIG. 2 as an example of a three-dimensional three-dimensional structure device related to the present invention.

A silicon fin portion 11 formed in a Fin type on the silicon substrate 1 is formed with a drain portion D, a channel portion, and a source portion S so as to cover the surface of the channel portion between the source portion S and the drain portion D. A portion made of polysilicon or metal of the gate electrode G is formed through the gate insulating film 9. In the source part S and the drain part D, it is necessary to introduce a high-concentration impurity exceeding 10 ²⁰ cm ⁻³ to lower the resistance. Reference numeral 16 denotes an insulating layer.

  As a method for doping the vertical walls of the source and drain portions of such a three-dimensional Fin-type FET, the present inventors have proposed the method shown in FIG. 3 (however, not disclosed). FIG. 3 is a cross-sectional view showing a region indicated by a broken line in FIG.

  In FIG. 3, a silicon fin portion 11 is formed on a silicon substrate 1 by etching using a hard mask 12 such as SiO 2 or SiN. Next, the planar portion (planar portion other than the silicon fin portion 11) of the silicon substrate 1 is covered with an insulating layer 16 such as SiO2, and both sides of the silicon fin portion 11 are left with the hard mask 12 used in the etching process remaining. A deposited film 2 containing boron B is deposited on the wall with plasma (FIG. 3a). At this time, the deposited film 2 is also formed on the insulating layer 16 which is an insulating film, but is removed later.

  Next, heavy ions such as Ge and Xe are implanted by irradiating the ion beam 5 obliquely from the upper left side of the silicon fin portion 11. Then, an electroactive impurity in silicon, which is present in the deposited film 2 by a knock-on effect described later, is introduced into the left side wall of the silicon fin portion 11 (FIG. 3a). Subsequently, the ion beam 5 is obliquely irradiated from the upper right side of the silicon fin portion 11 to implant heavy ions such as Ge and Xe. Then, the electroactive impurities in the silicon in the deposited film 2 are introduced into the right side wall of the silicon fin portion 11 (FIG. 3b). As a result, impurity diffusion layers 3 are formed in both side walls of the silicon fin portion 11 (FIG. 3c). Thereafter, the deposited film 2 is removed (FIG. 3d). The incident angle of the ion beam 5 with respect to the side wall of the silicon fin portion 11 (angle formed with respect to the vertical line) is preferably within 20 degrees and about 10 degrees.

  In the Fin-type FET produced by this method, the upper part of the silicon Fin portion 11 is not used as the channel region of the transistor. However, the use of the upper portion of the silicon fin portion 11 as a channel also makes it possible to reduce the height of the silicon fin portion 11 and increase the fin width (the size in the horizontal direction in FIG. 3), which is advantageous in production. . Further, the drive current can be increased, and the characteristics can be improved. This type of Fin-type FET is called TriFET. In that case, it is necessary to introduce an impurity having a concentration almost the same as that of the lower side wall into the upper side wall of the silicon fin portion 11, that is, the flat portion on the upper side of the silicon fin portion 11.

  However, the method proposed by the present inventors does not consider introduction of impurities into the planar portion above the silicon fin portion. Therefore, the upper part of the silicon Fin portion cannot be used effectively, and a Fin type FET with inferior drive current is obtained.

  An object of the present invention is to improve the doping method of impurity atoms to the planar portion and the side wall portion of the three-dimensional uneven portion of the three-dimensional structure device.

  A specific object of the present invention is to provide a method for diffusing an impurity having a concentration similar to that of a side wall portion into a planar portion of an upper portion of a silicon Fin portion in a three-dimensional structure device, for example, a Fin-type FET.

  A method for manufacturing a semiconductor device according to the present invention includes forming a three-dimensional concavo-convex portion in a semiconductor substrate that is a base of a semiconductor device by processing such as etching, and includes impurity atoms that can be carrier impurity atoms that become donors or acceptors inside the semiconductor substrate. The thin film is thickly deposited on the planar portion of the upper portion of the three-dimensional uneven portion, while being thinly deposited on the side wall portion of the three-dimensional uneven portion, and has an atom (heavier in atomic weight) than an impurity atom that becomes an electric carrier in the semiconductor substrate. By implanting ions of atoms) obliquely from above the three-dimensional uneven portion, impurity atoms are introduced into the side wall portion including the upper portion of the three-dimensional uneven portion using the recoil effect due to knock-on of ion implantation. At that time, the amount of introduced impurity atoms is adjusted by the thickness of the thin film, that is, the deposited film, and the phenomenon that the introduced amount of impurity atoms is reduced in the portion where the deposited film thickness is large is used. The amount of introduction of impurity atoms in the flat portion is the same. For this purpose, ion implantation in an oblique direction from obliquely above the three-dimensional uneven portion is performed twice from two oblique directions opposite to each other, and a side wall portion is formed on the flat portion on the upper portion of the three-dimensional uneven portion by one implantation. The principle of selecting the deposited film thickness at which about half of the impurity atoms are knocked on is used. If the ion implantation angle (angle between the direction perpendicular to the upper plane portion) is, for example, 10 °, the ion implantation angle with respect to the side wall surface of the three-dimensional uneven portion (angle between the direction perpendicular to the side wall surface) is 80. As will be described in detail later, since the actual dose amount is 17.6% defined by cos80 ° / cos10 ° compared to the upper surface of the three-dimensional uneven portion (upper flat portion), the three-dimensional uneven portion On the upper surface of the film, it is deposited with a sufficiently thick film thickness corresponding to it. In general, the deposited film by plasma is thick on the top surface of the three-dimensional uneven portion because it can control the coverage of the film deposition on the side wall and the upper surface of the three-dimensional uneven portion, and it is natural to deposit thinly on the side wall, and any formation is easy It is.

  According to an aspect of the present invention, a side wall portion and an upper flat portion are formed by processing on a surface of a semiconductor substrate which is a base of a semiconductor device, and a flat portion other than the side wall portion and the upper flat portion is an insulating layer. The semiconductor substrate on which the three-dimensional uneven portion covered with is formed is prepared, and an impurity thin film containing impurity atoms serving as donors or acceptors inside the semiconductor substrate is deposited on the surface of the semiconductor substrate. The impurity thin film is deposited thicker on the planar portion of the upper portion of the three-dimensional uneven portion than the side wall portion, and further, obliquely opposite to the ion implantation in the oblique direction from obliquely above the deposited impurity thin film of the three-dimensional uneven portion. In addition to performing ion implantation in an oblique direction from above, the impurity atoms are transferred from the inside of the impurity thin film to the side wall portion of the three-dimensional uneven portion of the semiconductor substrate by the ion implantation. The method of manufacturing a semiconductor device characterized by comprising the step of recoil inside the plane portion of the upper is provided. It is important that an impurity amount approximately half of the impurity amount introduced into the side wall portion in one ion implantation is introduced into the upper plane portion. In the ion implantation from the left and right sides of the upper part, it is concluded that the impurity introduction amounts of the side wall part and the upper flat part are almost the same.

  Several preferred embodiments are described below.

  The impurity introduction ratio to the side wall portion of the three-dimensional uneven portion and the upper flat portion is adjusted by adjusting the deposition thickness ratio between the side wall portion of the three-dimensional uneven portion and the upper flat portion.

  By adjusting the implantation angle in the oblique direction from the upper side of the ion implantation, the impurity introduction ratio into the side wall portion of the three-dimensional uneven portion and the upper planar portion is adjusted.

  By adjusting the deposition thickness ratio between the side wall portion of the three-dimensional uneven portion and the upper flat portion and adjusting the implantation angle in the oblique direction from the upper side of ion implantation, the side wall portion and the upper flat portion of the three-dimensional uneven portion It is configured to adjust the impurity introduction ratio.

  By adjusting the deposition thickness ratio between the side wall portion of the three-dimensional uneven portion and the upper flat portion and adjusting the implantation angle in the oblique direction from the upper side of ion implantation, the side wall portion and the upper flat portion of the three-dimensional uneven portion The impurity is introduced at a ratio of substantially 2 to 1.

  By performing both ion implantations from one oblique upper side and ion implantation from the opposite oblique upper side, substantially the same amount of impurities is introduced into the side wall portion and the upper flat portion of the three-dimensional uneven portion.

  The deposition thickness ratio between the side wall portion of the three-dimensional uneven portion and the upper planar portion is preferably such that the deposition thickness of the upper flat portion is at least twice the deposition thickness of the side wall portion of the three-dimensional uneven portion. .

  By adjusting the setting of the sidewall thin film thickness and the upper planar thickness of the impurity thin film, the impurity deposition material species, and the ion implantation, implantation ion species, implantation angle, implantation energy, or implantation dose amount. , The recoil condition, or the dose atomic weight corresponding to the implantation dose is controlled.

  Impurity atoms of the impurity thin film are any one of B, P, and As.

  As the impurity thin film, an impurity thin film containing B is deposited by plasma treatment using a gas containing diborane B2H6 or BF3.

  As the impurity thin film, an impurity thin film containing P is deposited by plasma treatment using a gas containing phosphine PH3.

  As the impurity thin film, an impurity thin film containing As is deposited by plasma treatment using a gas containing arsine AsH3.

  In the ion implantation step, the implanted ions are ions of heavy atoms having an atomic weight larger than any of B, P, and As which are impurity atoms of the impurity thin film.

  In the ion implantation step, an ion to be implanted is any one of Si, As, Ge, In, Sb, Xe, and Ar.

  The beam incident angle from the upper side of the ion implantation to the surface of the three-dimensional uneven portion of the semiconductor substrate is set to an inclination angle of substantially 20 ° or less.

  In the surface portion of the three-dimensional uneven portion of the semiconductor substrate, the impurity atoms of the impurity thin film are implanted into the semiconductor substrate from the impurity thin film in a direction substantially perpendicular to the surface (substantially perpendicular direction) by implanted ions. It is recoiled inside the surface by knocking-on collision with impurity atoms.

  The ion implantation is a low energy implantation of 5 keV or less.

  The ion implantation is performed at a low dose implantation atomic weight of 2E15 cm −2 or less.

  The impurity thin film is deposited thickly on a planar portion on the surface of the semiconductor substrate other than the three-dimensional uneven portion.

  The deposition rate of the impurity thin film deposited by the plasma treatment on the semiconductor substrate plane other than the three-dimensional uneven portion is large, and the deposition rate on the side surface of the three-dimensional uneven portion is made smaller than the semiconductor substrate plane to be thick in the semiconductor substrate plane. Deposit an impurity thin film.

  At this time, by constructing so that the deposition rate of the deposited film deposited by the plasma treatment on the semiconductor substrate plane is large and the deposition rate on the side wall of the three-dimensional uneven portion is smaller than that of the semiconductor substrate plane, On the surface of the substrate, a deposited film that is thicker than the deposited film formed on both side walls of the three-dimensional uneven portion is formed.

  After that, an ion beam is injected into the both side walls of the step of the three-dimensional uneven portion from two obliquely upward directions, so that a sufficient dose amount as a source / drain is uniformly placed on both side walls of the step of the three-dimensional uneven portion. A diffusion layer can be formed. The two obliquely upward directions are directions defined by an inclination angle (acute angle) in which the ion implantation angle θ from a perpendicular perpendicular to the plane of the semiconductor substrate is substantially 20 ° or less.

  According to the present invention, the same amount of impurities as that of the side wall portion of the three-dimensional uneven portion can be doped into the flat portion on the upper portion of the three-dimensional uneven portion formed on the semiconductor substrate.

FIG. 5 shows an ion implantation process flow according to an embodiment of the present invention. It is a perspective view for demonstrating Fin type FET to which this invention is applied. It is a figure for demonstrating the process flow of the manufacturing method of Fin type FET by the present inventors' proposal. It is a figure for demonstrating the relationship between the ion implantation angle for making the impurity diffusion amount the same, and the deposited film thickness formed in the upper plane part and side wall of a silicon | silicone Fin part. It is a characteristic view showing the relationship between the ion implantation angle, the deposited film thickness, and the amount of impurities introduced into silicon (semiconductor substrate). It is a figure for demonstrating the process flow of the manufacturing method of the Example at the time of applying this invention to manufacture of CMOS FET. It is a figure for demonstrating the recoil effect | action by the ion implantation of this invention. It is the figure which expanded and showed the recoil effect | action of FIG.

  An ion implantation process flow according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a region indicated by a broken line in FIG.

  First, the silicon fin portion 11 as described above is formed on the surface of the silicon substrate 1 by processing such as etching. Next, as shown in FIG. 1A, the planar portion of the silicon substrate 1 other than the silicon fin portion 11 is covered with an insulating layer 6 which is an insulating film made of SiO 2 or the like, and the same plasma treatment as described in FIG. A deposition film 2 containing a P-type or N-type impurity, for example, B, is deposited on the side wall of the silicon fin portion 11 by a method such as that described above, while a deposition film thicker than the deposition film 2 is deposited on the planar portion above the silicon fin portion 11. Deposit 2 '. Subsequently, an ion beam 5 of heavy ions made of impurities having a larger mass than the impurities in the deposited films 2, 2 ′ (atomic weight), for example, Xe, Ge, etc. is obliquely irradiated from the upper left side of the silicon fin portion 11. By implanting heavy ions, the electroactive impurities in the deposited films 2, 2 ′ in the deposited film 2, 2 ′, which will be described later, in the left side wall portion of the silicon fin portion 11 and in the planar portion on the upper portion of the silicon fin portion 11 To introduce. As a result, the impurity diffusion layer 3 is formed in the left side wall portion of the silicon fin portion 11, but the dose amount about half of that in the impurity diffusion layer 3 is formed in the upper planar portion of the silicon fin portion 11. This is a low impurity diffusion layer 4. The reason will be explained later.

  Subsequently, as shown in FIG. 1B, the heavy ion beam 5 made of impurities such as Xe, Ge, etc. used in FIG. By implanting ions, impurities that are electroactive in the silicon in the deposited films 2, 2 ′ are introduced into the right side wall portion of the silicon fin portion 11 and the planar portion above the silicon fin portion 11. As a result, the impurity diffusion layer 3 is formed in the side wall portions of the silicon fin portion 11, and the impurity diffusion layer 3 ′ is formed in the upper planar portion of the silicon fin portion 11.

  Here, the impurity dose amount (dose amount of the impurity diffusion layer 3) into the both side walls of the silicon fin portion 11 due to the ion beam 5 irradiation, and the impurity dose amount (impurity diffusion layer into the planar portion above the silicon fin portion 11). The 3 ′ dose) is preferably equal (conformal doping). In other words, in FIG. 1A or FIG. 1B, the amount of impurities introduced into the side wall portion of the silicon fin portion 11 and the amount of impurities introduced into the planar portion above the silicon fin portion 11 at that time are substantially equal. It is preferable that the ratio is 2: 1. For this purpose, the incident angle of the ion beam 5 (the angle formed with respect to the vertical line or the side wall surface of the silicon fin portion 11), the thickness t1 of the deposited film 2 and the thickness t2 of the deposited film 2 ′ (see FIG. 4). ) Is preferably set as follows.

  Referring to FIG. 4, the incident angle of the ion beam 5 with respect to the side wall surface of the silicon fin portion 11 (angle formed with respect to the vertical line) is set within 20 degrees in both FIG. 1 (a) and FIG. 1 (b). About 10 degrees is preferable. When the incident angle of the ion beam 5 is 10 degrees, the ion implantation angle to the side wall surface of the silicon fin portion 11 is 80 degrees, which is compared with the ion implantation angle 10 degrees to the planar portion on the upper side of the silicon fin section 11. The dose amount is cos 80 ° / cos 10 ° = 0.174. In other words, if only the dose amount Nd = 1E14 is required on the side wall of the silicon fin portion 11, the dose amount to the upper planar portion of the silicon fin portion 11 is 5.64E14. Therefore, the thickness t2 of the deposited film 2 ′ above the silicon fin portion 11 is compared with the thickness t1 of the deposited film 2, so that the dose amount into the planar portion above the silicon fin portion 11 is increased to the side wall of the silicon fin portion 11. It is possible to perform conformal doping by selecting and setting a value that is ½ of the dose amount and performing ion implantation with an ion beam of heavy ions. The thickness t2 of the deposited film 2 'is preferably at least twice the thickness t1 of the deposited film 2, and preferably t2: t1 = 10: 3. On the other hand, Xe is preferable to Ge for heavy ions.

  FIG. 5 shows the relationship between the ion implantation angle (90-θ) with respect to the side wall of the silicon fin portion, the deposited film thickness, and the impurity dose to the silicon substrate, and the ion implantation angle θ with respect to the planar portion above the silicon fin portion and the deposition. The relationship between the film thickness and the impurity dose to the silicon substrate is shown.

  Returning to FIG. 1, after the processing of FIG. 1 (b), the deposited films 2, 2 'are removed (FIG. 1c).

  When forming the deposited film by plasma treatment, the planar portion of the silicon substrate 1 other than the silicon fin portion is covered with the insulating layer, so that the deposited film is formed on the insulating layer. In this case, even if impurities are introduced into the insulating layer by performing heavy ion implantation by ion beam irradiation, there is no influence on the electrical characteristics of the device because it is an insulating layer and no problem occurs. Further, the thickness of the deposited film formed on the planar portion of the silicon substrate is larger than the thickness of the deposited film formed on the sidewall of the silicon fin portion, but there is no problem. The above points are the same in the embodiments described later.

  Next, an embodiment of the present invention will be described with reference to FIG.

  The present embodiment shows a process flow for forming a CMOS (Complementary Metal Oxide Semiconductor) FET. In this case, a deposited film containing P (phosphorus) and B (boron) is selectively formed on each of the N-type and P-type device regions, and N-type and P-type MOSFETs are formed by two mask alignments. In this method, extension regions of both types (hereinafter referred to as an N-type MOS portion and a P-type MOS portion, respectively) are formed on the same substrate as an N-type-Fin portion and a P-type-Fin portion.

  In FIG. 6, for the sake of convenience, as described in FIG. 2, a drain Fin portion (portion indicated by D in FIG. 2), channel, and the like are formed on the silicon Fin portion formed on the silicon substrate 1 by etching or the like. Sectional view when CMOSFETs composed of a Fin portion (the portion indicated by G in FIG. 2) and a source Fin portion (portion indicated by S in FIG. 2) are formed as an N-type MOS portion and a P-type MOS portion, respectively. Is shown. In particular, FIG. 6 is a cross-sectional view showing a Fin portion that is one of the source and drain of the N-type MOS portion and the P-type MOS portion, and a Fin portion that is the other of the source and drain of the N-type MOS portion and the P-type MOS portion. ing.

  In step (1) of FIG. 6 (upper left figure), a plane other than the surface of the P-Fin portion (P-Fin) that becomes the P-type MOS portion and the surface of the N-Fin portion (N-Fin) that becomes the N-type MOS portion in advance. The part is covered with an insulating layer 6. Subsequently, in a state where one N-Fin portion (N-Fin) serving as an N-type MOS portion is covered with a resist 61, the other surface of the P-Fin portion (P-Fin) serving as a P-type MOS portion ( A deposited film 2, 2 ′ having B (boron) on the side wall portion and the upper flat portion is deposited by plasma 22 as in FIG.

  Next, in step (2) (upper right diagram of FIG. 6), the N-Fin portion that becomes the N-type MOS portion is covered with the resist 61, and Xe ( Alternatively, heavy ions are implanted by sequentially irradiating the ion beam 5 of Ge) from the upper right (or upper left) diagonal direction and the upper left (or upper right) diagonal direction.

  In step (3) (the lower left diagram in FIG. 6), first, the resist 61 in the N-type MOS portion is removed. At the same time, the deposited films 2, 2 'in the P-type MOS portion are also removed. After that, with the P-Fin portion that becomes the P-type MOS portion covered with the resist 61 ', deposition with P (phosphorus) on the surface (side wall portion, upper flat portion) that becomes the N-type MOS portion Films 2-1 and 2-1 'are deposited with plasma 22' as in FIG.

  Next, in step (4) (lower right diagram in FIG. 6), the P-Fin portion that becomes the P-type MOS portion is covered with the resist 61 ′, and Xe is added to the N-Fin portion on the N-type MOS portion side. (Or Ge) ion beam 5 'is irradiated in this order from the upper right (or upper left) diagonal direction and the upper left (or upper right) diagonal direction to implant heavy ions. Thereafter, the deposited films 2-1 and 2-1 'on the N-type MOS portion side are removed together with the removal of the resist 61'.

  As described above, the N-type MOS portion having the impurity diffusion layers 3-1 and 3-1 ′ having a uniform dose amount on the side wall portion and the upper planar portion of the N-Fin portion (N-Fin), and P A pair of source-drain is formed by forming a P-type MOS portion having impurity diffusion layers 3 and 3 ′ having a uniform dose amount on the side wall portion and the upper plane portion of the -Fin portion (P-Fin). It is formed.

  7 and 8 are views for explaining the recoil action according to the embodiment of the present invention. Here, the case of step (2) in the upper right of FIG. 6 will be described, but only the portions necessary for the description are shown in both FIG. 7 and FIG.

  In FIG. 7, the impurity of the deposited film 2 is introduced from the deposited film 2 into the silicon Fin part 11 on the surface portion of the silicon Fin part 11 of the silicon substrate 1 by ion beam irradiation in the oblique direction from the upper left side with respect to the silicon Fin part. The atoms B are recoiled inside the silicon fin portion 11 by the knocking-on that collides with each other in a direction substantially perpendicular to the surface (substantially perpendicular direction).

  Normally, when a particle (atom / ion) accelerated at high speed enters a solid or liquid substance, it gradually loses energy while colliding with the atoms constituting the substance, and finally the substance Stops when the energy of the incident particle drops to a lower energy than the potential produced by. During this time, in the energy region used for normal ion implantation, dozens to thousands of atoms in the material receive energy.

  FIG. 7 shows the movement of one incident particle in order to facilitate understanding of the recoil action based on the above principle, but in actuality, as shown in an enlarged view in FIG. A ball clash is happening.

  In particular, when the mass of the incident particles is heavier than the material constituent atoms of the deposited film, it is possible to give energy to more constituent atoms, and it is possible to introduce much more target atoms into the semiconductor substrate than the number of incident particles. . Furthermore, since the energy of ions to be implanted can be set higher than the energy given to the target atom, the space charge effect can be suppressed lower than that of direct implantation, and the beam current can be increased.

[Effect of the embodiment]
As described above, according to the embodiment of the present invention, the impurities are uniformly introduced into all of the walls and the upper planar portion of the three-dimensional structure by the deposited thin film by plasma and the recoil (knock-on effect) action by ion implantation. be able to.

  Although the present invention has been described with reference to preferred embodiments, it is needless to say that the present invention is not limited to the above-described embodiments.

  For example, the solid substance which becomes the base of the semiconductor device is solid silicon (silicon to single crystal (single crystal) or poly (polycrystal)), GaAs, Ge, SiC, compound semiconductor, and the like.

  In addition, the recoil condition, the adjustment of the film thickness of the impurity thin film (deposited film), the setting of the impurity deposition material species, the adjustment of the ion implantation, the implantation ion species, the implantation angle, the implantation energy, or the implantation dose amount, That is, it is desirable to control the energy corresponding to the implantation of the impurity in the impurity thin film (depth corresponding to the implantation depth to the profile) or the dose atomic amount corresponding to the implantation dose.

  In this case, the thickness of the impurity thin film, the impurity deposition material species, the implanted ion species, or the ions are not introduced so that the ions themselves are hardly introduced into the three-dimensional uneven portion formed by processing the semiconductor substrate and remain in the impurity thin film. A non-injection condition may be set and adjusted by adjusting the setting of the implantation angle, implantation energy, or implantation dose.

  As impurity atoms of the impurity thin film, As may be used in addition to B and P.

  As the gas used for depositing the impurity thin film containing B by plasma treatment, a gas containing BF3 may be used instead of diborane B2H6.

  On the other hand, a preferred example of a gas used for depositing an impurity thin film containing P by plasma treatment is a gas containing phosphine PH3.

  A preferable example of a gas used for depositing an impurity thin film containing As by plasma treatment is a gas containing arsine AsH3.

  As the implanted ions in the ion implantation step, any one of Si, As, Ge, In, Sb, Xe, and Ar can be used.

  Note that after forming a deposited film containing B by plasma treatment with B2H6, the entire surface of the semiconductor substrate is covered with a resist protective film, and the resist protective film is selectively removed to expose the exposed portion of the B. Next, the deposited film containing P is formed in the removed portion by plasma treatment with PH3, and the entire resist protective film is removed, and then Ge, Si, As, In, Sb or Xe is removed. A process of implanting Ar ions over the entire surface of the semiconductor substrate may be configured.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2, 2 'Deposited film 3, 3', 4 Impurity diffusion layer 5 Ion beam 6, 16 Insulating layer 11 Silicon Fin part 12 Hard mask

Claims (6)

On the surface of the semiconductor substrate which is the base of the semiconductor device, a three-dimensional concavo-convex portion having a side wall portion and an upper flat portion by processing, and a flat portion other than the side wall portion and the upper flat portion covered with an insulating layer is formed. Preparing the formed semiconductor substrate,
By depositing an impurity thin film containing an impurity atom serving as a donor or acceptor inside the semiconductor substrate on the surface of the semiconductor substrate, the planar portion on the upper portion of the three-dimensional uneven portion is compared with the side wall portion of the three-dimensional uneven portion. Deposit a thin impurity film,
In addition, while performing ion implantation in an oblique direction from obliquely above the opposite side to the ion implantation in the oblique direction from the obliquely upward of the deposited impurity thin film of the three-dimensional uneven portion,
A method of manufacturing a semiconductor device, comprising: a step of recoiling the impurity atoms from the inside of the impurity thin film into the side wall portion and the upper planar portion of the semiconductor substrate by the ion implantation.   The structure is such that substantially the same amount of impurities is introduced into the side wall portion and the upper planar portion of the three-dimensional uneven portion by both ion implantation from one oblique upper side and ion implantation from the other oblique upper side. A method for manufacturing a semiconductor device according to claim 1.   3. The method of manufacturing a semiconductor device according to claim 2, wherein a beam incident angle from obliquely above the ion implantation with respect to the surface of the three-dimensional uneven portion of the semiconductor substrate is set to an inclination angle of substantially 20 ° or less.   4. The method of manufacturing a semiconductor device according to claim 1, wherein an impurity atom of the impurity thin film is any one of B, P, and As. 5.   5. The semiconductor according to claim 4, wherein in the ion implantation step, the implanted ions are ions of heavy atoms having an atomic weight larger than any of B, P, and As which are impurity atoms of the impurity thin film. Device manufacturing method.   In the surface portion of the three-dimensional uneven portion of the semiconductor substrate, the impurity atoms of the impurity thin film collide with the impurity atoms by the implanted ions in the direction substantially perpendicular to the surface from the impurity thin film to the semiconductor substrate. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the coil is recoiled inside the surface by a knock-on effect.

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