JP2015046468A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2015046468A JP2015046468A JP2013176460A JP2013176460A JP2015046468A JP 2015046468 A JP2015046468 A JP 2015046468A JP 2013176460 A JP2013176460 A JP 2013176460A JP 2013176460 A JP2013176460 A JP 2013176460A JP 2015046468 A JP2015046468 A JP 2015046468A
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- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
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- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
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- 229910052727 yttrium Inorganic materials 0.000 description 1
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- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
【解決手段】ポリイミド膜PIとゲート電極GEとの間にひずみ緩和膜RFを設けることによって、ポリイミド膜PIから電子供給層ESおよびチャネル層CHに印加される応力を抑制し、電子供給層ESおよびチャネル層CHに生じる応力ひずみを抑える。これにより、チャネル層CHにおけるチャネル電子濃度の変化を抑制して、パワーMISFETのしきい値電圧またはオン抵抗の変動を防止する。
【選択図】図3
Description
<関連技術の説明>
まず、実施の形態1におけるパワーMISFETについて説明する前に、関連技術におけるパワーMISFETについて説明する。図1は、関連技術におけるパワーMISFETの構成例を示す断面図である。
実施の形態1におけるパワーMISFETの構成例を図2および図3を用いて説明する。図2は、実施の形態1におけるパワーMISFETの一部を拡大して示す平面図である。図3は、図2のA−A線で切断した断面図である。
ここで、実施の形態1におけるパワーMISFETの特徴について以下に説明する。
実施の形態1におけるパワーMISFETの製造方法を図4〜図11を参照しながら説明する。図4〜図11は、パワーMISFETの断面図である。
<実施の形態2におけるパワーMISFETの構成>
実施の形態2におけるパワーMISFETは、ひずみ緩和膜RFの形状が、前述の実施の形態1におけるパワーMISFETと相違する。すなわち、前述の実施の形態1では、ひずみ緩和膜RFはゲート電極GEの上方に孤立して、フローティング状態で形成されている。しかしながら、実施の形態2では、ひずみ緩和膜RFはゲート電極GEの上方に形成され、かつ、ソース電極SEと繋がっている。すなわち、ひずみ緩和膜RFとソース電極SEとは一体に形成されている。
<実施の形態3におけるパワーMISFETの構成>
実施の形態3におけるパワーMISFETは、平面視において、隣り合うアクティブ領域ACの間に、電子供給層ESおよびチャネル層CHに生じる応力ひずみを抑制することのできる膜を設ける。
ここで、実施の形態3におけるパワーMISFETの特徴について以下に説明する。
前述の実施の形態3におけるパワーMISFETにおいても、前述した実施の形態1、2と同様にして、複数のゲート電極GEの上方に複数のひずみ緩和膜RFを形成することができる。
<実施の形態4におけるパワーMISFETの構成>
実施の形態4におけるパワーMISFETは、複数のドレインバス電極DLの下方に複数のダミーパタンを設けた点が、前述の実施の形態3におけるパワーMISFETと相違する。
AC アクティブ領域(活性領域)
BF バッファ層
CH チャネル層
DE ドレイン電極
DL ドレインバス電極(ドレインバスバー、ドレイン配線)
DP ドレインパッド
DUM ダミーパタン
ES 電子供給層
GE ゲート電極
GL1 第1ゲートバス電極(第1ゲートバスバー、第1ゲート配線)
GL2 第2ゲートバス電極(第2ゲートバスバー、第2ゲート配線)
GOX ゲート絶縁膜
GP ゲートパッド
IL1 第1層間絶縁膜
IL1 第2層間絶縁膜
MF 積層膜
OP1 ソースコンタクトホール
OP2 ドレインコンタクトホール
PI ポリイミド膜
PRO 保護膜
RF ひずみ緩和膜
SE ソース電極
SL ソースバス電極(ソースバスバー、ソース配線)
SP ソースパッド
TR トレンチ(溝)
Claims (20)
- 窒化物半導体層と、
アクティブ領域の前記窒化物半導体層上に第1絶縁膜を介して形成され、第1方向に延在するゲート電極と、
前記ゲート電極を覆うように形成された第2絶縁膜と、
前記ゲート電極の一方の側面側に前記ゲート電極と互いに離間して、前記第2絶縁膜に形成され、前記第1方向に延在する第1コンタクトホールと、
前記ゲート電極の他方の側面側に前記ゲート電極と互いに離間して、前記第2絶縁膜に形成され、前記第1方向に延在する第2コンタクトホールと、
前記第1コンタクトホールの内部に形成され、前記窒化物半導体層と電気的に接続するソース電極と、
前記第2コンタクトホールの内部に形成され、前記窒化物半導体層と電気的に接続するドレイン電極と、
前記ゲート電極の上方の前記第2絶縁膜上に形成されたひずみ緩和膜と、
前記ソース電極、前記ドレイン電極、および前記ひずみ緩和膜を覆うように形成された第3絶縁膜と、
前記第3絶縁膜上に形成された樹脂膜と、
を有する、半導体装置。 - 請求項1記載の半導体装置において、
前記ひずみ緩和膜は前記ソース電極と同一層である、半導体装置。 - 請求項1記載の半導体装置において、
前記ひずみ緩和膜は前記ソース電極と同一層であり、前記ひずみ緩和膜と前記ソース電極とは一体に形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記ひずみ緩和膜はアルミニウム合金膜を含む、半導体装置。 - 請求項4記載の半導体装置において、
前記アルミニウム合金膜はアルミニウム−銅合金膜またはアルミニウム−シリコン−銅合金膜である、半導体装置。 - 請求項1記載の半導体装置において、
前記ひずみ緩和膜は、下層からチタン膜、窒化チタン膜、アルミニウム合金膜、および窒化チタン膜を順次積層した積層膜、または下層からチタン膜、アルミニウム合金膜、および窒化チタン膜を順次積層した積層膜からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記ひずみ緩和膜は熱に対して引張応力が発生する材料からなり、前記樹脂膜は熱に対して圧縮応力が発生する材料からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記樹脂膜はポリイミド膜である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1コンタクトホールおよび前記第2コンタクトホールが、前記アクティブ領域から前記第1方向にはみ出している、半導体装置。 - 窒化物半導体層と、
前記窒化物半導体層上に第1絶縁膜を介して形成されたゲートパッドと、
前記ゲートパッドから第1方向に突き出た第1ゲートバス電極と、
前記第1ゲートバス電極から前記第1方向と直交する第2方向に突き出た複数の第2ゲートバス電極と、
前記ゲートパッド、前記第1ゲートバス電極、および前記複数の第2ゲートバス電極を覆うように形成された第2絶縁膜と、
前記第2絶縁膜上に形成されたソースパッドと、
前記ソースパッドから前記第2方向に突き出た複数のソースバス電極と、
前記第2絶縁膜上に形成され、前記ソースパッドと前記第2方向に対向して、互いに離間して設けられたドレインパッドと、
前記ドレインパッドから前記第2方向と反対方向に突き出た複数のドレインバス電極と、
前記複数のソースバス電極および前記複数のドレインバス電極を覆うように形成された第3絶縁膜と、
前記第3絶縁膜上に形成された樹脂膜と、
を有し、
前記複数のソースバス電極のそれぞれと、前記複数のドレインバス電極のそれぞれとが、平面視において、前記第1方向に沿って互い違いに配置され、
前記複数のソースバス電極のそれぞれと、前記複数の第2ゲートバス電極のそれぞれとが、前記第2絶縁膜を介して上下に重なるように配置されている、半導体装置。 - 前記10記載の半導体装置において、
前記複数のソースバス電極のそれぞれと、前記複数のドレインバス電極のそれぞれとに挟まれるように、平面視において、前記第2方向に延在する複数のアクティブ領域が設けられている、半導体装置。 - 請求項10記載の半導体装置において、さらに、
前記複数のドレインバス電極の下方の前記第2絶縁膜下に形成された複数のダミーパタン、
を有し、
前記複数のドレインバス電極のそれぞれと、前記複数のダミーパタンのそれぞれとが、前記第2絶縁膜を介して上下に重なるように配置されている、半導体装置。 - 請求項12記載の半導体装置において、
前記複数のダミーパタンは、前記第1ゲートバス電極および前記複数の第2ゲートバス電極と同一層である、半導体装置。 - 前記10記載の半導体装置において、さらに、
前記複数のソースバス電極のそれぞれから前記第1方向に突き出た複数のソース電極と、
前記複数のドレインバス電極のそれぞれから前記第1方向に突き出た複数のドレイン電極と、
前記複数の第2ゲートバス電極のそれぞれから前記第1方向に突き出た複数のゲート電極と、
を有し、
平面視において、前記複数のソース電極のそれぞれと、前記複数のドレイン電極のそれぞれとが、前記第2方向に沿って互い違いに配置され、
平面視において、前記複数のソース電極のそれぞれと、前記複数のドレイン電極のそれぞれとに挟まれるように、前記複数のゲート電極が設けられている、半導体装置。 - 請求項14記載の半導体装置において、さらに、
前記複数のゲート電極の上方の前記第2絶縁膜上に複数のひずみ緩和膜を有し、
前記複数のゲート電極のそれぞれと、前記複数のひずみ緩和膜のそれぞれとが、前記第2絶縁膜を介して上下に重なるように配置されている、半導体装置。 - 請求項15記載の半導体装置において、
前記複数のひずみ緩和膜は前記複数のソース電極と同一層である、半導体装置。 - 請求項15記載の半導体装置において、
前記複数のひずみ緩和膜は前記複数のソース電極と同一層であり、前記複数のひずみ緩和膜のそれぞれと、前記複数のソース電極のそれぞれとは一体に形成されている、半導体装置。 - 請求項10記載の半導体装置において、
前記複数のソースバス電極および前記複数のドレインバス電極はアルミニウム合金膜を含む、半導体装置。 - 請求項10記載の半導体装置において、
前記複数のソースバス電極および前記複数のドレインバス電極は、下層からチタン膜、窒化チタン膜、アルミニウム合金膜、および窒化チタン膜を順次積層した積層膜、または下層からチタン膜、アルミニウム合金膜、および窒化チタン膜を順次積層した積層膜からなる、半導体装置。 - 請求項10記載の半導体装置において、
前記樹脂膜はポリイミド膜である、半導体装置。
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JP6193677B2 (ja) | 2017-09-06 |
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