JP2015029150A - Semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-efficiency semiconductor light-emitting element.SOLUTION: There is provided a semiconductor light-emitting element including a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a third semiconductor layer, and a second electrode that are sequentially stacked. The first to third semiconductor layers and the light-emitting layer include a nitride semiconductor. The first semiconductor layer has a first conductivity type. The second semiconductor layer has a second conductivity type. The third semiconductor layer is provided on a part of the second semiconductor layer. The impurity concentration of the second conductivity type of the third semiconductor layer is lower than that of the second semiconductor layer. The second electrode includes a pad portion and a thin-line portion. The pad portion is provided on the third semiconductor layer. The thin-line portion extends from the pad portion, has a portion extending along a flat surface perpendicular to the stacking direction, and is in contact with the second semiconductor layer.

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  Semiconductor light emitting devices such as light emitting diodes (LEDs) have been developed. In semiconductor light emitting devices, improvement in efficiency is required. For example, there is a configuration in which an insulating layer for controlling a current path is provided in order to suppress light emission at a position overlapping with a light-shielding pad.

JP 2011-187872 A

  Embodiments of the present invention provide a highly efficient semiconductor light emitting device.

According to an embodiment of the present invention, a semiconductor light emitting device including a first electrode, a first semiconductor layer, a light emitting layer, a second semiconductor layer, a third semiconductor layer, and a second electrode is provided. . The first semiconductor layer is provided on the first electrode and includes a nitride semiconductor and is p-type. The light emitting layer is provided on the first semiconductor layer and includes a nitride semiconductor. The second semiconductor layer is provided on the light emitting layer, includes a nitride semiconductor, and is n-type. The third semiconductor layer is provided on a part of the second semiconductor layer and includes a nitride semiconductor. The third semiconductor layer has an impurity concentration that is lower than the n-type impurity concentration of the second semiconductor layer and equal to or less than 1 × 10 ¹⁷ / cm ³ . The second electrode includes a pad portion and a thin line portion. The pad portion is provided on the third semiconductor layer and is spaced from the second semiconductor layer and is light-shielding. The fine line portion extends from the pad portion. The thin line portion extends along a plane perpendicular to the stacking direction from the first semiconductor layer toward the second semiconductor layer and is in contact with the second semiconductor layer, and the thin line and the pad. And a connecting portion that connects the fine wire and the pad portion and extends along a side surface of the third semiconductor layer.

1 is a schematic perspective view showing a semiconductor light emitting element according to a first embodiment. 1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. 1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. FIG. 4A and FIG. 4B are schematic plan views showing the semiconductor light emitting device according to the first embodiment. 1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. 1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. It is a flowchart figure which shows the manufacturing method of the semiconductor light-emitting device based on 1st Embodiment. FIG. 8A to FIG. 8C are schematic views showing the semiconductor light emitting device according to the first embodiment. It is a typical sectional view showing a semiconductor light emitting element concerning a 2nd embodiment. It is a typical sectional view showing a semiconductor light emitting element concerning a 2nd embodiment. FIG. 6 is a schematic plan view showing a semiconductor light emitting element according to a second embodiment. It is a typical sectional view showing another semiconductor light emitting element concerning a 2nd embodiment. FIG. 13A to FIG. 13C are schematic plan views showing other semiconductor light emitting elements according to the second embodiment. 14A and 14B are schematic plan views showing the characteristics of the semiconductor light emitting device. It is a graph which shows the characteristic of a semiconductor light-emitting device. FIG. 16A to FIG. 16C are schematic plan views showing other semiconductor light emitting elements according to the second embodiment. It is a typical sectional view showing another semiconductor light emitting element concerning a 2nd embodiment. It is a typical sectional view showing another semiconductor light emitting element concerning a 2nd embodiment. It is a typical sectional view showing another semiconductor light emitting element concerning a 2nd embodiment. FIG. 20A to FIG. 20H are schematic plan views showing the configuration and characteristics of the semiconductor light emitting device according to the second embodiment. FIG. 21A to FIG. 21G are schematic cross-sectional views showing the semiconductor light emitting devices according to the embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic perspective view illustrating the configuration of the semiconductor light emitting device according to the first embodiment. 2 and 3 are schematic cross-sectional views illustrating the configuration of the semiconductor light emitting element according to the first embodiment. 2 is a cross-sectional view taken along line A1-A2 of FIG. 3 is a cross-sectional view taken along line A3-A4 of FIG.
FIG. 4A and FIG. 4B are schematic plan views illustrating the configuration of the semiconductor light emitting element according to the first embodiment. FIG. 4A illustrates a planar pattern of the second electrode 80 described later. FIG. 4B illustrates a planar pattern of the third semiconductor layer 60 described later.

  As shown in FIGS. 1, 2, 3, 4 (a) and 4 (b), the semiconductor light emitting device 110 according to the present embodiment includes a first electrode 40, a first semiconductor layer 10, The light emitting layer 30, the second semiconductor layer 20, the third semiconductor layer 60, and the second electrode 80 are included.

  The first semiconductor layer 10 is provided on the first electrode 40. The first semiconductor layer 10 includes a nitride semiconductor and has a first conductivity type. The light emitting layer 30 is provided on the first semiconductor layer 10 and includes a nitride semiconductor. The second semiconductor layer 20 is provided on the light emitting layer 30, includes a nitride semiconductor, and has the second conductivity type.

  For example, the first conductivity type is p-type and the second conductivity type is n-type. In the embodiment, the first conductivity type may be n-type and the second conductivity type may be p-type. In the following description, it is assumed that the first conductivity type is p-type and the second conductivity type is n-type.

  The third semiconductor layer 60 is provided on a part of the second semiconductor layer 20. The concentration of the second conductivity type impurity in the third semiconductor layer 60 is lower than the concentration of the second conductivity type impurity in the second semiconductor layer 20. The third semiconductor layer 60 includes a nitride semiconductor.

  As described above, in the semiconductor light emitting device 110, the stacked semiconductor layer 15 including the first semiconductor layer 10, the light emitting layer 30, the second semiconductor layer 20, and the third semiconductor layer 60 is provided.

  For example, at least one of Mg, Zn, and C is used as the first conductivity type (p-type) impurity. As the second conductivity type (n-type) impurity, for example, at least one of Si, Ge, Te, and Sn is used.

  The second semiconductor layer 20 includes, for example, Si as an impurity of the second conductivity type. The concentration of Si in the third semiconductor layer 60 is lower than the concentration of Si in the second semiconductor layer 20.

The first semiconductor layer 10 includes, for example, a GaN layer containing p-type impurities (at least one of Mg, Zn, and C). The concentration of the p-type impurity in the first semiconductor layer 10 is, for example, 1 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ²¹ cm ⁻³ or less. The first semiconductor layer 10 includes, for example, a p-side contact layer.

The second semiconductor layer 20 includes, for example, a GaN layer containing an n-type impurity (at least one of Si, Ge, Te, and Sn). The concentration of the p-type impurity in the second semiconductor layer 20 is, for example, 1 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less. The second semiconductor layer 20 includes, for example, an n-side contact layer.

The third semiconductor layer 60 includes, for example, a nitride semiconductor layer (for example, at least one of a GaN layer, an AlN layer, and an AlGaN layer) that is not doped with n-type impurities (such as Si, Ge, Te, and Sn). . The concentration of the p-type or n-type impurity in the third semiconductor layer 60 is, for example, 1 × 10 ¹⁷ cm ⁻³ or less. The concentration of the p-type or n-type impurity in the third semiconductor layer 60 is more preferably 1 × 10 ¹⁶ cm ⁻³ or less (for example, non-doped).

  The concentration of the second conductivity type impurity in the third semiconductor layer 60 is not more than 0.5 times the concentration of the second conductivity type impurity in the second semiconductor layer 20.

  Examples of the laminated semiconductor layer 15 and the light emitting layer 30 will be described later.

  A stacking direction from the first semiconductor layer 10 toward the second semiconductor layer 20 is taken as a Z-axis direction. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

  For example, the shape (planar shape) when the semiconductor light emitting element 110 is viewed along the Z-axis direction is a rectangle (for example, a rectangle). One side of the planar shape of the semiconductor light emitting device 110 is, for example, along the X-axis direction. Another side of the planar shape of the semiconductor light emitting device 110 is, for example, along the Y-axis direction. However, in the embodiment, the relationship between the X-axis direction and the direction of the side of the semiconductor light emitting element 110 is arbitrary.

  The second electrode 80 includes a pad portion 81 and a thin wire portion 82. The pad part 81 is provided on the third semiconductor layer 60. The fine wire portion 82 extends from the pad portion 81 and contacts the second semiconductor layer 20. The thin wire portion 82 includes a thin wire 82a and a connecting portion 82b. The fine wire 82a extends along the XY plane. The fine wire 82 a is in contact with the second semiconductor layer 20. The connecting portion 82b is provided between the thin wire 82a and the pad portion 81, and connects the thin wire 82a and the pad portion 81 to each other. The connection part 82 b is along at least the side surface of the third semiconductor layer 60. As described above, the thin wire portion 82 is a portion (thin wire) extending along a plane (XY plane) perpendicular to the stacking direction (Z-axis direction) from the first semiconductor layer 10 toward the second semiconductor layer 20. 82a).

  The third semiconductor layer 60 has an upper surface 60u and a lower surface 60l. The lower surface 60 l of the third semiconductor layer 60 faces the second semiconductor layer 20. The upper surface 60u is a surface opposite to the lower surface 60l. The upper surface 60u of the third semiconductor layer 60 has a portion 60p covered with the second electrode 80 and a portion 60q not covered with the second electrode 80. In this example, the third semiconductor layer 60 has irregularities 65. The unevenness 65 is provided in a portion 60 q of the upper surface 60 u of the third semiconductor layer 60 that is not covered with at least the second electrode 80.

  The first electrode 40 is provided on the lower surface 101 of the first semiconductor layer 10. In this example, the semiconductor light emitting device 110 further includes a support substrate 70, a first intermediate conductive layer 71, and a second intermediate conductive layer 72. The support substrate 70 is conductive. As the support substrate 70, for example, a conductive silicon substrate or the like is used. A first electrode 40 is provided on the support substrate 70. That is, the first electrode 40 is disposed between the support substrate 70 and the first semiconductor layer 10. The first intermediate conductive layer 71 is provided between the support substrate 70 and the first electrode 40. The second intermediate conductive layer 72 is provided between the support substrate 70 and the first intermediate conductive layer 71.

  For example, the first intermediate conductive layer 71 is formed on the surface (the lower surface 10l) of the first electrode 40. The second intermediate conductive layer 72 is formed on the surface of the support substrate 70. The support substrate 70 is bonded to the first electrode 40 by bonding the first intermediate conductive layer 71 and the second intermediate conductive layer 72 with the first intermediate conductive layer 71 and the second intermediate conductive layer 72 facing each other. Is done.

  The first intermediate conductive layer 71 is, for example, an adhesive metal layer. For the first intermediate conductive layer 71, for example, Ti or a Ti alloy is used. The second intermediate conductive layer 72 is a bonding metal layer. For the second intermediate conductive layer 72, for example, an AnSn alloy or the like is used.

  A metal (including an alloy) is used for the second electrode 80 and the first electrode 40. The material of the thin wire portion 82 of the second electrode 80 is the same material as at least a part of the pad portion 81. This provides good electrical properties and simplifies manufacturing.

  The semiconductor light emitting device 110 is, for example, a thin film type semiconductor light emitting device. As will be described later, in the semiconductor light emitting device 110, after the third semiconductor layer 60, the second semiconductor layer 20, the light emitting layer 30, and the first semiconductor layer 10 are sequentially grown on the growth substrate, A support substrate is bonded to the laminated semiconductor layer 15, and then the growth substrate is removed. The support substrate is bonded to the laminated semiconductor layer 15 through, for example, a bonding metal layer or directly.

  In this specification, “joining” includes not only the state of being directly fixed, but also the state of being fixed with another element inserted therebetween. Further, “provided on” includes not only the case of being disposed in direct contact but also the case of being disposed with another element interposed therebetween. Further, “opposite” includes not only a state of facing directly but also a state of facing indirectly by inserting another element therebetween. The term “laminated” includes not only the state of being stacked in contact with each other but also the state of being stacked with another layer interposed therebetween.

  In the semiconductor light emitting device 110, a voltage is applied between the second electrode 80 and the first electrode 40, and a current is supplied to the light emitting layer 30 via the first semiconductor layer 10 and the second semiconductor layer 20, and the light emitting layer Light is emitted from 30. The wavelength of the emission peak is, for example, not less than 370 nanometers (nm) and not more than 700 nm. The light is mainly emitted from the upper surface of the semiconductor light emitting device 110 to the outside.

  For example, an n-side contact layer is provided on the upper portion of the second semiconductor layer 20, and the n-side contact layer and the fine wire 82a are in contact with each other. The fine wire 82a is in ohmic contact with the second semiconductor layer 20 (specifically, the n-side contact layer).

  On the other hand, the impurity concentration in the third semiconductor layer 60 is low. The electrical resistance of the third semiconductor layer 60 is at least twice that of the second semiconductor layer 20. For this reason, the electrical resistance between the pad portion 81 provided on the upper surface 60 u of the third semiconductor layer 60 and the third semiconductor layer 60 is higher than the electrical resistance between the thin wire 82 a and the second semiconductor layer 20.

  For this reason, when a voltage is applied between the second electrode 80 and the first electrode 40, a current flows between the thin wire portion 82 (the thin wire 82 a) of the second electrode 80 and the second semiconductor layer 20. No current substantially flows between the pad portion 81 of the second electrode 80 and the third semiconductor layer 60. For this reason, light emission directly under and near the pad portion 81 is suppressed. Light is emitted below and in the vicinity of the thin line portion 82 (thin line 82a).

  A metal (including an alloy) is used for the pad portion 81 from the viewpoint of electrical connectivity. If light is emitted directly under and in the vicinity of the pad portion 81, the light is blocked by the pad portion 81 and is not emitted directly to the outside of the element, causing loss.

  On the other hand, in the embodiment, since the pad portion 81 is provided on the third semiconductor layer 60 having a low impurity concentration, light emission directly under and near the pad portion 81 is suppressed. Then, a current is injected from the thin line portion 82 (thin line 82 a) into the second semiconductor layer 20, and light emission at portions other than the pad portion 81 is promoted.

  The thin line portion 82 extends in the XY plane and has a function of spreading a current in the XY plane. Since the current flowing through the semiconductor layer is diffused to some extent, the current injected from the thin line portion 82 flows not only directly below the thin line portion 82 but also to a portion of the semiconductor layer other than directly below the thin line portion 82. For this reason, a relatively uniform current flows in the light emitting layer 30. As described above, since the current flowing through the semiconductor layer is diffused, the width of the thin wire portion 82 (the length in the direction perpendicular to the extending direction of the thin wire portion 82) can be set relatively narrow. The light emitted immediately below the thin wire portion 82 is reflected at the interface of each layer or the first electrode 40 to change its direction, and can be emitted from the upper surface of the element with a relatively small number of reflections. For this reason, the degree of loss due to absorption that occurs before light is extracted is low.

  On the other hand, from the viewpoint of electrical connectivity such as bonding, the size (width) of the pad portion 81 is set to be relatively large. For this reason, if the light is emitted directly under the pad portion 81, the light is reflected from the interface of each layer or the first electrode 40, etc., and changes its direction to be emitted from the upper surface of the element. Increased and loss is large. For this reason, it is desired to suppress light emission directly under the pad portion 81 as much as possible.

  In the embodiment, since the pad portion 81 is provided on the third semiconductor layer 60 having a low impurity concentration, light emission directly under and near the pad portion 81 is suppressed, so that loss can be suppressed. Thereby, high efficiency is obtained.

  In the present embodiment, the area of the third semiconductor layer 60 in the XY plane is preferably 2% or more and 10% or less of the area of the second semiconductor layer 20 in the XY plane. When the area of the third semiconductor layer 60 in the XY plane is within this range, the area of the thin line portion 82 of the second electrode 80 is secured, and light emission is promoted. If the area of the third semiconductor layer 60 in the XY plane is too large, light extraction is hindered, and if it is too small, current injection may be insufficient.

  In the embodiment, the ratio (S2 / S1) of the area S2 of the XY plane of the pad part 81 to the area S1 of the XY plane of the second electrode 80 is 20% or more and 656% or less. It is. When the area of the pad portion 81 is large as described above, it is easy to obtain the effect of improving the efficiency according to the present embodiment.

  The width of the thin wire portion 82a along the direction orthogonal to the extending direction of the thin wire portion 82 (for example, the Y-axis direction) is 6% or more and 15% or less of the direction of the pad portion 81 (the width along the Y-axis direction). Preferably there is. Within this range, the efficiency of light extraction can be increased while sufficient current is injected from the thin wire portion 82 of the second electrode 80.

In order to suppress the current injection from the pad portion 81, a configuration in which an insulating layer such as SiO ₂ is provided on a part of the second semiconductor layer 20 without providing the third semiconductor layer 60 is considered. It is done. However, since such an insulating layer has a thermal conductivity lower than that of a nitride semiconductor, heat is likely to accumulate. Further, by providing an insulating layer made of a material different from that of the nitride semiconductor, adhesion between the insulating layer and the nitride semiconductor is low, and reliability may be lowered. Moreover, due to the difference in thermal expansion coefficient between them, defects such as cracks are generated, and the reliability is likely to be lowered. Further, the adhesion between the insulating layer such as SiO ₂ and the metal (for example, Al) used for the second electrode 80 is low. The number of processes also increases.

  On the other hand, in the embodiment, the third semiconductor layer 60 made of a nitride semiconductor having good thermal conductivity is used in order to suppress current injection from the pad portion 81. Thereby, heat is hard to accumulate. Further, by using the third semiconductor layer 60 made of a material similar to that of other semiconductor layers, high adhesion can be obtained, no difference in thermal expansion coefficient occurs, defects such as cracks are suppressed, and reliability is improved. high. The adhesion between the third semiconductor layer 60 of nitride semiconductor and the metal (for example, Al) used for the second electrode 80 is high. Since the third semiconductor layer 60 grown before the growth of the second semiconductor layer 20 is used, the number of processes does not increase.

  By controlling the conductivity of the third semiconductor layer 60, the ratio of the current injected from the pad portion 81 into the semiconductor layer and the current injected from the thin wire portion 82 into the semiconductor layer is set to an arbitrary ratio. Can do. Thus, by providing the third semiconductor layer 30 instead of the insulating layer under the pad portion 81, the current density in the periphery of the pad portion 81 can be adjusted to an appropriate state, and the light emission distribution is made closer to a desired state. be able to. This further increases efficiency.

  For example, when the third semiconductor layer 60 is not provided, the concentrated light emission intensity in the vicinity of the pad portion 81 is about 1.5 times that of the other portions. At this time, the current can be made uniform by setting the current density in the third semiconductor layer 60 to about 1 / 1.5 of the current density in the second semiconductor layer 20. For this purpose, for example, the resistance of the third semiconductor layer 60 is set to 1.5 times the resistance of the second semiconductor layer 20.

  The resistance of the third semiconductor layer 60 is based on the thickness of the third semiconductor layer 60 and the conductivity (for example, a value based on the impurity concentration) in the third semiconductor layer 60. The resistance of the second semiconductor layer 30 is based on the thickness of the third semiconductor layer 30 and the conductivity in the third semiconductor layer 30 (for example, a value based on the impurity concentration). The conductivity of the third semiconductor layer 60 is determined in consideration of the thickness.

  Further, when the second semiconductor layer 20 is n-type, electrons are injected from the second electrode 80 into the second semiconductor layer. Electron injection efficiency is high. Therefore, if the pad portion 81 is also brought into contact with the second semiconductor layer 20 without providing the third semiconductor layer 60, electrons are injected from the pad portion 81 and the vicinity thereof into the second semiconductor layer 20, and the fine line portion. The injection of electrons from 82 is suppressed. That is, current is locally injected only in the vicinity of the pad portion 81, and no current is injected from the thin wire portion 82. For this reason, it is difficult to extract light, and light is emitted locally at the pad portion 81 and its vicinity, and light emission at other portions is reduced. That is, the in-plane light emission distribution is non-uniform, and the light extraction efficiency decreases.

  On the other hand, in the embodiment, even when the second semiconductor layer 20 is n-type, the pad portion 81 is provided on the high-resistance third semiconductor layer 60, and the pad portion 81 and the vicinity thereof are provided. Since the injection into the second semiconductor layer 20 is suppressed, the in-plane light emission distribution becomes uniform, and high light extraction efficiency is obtained. As a result, the efficiency is high.

  As described above, when the first conductivity type is the p-side and the second conductivity type is the n-type, the improvement of the high light extraction efficiency according to the embodiment becomes more effective.

  As shown in FIG. 4B, the third semiconductor layer 60 is provided on a part of the second semiconductor layer 20. For example, the third semiconductor layer 60 is provided with a trench 60 t that penetrates the third semiconductor layer 60. The trench 60 t reaches the second semiconductor layer 20. The second semiconductor layer 20 is exposed in the trench 60t.

  As shown in FIG. 4A, the thin wire 82a of the thin wire portion 82 of the second electrode 80 is provided so as to be embedded in the trench 60t.

  In the embodiment, the thin line portion 82 has a function of spreading the current in the XY plane. For this reason, it is preferable that a plurality of thin wire portions 82 are provided. The planar shape of the thin wire portion 82 (the shape when projected onto the XY plane) may be a closed shape or an open shape.

  As illustrated in FIGS. 2 and 3, in this example, the thin wire 82 a is embedded in the second semiconductor layer 20. As described above, at least a part of the thin line portion 82 may be embedded in the second semiconductor layer 20. When at least a part of the fine wire portion 82 (fine wire 82a) is embedded in the second semiconductor layer 20, in addition to the contact between the bottom surface of the fine wire portion 82 and the second semiconductor layer 20, the side surface of the fine wire portion 82 and the second semiconductor Layer 20 is in contact. For this reason, the electrical resistance between the thin wire | line part 82 and the 2nd semiconductor layer 20 can be reduced more.

  The second electrode 80 and the first electrode 40 are preferably reflective to the light emitted from the light emitting layer 30. Thereby, the light extraction efficiency can be improved.

  For example, the second electrode 80 preferably contains Al. Al has good ohmic contact with the n-type nitride semiconductor. When the second electrode 80 includes Al or an alloy containing Al, high reflectivity and high electrical characteristics can be obtained.

  The first electrode 40 preferably contains Ag. Ag has good ohmic contact with a p-type nitride semiconductor. When the first electrode 40 includes Ag or an alloy containing Ag, high reflectivity and high electrical characteristics can be obtained.

  For example, the depth of the irregularities 65 is 0.8 times or more the peak wavelength of light emitted from the light emitting layer 30. For example, the depth of the unevenness 65 is not more than 5 times the peak wavelength of light. The unevenness 65 allows the light emitted from the light emitting layer 30 to be efficiently extracted out of the device.

  As illustrated in FIG. 2, the thin wire portion 82 extends from the pad portion 81 along the side surface 60 s of the third semiconductor layer 60 and extends on the second semiconductor layer 20. That is, the pad portion 81 provided on the third semiconductor layer 60 and the fine wire 82a in contact with the second semiconductor layer 20 are connected by the connecting portion 82b therebetween. At this time, the side surface 60s of the third semiconductor layer 60 is preferably forward tapered so as not to be disconnected at the connection portion 82b.

  For example, the angle θ between the portion of the side surface 60s of the third semiconductor layer 60 where the second electrode 80 is provided and the XY plane is preferably 20 degrees or greater and 85 degrees or less.

  The taper angle θ of the side surface 60 s of the third semiconductor layer 60 is adjusted depending on the etching conditions when processing the third semiconductor layer 60. The processing conditions for the third semiconductor layer 60 can be the same as the processing conditions for processing the laminated semiconductor layer 15 and dividing the element. Thereby, the stability of processing improves. At this time, the taper angle θ of the side surface 60 s of the third semiconductor layer 60 substantially matches the taper angle of the side surface of the stacked semiconductor layer 15. For example, the angle θ between the portion of the side surface 60s of the third semiconductor layer 60 where the second electrode 80 is provided and the XY plane is equal to the side surface of the second semiconductor layer 20 and the XY plane. It is preferable that it is the same as angle (theta) 1 between planes.

  FIG. 5 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. FIG. 5 illustrates the state when the stacked semiconductor layer 15 is crystal-grown. That is, FIG. 5 illustrates the state of one stage of the manufacturing process of the semiconductor light emitting device 110.

  As shown in FIG. 5, the laminated semiconductor film 15 f is epitaxially grown on the growth substrate 5. The laminated semiconductor film 15 f becomes the laminated semiconductor layer 15. As a growth method of the laminated semiconductor film 15f, for example, a metal-organic chemical vapor deposition (MOCVD) method or a metal-organic vapor phase epitaxy method may be used. it can. The growth substrate 5 and the stacked semiconductor film 15 f are included in the stacked body 16.

For example, silicon (Si) is used for the growth substrate 5. For example, the growth substrate 5 is made of any one of Si, SiO ₂ , quartz, sapphire, GaN, SiC, and GaAs. At this time, the plane orientation of the growth substrate 5 is arbitrary. Hereinafter, an example in which a Si substrate is used as the growth substrate 5 will be described.

  A third semiconductor film 60 f is formed on the growth substrate 5. The third semiconductor film 60 f becomes at least a part of the third semiconductor layer 60. The second semiconductor film 20f is provided on the third semiconductor film 60f. The second semiconductor film 20 f becomes the second semiconductor layer 20. A light emitting film 30f is provided on the second semiconductor film 20f. The light emitting film 30 f becomes the light emitting layer 30. The first semiconductor film 10f is provided on the light emitting film 30f. The first semiconductor film 10 f becomes the first semiconductor layer 10.

  In this example, as the third semiconductor film 60f, for example, an AlN layer 62a, an AlGaN layer 63a, and a stacked intermediate layer 64 are provided. The AlN layer 62a is formed on the growth substrate 5.

The AlN layer 62a is formed by low temperature growth or high temperature growth.
In the case of low temperature growth, the formation temperature of the AlN layer 62a is, for example, not less than 400 ° C. and not more than 500 ° C. The thickness of the AlN layer 62a in the case of low temperature growth is, for example, 30 nm or more and 100 nm or less.
In the case of high-temperature growth, the formation temperature of the AlN layer 62a is, for example, 700 ° C. or more and 1200 ° C. or less. The thickness of the AlN layer 62a in the case of high temperature growth is, for example, not less than 100 nm and not more than 300 nm.
As the AlN layer 62a, a laminated film of an AlN layer grown at a low temperature and an AlN layer grown at a high temperature may be used.

  The AlGaN layer 63a is formed on the AlN layer 62a. The formation temperature of the AlGaN layer 63a is, for example, not less than 800 ° C. and not more than 1200 ° C. The thickness of the AlGaN layer 63a is, for example, not less than 300 nm and not more than 2000 nm. The Al composition ratio in the AlGaN layer 63a is 0.15 or more and less than 1. The AlGaN layer 63a may include a stacked film of a plurality of layers having different Al composition ratios. The AlGaN layer 63a may have a continuous change in the composition ratio.

  The stacked intermediate layer 64 is formed on the AlGaN layer 63a. The stacked intermediate layer 64 includes a plurality of first layers 61 and a plurality of second layers 62. The plurality of first layers 61 and the plurality of second layers 62 are alternately stacked. In this example, a third layer 63 is provided between the first layer 61 and the second layer 62. A second layer 62 is provided on the first layer 61, a third layer 63 is provided on the second layer 62, and another first layer 61 is provided on the third layer 63.

The Al composition ratio in the second layer 62 is higher than the Al composition ratio in the first layer 61. For the first layer 61, for example, GaN is used. For example, Al _x1 Ga _1-x1 N (0 <x1 ≦ 1) is used for the second layer 62. For the third layer 63, Al _x2 Ga _1-x2 N (0 <x2 <x1) is used.

  The thickness of the first layer 61 is, for example, 150 nm or more and 1000 nm or less, the thickness of the second layer 62 is 10 nm or more and 200 nm or less, and the thickness of the third layer 63 is 20 nm or more and 300 nm or less. At this time, the number of stacked layers (the number of the first layers 61 or the number of the second layers 62) is 1 or more and 5 or less.

  The total thickness of the stacked intermediate layer 64 is, for example, not less than 200 nm and not more than 7500 nm. The formation temperature of the first layer 61 is, for example, 800 ° C. or more and 1100 ° C. or less, the formation temperature of the second layer 62 is, for example, 500 ° C. or more and 800 ° C. or less, and the formation temperature of the third layer 63 is 700 It is not lower than 1200 ° C and not higher than 1200 ° C.

  In this example, the first layer 61 is provided on the AlGaN layer 63a. A second semiconductor film 20 f is provided on the last third layer 63.

  The uppermost third layer 63 (AlGaN layer) is in contact with, for example, the second semiconductor film 20f (second semiconductor layer 20). However, in the embodiment, another layer may be provided between the uppermost third layer 63 and the second semiconductor film 20f (second semiconductor layer 20). For example, the semiconductor light emitting device 110 may further include a stacked film provided between the uppermost third layer 63 and the second semiconductor film 20f (second semiconductor layer 20). This laminated film includes, for example, a plurality of high band gap energy layers and a plurality of low band gap energy layers that are alternately laminated. The high band gap energy layer is, for example, a GaN layer. The low band gap energy layer is, for example, an InGaN layer. With this laminated film, for example, good crystallinity can be obtained. This stacked film may be regarded as a part of the third semiconductor film 60f (third semiconductor layer 60), for example.

  The uppermost layer in the laminated intermediate layer 64 may be other layers instead of the third layer 63 (AlGaN layer). For example, the first layer 61 (for example, a GaN layer) may be disposed on the top of the stacked intermediate layer 64. Further, the second layer 62 (for example, an AlN layer) may be disposed on the top of the laminated intermediate layer 64.

  In the semiconductor light emitting device 110, the third semiconductor layer 60 includes, for example, at least a part of the stacked intermediate layer 64. The third semiconductor layer 60 includes a first layer 61. For example, the third semiconductor layer 60 further includes a third layer 63. The third semiconductor layer 60 includes, for example, a second layer 62. The third semiconductor layer 60 may further include an AlGaN layer 62a and an AlN layer 63a.

As described above, the third semiconductor layer 60 may include a GaN layer (for example, the first layer 61). The concentration of impurities of the second conductivity type in this GaN layer is 1 × 10 ¹⁷ / cm ³ or less.

The third semiconductor layer 60 may include an Al _x1 GaN _1-x1 N layer (0 <x1 ≦ 1), that is, at least one of the second layer 62 and the third layer 63.

That is, the third semiconductor layer 60 can include a nitride semiconductor multilayer film. The nitride semiconductor multilayer _film, Al _{z1 Ga 1-z1} N layer _{(0 <z1 <1),} Al z1 Ga 1-z1 Al provided on the N layer z2 _{Ga 1-z2} N layer (z1 < and _{z2 ≦ 1), Al z2 Ga} 1-z2 Al provided on the N layer z3 _{Ga 1-z3} N layer (0 ≦ z3 <x1), can contain. The Al _z1 Ga _{1 -z1} N layer is, for example, the third layer 63, the Al _z2 Ga _{1 -z2} N layer is, for example, the second layer 62, and the Al _z3 Ga _{1 -z3} N layer (0 ≦ z3 < x1) is, for example, the first layer 61.
A plurality of nitride semiconductor multilayer films may be stacked in the stacking direction (Z-axis direction).

FIG. 6 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. FIG. 6 shows one example of the configuration of the light emitting layer 30.
As shown in FIG. 6, the light emitting layer 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31. For example, a plurality of barrier layers 31 and a plurality of well layers 32 are alternately stacked along the Z-axis direction.

The well layer 32 includes In _x0 Ga _1-x0 N (0 <x0 <1). The barrier layer 31 includes GaN. That is, the well layer 32 contains In, and the barrier layer 31 does not substantially contain In. The band gap energy in the barrier layer 31 is larger than the band gap energy in the well layer 32.

  The light emitting layer 30 may have a single quantum well (SQW) configuration. At this time, the light emitting layer 30 includes two barrier layers 31 and a well layer 32 provided between the barrier layers 31. Alternatively, the light emitting layer 30 may have a multi quantum well (MQW) configuration. At this time, the light emitting layer 30 includes three or more barrier layers 31 and a well layer 32 provided between the barrier layers 31.

  That is, the light emitting layer 30 includes, for example, (n + 1) barrier layers 31 and n well layers 32 (n is an integer of 2 or more). The (i + 1) -th barrier layer BL (i + 1) is disposed between the i-th barrier layer BLi and the first semiconductor layer 10 (i is an integer not less than 1 and not more than (n−1)). The (i + 1) th well layer WL (i + 1) is disposed between the i-th well layer WLi and the first semiconductor layer 10. The first barrier layer BL1 is provided between the second semiconductor layer 20 and the first well layer WL1. The nth well layer WLn is provided between the nth barrier layer BLn and the (n + 1) th barrier layer BL (n + 1). The (n + 1) th barrier layer BL (n + 1) is provided between the nth well layer WLn and the first semiconductor layer 10.

Hereinafter, an example of a method for manufacturing the semiconductor light emitting device 110 will be described.
FIG. 7 is a flowchart illustrating the method for manufacturing the semiconductor light emitting element according to the first embodiment.
As shown in FIG. 7, the stacked body 16 is prepared (step S110). The stacked body 16 includes a growth substrate 5 and a stacked semiconductor film 15f. The laminated semiconductor film 15f includes a first conductivity type first semiconductor film 10f, a second conductivity type second semiconductor film 20f provided between the growth substrate 5 and the first semiconductor film 10f, and a first semiconductor. The light emitting film 30f provided between the film 10f and the second semiconductor film 20f and the impurity concentration of the second conductivity type provided between the growth substrate 5 and the second semiconductor film 20f are higher than those of the second semiconductor film 20f. A lower third semiconductor film 60f.

  The manufacturing method may include a step of forming the stacked body 16 (that is, a step of growing the stacked semiconductor film 15f on the growth substrate 5).

  As shown in FIG. 7, the first electrode 40 is formed (step S120). For example, an Ag film to be the first electrode 40 is formed on the entire top surface of the processed body. The thickness of the Ag film is, for example, 100 nm or more and 400 nm or less. Further, a Ti film to be the first intermediate conductive layer 71 is formed on the Ag film. The thickness of this Ti film is, for example, 5 nm or more and 100 nm or less. The first intermediate conductive layer 71 functions as a barrier metal.

  As shown in FIG. 7, the conductive support substrate 70 is bonded to the first electrode 40 (step S130). For example, a silicon substrate provided with a second intermediate conductive layer 72 (for example, AuSn layer) on the main surface is prepared as the support substrate 70. The first electrode 40 and the support substrate 70 are disposed so that the first intermediate conductive layer 71 and the second intermediate conductive layer 72 are opposed to each other. Then, the first intermediate conductive layer 71 and the second intermediate conductive layer 72 are brought into contact with each other and heated to join the first electrode 40 and the support substrate 70 together.

  As shown in FIG. 7, the growth substrate 5 is removed (step S140). This removal is performed, for example, by at least one of grinding and etching.

  As shown in FIG. 7, a part of the third semiconductor film 60f is removed (step S150). For example, a trench (trench 60t) penetrating the third semiconductor film 60f is formed in the third semiconductor film 60f.

  As shown in FIG. 7, the unevenness 65 is formed on the surface of the third semiconductor film 60f. For the formation of the irregularities 65, for example, a wet process using KOH or an arbitrary dry etching process can be used.

As shown in FIG. 7, the second electrode 80 is formed (step S170). For example, after a resist having a predetermined shape is formed on the processed body, a conductive film is formed, and the resist is removed to form a conductive film having a predetermined shape. Part of this conductive film is in contact with the second semiconductor film 20f (second semiconductor layer 20) through the trench 60t. Thereby, the thin wire | line part 82 and the pad part 81 of the 2nd electrode 80 are formed.
Thereby, the semiconductor light emitting device 110 is obtained.

  In addition, the order of said step S110-S170 can be changed in the technically possible range. At least two of steps S110 to S170 may be performed simultaneously as far as technically possible.

  According to the method for manufacturing a semiconductor light emitting device according to this embodiment, a highly efficient method for manufacturing a semiconductor light emitting device can be provided.

  During the removal of the growth substrate 5 (step S140), a part of the third semiconductor film 60f formed on the growth substrate 5 is left and a part thereof is removed. For example, the AlGaN layer 62a and the AlN layer 63a in the third semiconductor film 60f are removed, and at least a part of the stacked intermediate layer 64 remains. For example, a part of the remaining stacked intermediate layer 64 becomes the third semiconductor layer 60.

  The unevenness 65 is formed on at least a part of the remaining laminated intermediate layer 64, for example. A part of the unevenness 65 may reach the second semiconductor layer 20.

FIG. 8A to FIG. 8C are schematic views illustrating the configuration of the semiconductor light emitting element according to the first embodiment.
8A and 8B show a case where a laminated semiconductor film 15f is formed on the growth substrate 5, and after the growth substrate 5 is removed, the surface of the first semiconductor layer 10 is changed to the semiconductor layer. The result of having analyzed the element contained by SIMS (Secondary Ion Mass Spectrometry) is represented. The horizontal axis in these drawings is the position in the Z-axis direction (depth direction). The vertical axis | shaft of Fig.8 (a) is the density | concentration C (Al) of Al (Al ion). The vertical axis | shaft of FIG.8 (b) is the density | concentration C (Si) of Si. FIG. 8C schematically illustrates a semiconductor layer corresponding to the horizontal axis of FIGS. 8A and 8B.

  As shown in FIG. 8A, the Al concentration is high in a part of the first semiconductor layer 10. The portion where the Al concentration is high corresponds to the electron overflow suppression layer. In the light emitting layer 30 and the second semiconductor layer 20, the Al concentration is low. In the third semiconductor layer 60, the Al concentration is high in the third layer 63 and the second layer 62. In the first layer 61, the Al concentration is low.

  As illustrated in FIG. 8A, in the first layer 61, the second layer 62, and the third layer 63, the concentration of Al may be continuously changed. Moreover, you may change discontinuously. Although the boundary between the first layer 61, the second layer 62, and the third layer 63 may be unclear, the presence of the high Al concentration portion, the low portion, and the intermediate portion, The presence of the first layer 61, the second layer 62, and the third layer 63 can be confirmed.

  As illustrated in FIG. 8B, the first semiconductor layer 10 has a low Si concentration, and the second semiconductor layer 20 has a high Si concentration. In this example, Si is observed in the light emitting layer 30. The concentration of Si in the light emitting layer 30 is lower than the concentration of Si in the second semiconductor layer 20.

  In this example, high concentration of Si is detected in a part of the third semiconductor layer 60 on the second semiconductor layer 20 side (third layer 63) (part PA in FIG. 8B). In this portion, fluctuation of the Si concentration occurs. Excluding the portion PA, the Si concentration in the third semiconductor layer 60 is lower than the Si concentration in the second semiconductor layer 20. As described above, the second semiconductor layer 20 is locally localized between the second semiconductor layer 20 and the portion of the second semiconductor layer 20 where the second conductivity type impurity concentration is low in the second semiconductor layer 20. In addition, a portion where the impurity concentration of the second conductivity type is higher than that of the second semiconductor layer 20 (a portion PA where fluctuation of the Si concentration occurs) may be provided. In this case, a portion in which the impurity concentration of the second conductivity type is lower than the impurity concentration of the second conductivity type in the second semiconductor layer 20 can be regarded as the third semiconductor layer 60.

The concentration of Si (second conductivity type impurity) in the first layer 61 (GaN layer) of the third semiconductor layer 60 is 1 × 10 ¹⁷ / cm ³ or less.

(Second Embodiment)
9 and 10 are schematic cross-sectional views illustrating the configuration of the semiconductor light emitting element according to the second embodiment. 9 is a cross-sectional view corresponding to the cross section along line A1-A2 of FIG. 10 is a cross-sectional view corresponding to the cross section along line A3-A4 of FIG.
FIG. 11 is a schematic plan view illustrating the configuration of the semiconductor light emitting element according to the second embodiment. FIG. 11 illustrates a planar pattern of the high resistance portion 45 described later.

  As shown in FIGS. 9 to 11, the semiconductor light emitting device 120 according to the embodiment includes the first semiconductor layer 10, the light emitting layer 30, the second semiconductor layer 20, the third semiconductor layer 60, the second electrode 80, and the first electrode. In addition to the one electrode 40, a high resistance portion 45 is further included. The configurations of the first semiconductor layer 10, the light emitting layer 30, the second semiconductor layer 20, the third semiconductor layer 60, the second electrode 80, and the first electrode 40 are the same as those of the semiconductor light emitting device 110, and thus the description thereof is omitted. The pattern of the thin wire 82a in the semiconductor light emitting device 120 is as illustrated in FIG.

  The high resistance part 45 is provided between the first electrode 40 and the first semiconductor layer 10. The high resistance portion 45 overlaps the thin wire 82a when projected onto a plane (XY plane) perpendicular to the stacking direction (Z-axis direction).

  The high resistance portion 45 has a portion 45p that overlaps the thin wire 82a when projected onto the XY plane. In this example, the high resistance portion 45 also includes a portion 45q that overlaps the pad portion 81 when projected onto the XY plane. However, as will be described later, the portion 45q overlapping the pad portion 81 may not be provided.

  The resistance of the high resistance part 45 is higher than the resistance of the first semiconductor layer 10. Alternatively, the contact resistance between the high resistance portion 45 and the first semiconductor layer 10 is higher than the contact resistance between the first electrode 40 and the first semiconductor layer 10. Alternatively, the contact resistance between the high resistance portion 45 and the first electrode 40 is higher than the contact resistance between the first semiconductor layer 10 and the first electrode 40.

  For example, the conductivity of the high resistance portion 45 is lower than the conductivity of the first semiconductor layer 10. For example, the electrical resistance between the first electrode 40 and the first semiconductor layer 10 in the portion where the high resistance portion 45 is not provided between the first electrode 40 and the first semiconductor layer 10 is the first electrode 40. The electrical resistance between the first electrode 40 and the first semiconductor layer 10 is lower in the portion where the high resistance portion 45 is provided between the first semiconductor layer 10 and the first semiconductor layer 10.

  For example, the high resistance portion 45 is insulative. The high resistance portion 45 can include at least one of a metal oxide, a metal nitride, and a metal oxynitride.

For example, when Ag is used as the first electrode 40 and p-type GaN is used as the first semiconductor layer 10, if SiO ₂ is used as the high resistance portion 45, the contact resistance between the high resistance portion 45 and the first semiconductor layer 10. Becomes higher than the contact resistance between the first electrode 40 and the first semiconductor layer 10.

  In this example, the high resistance portion 45 is embedded in the first electrode 40, but the high resistance portion 45 may be embedded in the first semiconductor layer 10.

  The high resistance unit 45 controls a current path that flows from the first electrode 40 to the first semiconductor layer 10. Since the high resistance portion 45 has a portion that overlaps the thin wire 82a when projected onto the XY plane, the high resistance portion 45 suppresses the current to the light emitting layer 30 in the portion that overlaps the thin wire 82a, and emits light at this portion. Suppress. As a result, light emission directly under the thin wire 82a that shields light is suppressed, so that the light emission efficiency is further improved.

FIG. 12 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting element according to the second embodiment. FIG. 12 is a cross-sectional view corresponding to the cross section along line A1-A2 of FIG.
FIG. 13A to FIG. 13C are schematic plan views illustrating the configuration of another semiconductor light emitting element according to the second embodiment. FIG. 13A illustrates a planar pattern of the second electrode 80. FIG. 13B illustrates a planar pattern of the third semiconductor layer 60. FIG. 13C illustrates a planar pattern of the high resistance portion 45.

  As shown in FIG. 12 and FIGS. 13A to 13C, the semiconductor light emitting element 121 is different from the semiconductor light emitting element 120 in the pattern of the high resistance portion 45. Since the configuration other than this is the same as that of the semiconductor light emitting device 120, description thereof is omitted.

  In the semiconductor light emitting device 121, the portion 45q overlapping the pad portion 81 is not provided. That is, the high resistance portion 45 does not overlap at least a part of the pad portion 81 when projected onto the XY plane. Also in this case, the high resistance portion 45 has a portion 45p that overlaps the thin wire 82a when projected onto the XY plane.

  Immediately below the pad portion 81, current injection is suppressed by the third semiconductor layer 60, so that light emission is sufficiently suppressed immediately below the pad portion 81 without providing the high resistance portion 45. For this reason, the part 45q which overlaps with the pad part 81 of the high resistance part 45 can be omitted.

When, for example, SiO ₂ or the like is used as the high resistance portion 45, the high resistance portion 45 functions as a light absorber. For this reason, light absorption is suppressed more by making the area of the high resistance part 45 small.

  On the other hand, a thin wire 82a is provided in order to spread the current in the XY plane, and current (for example, electron current) is injected from the thin wire 82a into the semiconductor layer. Since the thin wire 82a shields (attenuates) light, it is more preferable that light is not emitted as much as possible immediately below the thin wire 82a. In the semiconductor light emitting devices 120 and 121, by providing the high resistance portion 45, light emission directly below the thin wire 82a is suppressed, and higher efficiency is obtained. Furthermore, in the semiconductor light emitting device 121 in which the high resistance portion 45 has a shape that does not overlap the pad portion 81, light absorption in the high resistance portion 45 is suppressed, and higher efficiency than that of the semiconductor light emitting device 120 is obtained.

14A and 14B are schematic plan views illustrating characteristics of the semiconductor light emitting element.
FIG. 14A illustrates the light emission characteristics of the semiconductor light emitting device 121 according to this embodiment. FIG. 14B illustrates characteristics of the semiconductor light emitting device 119 of the reference example. In the semiconductor light emitting device 119, the third semiconductor layer 60 is not provided, and the pad portion 81 and the thin wire portion 82 of the second electrode 80 are in contact with the second semiconductor layer 20. Further, the high resistance portion 45 is not provided in the semiconductor layer 119. In these drawings, a bright part indicates that the luminance of light emission is high, and a dark part indicates that the luminance of light emission is low.

  As shown in FIG. 14B, the semiconductor light emitting device 119 of the reference example emits light locally in the vicinity of the pad portion 81, and the luminance is low in a portion far from the pad portion 81. Thus, in the semiconductor light emitting device 119, light emission is non-uniform in the plane.

  As shown in FIG. 14A, in the semiconductor light emitting device 121 according to the embodiment, local light emission in the vicinity of the pad portion 81 is suppressed, and the in-plane uniformity of light emission is improved. In this example, high luminance is obtained even at a portion far from the pad portion 81. This example is for showing that the third semiconductor layer 60 can suppress local light emission in the vicinity of the pad portion 81, and the luminance in the portion far from the pad portion 81 is the luminance in the vicinity of the pad portion 81. Higher than. However, as will be described later, in-plane brightness uniformity can be further improved by changing the design of the pattern of the thin line portion 82.

FIG. 15 is a graph illustrating characteristics of the semiconductor light emitting device.
These drawings illustrate the measurement results of the light output Po of the semiconductor light emitting device 121 and the semiconductor light emitting device 119. The horizontal axis in FIG. 15 is the wavelength λ (nm). The vertical axis in FIG. 15 represents the optical output Po (milliwatt: mW).

  As shown in FIG. 15, the semiconductor light emitting device 121 according to the embodiment provides a higher light output Po than the semiconductor light emitting device 119 of the reference example. For example, the light output Po of the semiconductor light emitting device 120 is about 5% higher than the light output Po of the semiconductor light emitting device 119.

  In addition, in the semiconductor light emitting device 119, there is a configuration (referred to as a semiconductor light emitting device 119a) in which only the high resistance portion 45 is provided without providing the third semiconductor layer 60. This also suppresses light emission directly below the pad portion 81 and the thin wire 82a and improves the light output. According to an experiment by the present inventor, the light output Po of the semiconductor light emitting device 119a having this configuration is about 3% higher than the light output Po of the semiconductor light emitting device 119.

  Further, the light output of the semiconductor light emitting device 110 according to the first embodiment in which the high resistance portion 45 is not provided is approximately 2.5% higher than the light output Po of the semiconductor light emitting device 119. The semiconductor light emitting device 110 is advantageous in that high efficiency can be obtained by a simple configuration and process in which the third semiconductor layer 60 is left.

  Further, according to the second embodiment in which both the third semiconductor layer 60 and the high resistance portion 45 are provided, very high efficiency can be obtained.

  FIG. 16A to FIG. 16C are schematic plan views illustrating the configuration of another semiconductor light emitting element according to the second embodiment. FIG. 16A illustrates a planar pattern of the second electrode 80. FIG. 16B illustrates a planar pattern of the third semiconductor layer 60. FIG. 16C illustrates a planar pattern of the high resistance portion 45.

  As illustrated in FIG. 16A to FIG. 16C, the semiconductor light emitting element 122 includes the semiconductor light emitting element 121 and the pattern of the second semiconductor layer 20 exposed from the third semiconductor layer 60 (that is, the thin line portion 82. ) Pattern). Since the other configuration is the same as that of the semiconductor light emitting device 121, the description thereof is omitted.

  As shown in FIG. 16B, in the semiconductor light emitting device 122, the second semiconductor layer 20 exposed from the third semiconductor layer 60 is separated from the pattern of the pad portion 81. A connection portion 82 b is provided between the second semiconductor layer 20 exposed from the third semiconductor layer 60 and the pad portion 81.

  Light emitted from one point of the light emitting layer 30 travels through the semiconductor layer while spreading. For this reason, the light extraction efficiency is improved by separating the light emitting position from the pad portion 81 that shields (attenuates) the light by a certain distance. The distance along the XY plane between the end of the second semiconductor layer 20 exposed from the third semiconductor layer 60 and the pad portion 81 is, for example, the distance between the second semiconductor layer 20 and the third semiconductor layer 60. More than 1 times the thickness. And about 10 times or less is preferable. For example, when the thickness of the third semiconductor layer 60 is not less than 2 μm and not more than 3 μm, in the XY plane between the end of the second semiconductor layer 20 exposed from the third semiconductor layer 60 and the pad portion 81. The distance along the line is, for example, 5 μm or more and 20 μm or less.

17 to 19 are schematic cross-sectional views illustrating the configuration of another semiconductor light emitting element according to the second embodiment. 17 to 19 are cross-sectional views corresponding to the cross section taken along line A1-A2 of FIG.
As shown in FIG. 17, in the semiconductor light emitting device 123 according to the present embodiment, a part of the second electrode 80 extends also on the third semiconductor layer 60. The rest is the same as the semiconductor light emitting device 121.

  As shown in FIG. 18, in the semiconductor light emitting device 124 according to the present embodiment, the end of the portion (thin wire 82 a) extending along the XY plane of the thin wire portion 82 is separated from the third semiconductor layer 60. doing. The rest is the same as the semiconductor light emitting device 121.

  In the semiconductor light emitting device 123 or 124, for example, the margin of the pattern shape of the second electrode 80 is wide, and the manufacturing becomes easy.

  As shown in FIG. 19, in the semiconductor light emitting device 125 according to the present embodiment, the upper surface 82 au of the portion (thin wire 82 a) extending along the XY plane of the thin wire portion 82 is formed on the second semiconductor layer 20. It is below the upper surface 20u. The rest is the same as the semiconductor light emitting device 121. In the semiconductor light emitting device 125, at least one margin such as the thickness of the second semiconductor layer 20, the depth of the trench 60 t formed in the third semiconductor layer 60, and the thickness of the second electrode 80 becomes wide. Manufacturing becomes easy.

FIG. 20A to FIG. 20H are schematic plan views illustrating the configuration and characteristics of the semiconductor light emitting device according to the second embodiment.
These drawings illustrate the result of simulating the light emission characteristics when the pattern shape of the second electrode 80 is changed. 20A to 20D show the shape of the second electrode 80 in the semiconductor light emitting devices 126 to 129 according to the embodiment. 20 (e) to 20 (h) show the in-plane distribution of the luminance of light emission in the semiconductor light emitting elements 126 to 129, respectively. 20 (e) to 20 (h), a bright part indicates that the luminance is high, and a dark part indicates that the luminance is low. In these examples, the configuration of the high resistance portion 45 is the same as the configuration of the semiconductor light emitting element 121. That is, the high resistance portion 45 is provided at a position overlapping the thin wire 82 a and is not provided at a position overlapping the pad portion 81.

  As shown in FIG. 20A, in the semiconductor light emitting device 126, both ends of three thin wires 82a extending in the X-axis direction are connected by two thin wires 82a extending in the Y-axis direction. Yes. As shown in FIG. 20E, in the semiconductor light emitting device 126, light emission is not concentrated only in the vicinity of the pad portion 81, but is also emitted in the vicinity of the thin wire 82a. Is expensive.

  As shown in FIG. 20B, in the semiconductor light emitting device 127, one end of three thin wires 82a extending in the X-axis direction is connected by one thin wire 82a extending in the Y-axis direction. Has been. The other end of the three thin wires 82a is open. As shown in FIG. 20F, in the semiconductor light emitting device 127, light emission in the vicinity of the pad portion 81 is further suppressed, and light emission along the thin line 82a is further promoted.

  As shown in FIG. 20C, in the semiconductor light emitting device 128, one end of four thin wires 82a extending in the X-axis direction is connected by one thin wire 82a extending in the Y-axis direction. Has been. The other ends of the four thin wires 82a are open. As shown in FIG. 20G, in the semiconductor light emitting device 128, the in-plane uniformity of light emission is further improved than that of the semiconductor light emitting device 127.

  As shown in FIG. 20D, in the semiconductor light emitting device 129, one end of five thin wires 82a extending in the X-axis direction is connected by one thin wire 82a extending in the Y-axis direction. Has been. The other end of the five thin wires 82a is open. As shown in FIG. 20H, in the semiconductor light emitting device 129, the in-plane uniformity of light emission is further improved as compared with the semiconductor light emitting device 128.

  When the pitch of the plurality of thin wires 82a extending in the Y-axis direction becomes narrow, the in-plane uniformity of light emission can be improved. However, the light extraction efficiency decreases as the number of the thin wires 82a increases. The width of each thin wire 82a is set so that the resistance of the thin wire 82a is sufficiently low.

  In the semiconductor light emitting devices 127 to 129, the in-plane distribution of light emission is further improved. As described above, when a plurality of thin wires 82a (portions extending along the XY plane) are provided, at least two of the thin wires 82a are connected to ends opposite to the pad portions 81 of the thin wires 82a. Preferably not.

In the first and second embodiments, the third semiconductor layer 60 can have various configurations as follows.
FIG. 21A to FIG. 21G are schematic cross-sectional views illustrating the configuration of the semiconductor light emitting element according to the embodiment.
These drawings illustrate the configuration of the second semiconductor layer 20 and the third semiconductor layer 60 together with the second electrode 80. These drawings are cross-sectional views corresponding to a part of the cross-sectional view illustrated in FIG.
As shown in FIG. 21A, in the semiconductor light emitting device 131 according to the embodiment, the first layer 61 (as the third semiconductor layer 60 is formed on the second semiconductor layer 20 (for example, the n-type GaN layer). For example, a GaN layer) is provided, a third layer 63 (for example, an AlGaN layer) is provided on the first layer 61, and a second layer 62 (for example, an AlN layer) is provided on the third layer 63. The pad portion 81 is in contact with the second layer 62, and the thin wire portion 82 a is in contact with the second semiconductor layer 20.

  As shown in FIG. 21B, in the semiconductor light emitting device 132 according to the embodiment, the first layer 61 (as the third semiconductor layer 60 is formed on the second semiconductor layer 20 (for example, the n-type GaN layer). For example, a GaN layer), a third layer 63 (for example, an AlGaN layer), and a second layer 62 (for example, an AlN layer) are provided, and another first layer 61 is provided on the second layer 62. The pad portion 81 is in contact with the upper first layer 61, and the thin wire portion 82 a is in contact with the second semiconductor layer 20.

  As illustrated in FIG. 21C, in the semiconductor light emitting device 133 according to the embodiment, the third semiconductor layer 60 is provided on the second semiconductor layer 20 (for example, an n-type GaN layer). The third semiconductor layer 60 includes, for example, a plurality of first layers 61 and a plurality of second layers 62 that are alternately stacked (see, for example, FIG. 5). The third semiconductor layer 60 may further include a third layer 63 provided between the first layer 61 and the second layer 62.

  As shown in FIG. 21D, in the semiconductor light emitting device 134 according to the embodiment, the thickness of a part of the second semiconductor layer 20 (for example, the n-type GaN layer) is thicker than the thickness of other parts. . A first layer 61 (for example, a GaN layer) is provided as the third semiconductor layer 60 on the thick portion, and a third layer 63 (for example, an AlGaN layer) is provided on the first layer 61. A second layer 62 (for example, an AlN layer) is provided on the third layer 63. The pad portion 81 is in contact with the second layer 62, and the thin wire portion 82 a is in contact with the second semiconductor layer 20.

  As shown in FIG. 21E, also in the semiconductor light emitting device 135 according to the embodiment, the thickness of a part of the second semiconductor layer 20 (for example, the n-type GaN layer) is thicker than the thickness of other parts. . A third layer 63 (for example, an AlGaN layer) is provided as the third semiconductor layer 60 on the thick portion, and a second layer 62 (for example, an AlN layer) is provided on the third layer 63. A first layer 61 (for example, a GaN layer) is provided on the second layer 62. The pad portion 81 is in contact with the first layer 61, and the thin wire portion 82 a is in contact with the second semiconductor layer 20.

  As shown in FIG. 21F, also in the semiconductor light emitting device 136 according to the embodiment, the thickness of a part of the second semiconductor layer 20 (for example, the n-type GaN layer) is thicker than the thickness of other parts. . A third layer 63 (for example, an AlGaN layer) is provided as the third semiconductor layer 60 on the thick portion, and a second layer 62 (for example, an AlN layer) is provided on the third layer 63. ing. The pad portion 81 is in contact with the second layer 62, and the thin wire portion 82 a is in contact with the second semiconductor layer 20. In the configuration of the semiconductor light emitting device 136, a first layer 61 (for example, an AlGaN layer) is provided as the third semiconductor layer 60, and a second layer 62 (for example, an AlN layer) is provided on the first layer 61. May be considered. As described above, the second layer 62 is a layer having a higher Al composition ratio than the first layer 61, and AlGaN may be used as the first layer 61 and AlN may be used as the second layer 62.

  As illustrated in FIG. 21G, also in the semiconductor light emitting device 137 according to the embodiment, the thickness of a part of the second semiconductor layer 20 (for example, the n-type GaN layer) is thicker than the thickness of the other part. . A third layer 63 (for example, an AlGaN layer) is provided as the third semiconductor layer 60 on the thick portion, and a second layer 62 (for example, an AlN layer) is provided on the third layer 63. A first layer 61 (for example, a GaN layer) is provided on the second layer 62. The pad portion 81 is in contact with the first layer 61, and the thin wire portion 82 a is in contact with the second semiconductor layer 20.

  In order to increase the efficiency of a light emitting device using a nitride semiconductor, it is desired to suppress the concentration of current around the pad portion 81 of the n-side electrode. By suppressing the current concentration, a uniform light emission distribution is obtained in the surface, and the light emission efficiency is improved. A method of suppressing current concentration and improving light emission efficiency by providing an insulating layer between the second semiconductor layer 20 and the pad portion 81 of the n-side electrode can be considered. However, in the case where such an insulating layer is used, the reliability depends on the large difference in thermal conductivity or the low adhesion between the insulating layer and the n-side electrode. Sex is reduced.

  In the embodiment, the pad portion 81 of the n-side electrode (second electrode 80) is formed on the low-conductivity third semiconductor layer 60, and the thin wire portion 82 is formed on the n-type second semiconductor layer 20. Form. Thereby, the in-plane light emission distribution can be made uniform, and the light emission efficiency can be improved. Further, since the n-side electrode is formed on the third semiconductor layer 60 of nitride semiconductor having high thermal conductivity and good adhesion to the electrode, deterioration due to heat generation is suppressed, and peeling of the electrode is suppressed. According to the embodiment, it is possible to provide a semiconductor light emitting device with high in-plane uniformity of light emission distribution, high efficiency, and high reliability.

  According to the embodiment, a highly efficient semiconductor light emitting device can be provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strict vertical and strict parallel but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. is good.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding a specific configuration of each element such as a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a light emitting layer, a second electrode, a first electrode, a support substrate, and a growth substrate included in the semiconductor light emitting element. Are included in the scope of the present invention as long as those skilled in the art can implement the present invention in the same manner by appropriately selecting from the well-known ranges and obtain similar effects.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor light-emitting elements that can be implemented by those skilled in the art based on the semiconductor light-emitting elements described above as embodiments of the present invention are included in the scope of the present invention as long as they include the gist of the present invention. Belonging to.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 5 ... Substrate for growth, 10 ... First semiconductor layer, 10f ... First semiconductor film, 10l ... Lower surface, 15 ... Multilayer semiconductor layer, 15f ... Multilayer semiconductor film, 16 ... Multilayer body, 20 ... Second semiconductor layer, 20f ... 2nd semiconductor film, 20u ... upper surface, 30 ... light emitting layer, 30f ... light emitting film, 31 ... barrier layer, 32 ... well layer, 40 ... first electrode, 45 ... high resistance part, 45p ... part, 45q ... part, 60 ... third semiconductor layer, 60f ... third semiconductor film, 60l ... lower surface, 60p ... part, 60q ... part, 60s ... side surface, 60t ... trench, 60u ... upper surface, 61 ... first layer, 62 ... second layer, 62a ... AlN layer, 63 ... third layer, 63a ... AlGaN layer, 64 ... laminated intermediate layer, 65 ... unevenness, 70 ... support substrate, 71 ... first intermediate conductive layer, 72 ... second intermediate conductive layer, 80 ... second electrode 81: Pad portion, 82: Fine wire portion, 82a: Fine wire, 82au ... Upper surface, 82b ... Connection portion, θ, θ1 ... Angle, λ: Wavelength, 110, 119, 120-129, 131-137 ... Semiconductor light emitting device, BL ... Barrier layer, C (Al) ... Al concentration, C (Si) ... Si concentration, PA ... Part, Po ... Light output, WL ... Well layer

The first semiconductor layer 10 includes, for example, a GaN layer containing p-type impurities (at least one of Mg, Zn, and C). The first semiconductor layer 10, the concentration of the p-type impurity, for example, Ru der 1 × ¹⁰ 18 ^{cm -3} or more 5 × ¹⁰ 21 ^{cm -3} or less. The first semiconductor layer 10 includes, for example, a p-side contact layer.

The second semiconductor layer 20 includes, for example, a GaN layer containing an n-type impurity (at least one of Si, Ge, Te, and Sn). In the second semiconductor layer 20, the concentration of n-type impurity, for example, Ru der 1 × ¹⁰ 17 ^{cm -3} or more 2 × ¹⁰ 19 ^{cm -3} or less. The second semiconductor layer 20 includes, for example, an n-side contact layer.

In embodiments, the ratio of the X-Y plane of the area S2 of the pad portion 81 for the X-Y plane of the area S1 of the second electrode 80 (S2 / S1) is 20% or more. When the area of Pas head portion 81 is thus large, the effect of efficiency improvement of the present embodiment is easily obtained.

By controlling the conductivity of the third semiconductor layer 60, the ratio of the current injected from the pad portion 81 into the semiconductor layer and the current injected from the thin wire portion 82 into the semiconductor layer is set to an arbitrary ratio. Can do. Thus, by providing the third semiconductor layer 60 instead of the insulating layer under the pad portion 81, the current density in the periphery of the pad portion 81 can be adjusted to an appropriate state, and the light emission distribution can be made to a more desired state. You can get closer. This further increases efficiency.

The resistance of the third semiconductor layer 60 is based on the thickness of the third semiconductor layer 60 and the conductivity (for example, a value based on the impurity concentration) in the third semiconductor layer 60 . The conductivity of the third semiconductor layer 60 is determined in consideration of the thickness.

Thus, when the second conductivity type first conductivity type is p-type is n-type, the improvement of the high light extraction efficiency according to the embodiment, it becomes more effective.

The third semiconductor layer _60, Al x1 _{G a 1 -x1} N layer (0 <x1 ≦ 1), i.e., at least one of the second layer 62 and third layer 63 may include.

During the removal of the growth substrate 5 (step S140), a part of the third semiconductor film 60f formed on the growth substrate 5 is left and a part thereof is removed. For example, the third semiconductor film A l N layer 62a and Al Ga N layer 63a of the 60f are removed, at least a portion of the lamination interlayer 64 remains. For example, a part of the remaining stacked intermediate layer 64 becomes the third semiconductor layer 60.

In this example, high concentration of Si is detected in a part of the third semiconductor layer 60 on the second semiconductor layer 20 side (third layer 63) (part PA in FIG. 8B). In this portion, fluctuation of the Si concentration occurs. Excluding the portion PA, the Si concentration in the third semiconductor layer 60 is lower than the Si concentration in the second semiconductor layer 20. As described above, the second semiconductor layer 20 has a local concentration between the second semiconductor layer 20 and a portion of the second semiconductor layer 60 in which the second conductivity type impurity concentration is lower than the second conductivity type impurity concentration. In particular, a portion where the impurity concentration of the second conductivity type is higher than that of the second semiconductor layer 20 (a portion PA where fluctuation of the Si concentration occurs) may be provided. In this case, a portion in which the impurity concentration of the second conductivity type is lower than the impurity concentration of the second conductivity type in the second semiconductor layer 20 can be regarded as the third semiconductor layer 60.

14A and 14B are schematic plan views illustrating characteristics of the semiconductor light emitting element.
FIG. 14A illustrates the light emission characteristics of the semiconductor light emitting device 121 according to this embodiment. FIG. 14B illustrates characteristics of the semiconductor light emitting device 119 of the reference example. In the semiconductor light emitting device 119, the third semiconductor layer 60 is not provided, and the pad portion 81 and the thin wire portion 82 of the second electrode 80 are in contact with the second semiconductor layer 20. Further, in the semiconductor light emitting device 119, the high resistance portion 45 is not provided. In these drawings, a bright part indicates that the luminance of light emission is high, and a dark part indicates that the luminance of light emission is low.

As shown in FIG. 15, the semiconductor light emitting device 121 according to the embodiment provides a higher light output Po than the semiconductor light emitting device 119 of the reference example. For example, the optical output Po of the semiconductor light emitting element 12 1 is about 5% higher than the light output Po of the semiconductor light emitting element 119.

In the first and second embodiments, the third semiconductor layer 60 can have various configurations as follows.
FIG. 21A to FIG. 21G are schematic cross-sectional views illustrating the configuration of the semiconductor light emitting element according to the embodiment.
These drawings illustrate the configuration of the second semiconductor layer 20 and the third semiconductor layer 60 together with the second electrode 80. These drawings are cross-sectional views corresponding to a part of the cross-sectional view illustrated in FIG.
As shown in FIG. 21A, in the semiconductor light emitting device 131 according to the embodiment, the first layer 61 (as the third semiconductor layer 60 is formed on the second semiconductor layer 20 (for example, the n-type GaN layer). For example, a GaN layer) is provided, a third layer 63 (for example, an AlGaN layer) is provided on the first layer 61, and a second layer 62 (for example, an AlN layer) is provided on the third layer 63. Pad portion 81, the contact second layer 62, fine lines 8 2a is in contact with the second semiconductor layer 20.

As shown in FIG. 21B, in the semiconductor light emitting device 132 according to the embodiment, the first layer 61 (as the third semiconductor layer 60 is formed on the second semiconductor layer 20 (for example, the n-type GaN layer). For example, a GaN layer), a third layer 63 (for example, an AlGaN layer), and a second layer 62 (for example, an AlN layer) are provided, and another first layer 61 is provided on the second layer 62. Pad portion 81 is in contact with the first layer 61 of the upper, thin lines 8 2a is in contact with the second semiconductor layer 20.

As shown in FIG. 21D, in the semiconductor light emitting device 134 according to the embodiment, the thickness of a part of the second semiconductor layer 20 (for example, the n-type GaN layer) is thicker than the thickness of other parts. . A first layer 61 (for example, a GaN layer) is provided as the third semiconductor layer 60 on the thick portion, and a third layer 63 (for example, an AlGaN layer) is provided on the first layer 61. A second layer 62 (for example, an AlN layer) is provided on the third layer 63. Pad portion 81, the contact second layer 62, fine lines 8 2a is in contact with the second semiconductor layer 20.

As shown in FIG. 21E, also in the semiconductor light emitting device 135 according to the embodiment, the thickness of a part of the second semiconductor layer 20 (for example, the n-type GaN layer) is thicker than the thickness of other parts. . A third layer 63 (for example, an AlGaN layer) is provided as the third semiconductor layer 60 on the thick portion, and a second layer 62 (for example, an AlN layer) is provided on the third layer 63. A first layer 61 (for example, a GaN layer) is provided on the second layer 62. Pad portion 81, in contact first layer 61, thin lines 8 2a is in contact with the second semiconductor layer 20.

As shown in FIG. 21F, also in the semiconductor light emitting device 136 according to the embodiment, the thickness of a part of the second semiconductor layer 20 (for example, the n-type GaN layer) is thicker than the thickness of other parts. . A third layer 63 (for example, an AlGaN layer) is provided as the third semiconductor layer 60 on the thick portion, and a second layer 62 (for example, an AlN layer) is provided on the third layer 63. ing. Pad portion 81, the contact second layer 62, fine lines 8 2a is in contact with the second semiconductor layer 20. In the configuration of the semiconductor light emitting device 136, a first layer 61 (for example, an AlGaN layer) is provided as the third semiconductor layer 60, and a second layer 62 (for example, an AlN layer) is provided on the first layer 61. May be considered. As described above, the second layer 62 is a layer having a higher Al composition ratio than the first layer 61, and AlGaN may be used as the first layer 61 and AlN may be used as the second layer 62.

As illustrated in FIG. 21G, also in the semiconductor light emitting device 137 according to the embodiment, the thickness of a part of the second semiconductor layer 20 (for example, the n-type GaN layer) is thicker than the thickness of the other part. . A third layer 63 (for example, an AlGaN layer) is provided as the third semiconductor layer 60 on the thick portion, and a second layer 62 (for example, an AlN layer) is provided on the third layer 63. A first layer 61 (for example, a GaN layer) is provided on the second layer 62. Pad portion 81, in contact first layer 61, thin lines 8 2a is in contact with the second semiconductor layer 20.

Claims (18)

A first electrode;
A p-type first semiconductor layer including a nitride semiconductor provided on the first electrode;
A light emitting layer provided on the first semiconductor layer and including a nitride semiconductor;
An n-type second semiconductor layer provided on the light emitting layer and including a nitride semiconductor;
A third semiconductor layer provided on a part of the second semiconductor layer, including a nitride semiconductor and having an impurity concentration of 1 × 10 ¹⁷ / cm ³ or less lower than an n-type impurity concentration of the second semiconductor layer; A semiconductor layer;
A light-shielding pad portion provided on the third semiconductor layer and spaced from the second semiconductor layer;
A fine wire portion extending from the pad portion;
A second electrode comprising:
With
The thin line portion is
A light-shielding fine line extending along a plane perpendicular to the stacking direction from the first semiconductor layer toward the second semiconductor layer and in contact with the second semiconductor layer;
A connection portion provided between the fine wire and the pad portion, connecting the fine wire and the pad portion, and along a side surface of the third semiconductor layer;
A semiconductor light emitting device comprising: A high resistance portion that is provided between the first electrode and the first semiconductor layer and that overlaps the thin line when projected onto the plane;
The semiconductor light emitting element according to claim 1, wherein a resistance of the high resistance portion is higher than a resistance of the first semiconductor layer. A high resistance portion that is provided between the first electrode and the first semiconductor layer and that overlaps the thin line when projected onto the plane;
The semiconductor light emitting element according to claim 1, wherein a contact resistance between the high resistance portion and the first semiconductor layer is higher than a contact resistance between the first electrode and the first semiconductor layer. A high resistance portion that is provided between the first electrode and the first semiconductor layer and that overlaps the thin line when projected onto the plane;
The semiconductor light emitting element according to claim 1, wherein a contact resistance between the high resistance portion and the first electrode is higher than a contact resistance between the first semiconductor layer and the first electrode.   The semiconductor light emitting element according to claim 2, wherein the high resistance portion does not overlap at least a part of the pad portion when projected onto the plane.   The semiconductor light emitting element according to claim 1, wherein at least a part of the thin line portion is embedded in the second semiconductor layer.   The semiconductor light emitting element according to claim 1, wherein a material of the thin wire portion is the same material as at least a part of the pad portion.   The angle between the portion of the side surface of the third semiconductor layer where the connection portion is provided and the plane is 20 degrees or more and 85 degrees or less. The semiconductor light emitting element as described. Of the side surface of the third semiconductor layer, the angle between the portion where the connection portion is provided and the plane is
The semiconductor light emitting element according to claim 8, wherein the angle between the side surface of the second semiconductor layer and the plane is the same.   10. The concentration of the n-type impurity in the third semiconductor layer is not more than 0.5 times the concentration of the n-type impurity in the second semiconductor layer. 10. Semiconductor light emitting device.   The semiconductor light emitting element according to claim 1, wherein the third semiconductor layer includes a GaN layer. The semiconductor light emitting element according to claim 1, wherein the third semiconductor layer includes an Al _x1 Ga _1-x1 N layer (0 <x1 ≦ 1).   The semiconductor light-emitting device according to claim 1, wherein the third semiconductor layer has unevenness provided in at least a portion of the upper surface of the third semiconductor layer that is not covered with the second electrode. element.   The semiconductor light-emitting device according to claim 1, wherein a plurality of the thin lines are provided, and ends of at least two of the plurality of thin lines opposite to the pad portions are not connected to each other. element.   The semiconductor light emitting element according to claim 1, wherein an electrical resistance of the third semiconductor layer is twice or more an electrical resistance of the second semiconductor layer. The second electrode includes Al;
The semiconductor light emitting element according to claim 1, wherein the first electrode contains Ag.   The ratio of the area on the plane of the pad portion to the area on the plane of the second electrode is 20% or more, The semiconductor light emitting element according to claim 1.   The width of the thin line portion along a direction orthogonal to the extending direction of the thin line portion is 6% or more and 15% or less of a width along the orthogonal direction of the pad portion. The semiconductor light emitting element as described in one.