JP2015015072A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cope with variations in the amount of held data during standby.SOLUTION: A semiconductor integrated circuit includes a logic circuit (logic) and a plurality of SRAM modules 2 and 3. The plurality of SRAM modules can perform power-supply control independently of the logic circuit, and can also perform power-supply control independently from each other. More specifically, one terminal (arvss) and the other terminal (vssm) of a potential control circuit of each SRAM module are connected to a cell array (cell_array) and a local power supply line (vssm). The local power supply line (vssm) of one SRAM module 2 and the other SRAM module 3 is shared by a shared local power supply line (vssm22). One and the other power switches PWSW22 and PWSW23 of the one and the other SRAM modules 2 and 3 are commonly connected to the shared local power supply line (vssm22).

Description

  The present invention relates to a semiconductor integrated circuit and an operation method thereof, and more particularly to a technique effective for dealing with a change in the amount of retained data in a standby state.

  As the semiconductor manufacturing process is miniaturized, the number of MOSFETs integrated in a single large scale integrated circuit (LSI) can be increased, and the leakage current increases. Especially in mobile applications, this type of system-on-a-chip (SoC) needs to meet stringent leakage current requirements due to limited battery capacity. According to the following Non-Patent Document 1, an effective method for such a situation is that power is supplied to the necessary IP while the power is cut off at the standby IP. Therefore, a fine-grained power gating scheme that uses a large number of power supply regions is required to realize a low power consumption LSI for mobile SoC.

  In the following Patent Document 1, the first area includes a central processing unit and peripheral circuit modules, and the second area includes an internal memory and a backup register in order to achieve both a low standby current due to power interruption and a high-speed recovery from standby due to an interrupt. In the information processing apparatus, the first area is controlled to supply current by a first power switch, and the second area is controlled to supply current by a second power switch. At the time of transition to the standby mode, after the internal information is saved in the internal memory or the backup register, the first power switch is turned off, the supply of current to the first area is stopped, and the second power switch is turned off. The internal information saved in the second area can be held.

  In Patent Document 2 below, a switch, a diode-connected MOS transistor, and a resistor are connected in parallel between a source line to which a source electrode of a driving MOS transistor is connected and a ground potential line in order to reduce leakage current of the SRAM circuit. It is described to do. During standby, the switch connected between the source line and the ground potential line is controlled to be in an OFF state, and the potential of the source line is higher than the ground potential due to the relationship between the leakage current of the memory cell, the diode-connected MOS transistor, and the resistance. Set and the leakage current is reduced. A switch MOS transistor is connected between the ground potential side power supply line of the peripheral circuit of the SRAM excluding the word driver and the ground potential, and this switch MOS transistor is controlled to be turned off by a control signal during standby. Accordingly, the ground potential side power supply line of the peripheral circuit of the SRAM rises, and the leakage current of the peripheral circuit during standby is reduced.

  Patent Document 3 below describes that a leakage current reducing circuit is connected between a low potential terminal of a latch circuit or SRAM cell configured by CMOS and a ground potential. The leakage current reduction circuit includes an NMOS switching transistor, a control PMOS transistor, and a control NMOS transistor. The drain / source path of the NMOS switching transistor is connected between the low potential terminal and the ground potential, and the source, gate, and drain of the control PMOS transistor Are connected to the power supply voltage, the standby signal terminal and the gate of the NMOS switching transistor, respectively, and the drain, gate and source of the control NMOS transistor are connected to the low potential terminal, the gate of the NMOS switching transistor and the standby signal terminal, respectively. In operation of the circuit, in response to the low level signal at the standby signal terminal, the control PMOS transistor, the control NMOS transistor, and the NMOS switching transistor are turned on, off, and on, respectively, and the low potential terminal has a low impedance to the ground potential. Therefore, the latch circuit or SRAM cell composed of CMOS executes normal operation. During standby, in response to a high level signal at the standby signal terminal, the control PMOS transistor and the control NMOS transistor are turned off and on, respectively, and the NMOS switching transistor reduces the leakage current of the latch circuit or SRAM cell composed of CMOS. By operating like a MOS diode as a bias current, the potential of the low potential terminal is held at a constant potential higher than the ground potential, and the leakage current during standby is reduced.

  Patent Document 4 listed below describes that a voltage supply circuit is connected between a power supply voltage line and a memory cell power supply line in order to achieve both a static noise margin and a write margin even with a low power supply voltage in a static RAM. ing. At the time of writing, a high level control signal is supplied to the gate of the P-channel MOSFET of the voltage supply circuit, the P-channel MOSFET is turned off, the voltage of the memory cell power line is lowered, the static noise margin is lowered, and the write margin is reduced. Be improved.

JP 2005-011166 A JP 2004-206745 A JP 2007-150761 A JP 2006-085786 A

Yusuke Kano et al, “Hierarchical Power Distribution, Power Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SOCs”, U U E L 42, NO. 1, JANUARY 2007, PP. 74-83.

  Prior to the present invention, the present inventors engaged in research and development of a semiconductor integrated circuit with low power consumption.

  FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit studied by the present inventors prior to the present invention.

  The semiconductor integrated circuit shown in FIG. 2 includes a logic circuit (logic), a static RAM (SRAM1, SRAM2, SRAM3), and power switches PWSW21, PWSW22. The static RAM (SRAM1, SRAM2, SRAM3) includes a cell array (cell_array), a peripheral circuit (peripheral), a source line potential control circuit (arvss_control), and peripheral circuit power switches PESW21, PESW22, and PESW23.

  Since the control signal cnt_21 falls when the power is shut off, the power switch PWSW21 connected to the logic circuit (logic) and the static RAM (SRAM1) is turned off. Accordingly, the potential of the local power supply vssl21 in the power supply domain rises to the power supply potential Vdd, and the logic circuit (logic) and the static RAM (SRAM1) connected to the local power supply vssl21 are cut off. Accordingly, all data stored in the static RAM (SRAM 1) connected to the local power supply vssl21 is discarded. Therefore, the data that needs to be stored is stored in other static RAMs (SRAM2, SRAM3) connected to other local power supply vssm22, and the other power switch PWSW22 is kept on even when the power is cut off. Yes. As a result, the other local power supply vssm22 is maintained at the ground potential Vss.

  On the other hand, when the power is shut off, the peripheral circuit power switches PESW22 and PESW23 are turned off by the peripheral circuit (peripheral) control circuit (RSCNT) of the other static RAM (SRAM2, SRAM3) connected to the other local power supply vssm22. On the other hand, the source line potential control circuit arvss_control sets the potentials of the cell array source lines arvss22 and arvss23 of the cell arrays (cell_array) of other static RAMs (SRAM2 and SRAM3) to a level slightly higher than the ground potential Vss. Therefore, by turning off the peripheral circuit power switches PESW22 and PESW23, it is possible to cut off leakage currents of peripheral circuits (peripherals) other than some circuits such as the control circuit (RSCNT) and the word driver. Furthermore, the cell array (cell_array) is not damaged by the potential of the cell array source lines arvss22 and arvss23, which is slightly higher than the ground potential Vss of the cell array source lines arvss22 and arvss23. ) Current can be reduced.

  FIG. 3 is a diagram showing a configuration of a source line potential control circuit (arvss_control) of another static type RAM (SRAM2, SRAM3) of the semiconductor integrated circuit studied by the present inventors prior to the present invention shown in FIG. It is.

  FIG. 3 shows a cell array (cell_array) and a source line potential control circuit (arvss_control), as well as a peripheral circuit (peripheral) and a peripheral circuit power switch PESW. As shown in FIG. 3, the source line potential control circuit (arvss_control) includes a power switch SW1, a resistor RN1, and a diode-connected MOS transistor MN1 connected in parallel between the cell array source line arvss and the ground potential Vss. Yes. In response to the fall of the control signal rs, the peripheral circuit power switch PESW is turned off, and the leakage current of the peripheral circuit (peripheral) other than the control circuit (RSCNT) and the word driver is cut off, while the source line potential control The power switch SW1 of the circuit (arvss_control) is also turned off. As a result, the potential of the cell array source line arvss is set to a potential slightly higher than the ground potential Vss by the current path between the resistor RN1 of the source line potential control circuit (arvss_control) and the diode-connected MOS transistor MN1. The current of the cell array (cell_array) is reduced to such an extent that the data retained in the cell array (cell_array) of the static RAM (SRAM 23) is not destroyed.

  FIG. 4 shows operation waveforms of each part of the source line potential control circuit (arvss_control) of another static type RAM (SRAM2, SRAM3) of the semiconductor integrated circuit examined by the present inventors prior to the present invention shown in FIG. FIG.

  When the control signals rs21, 22, and 23 rise, the control signals rsb21, 22, and 23 fall, so that the peripheral circuit power switches PESW21, 22, and 23 are turned off. Since the peripheral circuit power switches PESW 21, 22, and 23 are turned off in this way, the current path from the peripheral circuit (peripheral) of each SRAM module (SRAM1, SRAM2, SRAM3) to the ground potential Vss is cut off, and the SRAM module The potentials of the local power supply lines vssp21, 22, and 23 of the peripheral circuits (SRAM1, SRAM2, SRAM3) rise to the power supply voltage Vdd or the vicinity thereof. However, since the control circuits (rscnt, RSCNT) that generate the control signals rsb21, rsb22, rsb23 that control the peripheral circuit power switches PESW21, 22, 23 need to output a low level signal, the local power lines vssp21, 22 , 23 instead of directly connected to other local power sources vssl21, vssm22. In addition, a circuit that needs to output a low level signal such as a word driver is also directly connected to other local power sources vssl21 and vssm22. Further, when the control signals rsb21, 22, and 23 fall, the voltage of the cell array source lines arvss21, 22, and 23 is increased by the source line potential control circuit (arvss_control). However, the voltage is raised to a voltage level (for example, several hundred millivolts) that does not destroy the data held in the cell array cell_array of the SRAM 1, 2, and 3. As a result, it is possible to reduce the leakage current of the SRAMs 1, 2, and 3 while retaining the retained data of the SRAMs 1, 2, and 3.

  Further, when the logic circuit (logic) of the logic circuit portion does not need to operate, the power supply switch PWSW21 is turned off by turning off the control signal cnt21, and the power supply of the logic circuit (logic) is cut off. The As a result, the local power supply line vssl21 of the logic circuit (logic) rises to or near the power supply voltage Vdd. At this time, since the cell array source line arvss21 of the cell array (cell_array) of the static RAM (SRAM1) connected to the local power supply line vssl21 also rises to the power supply voltage Vdd or the vicinity thereof, the static RAM (SRAM1) stores the retained data. I can't hold it.

  Further, in order to reduce power consumption, the control signal cnt22 is set to a low state, thereby entering a deep standby state. The power switch PWSW22 connected to the other static RAM (SRAM2, 3) is turned off, and the other local power supply vssm22 also rises to or near the power supply voltage Vdd. As a result, the leakage current of other static RAMs (SRAMs 2 and 3) can be reduced.

  As described above, the control method shown in FIGS. 2 to 4 can reduce current consumption of a semiconductor integrated circuit including a plurality of SRAM modules such as a system-on-chip (SoC). However, according to the control method shown in FIG. 4, the plurality of SRAM modules are collectively brought into a deep standby state. As a result of studies by the present inventors, it has been found that in a semiconductor integrated circuit such as a system-on-chip (SoC), the amount of data held in the deep standby state in a plurality of SRAM modules varies greatly depending on the operation state and the operation program. On the other hand, it has been clarified by examination by the present inventors that the control method shown in FIG. 4 cannot cope with a change in the amount of retained data in the deep standby state.

  The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to provide a semiconductor integrated circuit that can cope with a change in the amount of retained data in a standby state.

  Another object of the present invention is to reduce the chip area of a semiconductor integrated circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a typical embodiment of the present invention is a semiconductor integrated circuit including a logic circuit (logic) and a plurality of SRAM modules (SRAMs 2 and 3) capable of storing data related to the logic circuit.

  The plurality of SRAM modules (SRAMs 2 and 3) can be controlled in power supply independently of the logic circuit (logic).

  Independent power control is possible among the plurality of SRAM modules (SRAMs 2 and 3) (see FIGS. 5 and 11).

  Specifically, one terminal (arvss) and the other terminal (vssm) of the potential control circuit (arvss_control) of each of the SRAM modules (SRAMs 2 and 3) are the cell array (cell_array) and the local power supply line. (vssm).

  A local power supply line (vssm) of one SRAM module of the plurality of SRAM modules (SRAM2, 3) and a local power supply line (vssm) of the other SRAM module of the plurality of SRAM modules (SRAM2, 3) are shared local power supply. Shared by line (vssm22).

  The power switch (PWSW22) of the one SRAM module of the plurality of SRAM modules (SRAM2, 3) and the power switch (PWSW23) of the other SRAM module of the plurality of SRAM modules (SRAM2, 3) are shared. It is characterized by being commonly connected to a local power line (vssm 22) (see FIG. 11).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to provide a semiconductor integrated circuit that can cope with a change in the amount of retained data in the standby state.

FIG. 1 shows an example of the configuration of a semiconductor integrated circuit according to a twenty-fourth embodiment of the present invention incorporating three SRAM modules (SRAMs 1, 2, and 3) according to any one of the first to twenty-third embodiments of the present invention. FIG. FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit studied by the present inventors prior to the present invention. FIG. 3 is a diagram showing a configuration of a source line potential control circuit (arvss_control) of another static type RAM (SRAM2, SRAM3) of the semiconductor integrated circuit studied by the present inventors prior to the present invention shown in FIG. It is. FIG. 4 shows operation waveforms of each part of the source line potential control circuit (arvss_control) of another static type RAM (SRAM2, SRAM3) of the semiconductor integrated circuit examined by the present inventors prior to the present invention shown in FIG. FIG. FIG. 5 is a diagram showing a configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 6 is a diagram showing the configuration of the source line potential control circuit (arvss_control) of the SRAM module (SRAM1, SRAM2, SRAM3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. FIG. 7 is a diagram showing a configuration of three SRAM modules (SRAMs 1, 2, and 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. FIG. 8 is a diagram showing a configuration of a source line potential control circuit (arvss_control) of the SRAM module of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. FIG. 9 is a diagram showing another configuration of the three SRAM modules (SRAM 1, 2, 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. FIG. 10 is a diagram showing a chip layout configuration of three SRAM modules (SRAMs 1, 2, and 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. FIG. 11 is a diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. 12 shows three SRAM modules (SRAMs 1, 2, 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5 or the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. It is a figure which shows the structure of the several memory cell (MC) contained in each SRAM module. FIG. 13 shows three SRAM modules (SRAMs 1, 2, 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5 or the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. It is a figure which shows the other structure of the several memory cell (MC) contained in each SRAM module. FIG. 14 is a diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 15 shows a configuration of a plurality of memory cells (MC) included in each SRAM module of the three SRAM modules (SRAM 1, 2, 3) of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. FIG. FIG. 16 shows another configuration of a plurality of memory cells (MC) included in each SRAM module of the three SRAM modules (SRAM 1, 2, 3) of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. FIG. FIG. 17 shows another configuration of a plurality of memory cells (MC) included in each SRAM module of the three SRAM modules (SRAM 1, 2, 3) of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. FIG. FIG. 18 is a diagram showing a configuration of a semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 19 is a diagram showing a configuration of a semiconductor integrated circuit according to the fifth embodiment of the present invention. FIG. 20 is a diagram showing a configuration of a semiconductor integrated circuit according to the sixth embodiment of the present invention. FIG. 21 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the seventh embodiment of the present invention. FIG. 22 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the eighth embodiment of the present invention. FIG. 23 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the ninth embodiment of the present invention. FIG. 24 is a diagram showing a configuration of each SRAM module of three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the tenth embodiment of the present invention. FIG. 25 is a diagram showing the configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the eleventh embodiment of the present invention. FIG. 26 is a diagram showing a configuration of each SRAM module of three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twelfth embodiment of the present invention. FIG. 27 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the thirteenth embodiment of the present invention. FIG. 28 is a diagram showing a configuration of each SRAM module of three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the fourteenth embodiment of the present invention. FIG. 29 is a diagram showing a configuration of each SRAM module of three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the fifteenth embodiment of the present invention. FIG. 30 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the sixteenth embodiment of the present invention. FIG. 31 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the seventeenth embodiment of the present invention. FIG. 32 shows a structure of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the eighteenth embodiment of the present invention. FIG. 33 shows a structure of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the nineteenth embodiment of the present invention. FIG. 34 is a diagram showing the configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twentieth embodiment of the present invention. FIG. 35 shows a structure of each SRAM module of the three SRAM modules (SRAMs 1, 2, and 3) included in the semiconductor integrated circuit according to the twenty-first embodiment of the present invention. FIG. 36 shows a structure of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twenty-second embodiment of the present invention. FIG. 37 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twenty-third embodiment of the present invention.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A typical embodiment of the present invention is a semiconductor integrated circuit including a logic circuit (logic) and a plurality of SRAM modules (SRAMs 2 and 3) capable of storing data related to the logic circuit. .

  The plurality of SRAM modules (SRAMs 2 and 3) can be controlled in power supply independently of the logic circuit (logic).

  Independent power control is possible among the plurality of SRAM modules (SRAMs 2 and 3) (see FIGS. 5 and 11).

  According to the embodiment, it is possible to cope with a change in the amount of retained data in the standby state.

  The semiconductor integrated circuit according to a preferred embodiment further includes another SRAM module (SRAM 1) that can control power supply in common with the logic circuit (logic).

  The logic circuit (logic) and the other SRAM module (SRAM 1) can be controlled in a power-off state in common.

  Before the logic circuit (logic) and the other SRAM module (SRAM1) are commonly controlled to the power-off state, the data of the other SRAM module (SRAM1) is stored in the plurality of SRAM modules (SRAM2, 3). ) Can be saved in at least one of the SRAM modules (see FIGS. 5 and 11).

  The semiconductor integrated circuit according to another preferred embodiment further includes a plurality of power switches (PWSWs 21, 22, and 23).

  The other SRAM modules (SRAM1), the SRAM modules of the plurality of SRAM modules (SRAM2, 3), and the power switches of the plurality of power switches (PWSW21, 22, 23) are connected in series. is there.

  Each of the plurality of power switches (PWSW 21, 22, 23) is controlled to be in an OFF state, so that each of the SRAM modules can be controlled to be in a power cutoff state.

  Each of the plurality of power switches (PWSW 21, 22, 23) is controlled to be in an ON state, whereby each of the SRAM modules can be controlled to an active state and a standby state. (See FIGS. 5 and 11).

  According to a more preferred embodiment, each SRAM module includes a peripheral circuit (peripheral), a cell array (cell_array), and a potential control circuit (arvss_control).

  In each of the SRAM modules, the cell array (cell_array) and the potential control circuit (arvss_control) are connected in series. The cell array (cell_array) and the potential control circuit (arvss_control) are connected in series and the peripheral circuit (peripheral). Is characterized by being connected in parallel.

  According to another more preferred embodiment, in each SRAM module controlled to the active state, between one terminal (arvss) and the other terminal (vssm) of the potential control circuit (arvss_control). The terminal voltage (arvss-vssm) is controlled to a low voltage state, and the power supply voltage (Vdd-Vss) is supplied to the peripheral circuit (peripheral), while the power supply voltage (Vdd-Vss) is supplied to the cell array (cell_array). ) Is supplied by the potential control circuit (arvss_control).

  In each SRAM module controlled to the standby state, the voltage (arvss-vssm) between the terminals of the potential control circuit (arvss_control) is controlled to a high voltage state higher than the low voltage, and the power supply voltage (Vdd− Vss) is stopped from being supplied to the peripheral circuit (peripheral), and an operating voltage lower than the power supply voltage (Vdd−Vss) is supplied to the cell array (cell_array) by the potential control circuit (arvss_control). To do.

  In a specific embodiment, the one terminal (arvss) and the other terminal (vssm) of the potential control circuit (arvss_control) of each SRAM module are connected to the cell array (cell_array) and the local power line (vssm). Connected to each.

  A local power supply line (vssm) of one SRAM module of the plurality of SRAM modules (SRAM2, 3) and a local power supply line (vssm) of the other SRAM module of the plurality of SRAM modules (SRAM2, 3) are shared local power supply. Shared by line (vssm22).

  The power switch (PWSW22) of the one SRAM module of the plurality of SRAM modules (SRAM2, 3) and the power switch (PWSW23) of the other SRAM module of the plurality of SRAM modules (SRAM2, 3) are shared. It is characterized by being commonly connected to a local power line (vssm 22) (see FIG. 11).

  In a more specific embodiment, a P-well in which a plurality of N-channel MOS transistors of the cell array (cell_array) of the one SRAM module of the plurality of SRAM modules (SRAM2, 3) are formed, and the plurality of SRAMs The P well in which the plurality of N channel MOS transistors of the cell array (cell_array) of the other SRAM module of the modules (SRAMs 2 and 3) is formed is a common P well. (See FIG. 11).

  In another more specific embodiment, between the one terminal (arvss) and the other terminal (vssm) of the potential control circuit (arvss_control) of each SRAM module, the inter-terminal voltage ( a voltage drop element (RN1, MN1) that sets the high voltage state (arvss-vssm) to a control switch (SW1) that sets the inter-terminal voltage (arvss-vssm) to the low voltage state. It is a characteristic (see FIG. 3).

  In a different more specific embodiment, the cell array (cell_array) of each SRAM module includes a pair of drive N-channel MOS transistors (MNDL, MNDR) and a pair of load P-channel MOS transistors (MPUL, MPUR). It has a plurality of SRAM memory cells (MC) including a pair of transfer N-channel MOS transistors (MNSL, MNSR) (see FIG. 12).

  The semiconductor integrated circuit according to the most specific embodiment includes a plurality of data processing units (CPU1, CPU2, Video, Audio).

  Each data processing unit of the plurality of data processing units includes the logic circuit (logic) and the plurality of SRAM modules (SRAMs 2 and 3) (see FIG. 1).

  [2] A typical embodiment of another aspect of the present invention is a semiconductor including a logic circuit (logic) and a plurality of SRAM modules (SRAMs 2 and 3) capable of storing data related to the logic circuit. An operation method of an integrated circuit. This operation method has the following steps (see FIGS. 5 and 11).

  Enabling power control of the logic circuit (logic) independently of the plurality of SRAM modules (SRAMs 2 and 3).

  Enabling independent power control between the plurality of SRAM modules (SRAMs 2 and 3);

  According to the embodiment, it is possible to cope with a change in the amount of retained data in the standby state.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<< Configuration of Semiconductor Integrated Circuit of First Embodiment >>
FIG. 5 is a diagram showing a configuration of the semiconductor integrated circuit according to the first embodiment of the present invention.

  The semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5 is different from the semiconductor integrated circuit examined by the present inventors prior to the present invention shown in FIG. 2 in the following points.

  That is, in the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5, the power switch PWSW22 is connected between the local power supply vssm22 of the SRAM module (SRAM2) and the ground potential Vss, and the control of the power switch PWSW22 is performed. A control signal cnt22 is supplied to the gate, a power switch PWSW23 is connected between the local power supply vssm23 of the SRAM module (SRAM3) and the ground potential Vss, and a control signal cnt23 is supplied to the control gate of the power switch PWSW23. The

  In the SRAM module (SRAM2) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5, the peripheral circuit power switch PEWS22 is connected between the peripheral circuit (peripheral) and the local power supply vssm22, and the cell array (cell_array) is connected. ) And a local power supply vssm 22 are connected to a source line potential control circuit (arvss_control). The control signal rsb22 of the peripheral circuit (peripheral) control circuit (RSCNT) is supplied to the control gate of the peripheral circuit power switch PEWS22 and the control input terminal of the source line potential control circuit (arvss_control).

  In the SRAM module (SRAM3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5, a peripheral circuit power switch PEWS23 is connected between the peripheral circuit (peripheral) and the local power supply vssm23, and a cell array (cell_array). And a local power supply vssm23 are connected to a source line potential control circuit (arvss_control). The control signal rsb23 of the peripheral circuit (peripheral) control circuit (RSCNT) is supplied to the control gate of the peripheral circuit power switch PEWS23 and the control input terminal of the source line potential control circuit (arvss_control).

  Inside the SRAM module (SRAM1) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5, as with the SRAM module (SRAM1) of the semiconductor integrated circuit shown in FIG. A peripheral circuit power switch PEWS21 is connected between the power supply vssl21 and a source line potential control circuit (arvss_control) is connected between the cell array (cell_array) and the local power supply vssl21. The control signal rsb21 of the peripheral circuit (peripheral) control circuit (RSCNT) is supplied to the control gate of the peripheral circuit power switch PEWS21 and the control input terminal of the source line potential control circuit (arvss_control).

  The local power supply vssl21 of the SRAM module (SRAM1) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5 is a logic circuit (logic) similar to the SRAM module (SRAM1) of the semiconductor integrated circuit shown in FIG. ) And the power switch PWSW21.

  FIG. 6 is a diagram showing the configuration of the source line potential control circuit (arvss_control) of the SRAM module (SRAM1, SRAM2, SRAM3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG.

  FIG. 6 shows a cell array (cell_array), a source line potential control circuit (arvss_control), and a power switch PWSW. As shown in FIG. 6, the source line potential control circuit (arvss_control) includes a power switch NSW, a resistor RESI, and a diode-connected MOS transistor DIOD connected in parallel between the cell array source line arvss and the local power source vssm. .

《Active state》
In the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5, when a write operation or a read operation is performed on any one of the three SRAM modules (SRAM1, 2, 3), three control signals At the same time as setting any one of cnt21, cnt22, and cnt23 to a high level, any one of the three control signals rsb21, rsb22, and rsb23 is set to a high level.

  In the activated SRAM module, the power switch PWSW is turned on by the control signal cnt, and the peripheral circuit power switch PESW is responded to the rise of the control signal rsb of the peripheral circuit (peripheral) control circuit (RSCNT). Is turned on and the peripheral circuit (peripheral) is activated, while the power switch NSW of the source line potential control circuit (arvss_control) is also turned on. Therefore, the potential of the cell array source line arvss is set to the ground potential Vss by the source line potential control circuit (arvss_control), and the write operation or read operation of the cell array (cell_array) of the activated SRAM module can be performed. Become.

《Deep standby state》
In the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5, the power switch PWSW21 is turned off by setting the control signal cnt21 to the low level, so that the logic circuit (logic) and the SRAM module (SRAM1) Is in a deep standby state. When it is necessary to save the data of the SRAM module (SRAM1), the data of the SRAM module (SRAM1) is saved in the other SRAM modules (SRAM2, SRAM3) before entering the deep standby state. Further, since the power switch PWSW22 is turned off by setting the control signal cnt22 to the low level, the SRAM module (SRAM2) is brought into a deep standby state. When it is necessary to save the data of the SRAM module (SRAM2), the data of the SRAM module (SRAM2) is saved in the other SRAM modules (SRAM1, SRAM3) before the deep standby state is set. Similarly, by setting the control signal cnt23 to the low level, the power switch PWSW23 is turned off, so that the SRAM module (SRAM3) is brought into a deep standby state. When it is necessary to save the data of the SRAM module (SRAM3), the data of the SRAM module (SRAM3) is saved in the other SRAM modules (SRAM1, SRAM2) before the deep standby state is set. In this way, according to the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5, the amount of retained data in the deep standby state can be changed.

<Standby state>
In the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5, three control signals cnt21, cnt22, and cnt23 are set to a high level, while any one of the three control signals rsb21, rsb22, and rsb23 is set to a low level. By setting, one of the three SRAM modules (SRAM 1, 2, 3) is set to the standby state. In the SRAM module in the standby state, the peripheral circuit power switch PESW is turned off in response to the falling edge of the control signal rsb of the peripheral circuit (peripheral) control circuit (RSCNT), and other than the control circuit (RSCNT) The peripheral circuit (peripheral) leak current is cut off, while the power switch NSW of the source line potential control circuit (arvss_control) is also turned off. Therefore, the potential of the cell array source line arvss is set to a potential slightly higher than the ground potential Vss by the resistor RESI of the source line potential control circuit (arvss_control) and the current path of the diode-connected MOS transistor DIOD, and the standby state is set. The current of the cell array (cell_array) is reduced to such an extent that the retained data of the cell array (cell_array) of the SRAM module is not destroyed.

<< Configuration of SRAM module >>
FIG. 7 is a diagram showing a configuration of three SRAM modules (SRAMs 1, 2, and 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG.

  The SRAM module shown in FIG. 7 includes a control unit including a cell array (ARRAY_BIT [1]... ARRAY_BIT [n]) and a source line potential control circuit (ARVSS_CNT [1]... ARVSS_CNT [n]). (CONTROL), a word driver (WORD_DRIVER) for driving a word line, an I / O unit (IO [1] ... IO [n]) for inputting / outputting data, a power switch (PWSW [1] ... PWSW [n]) Is included.

  The cell array (ARRAY_BIT [1],..., ARRAY_BIT [n]) includes a plurality of word lines wl [1]... Wl [m] and a plurality of complementary bit line pairs bb [1], bt [1], bb [2]. , Bt [2] and a plurality of memory cells (MC). The word driver (WORD_DRIVER) includes a plurality of CMOS inverters connected to a plurality of word lines wl [1]... Wl [m]. The I / O unit (IO [1]... IO [n]) includes a plurality of selectors connected to a plurality of complementary bit line pairs bb [1], bt [1], bb [2], bt [2] ( SELECTOR) and a plurality of sense amplifiers (SA). Similarly to FIG. 6, the source line potential control circuit (ARVSS_CNT [1]... ARVSS_CNT [n]) is diode-connected with a power switch NSW, a resistor RESI connected in parallel between the cell array source line arvss and the local power source vssm. MOS transistor DIOD is included. In response to the address signal a [1]... A [k], the control unit (CONTROL) sends a plurality of CMOS inverters of the word driver (WORD_DRIVER) and I / O units (IO [1]... IO [n]). And a decoder (DECODER) that drives a plurality of selectors (SELECTOR). The control unit (CONTROL) includes a CMOS inverter and a power switch (PWSW [1]) that generate a control signal rsb1 supplied to the control gate of the power switch NSW of the source line potential control circuit (ARVSS_CNT [1]... ARVSS_CNT [n]). ... PWSW [n]) and a CMOS inverter that generates a control signal cnt to be supplied to the control gate.

  In a semiconductor integrated circuit such as a system-on-chip (SoC), a compile drum (CRAM) capable of various combinations of SRAM component parts is used in order to meet various user requirements. In the compile drum (CRAM) shown in FIG. 7, the source line potential control circuit (ARVSS_CNT [1]... ARVSS_CNT [n]) and the power switch (PWSW [1]... PWSW [n]) are in bit units ([1]. ... [n]). Therefore, in the compile drum (CRAM) shown in FIG. 7, the number of columns of memory cells (MC) and I / O units (IO [1]. It is possible to cope easily by changing the number of [n]). That is, in the compile drum (CRAM) of FIG. 7, the source line potential control circuit (ARVSS_CNT [1]... ARVSS_CNT [n]) and the power switch (PWSW [1]... PWSW [n]) are in bit units ([1]. [N]), even when the number of bits of the compile drum (CRAM) changes, the number of source line potential control circuits and power switch Therefore, the potential of the cell array source line arvss can be maintained appropriately.

  The compile drum (CRAM) shown in FIG. 7 employs a two-column multiplex system in which one I / O line (q [1]... Q [n]) is shared by two memory cell columns. . Of course, the number of column multiplexes can be any number.

  FIG. 8 is a diagram showing a configuration of a source line potential control circuit (arvss_control) of the SRAM module of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG.

  The source line potential control circuit (arvss_control) shown in FIG. 8 includes a resistor RESI connected between the cell array source line arvss and the local power supply vssm, an NMOS switching transistor MDIOD_SW, a control PMOS transistor MPG, and a control NMOS transistor. Including MNG. The drain / source path of the NMOS switching transistor MDIOD_SW is connected between the cell array source line arvss and the local power supply vssm, and the source, gate and drain of the control PMOS transistor MPG are the power supply voltage gcnt, standby signal terminal rs and NMOS, respectively. The drain, the source and the gate of the control NMOS transistor MNG are connected to the cell array source line arvss, the gate of the NMOS switching transistor MDIOD_SW and the standby signal terminal rs, respectively. During the operation of the circuit, the control PMOS transistor MPG, the control NMOS transistor MNG, and the NMOS switching transistor MDIOD_SW are turned on, off, and on, respectively, in response to the low level signal at the standby signal terminal rs. Since the line arvss is connected to the local power supply vssm with a low impedance, the cell array (cell_array) executes a normal operation. During standby, the control PMOS transistor MPG and the control NMOS transistor MNG are turned off and on in response to the high level signal at the standby signal terminal rs, and the NMOS switching transistor MDIOD_SW uses the leakage current of the cell array (cell_array) as a bias current. By operating like a MOS diode, the potential of the cell array source line arvss is held at a constant potential higher than the local power supply vssm, and the leakage current during standby is reduced.

  FIG. 9 is a diagram showing another configuration of the SRAM module (SRAM 1, 2, 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG.

  The SRAM module shown in FIG. 9 differs from the SRAM module shown in FIG. 7 in that the source line potential control circuit (arvss_control) of the SRAM module shown in FIG. 9 does not have the circuit configuration shown in FIG. The configuration is adopted. In the SRAM module shown in FIG. 9, one control PMOS transistor MPG and one control NMOS transistor MNG driving a plurality of NMOS switching transistors MDIOD_SW in a plurality of source line potential control circuits (arvss_control) are controlled by It is arranged in one place inside the unit (CONTROL).

  As described above, according to the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. 5 to 9, the first power switch PWSW 21 connected to the first SRAM module (SRAM 1) is provided. The first local power supply line vssl21 is set to the high level by controlling to the off state by the low-level first control signal cnt21, and the logic circuit (logic) and the first SRAM module (SRAM1) are in the deep standby state. Is done. In this state, the second power supply switch PWSW22 connected to the second SRAM module (SRAM2) is controlled to be turned on by the high-level second control signal cnt22, so that the second local power supply line vssm22 is low. The level of the second SRAM module (SRAM2) can be set to the active state or the standby state by the control signal rsb22. In this state, the third power supply switch PWSW23 connected to the third SRAM module (SRAM3) is controlled to be turned on by the high-level third control signal cnt23, whereby the third local power supply line vssm23. Becomes the low level, and the third SRAM module (SRAM 3) can be set to the active state or the standby state by the control signal rsb23. Therefore, according to the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. 5 to 9, it is possible to cope with a change in the amount of SRAM retained data in the deep standby state.

  Further, in the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. 5 to 9, the power switches PWSW21, PWSW22, and PWSW23 are replaced from N-channel MOS transistors to P-channel MOS transistors, and power switches PWSW21, PWSW22, It is possible to change the connection location of the PWSW 23 from the ground potential Vss side to the power supply voltage Vdd side. At this time, the local power supply lines vssl21, vssm22, and vssm23 are also changed from the ground potential Vss side to the local power supply lines vdd21, vddm22, and vddm23 on the power supply voltage Vdd side. Further, the peripheral circuit power switches PESW21, PESW22, and PESW23 are also replaced from N-channel MOS transistors to P-channel MOS transistors. And the peripheral circuit (peripheral). Further, the connection point of the source line potential control circuit (arvss_control) is also changed between the local power supply lines vdd21, vddm22, and vddm23 on the power supply voltage Vdd side and the cell array (cell_array).

  However, in the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. 5 to 9, the first power supply switch PWSW21 is exclusively used for the first SRAM module (SRAM1), and the second SRAM is used. A second power switch PWSW22 is exclusively used for the module (SRAM2), and a third power switch PWSW23 is exclusively used for the third SRAM module (SRAM3), and the first local power supply line vssl21 is used. The second local power supply line vssm22 and the third local power supply line vssm23 need to be electrically separated from each other. Since the three power switches PWSW21, PWSW22, and PWSW23 are used exclusively for the SRAM modules of the three SRAM modules (SRAM1, 2, 3), the element size of each power switch is the size of each SRAM module. Must be set corresponding to the operating current. Since the first local power supply line vssl21, the second local power supply line vssm22, and the third local power supply line vssm23 need to be electrically separated from each other, the three SRAM modules (SRAM1, 2, 3, Each P well region in which a plurality of N channel MOS transistors of each SRAM module is formed needs to be electrically isolated from each other.

<< Chip Layout of Embodiment 1 >>
FIG. 10 is a diagram showing a chip layout configuration of three SRAM modules (SRAMs 1, 2, and 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG.

  As shown in FIG. 10, a first local power supply line vssl21 for the logic circuit (logic) and the first SRAM module (SRAM1), and a second local power supply line for the second SRAM module (SRAM2). The vssm 22 and the third local power supply line vssm 23 for the third SRAM module (SRAM 3) are electrically separated from each other. A first power supply switch PWSW21 used exclusively for the first SRAM module (SRAM1) and the logic circuit (logic) is connected between the first local power supply line vssl21 and the ground potential Vss. A second power supply switch PWSW22 used exclusively for the second SRAM module (SRAM2) is connected between the second local power supply line vssm22 and the ground potential Vss, while the third local power supply line vssm23 and A third power switch PWSW 23 used exclusively for the third SRAM module (SRAM 3) is connected between the ground potential Vss.

  A plurality of N-channel MOS transistors for configuring the first power switch PWSW21 are formed in the first power switch area PWSW_AREA1, and a plurality of N-channel MOS transistors for configuring the second power switch PWSW22 are the second A plurality of N-channel MOS transistors that are formed in the power switch region PWSW_AREA2 and constitute the third power switch PWSW23 are formed in the third power switch region PWSW_AREA3.

  A logic circuit (logic) connected to the first local power supply line vssl21 and a plurality of N-channel MOS transistors of the first SRAM module (SRAM1) are formed in the first P well region WELL_AREA1, and the second local power supply line A plurality of N-channel MOS transistors of the second SRAM module (SRAM2) connected to the vssm22 are formed in the second P well region WELL_AREA2, and the third SRAM module (SRAM3) connected to the third local power supply line vssm23. Are formed in the third P-well region WELL_AREA3. As shown in FIG. 10, on the main surface of the semiconductor chip of the semiconductor integrated circuit, the first P well region WELL_AREA1 and the second P well region WELL_AREA2 are electrically connected by an N-type region having a minimum separation space wspace. The second P-well region WELL_AREA2 and the third P-well region WELL_AREA3 also need to be electrically separated by the N-type region having the minimum separation space wspace. Therefore, the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 10 has a disadvantage that the semiconductor chip area becomes relatively large.

  The above is the case of a semiconductor integrated circuit having a triple well structure. In the case of a semiconductor integrated circuit having a double well structure, the power well switch is cut off by the power supply voltage Vdd side, and the N well regions of different power cut off regions need to be separated by the P well region. Therefore, the semiconductor integrated circuit having the double well structure also has a disadvantage that the area of the semiconductor chip becomes relatively large as in the case of the triple well structure.

  The semiconductor integrated circuit according to the second embodiment of the present invention described below solves this drawback.

[Embodiment 2]
<< Configuration of Semiconductor Integrated Circuit of Second Embodiment >>
FIG. 11 is a diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.

  The semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11 is different from the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG.

  That is, in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11, the local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are the second local power lines. The power line vssm22 is shared. Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  In the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11, the local power supply line of the logic circuit (logic) and the local power supply line of the first SRAM module (SRAM1) are the first local power supply line vssl21. Shared on. Furthermore, the first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1).

  In the first SRAM module (SRAM1), the peripheral circuit power switch PESW21 is connected between the peripheral circuit (peripheral) and the first local power supply line vssl21, and the cell array source line arvss21 of the cell array (cell_array) is connected to the first SRAM module (SRAM1). A source line potential control circuit including an active power switch SW21, a resistor RN21, a diode-connected MOS transistor MN21, and a switch MSW21 is connected between the local power lines vssl21. The parallel connection of the resistor RN21 and the diode-connected MOS transistor MN21 and the switch MSW21 are connected in series, and the switch MSW21 and the first power switch PWSW21 are connected in series.

  Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). A source line potential control circuit including an active power switch SW22, a resistor RN22, a diode-connected MOS transistor MN22, and a switch MSW22 is connected between the local power lines vssm22. The parallel connection of the resistor RN22 and the diode-connected MOS transistor MN22 and the switch MSW22 are connected in series, and the switch MSW22 and the second power switch PWSW22 are connected in series.

  Also in the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the second SRAM. A source line potential control circuit including an active power switch SW23, a resistor RN23, a diode-connected MOS transistor MN23, and a switch MSW23 is connected between the local power lines vssm22. The parallel connection of the resistor RN23 and the diode-connected MOS transistor MN23 and the switch MSW23 are connected in series, and the switch MSW23 and the third power switch PWSW23 are connected in series.

  Since the switches MSW1, 22 and 23 of the source line potential control circuit only need to be able to pass a minute leakage current during standby, the switch size can be reduced, and the overhead of the area occupied by the semiconductor chip can be suppressed. It becomes possible.

<< Active state of logic and first SRAM >>
Since the control signal cnt21 is set to a high level and the first power switch PWSW21 is turned on to activate the logic circuit (logic) and the first SRAM module (SRAM1), the logic circuit (logic) And the potential of the first local power supply line vssl21 to which the first SRAM module (SRAM1) is connected are set to the ground potential Vss. Further, since the control signal rsb21 is set to a high level and the peripheral circuit power switch PESW21 and the active power switch SW21 are turned on, the peripheral circuit (peripheral) and the cell array (cell_array) of the first SRAM module (SRAM1) are Activated. Therefore, in this active state, the logic circuit (logic) can execute a logic operation, while the write operation or the read operation of the first SRAM module (SRAM 1) can be executed.

<< Standby state of logic and first SRAM >>
Since the control signal cnt21 is set to a high level and the first power switch PWSW21 is turned on to bring the logic circuit (logic) and the first SRAM module (SRAM1) into a standby state, the logic circuit (logic) And the potential of the first local power supply line vssl21 to which the first SRAM module (SRAM1) is connected are set to the ground potential Vss. The control signal rsb21 is set to a low level, and the peripheral circuit power switch PESW21 and the active power switch SW21 are turned off. Further, the control signal rs21 is set to a high level, and the switch MSW21 of the source line potential control circuit is turned on. Accordingly, the potential of the cell array source line arvss21 of the cell array (cell_array) of the first SRAM module (SRAM1) is set to a level slightly higher than the ground potential Vss, and the cell array (cell_array) data is not destroyed to such an extent that the stored data is not destroyed. The current of (cell_array) can be reduced.

<< Array shutoff state of logic and first SRAM >>
Since the control signal cnt21 is set to a low level and the first power switch PWSW21 is turned off to bring the logic circuit (logic) and the first SRAM module (SRAM1) into an array cutoff state, the logic circuit (logic ) And the first local power supply line vssl21 connected to the first SRAM module (SRAM1) is set to a level substantially close to the power supply voltage Vdd. Further, the control signal rsb21 is set to a low level, and the peripheral circuit power switch PESW21 and the active power switch SW21 are turned off. Further, the control signal rs21 is set to a low level, and the switch MSW21 of the source line potential control circuit is turned off.

<< Active state of second and third SRAMs >>
Since the control signals cnt22 and cnt23 are set to a high level to activate the second and third SRAM modules (SRAM2 and 3), the second and third power switches PWSW22 and PWSW23 are turned on. The potential of the second local power supply line vssm22 to which the second and third SRAM modules (SRAM2, 3) are connected is set to the ground potential Vss. Furthermore, since at least one of the control signals rsb22 and rsb23 is set to a high level and at least one of the peripheral circuit power switches PESW22 and PESW23 and at least one of the active power switches SW22 and SW23 are turned on, the second and third At least one peripheral circuit (peripheral) and cell array (cell_array) of the SRAM modules (SRAMs 2 and 3) are activated. Therefore, it is possible to execute a write operation or a read operation with this active SRAM module.

<< Standby state of one of the second and third SRAMs >>
In order to set one of the second and third SRAM modules (SRAM2, 3) to the standby state, the control signals cnt22 and cnt23 are set to the high level, and the second and third power switches PWSW22 and PWSW23 are turned on. Therefore, the potential of the second local power supply line vssm22 to which the second and third SRAM modules (SRAM2, 3) are connected is set to the ground potential Vss. Furthermore, one of the control signals rsb22 and rsb23 is set to a low level, and one of the peripheral circuit power switches PESW22 and PESW23 and one of the active power switches SW22 and SW23 are turned off. Further, one of the control signals rs22 and rs23 is set to a high level, and one of the switches MSW22 and MSW23 of the source line potential control circuit is turned on. Therefore, one potential of the cell array source lines arvss22 and arvss23 of one cell array (cell_array) of the second and third SRAM modules (SRAMs 2 and 3) is set to a level slightly higher than the ground potential Vss, and the cell array ( The current of the cell array (cell_array) can be reduced to such an extent that the stored data of the cell_array) is not destroyed. In this one standby state, there is no problem whether the control signals rs22 and rs23 are set to either the high level or the low level for the active SRAM module.

<< One of the second and third SRAMs in an interrupted state >>
One of the control signals cnt22 and cnt23 is set to a low level in order to shut off one array of the second and third SRAM modules (SRAMs 2 and 3). Further, one or both of the control signals rsb22 and rsb23 are set to a low level, and one or both of the peripheral circuit power switches PESW22 and PESW23 and one or both of the active power switches SW22 and SW23 are turned off. Further, only one of the control signals rs22 and rs23 is set to a low level, and only one of the switches MSW22 and MSW23 of the source line potential control circuit is turned off. There is no problem even if the state of the SRAM module that is not interrupted by the array is set to either the standby state or the active state.

<< Array shutoff state of both the second and third SRAMs >>
Both control signals rsb22 and rsb23 are set to a low level in order to put both the second and third SRAM modules (SRAMs 2 and 3) in the array cutoff state, and both the peripheral circuit power switches PESW22 and PESW23 and the active power switch Both SW22 and SW23 are turned off. Further, both the control signals rs22 and rs23 are set to a low level, and both the deep standby switches MSW22 and MSW23 of the source line potential control circuit are turned off.

<< Deep standby state of the second and third SRAM >>
Since both the control signals cnt22 and cnt23 are set to a low level and both the second and third power switches PWSW22 and PWSW23 are turned off, the second and third SRAM modules (SRAM2, 3) are connected. The potential of the second local power supply line vssm22 is set to a level close to the power supply voltage Vdd due to the leakage current of the second and third SRAM modules.

<< Chip Layout of Embodiment 2 >>
Therefore, when executing the chip layout of the three SRAM modules (SRAMs 1, 2, 3) of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11, the second layout shown in the layout diagram of FIG. It becomes possible to omit the N-type region having the minimum separation space wspace between the P well region WELL_AREA2 and the third P well region WELL_AREA3. That is, in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11, the local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are the second local power lines. This is because the second P well region WELL_AREA2 and the third P well region WELL_AREA3 do not need to be electrically separated because they are shared by the power supply line vssm22. As a result, according to the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11, the semiconductor chip area which the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. It is possible to eliminate the shortcomings.

  Furthermore, according to the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11, the second power switch PWSW22 connected between the shared second local power supply line vssm22 and the ground potential Vss and the second power switch PWSW22 are connected. The third power switch PWSW 23 is shared by the second SRAM module (SRAM 2) and the third SRAM module (SRAM 3). Therefore, the element sizes of the second power switch PWSW22 and the third power switch PWSW23 need to be set corresponding to the operating currents of the second SRAM module (SRAM2) and the third SRAM module (SRAM3). There is no. As a result, each element size of the second power switch PWSW22 and the third power switch PWSW23 in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11 is the same as that of the present invention shown in FIG. Compared with the semiconductor integrated circuit according to the first embodiment, it can be made smaller.

  Furthermore, in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11, the on-resistances of the switches MSW21, MSW22, and MSW23 can be made relatively large, so that the switches MSW21, MSW22, and MSW23 There is no need to increase the element size. Therefore, the increase of the semiconductor chip area in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11 due to the addition of the switches MSW21, MSW22, and MSW23 is negligible. In the case of the semiconductor integrated circuit having the double well structure described in the last part of the first embodiment, the effect of reducing the semiconductor chip area is the same.

《Memory cell》
12 shows three SRAM modules (SRAMs 1, 2, 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5 or the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. It is a figure which shows the structure of the several memory cell (MC) contained in each SRAM module.

  As shown in FIG. 12, each memory cell (MC) of the plurality of memory cells (MC) includes a pair of driving N-channel MOS transistors (MNDL, MNDR) and a pair of load P-channel MOS transistors (MPUL, MPUR). And a pair of transfer N-channel MOS transistors (MNSL, MNSR). A gate and a P well of a pair of transfer N channel MOS transistors (MNSL, MNSR) are connected to a word line wl and a local power supply vssm, respectively. The source and P well of a pair of driving N channel MOS transistors (MNDL, MNDR) are connected to a cell array source line arvss and a local power source vssm, respectively, and a pair of load P channel MOS transistors (MPUL, MPUR). The source and the N well are connected to the power supply voltage Vdd.

  The drain of the left drive N channel MOS transistor (MNDL), the drain of the left load P channel MOS transistor (MPUL), the gate of the right drive N channel MOS transistor (MNDR), and the right load P channel MOS transistor (MPUR) The gate constitutes one storage node of the memory cell (MC). One storage node of the memory cell (MC) is connected to the non-inverted bit line bt via the source / drain path of the left transfer N-channel MOS transistor (MNSL).

  The drain of the right drive N channel MOS transistor (MNDR), the drain of the right load P channel MOS transistor (MPUR), the gate of the left drive N channel MOS transistor (MNDL), and the load P channel MOS transistor (MPUL) of the left side. The gate constitutes the other storage node of the memory cell (MC). The other storage node of the memory cell (MC) is connected to the inverted bit line bb via the source / drain path of the right transfer N-channel MOS transistor (MNSR).

  FIG. 13 shows three SRAM modules (SRAMs 1, 2, 3) of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 5 or the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. It is a figure which shows the other structure of the several memory cell (MC) contained in each SRAM module.

  The memory cell (MC) shown in FIG. 13 is different from the memory cell (MC) shown in FIG. 12 in that the memory cell (MC) shown in FIG. 13 has a P of a pair of driving N-channel MOS transistors (MNDL, MNDR). The P well of the well and a pair of transfer N-channel MOS transistors (MNSL, MNSR) are connected to the cell array source line arvss instead of being connected to the local power supply vssm as in the memory cell (MC) of FIG. It is that. That is, depending on the magnitude of the leak component of the memory cell (MC), the memory cell (MC) shown in FIG. 13 is more effective in reducing the leakage current than the memory cell (MC) shown in FIG. is there. Specifically, when the substrate leak is more dominant than the subthreshold leak, the memory cell (MC) in FIG. 13 is more effective in reducing the leak current.

[Embodiment 3]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 3 >>
FIG. 14 is a diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment of the present invention.

  The semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 14 is different from the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11 in the following points.

  That is, the first difference is constituted by the N channel MOS transistors of the source line potential control circuit of the three SRAM modules (SRAMs 1, 2, and 3) of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. The switches MSW21, MSW22, and MSW23 are replaced with switches MPSW21, MPSW22, and MPSW23 configured by P-channel MOS transistors of the source line potential control circuit of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. That is.

  The next difference is the connection of the switches MPSW21, MPSW22, MPSW23 of each source line potential control circuit of the three SRAM modules (SRAM1, 2, 3) of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. This is that the location is changed between the cell array (cell_array) and the power supply voltage Vdd from between the cell array (cell_array) and the local power supply lines vssl21 and vssm22.

  The operating current of the memory cell (MC) during the read operation is dominated by the current flowing from the bit line to the cell array source line arvss on the ground potential Vss side, and the operating current of the memory cell (MC) during the write operation is the bit line The current flowing by driving is dominant, and the current flowing through the cell array source line arvdd on the power supply voltage Vdd side is very small. For this reason, the switches MPSW21, MPSW22, and MPSW23 of the source line potential control circuit only need to be able to flow a minute leakage current during standby, so that the switch size can be reduced and the overhead of the semiconductor chip occupation area can be reduced. Can be suppressed.

<< Active state of logic and first SRAM >>
Since the control signal cnt21 is set to a high level and the first power switch PWSW21 is turned on to activate the logic circuit (logic) and the first SRAM module (SRAM1), the logic circuit (logic) And the potential of the first local power supply line vssl21 to which the first SRAM module (SRAM1) is connected are set to the ground potential Vss. Further, the control signal rsb21 is set to a high level, the control signal rsp21 is set to a low level, and the peripheral circuit power switch PESW21, the active power switch SW21, and the switch MPSW21 are turned on, so that the first SRAM module (SRAM1) The peripheral circuit (peripheral) and the cell array (cell_array) are activated. Therefore, in this active state, the logic circuit (logic) can execute a logic operation, while the write operation or the read operation of the first SRAM module (SRAM 1) can be executed.

  Note that when the write operation of the first SRAM module (SRAM1) is executed, the control signal rsp21 is changed in the high level direction to reduce the conductivity of the switch MPSW21 and the cell array (SRAM1) of the first SRAM module (SRAM1). cell_array) can be executed to lower the old data retention function.

<< Standby state of logic and first SRAM >>
Since the control signal cnt21 is set to a high level and the first power switch PWSW21 is turned on to bring the logic circuit (logic) and the first SRAM module (SRAM1) into a standby state, the logic circuit (logic) And the potential of the first local power supply line vssl21 to which the first SRAM module (SRAM1) is connected are set to the ground potential Vss. The control signal rsb21 is set to a low level, and the peripheral circuit power switch PESW21 and the active power switch SW21 are turned off. Further, the control signal rsp21 is set to a low level, and the switch MPSW21 of the source line potential control circuit is turned on. Accordingly, the potential of one cell array source line arvss21 of the cell array (cell_array) of the first SRAM module (SRAM1) is set to a level slightly higher than the ground potential Vss, and the cell array (cell_array) data is not destroyed to such an extent that the stored data is not destroyed. Current is reduced.

<< Deep standby state of logic and first SRAM >>
In order to set the logic circuit (logic) and the first SRAM module (SRAM1) in the deep standby state, the control signal cnt21 is set to the low level, and the first power switch PWSW21 is turned off, so that the logic circuit (logic ) And the first local power supply line vssl21 to which the first SRAM module (SRAM1) is connected is set to a level substantially close to the power supply voltage Vdd, and the memory of the cell array (cell_array) of the first SRAM module (SRAM1). The leakage current of the cell (MC) can be reduced to substantially zero.

<< Active state of one of the second and third SRAMs >>
One of the control signals cnt22 and cnt23 is set to a high level to activate one of the second and third SRAM modules (SRAM2 and 3), and one of the second and third power switches PWSW22 and PWSW23 Since it is in the ON state, the potential of the second local power supply line vssm22 to which the second and third SRAM modules (SRAM2, 3) are connected is set to the ground potential Vss. Further, one of the control signals rsb22 and rsb23 is set to a high level, one of the control signals rssp22 and rsp23 is set to a low level, one of the peripheral circuit power switches PESW22 and PESW23, one of the active power switches SW22 and SW23, and the deep. Since one of the standby switches MPSW22 and MPSW23 is turned on, one of the peripheral circuits (peripheral) and the cell array (cell_array) of the second and third SRAM modules (SRAMs 2 and 3) are activated. Therefore, the write operation or the read operation can be executed in the active SRAM module. When the write operation of the active SRAM module is executed, one of the control signals rsp22 and rsp23 is changed to a high level direction in the same manner as the first SRAM module (SRAM1), and the continuity of one of the switches MPSW22 and MPSW23 is changed. It is possible to execute write assist that lowers the old data holding function of the cell array of the active SRAM module.

<< Standby state of one of the second and third SRAMs >>
In order to set one of the second and third SRAM modules (SRAM2, 3) to the standby state, one of the control signals cnt22 and cnt23 is set to a high level, and one of the second and third power switches PWSW22 and PWSW23 is Since it is in the ON state, the potential of the second local power supply line vssm22 to which the second and third SRAM modules (SRAM2, 3) are connected is set to the ground potential Vss. Further, one of the control signals rsb22 and rsb23 is set to a low level, and one of the peripheral circuit power switches PESW22 and PESW23 and one of the active power switches SW22 and SW23 are turned off. Further, the control signals rsp22 and rsp23 are set to a low level, and the switches MPSW22 and MPSW23 of the source line potential control circuit are turned on.

  Therefore, the cell array source lines arvss22 and arvss23 of one cell array (cell_array) of the second and third SRAM modules (SRAMs 2 and 3) are set to a level slightly higher than the ground potential Vss, and the cell array (cell_array) is set. Thus, the current of the cell array (cell_array) can be reduced to such an extent that the stored data is not destroyed.

<< Array power cutoff state of only one of the second and third SRAMs >>
One of the control signals cnt22 and cnt23 is set to a high level so that only one of the second and third SRAM modules (SRAM2, 3) is in the array power supply cutoff state, and the second and third power switches PWSW22 and PWSW23 are set. Since only one of them is turned on, the potential of the second local power supply line vssm22 to which the second and third SRAM modules (SRAM2, 3) are connected is set to the ground potential Vss. Further, only one of the control signals rsb22 and rsb23 is set to a low level, and only one of the peripheral circuit power switches PESW22 and PESW23 and only one of the active power switches SW22 and SW23 are turned off. Further, only one of the control signals rsp22 and rsp23 is set to the high level, and only one of the switches MPSW22 and MPSW23 of the source line potential control circuit is turned off.

  In one SRAM module in which the switch MPSW22 or the switch MPSW23 is turned off, the leakage current of the memory cell (MC) in the array power supply cut-off state can be effectively reduced as compared with the standby state in which data is held. It becomes.

<< Array power cutoff state of both the second and third SRAMs >>
Since one of the control signals cnt22 and cnt23 is set to a high level and only one of the second and third power switches PWSW22 and PWSW23 is turned on, the second and third SRAM modules (SRAM2, 3) are connected. The potential of the second local power supply line vssm22 thus set is set to the ground potential Vss. Further, both the control signals rsb22 and rsb23 are set to a low level, and both the peripheral circuit power switches PESW22 and PESW23 and both the active power switches SW22 and SW23 are turned off. Furthermore, both the control signals rsp22 and rsp23 are set to a high level, and both the switches MPSW22 and MPSW23 of the source line potential control circuit are turned off, so that the second and third states are compared with the standby state holding data. It is possible to effectively reduce the leakage of the array power of both the SRAMs. In addition, the second and third power switches PWSW22 and PWSW23 have an effect that the recovery from the shut-off state is faster than the array power shut-off in which the second power switches PWSW22 and PWSW23 are controlled to be turned off by the low-level control signals cnt22 and cnt23. is there.

<< Deep standby state of both the second and third SRAM >>
Since the control signal cnt22 is set to a low level in order to set both the second and third SRAM modules (SRAM2, 3) to the deep standby state and the power switch PWSW22 is turned off, the second and third SRAMs The potential of the second local power supply line vssm22 to which the modules (SRAMs 2 and 3) are connected is set to a level close to the power supply voltage Vdd, and the leakage current can be reduced to substantially zero.

《Memory cell》
FIG. 15 shows a configuration of a plurality of memory cells (MC) included in each SRAM module of the three SRAM modules (SRAM 1, 2, 3) of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. FIG.

  The memory cell (MC) shown in FIG. 15 is different from the memory cell (MC) shown in FIG. 12 in that the source of a pair of load P-channel MOS transistors (MPUL, MPUR) is connected to the power supply voltage Vdd. Instead, it is connected to the cell array source line arvdd to which the deep standby switch MPSW is connected.

  FIG. 16 shows another configuration of a plurality of memory cells (MC) included in each SRAM module of the three SRAM modules (SRAM 1, 2, 3) of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. FIG.

  The memory cell (MC) shown in FIG. 16 is different from the memory cell (MC) shown in FIG. 15 in that the N well of a pair of load P-channel MOS transistors (MPUL, MPUR) is connected to the power supply voltage Vdd. In other words, it is connected to the cell array source line arvdd to which the deep standby switch MPSW is connected.

  From the viewpoint of reducing the leakage current of the memory cell (MC), the memory cell (MC) shown in FIG. 16 is more advantageous than the memory cell (MC) shown in FIG. However, in the memory cell (MC) shown in FIG. 16, the N well of a pair of load P-channel MOS transistors (MPUL, MPUR) connected to the cell array source line arvdd is connected to the peripheral circuit ( (peripheral) and other N-wells of P-channel MOS transistors (MPUL, MPUR) other than SRAM modules must be electrically isolated.

  For example, in a semiconductor integrated circuit having a triple well structure, in order to electrically isolate a plurality of N wells of a plurality of P channel MOS transistors from each other, a plurality of N wells are formed apart from each other in a P-type substrate. There is a need to. Therefore, from the viewpoint of reducing the chip area of the semiconductor integrated circuit, the memory cell (MC) shown in FIG. 15 is more advantageous than the memory cell (MC) shown in FIG. As a result, in designing a semiconductor integrated circuit, if priority is given to reducing the chip area of the semiconductor integrated circuit, the memory cell (MC) shown in FIG. 15 is selected, and if reduction of leakage current of the memory cell (MC) is given priority. The memory cell (MC) shown in FIG. 16 is selected.

  FIG. 17 shows another configuration of a plurality of memory cells (MC) included in each SRAM module of the three SRAM modules (SRAM 1, 2, 3) of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. FIG.

  The memory cell (MC) shown in FIG. 17 is different from the memory cell (MC) shown in FIG. 15 in that the PMOS substrate bias voltage Vbp is supplied to the N well of a pair of load P-channel MOS transistors (MPUL, MPUR). On the other hand, the NMOS substrate bias voltage Vbn is supplied to the P well of the pair of driving N channel MOS transistors (MNDL, MNDR) and the pair of transfer N channel MOS transistors (MNSL, MNSR). The PMOS substrate bias voltage Vbp and the NMOS substrate bias voltage Vbn are generated from a substrate bias generation circuit (not shown), and the substrate bias generation circuit has appropriate voltage values in response to variations in the manufacturing process, temperature, and power supply voltage. A PMOS substrate bias voltage Vbp and an NMOS substrate bias voltage Vbn are generated. Accordingly, the logic threshold voltage of the CMOS inverter composed of a pair of load P-channel MOS transistors (MPUL, MPUR) and a pair of driving N-channel MOS transistors (MNDL, MNDR) of the memory cell (MC) is determined as the operating voltage arvdd. It is set to a voltage value approximately in the middle of -arvss. As a result, the leakage current of the memory cell (MC) is reduced, and the data retention characteristics of the memory cell (MC) can be improved.

[Embodiment 4]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 4 >>
FIG. 18 is a diagram showing a configuration of a semiconductor integrated circuit according to the fourth embodiment of the present invention.

  The semiconductor integrated circuit according to the fourth embodiment of the present invention shown in FIG. 18 is different from the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG.

  That is, the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 18 includes a deep standby composed of an N-channel MOS transistor included in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. Switches MSWS21, MSWS22, and MSWS23 are added between the cell array source lines arvss21, 22, and 23 and the local power supply lines vssl21 and vssm22.

  As a result, in the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 18, the deep standby switches MPSWS21, MPSWS22, and MPSWS23 formed of P-channel MOS transistors are connected to the cell array source line of the power supply voltage Vdd and the cell array (cell_array). Deep standby switches MSWS21, MSWS22, and MSWS23, which are connected between arvdd21, 22, and 23 and configured by N-channel MOS transistors, are connected between cell array source lines arvss21, 22, and 23 and local power supply lines vssl21 and vssm22. ing.

  In the deep standby state of the logic circuit (logic) and the first SRAM module (SRAM1), the control signal cnt21 is set to the low level, the first power switch PWSW21 is turned off, and the control signal rsb21 is set to the low level. Then, the peripheral circuit power switch PESW21 and the active power switch SW21 are turned off. Further, the control signal rs21 is set to a low level, the control signal rsp21 is set to a high level, and the switches MSW21 and MPSW21 of the source line potential control circuit are turned off.

  In the deep standby state of the second SRAM module (SRAM2), the control signal cnt22 is set to a low level, the second power switch PWSW22 is turned off, the control signal rsb22 is set to a low level, and the peripheral circuit power supply The switch PESW22 and the active power switch SW22 are turned off. Further, the control signal rs22 is set to a low level, the control signal rsp22 is set to a high level, and the switches MSW22 and MPSW22 of the source line potential control circuit are turned off.

  Further, in the deep standby state of the third SRAM module (SRAM 3), the control signal cnt23 is set to a low level, the third power switch PWSW23 is turned off, the control signal rsb23 is set to a low level, and the peripheral circuit power supply is set. The switch PESW23 and the active power switch SW23 are turned off. Further, the control signal rs23 is set to a low level, the control signal rsp23 is set to a high level, and the switches MSW23 and MPSW23 of the source line potential control circuit are turned off.

  In the semiconductor integrated circuit according to the fourth embodiment of the present invention shown in FIG. 18, three SRAM modules (SRAMs 1, 2, 3) include deep standby switches MPSWS21, MPSWS22, and MPSWS23 each composed of a P-channel MOS transistor on the power source side. Deep standby switches MSWS21, MSWS22, and MSWS23, which are N-channel MOS transistors on the ground side, are connected. In the deep standby state, in particular, since both the power supply side deep standby switches MPSWS21, 22, 23 and the ground side deep standby switches MSWS21, 22, 23 are controlled to the off state, the cell array (cell_array) controlled to the deep standby state is controlled. Leakage current can be reliably reduced. Accordingly, the power supply voltage Vdd is supplied to the N well of the pair of load P-channel MOS transistors (MPUL, MPUR) in the plurality of memory cells (MC) of the cell array (cell_array), and the pair of drive N-channel MOS transistors (MNDL). MNDR) and a pair of transfer N-channel MOS transistors (MNSL, MNSR), the leakage current of the memory cell (MC) in the deep standby state is reduced even when the potential of the local power supply line vssm22 is supplied to the P well. It becomes possible. The leakage current in the deep standby state becomes a weak reverse current at the PN junction between the N well to which the power supply voltage Vdd is supplied and the P well to which the potential of the local power supply line vssm22 is supplied.

[Embodiment 5]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 5 >>
FIG. 19 is a diagram showing a configuration of a semiconductor integrated circuit according to the fifth embodiment of the present invention.

  The semiconductor integrated circuit according to the fifth embodiment of the present invention shown in FIG. 19 is different from the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11 in the following points.

  That is, the gate and cell array of the N channel MOS transistors MN21, MN22, MN23 of the source line potential control circuit of the three SRAM modules (SRAM1, 2, 3) of the semiconductor integrated circuit according to the fifth embodiment of the present invention shown in FIG. The drain / source paths of the P-channel MOS transistors MCP21, MCP22, MCP23 are connected between the source lines arvss21, 22, 23, while the source line potential control circuit of the three SRAM modules (SRAM1, 2, 3) is connected. The drain / source paths of the N-channel MOS transistors MCN21, MCN22, and MCN23 are connected between the gates of the N-channel MOS transistors MN21, MN22, and MN23 and the local power supply lines vssl21 and vssm22.

  First, in the active state of the SRAM module (SRAM 1, 2, 3), the control signals cnt21, 22, 23 are set to the high level, the power switches PWSW21, 22, 23 are turned on, and the local power lines vssl21, vssm22 are set. Is set to the ground potential Vss. Next, the control signals rsb21, 22, 23 are set to a high level, and the peripheral circuit power switches PESW21, 22, 23 and the active power switches SW21, 22, 23 are turned on. ) Peripheral circuit and cell array (cell_array) are activated.

  Next, in the standby state of the SRAM module (SRAM 1, 2, 3), the control signals cnt21, 22, 23 are set to the high level, and the power switches PWSW21, 22, 23 are turned on. Further, the control signals rsb21, 22, 23 are set to a low level, and the peripheral circuit power switches PESW21, 22, 23 and the active power switches SW21, 22, 23 are turned off. At this time, the control signals rs21, 22, and 23 are set to low level, the P-channel MOS transistors MCP21, MCP22, and MCP23 are turned on, and the N-channel MOS transistors MN21, MN22, and MN23 of the source line potential control circuit operate as diodes. To do. Therefore, the potentials of the cell array source lines arvss 21, 22, and 23 of the cell array (cell_array) of the SRAM module (SRAM 1, 2, 3) are set to a level slightly higher than the ground potential Vss, and the data held in the cell array (cell_array) is not destroyed. To the extent the cell array current is reduced.

  In the deep standby state of the SRAM module (SRAM 1, 2, 3), the control signals cnt21, 22, 23 are set to a low level, and the power switches PWSW21, 22, 23 are turned off. Further, the control signals rsb21, 22, 23 are set to a low level, and the peripheral circuit power switches PESW21, 22, 23 and the active power switches SW21, 22, 23 are turned off. At this time, the control signals rs21, 22, and 23 are set to the high level, the N-channel MOS transistors MCN21, MCN22, and MCN23 are turned on, and the N-channel MOS transistors MN21, MN22, and MN23 of the source line potential control circuit are turned off. It becomes. Therefore, the operating current of the cell array (cell_array) of the SRAM module (SRAM 1, 2, 3) can be significantly reduced by setting the resistance values of the resistors RN21, 22, 23 of the source line potential control circuit to a high resistance. Is possible.

[Embodiment 6]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 6 >>
FIG. 20 is a diagram showing a configuration of a semiconductor integrated circuit according to the sixth embodiment of the present invention.

  The semiconductor integrated circuit according to the sixth embodiment of the present invention shown in FIG. 20 is different from the semiconductor integrated circuit according to the fifth embodiment of the present invention shown in FIG. 19 in the following points.

  That is, the resistors RN21, 22, and 23 of the source line potential control circuit of the three SRAM modules (SRAMs 1, 2, and 3) of the semiconductor integrated circuit according to the fifth embodiment of the present invention shown in FIG. In other words, the N-channel MOS transistors MRN21, 22, 23 of the source line potential control circuit of the three SRAM modules (SRAM1, 2, 3) of the semiconductor integrated circuit according to the sixth embodiment are replaced. Since a CMOS inverter is connected to the control gates of the N-channel MOS transistors MRN21, 22, 23, the inverted signals of the control signals rs21, 22, 23 are supplied to the control gates of the N-channel MOS transistors MRN21, 22, 23. Is done.

  Therefore, in the deep standby state of the semiconductor integrated circuit according to the sixth embodiment of the present invention shown in FIG. 20, the N-channel MOS transistors MN21, MN22, and MN23 of the source line potential control circuit are activated by the high level control signals rs21, 22, and 23. When the transistor is turned off, the N-channel MOS transistors MRN21, 22, and 23 are also turned off, and the operating current of the cell array (cell_array) of the SRAM module (SRAM1, 2, 3) can be greatly reduced. Become.

[Embodiment 7]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 7 >>
FIG. 21 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the seventh embodiment of the present invention.

  Although the semiconductor integrated circuit according to the seventh embodiment of the present invention is not shown in FIG. 21, the local power supply of the logic circuit (logic) is similar to the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. The line and the local power line of the first SRAM module (SRAM 1) are shared by the first local power line vssl21. The local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are shared by the second local power supply line vssm22. The first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1). Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  In the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the seventh embodiment of the present invention, the peripheral circuit power switch PESW21 is connected between the peripheral circuit (peripheral) and the first local power supply line vssl21. A source line potential control circuit described below is connected between the cell array source line arvss21 and the first local power supply line vssl21 of the cell array (cell_array). Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, in the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the third SRAM module (SRAM3). A source line potential control circuit described below is connected between the two local power supply lines vssm22.

<< Source line potential control circuit >>
As shown in FIG. 21, the source line potential control circuit of each SRAM module of the three SRAM modules (SRAM 1, 2 and 3) included in the semiconductor integrated circuit according to the seventh embodiment of the present invention includes a cell array source line arvss and A parallel connection of a resistor RN1 and an N-channel MOS transistor MN_L1 is included between the local power supply line vssm.

  Source / drain paths of two P-channel MOS transistors MP_L1 and MP_L2 are connected in series between the power supply voltage Vdd and the control gate of the N-channel MOS transistor MN_L1, and between the drain of the N-channel MOS transistor MN_L1 and the control gate. The drain / source paths of the two N-channel MOS transistors MN_L5 and MN_L4 are connected in series.

  Between the control gate of the N-channel MOS transistor MN_L1 and the local power supply line vssm, the drain / source path of the N-channel MOS transistor MN_L3 to which the control signal rs2 is supplied is connected to the control gate.

  The control signal rsb1 is supplied to the input terminal of the CMOS inverter INV_L1, and the output signal of the CMOS inverter INV_L1 is supplied to the control gate of the P-channel MOS transistor MP_L2 and the control gate of the N-channel MOS transistor MN_L4. The control signal rs2 is supplied to the control gate of the P-channel MOS transistor MP_L1 and the input terminal of the CMOS inverter INV_L2, and the output signal of the CMOS inverter INV_L2 is supplied to the control gate of the N-channel MOS transistor MN_L5.

《Active state》
In the active state of the SRAM module shown in FIG. 21, the control signal cnt, the control signal rsb1, and the control signal rs2 are set to a high level, a high level, and a low level, respectively, so that the power switch PWSW is turned on and connected in series 2 The P channel MOS transistors MP_L1 and MP_L2 are turned on, and the N channel MOS transistor MN_L1 is turned on.

  Accordingly, the local power supply line vssm is set to the ground potential Vss, and the peripheral circuit power switch PESW is also turned on, so that the peripheral circuit (peripheral) is activated. Further, the potential of the cell array source line arvss is set to the ground potential Vss by turning on the N-channel MOS transistor MN_L1, and the cell array (cell_array) is also activated, so that the write operation or read operation of the SRAM module shown in FIG. Execution becomes possible.

<Standby state>
In the standby state of the SRAM module shown in FIG. 21, since the control signal cnt, the control signal rsb1, and the control signal rs2 are set to the high level, the low level, and the low level, respectively, the power switch PWSW is turned on and connected in series 2 The N channel MOS transistors MN_L5 and MN_L4 are turned on, and the N channel MOS transistor MN_L1 operates as a diode.

  Therefore, the peripheral circuit power switch PESW is turned off, and the peripheral circuit (peripheral) is set in the standby state. Further, the potential of the cell array source line arvss is set to a level slightly higher than the ground potential Vss by the diode operation of the N-channel MOS transistor MN_L1, and the current of the cell array is reduced to such an extent that the stored data of the cell array (cell_array) is not destroyed.

《Deep standby state》
In the deep standby state of the SRAM module shown in FIG. 21, the control signal rsb1 and the control signal rs2 are set to a low level and a high level, respectively, so that the channel MOS transistor MN_L3 is turned on and the N channel MOS transistor MN_L1 is turned off. Become. Accordingly, by setting the resistance value of the resistor RN1 of the source line potential control circuit to a high resistance, the operating current of the cell array (cell_array) of the SRAM module can be greatly reduced.

[Embodiment 8]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 8 >>
FIG. 22 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the eighth embodiment of the present invention.

  The semiconductor integrated circuit according to the eighth embodiment of the present invention is not shown in FIG. 22, but is similar to the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. The line and the local power line of the first SRAM module (SRAM 1) are shared by the first local power line vssl21. The local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are shared by the second local power supply line vssm22. The first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1). Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  In the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the eighth embodiment of the present invention, the peripheral circuit power switch PESW21 is connected between the peripheral circuit (peripheral) and the first local power supply line vssl21. A source line potential control circuit described below is connected between the cell array source line arvss21 and the first local power supply line vssl21 of the cell array (cell_array). Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, in the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the third SRAM module (SRAM3). A source line potential control circuit described below is connected between the two local power supply lines vssm22.

<< Source line potential control circuit >>
As shown in FIG. 22, the source line potential control circuit of each SRAM module of the three SRAM modules (SRAMs 1, 2, 3) included in the semiconductor integrated circuit according to the eighth embodiment of the present invention is the cell array source line arvss. A parallel connection of a resistor RN1 and an N-channel MOS transistor MN_L1 is included between the local power supply line vssm.

  Source / drain paths of two P-channel MOS transistors MP_L1 and MP_L2 are connected in series between the power supply voltage Vdd and the control gate of the N-channel MOS transistor MN_L1, and between the drain of the N-channel MOS transistor MN_L1 and the control gate. The source / drain paths of the two P-channel MOS transistors MP_L5 and MP_L4 are connected in series.

  Between the control gate of the N-channel MOS transistor MN_L1 and the local power supply line vssm, the drain / source path of the N-channel MOS transistor MN_L3 to which the control signal rs2 is supplied is connected to the control gate.

  The control signal rsb1 is supplied to the control gate of the P-channel MOS transistor MP_L4 and the input terminal of the CMOS inverter INV_L1, and the output signal of the CMOS inverter INV_L1 is supplied to the control gate of the P-channel MOS transistor MP_L2. The control signal rs2 is supplied to the control gate of the P channel MOS transistor MP_L1 and the control gate of the P channel MOS transistor MP_L5.

《Active state》
In the active state of the SRAM module shown in FIG. 22, the control signal cnt, the control signal rsb1, and the control signal rs2 are set to the high level, the high level, and the low level, respectively, so that the power switch PWSW is turned on and the 2 connected in series The P channel MOS transistors MP_L1 and MP_L2 are turned on, and the N channel MOS transistor MN_L1 is turned on.

  Accordingly, the local power supply line vssm is set to the ground potential Vss, and the peripheral circuit power switch PESW is also turned on, so that the peripheral circuit (peripheral) is activated. Further, the potential of the cell array source line arvss is set to the ground potential Vss by turning on the N-channel MOS transistor MN_L1, and the cell array (cell_array) is also activated, so that the write operation or read operation of the SRAM module shown in FIG. Execution becomes possible.

<Standby state>
In the standby state of the SRAM module shown in FIG. 22, the control signal cnt, the control signal rsb1, and the control signal rs2 are set to a high level, a low level, and a low level, respectively, so that the power switch PWSW is turned on and connected in series 2 The P channel MOS transistors MP_L5 and MP_L4 are turned on, and the N channel MOS transistor MN_L1 operates as a diode.

  Therefore, the peripheral circuit power switch PESW is turned off, and the peripheral circuit (peripheral) is set in the standby state. Further, the potential of the cell array source line arvss is set to a level slightly higher than the ground potential Vss by the diode operation of the N-channel MOS transistor MN_L1, and the current of the cell array is reduced to such an extent that the stored data of the cell array (cell_array) is not destroyed.

《Deep standby state》
In the deep standby state of the SRAM module shown in FIG. 22, since the control signal rsb1 and the control signal rs2 are set to the low level and the high level, respectively, the N channel MOS transistor MN_L3 is turned on and the N channel MOS transistor MN_L1 is turned off. It becomes. Accordingly, by setting the resistance value of the resistor RN1 of the source line potential control circuit to a high resistance, the operating current of the cell array (cell_array) of the SRAM module can be greatly reduced.

[Embodiment 9]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 9 >>
FIG. 23 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the ninth embodiment of the present invention.

  Although the semiconductor integrated circuit according to the ninth embodiment of the present invention is not shown in FIG. 23, the local power supply of the logic circuit (logic) is similar to the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. The line and the local power line of the first SRAM module (SRAM 1) are shared by the first local power line vssl21. The local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are shared by the second local power supply line vssm22. The first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1). Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  Further, in the semiconductor integrated circuit according to the ninth embodiment of the present invention, although not shown in FIG. 23, the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. The deep standby switches MPSWS21, MPSWS22, and MPSWS23 thus connected are connected between the power supply voltage Vdd and the cell array source lines arvdd21, 22, 23 of the cell array (cell_array).

  In the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the ninth embodiment of the present invention, the peripheral circuit power switch PESW21 is connected between the peripheral circuit (peripheral) and the first local power supply line vssl21. A source line potential control circuit described below is connected between the cell array source line arvss21 and the first local power supply line vssl21 of the cell array (cell_array). Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, in the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the third SRAM module (SRAM3). A source line potential control circuit described below is connected between the two local power supply lines vssm22.

<< Power source side source line potential control circuit >>
As shown in FIG. 23, the source line potential control circuit on the power supply side of each SRAM module of the three SRAM modules (SRAM1, 2, 3) included in the semiconductor integrated circuit according to the ninth embodiment of the present invention is the power supply voltage Vdd. And a power supply side cell array source line arvdd include a P channel MOS transistor MP1, and a control signal rs2 is supplied to the control gate of the P channel MOS transistor MP1.

《Ground side source line potential control circuit》
As shown in FIG. 23, the source line potential control circuit on the ground side of each SRAM module of the three SRAM modules (SRAM1, 2, 3) included in the semiconductor integrated circuit according to the ninth embodiment of the present invention is a cell array source. A parallel connection of a resistor RN1 and an N-channel MOS transistor MN_L1 is included between the line arvss and the local power supply line vssm.

  The source / drain path of the P-channel MOS transistor MP_M1 is connected between the power supply voltage Vdd and the control gate of the N-channel MOS transistor MN_L1, and the N-channel MOS transistor MN_M1 is connected between the drain of the N-channel MOS transistor MN_L1 and the control gate. The drain and source paths are connected.

  The control signal rsb1 is supplied to the input terminal of the CMOS inverter INV_L1, and the output signal of the CMOS inverter INV_L1 is supplied to the control gate of the P-channel MOS transistor MP_M1 and the control gate of the N-channel MOS transistor MN_M1.

《Active state》
In the active state of the SRAM module shown in FIG. 23, the control signal cnt, the control signal rsb1, and the control signal rs2 are set to a high level, a high level, and a low level, respectively, so that the power switch PWSW is turned on. Therefore, in the source line potential control circuit on the ground side, the P channel MOS transistor MP_M1 is turned on and the N channel MOS transistor MN_L1 is turned on, whereas in the source line potential control circuit on the power supply side, the P channel MOS transistor MP1 is turned on.

  Accordingly, the local power supply line vssm is set to the ground potential Vss, and the peripheral circuit power switch PESW is also turned on, so that the peripheral circuit (peripheral) is activated. Further, the potential of the power supply side cell array source line arvdd is set to the power supply voltage Vdd when the P channel MOS transistor MP1 is turned on, and the potential of the ground side cell array source line arvss is changed to the ground potential Vss when the N channel MOS transistor MN_L1 is turned on. And the cell array (cell_array) is also activated, and the SRAM module shown in FIG. 23 can execute the write operation or read operation.

<Standby state>
In the standby state of the SRAM module shown in FIG. 23, the control signal cnt, the control signal rsb1, and the control signal rs2 are set to the high level, the low level, and the low level, respectively, so that the power switch PWSW is turned on and the N-channel MOS transistor MN_M1 Is turned on, and the N-channel MOS transistor MN_L1 operates as a diode.

  Therefore, the peripheral circuit power switch PESW is turned off, and the peripheral circuit (peripheral) is set in the standby state. In the power source side source line potential control circuit, the P channel MOS transistor MP1 between the power source voltage Vdd, the power source side cell array source line arvdd, and the local power source line vssm is controlled to be in an ON state. Furthermore, in the ground side source line potential control circuit, the potential of the cell array source line arvss is set to a level slightly higher than the ground potential Vss by the diode operation of the N channel MOS transistor MN_L1, and the data held in the cell array (cell_array) is stored. The cell array current is reduced to such an extent that it is not destroyed.

《Deep standby state》
In the deep standby state of the SRAM module shown in FIG. 23, the control signal rsb1 and the control signal rs2 are set to a low level and a high level, respectively. Accordingly, the P-channel MOS transistor MP1 of the power source side source line potential control circuit is turned off, while the N-channel MOS transistor MN_M1 is turned on in the ground side source line potential control circuit, and the N-channel MOS transistor MN_L1 is turned off. It becomes a state. Therefore, the operating current of the cell array (cell_array) of the SRAM module can be significantly reduced by setting the resistance value of the resistor RN1 of the source line potential control circuit on the ground side to a high resistance.

[Embodiment 10]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 10 >>
FIG. 24 is a diagram showing a configuration of each SRAM module of three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the tenth embodiment of the present invention.

  The semiconductor integrated circuit according to the tenth embodiment of the present invention is not shown in FIG. 24. However, as in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. The line and the local power line of the first SRAM module (SRAM 1) are shared by the first local power line vssl21. The local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are shared by the second local power supply line vssm22. The first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1). Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  In the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the tenth embodiment of the present invention, the peripheral circuit power switch PESW21 is connected between the peripheral circuit (peripheral) and the first local power supply line vssl21, and the cell array. A source line potential control circuit described below is connected between the cell array source line arvss21 of (cell_array) and the first local power supply line vssl21. Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, in the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the third SRAM module (SRAM3). A source line potential control circuit described below is connected between the two local power supply lines vssm22.

<< Source line potential control circuit >>
As shown in FIG. 24, the source line potential control circuit of each SRAM module of the three SRAM modules (SRAM 1, 2 and 3) included in the semiconductor integrated circuit according to the tenth embodiment of the present invention includes the cell array source line arvss and the local An active power switch SW1, a resistor RN1, an N-channel MOS transistor MNOP1, and a deep standby switch MN2 are included between the power lines vssm. The parallel connection of the resistor RN1 and the N-channel MOS transistor MNOP1 and the deep standby switch MN2 are connected in series, and the deep standby switch MN2 and the power switch PWSW are connected in series.

  The semiconductor integrated circuit according to the tenth embodiment of the present invention shown in FIG. 24 particularly includes a differential amplifier DA1, and the potential of the cell array source line arvss at the drain of the N-channel MOS transistor MNOP1 is the non-inverting input terminal ( +), The reference voltage Vref is supplied to the inverting input terminal (−) of the differential amplifier DA1, and the output signal of the differential amplifier DA1 is supplied to the control gate of the N-channel MOS transistor MNOP1.

《Active state》
In the active state of the SRAM module shown in FIG. 24, the control signal cnt, the control signal rs1, and the control signal rs2 are set to a high level, a high level, and a low level, respectively, so that the power switch PWSW is turned on. Accordingly, the local power supply line vssm is set to the ground potential Vss, and the peripheral circuit power switch PESW is also turned on, so that the peripheral circuit (peripheral) is activated. Further, the potential of the cell array source line arvss is set to the ground potential Vss by the on state of the active power switch SW1, and the cell array (cell_array) is also activated, and the SRAM module writing operation or reading operation shown in FIG. 24 is executed. Is possible.

<Standby state>
In the standby state of the SRAM module shown in FIG. 24, first, the differential amplifier DA1 is activated, and the control signal cnt, control signal rs1, and control signal rs2 are set to high level, low level, and high level, respectively, and the power switch PWSW Is turned on, the peripheral circuit power switch PESW is turned off, the peripheral circuit (peripheral) is set in the standby state, the active power switch SW1 is turned off, and the deep standby switch MN2 is turned on. Further, the activation of the differential amplifier DA1 causes the control gate of the N-channel MOS transistor MNOP1 to have the potential of the cell array source line arvss at the drain of the N-channel MOS transistor MNOP1 substantially equal to the reference voltage Vref. Is controlled by the output signal. Thus, in the source line potential control circuit, the potential of the cell array source line arvss is set to the level of the reference voltage Vref slightly higher than the ground potential Vss by the operations of the differential amplifier DA1 and the N-channel MOS transistor MNOP1. The cell array current is reduced to such an extent that the stored data of the cell array (cell_array) is not destroyed. Note that the value of the reference voltage Vref is set to an appropriate voltage value in response to variations in the manufacturing process, temperature, and power supply voltage.

《Deep standby state》
In the deep standby state of the SRAM module shown in FIG. 24, the control signal rs1 and the control signal rs2 are set to a low level and a low level, respectively, and the peripheral circuit power switch PESW, the active power switch SW1, and the deep standby switch MN2 are turned off. It becomes. Therefore, the operating current of the cell array (cell_array) of the SRAM module can be greatly reduced.

[Embodiment 11]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 11 >>
FIG. 25 is a diagram showing the configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the eleventh embodiment of the present invention.

  In the semiconductor integrated circuit according to the eleventh embodiment of the present invention, although not shown in FIG. 25, as in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. The line and the local power line of the first SRAM module (SRAM 1) are shared by the first local power line vssl21. The local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are shared by the second local power supply line vssm22. The first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1). Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  In the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the eleventh embodiment of the present invention, the peripheral circuit power switch PESW21 is connected between the peripheral circuit (peripheral) and the first local power supply line vssl21, and the cell array. A source line potential control circuit described below is connected between the cell array source line arvss21 of (cell_array) and the first local power supply line vssl21. Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, in the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the third SRAM module (SRAM3). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, a bias circuit described below is connected to the source line potential control circuit.

<< Source line potential control circuit >>
As shown in FIG. 25, the source line potential control circuit of each SRAM module of the three SRAM modules (SRAM 1, 2 and 3) included in the semiconductor integrated circuit according to the eleventh embodiment of the present invention includes the cell array source line arvss and the local An active power switch SW1, an N-channel MOS transistor MNI1, and a deep standby switch MNI2 are included between the power lines vssm. The N-channel MOS transistor MNI1 and the deep standby switch MNI2 are connected in series, and the series connection and the active power switch SW1 are connected in parallel.

<Bias circuit>
As shown in FIG. 25, the source line potential control circuit of each SRAM module of the three SRAM modules (SRAM1, 2, 3) included in the semiconductor integrated circuit according to the eleventh embodiment of the present invention includes the power supply voltage Vdd and the local power supply. A bias circuit including a resistor RN2, a P-channel MOS transistor MP_ICNT, and an N-channel MOS transistor MN_MIR connected in series is connected between the line vssm.

  In the bias circuit, the source of the P-channel MOS transistor MP_ICNT is connected to the power supply voltage Vdd via the resistor RN2, the control signal ibiase is supplied to the control gate of the P-channel MOS transistor MP_ICNT, and the drain of the P-channel MOS transistor MP_ICNT is N It is connected to the channel MOS transistor MN_MIR. By connecting the drain and the control gate of the N-channel MOS transistor MN_MIR, the N-channel MOS transistor MN_MIR is diode-connected, the diode-connected N-channel MOS transistor MN_MIR of the bias circuit and the N-channel MOS transistor of the source line potential control circuit MNI1 constitutes a current mirror.

《Active state》
In the active state of the SRAM module shown in FIG. 25, the control signal cnt and the control signal rsb1 are set to a high level and a high level, respectively, and the power switch PWSW is turned on. Accordingly, the local power line vssm is set to the ground potential Vss, the peripheral circuit power switch PESW is also turned on, and the peripheral circuit (peripheral) is activated. Furthermore, when the active power switch SW1 is turned on, the potential of the cell array source line arvss is set to the ground potential Vss, and the cell array (cell_array) is also activated, so that the write operation or read operation of the SRAM module shown in FIG. Can be executed.

<Standby state>
In the standby state of the SRAM module shown in FIG. 25, first, the control signal ibiase is set to the low level, and the P-channel MOS transistor MP_ICNT is controlled to be in the ON state by the bias circuit. Further, the control signal cnt, the control signal rsb1, and the control signal rs2 are respectively set to high level, low level, and high level, the power switch PWSW is turned on, the peripheral circuit power switch PESW is turned off, and the peripheral circuit (peripheral) ) Is set to the standby state, and the deep standby switch MNI2 is turned on. Furthermore, the potential of the cell array source line arvss is slightly higher than the ground potential Vss by the operation of the current mirror composed of the diode-connected N-channel MOS transistor MN_MIR of the bias circuit and the N-channel MOS transistor MNI1 of the source line potential control circuit. Since the level is set, the current of the cell array is reduced to such an extent that the stored data of the cell array (cell_array) is not destroyed.

《Deep standby state》
In the deep standby state of the SRAM module shown in FIG. 25, the control signal rsb1 and the control signal rs2 are set to a low level and a low level, respectively, the peripheral circuit power switch PESW is turned off, and the deep standby switch MNI2 is turned off. . Therefore, the operating current of the cell array (cell_array) of the SRAM module can be greatly reduced.

[Embodiment 12]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 12 >>
FIG. 26 is a diagram showing a configuration of each SRAM module of three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twelfth embodiment of the present invention.

  The semiconductor integrated circuit according to the twelfth embodiment of the present invention is not shown in FIG. 26. However, as in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. The line and the local power line of the first SRAM module (SRAM 1) are shared by the first local power line vssl21. The local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are shared by the second local power supply line vssm22. The first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1). Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  In the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the twelfth embodiment of the present invention, the peripheral circuit power switch PESW21 is connected between the peripheral circuit (peripheral) and the first local power supply line vssl21, and the cell array. A source line potential control circuit described below is connected between the cell array source line arvss21 of (cell_array) and the first local power supply line vssl21. Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, in the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the third SRAM module (SRAM3). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, a bias circuit described below is connected to the source line potential control circuit.

<< Source line potential control circuit and bias circuit >>
As shown in FIG. 26, the source line potential control circuit of each SRAM module of the three SRAM modules (SRAM 1, 2 and 3) included in the semiconductor integrated circuit according to the twelfth embodiment of the present invention includes the cell array source line arvss and the local An active power switch SW1, an N-channel MOS transistor MNI21, a deep standby switch MN2, a CMOS transfer switch PASSSTR, and a CMOS inverter INV_PASS are included between the power lines vssm. In the source line potential control circuit, the active power switch SW1 and the N-channel MOS transistor MNI21 are connected in parallel between the cell array source line arvss and the local power line vssm. Between the control gate of the N-channel MOS transistor MNI21 and the local power supply line vssm, the drain / source path of the deep standby switch MN2 to which the control signal rs2 is supplied is connected to the control gate.

  As shown in FIG. 26, the source line potential control circuit of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twelfth embodiment of the present invention includes the power supply voltage Vdd and the local power supply. A bias circuit including a resistor RN2, a P-channel MOS transistor MP_ICNT, and an N-channel MOS transistor MN_MIR connected in series is connected between the line vssm.

  In the bias circuit, the source of the P-channel MOS transistor MP_ICNT is connected to the power supply voltage Vdd via the resistor RN2, the control signal ibiase is supplied to the control gate of the P-channel MOS transistor MP_ICNT, and the drain of the P-channel MOS transistor MP_ICNT is N It is connected to the channel MOS transistor MN_MIR. By connecting the drain of the N-channel MOS transistor MN_MIR and the control gate, the N-channel MOS transistor MN_MIR is diode-connected. The diode-connected N-channel MOS transistor MN_MIR of the bias circuit and the N-channel MOS transistor MNI21 of the source line potential control circuit are connected via the drain / source paths of the P-channel MOS transistor and N-channel MOS transistor connected in parallel with the CMOS transfer switch PASSSTR. Connected. The control signal rsb1 is supplied to the control gate of the P-channel MOS transistor of the CMOS transfer switch PASSSTR and the input terminal of the CMOS inverter INV_PASS, and the output signal of the CMOS inverter INV_PASS is supplied to the control gate of the N-channel MOS transistor of the CMOS transfer switch PASSSTR. . In the standby state, the control signal rsb1 is set to a low level, both the P-channel MOS transistor and the N-channel MOS transistor connected in parallel of the CMOS transfer switch PASSSTR are turned on, and the diode-connected N-channel MOS transistor MN_MIR of the bias circuit The N channel MOS transistor MNI21 of the source line potential control circuit constitutes a current mirror.

《Active state》
In the active state of the SRAM module shown in FIG. 26, the control signal cnt and the control signal rsb1 are set to a high level and a high level, respectively, and the power switch PWSW is turned on. Accordingly, the local power line vssm is set to the ground potential Vss, the peripheral circuit power switch PESW is also turned on, and the peripheral circuit (peripheral) is activated. Furthermore, when the active power switch SW1 is turned on, the potential of the cell array source line arvss is set to the ground potential Vss, and the cell array (cell_array) is also activated, so that the write operation or read operation of the SRAM module shown in FIG. Can be executed.

<Standby state>
In the standby state of the SRAM module shown in FIG. 26, first, the control signal ibiase is set to the low level, and the P-channel MOS transistor MP_ICNT is controlled to be in the ON state by the bias circuit. Further, the control signal cnt, the control signal rsb1, and the control signal rs2 are respectively set to a high level, a low level, and a low level, the power switch PWSW is turned on, the peripheral circuit power switch PESW is turned off, and the peripheral circuit (peripheral) ) Is set to the standby state, and the active power switch SW1 is turned off. Further, the potential of the cell array source line arvss is slightly higher than the ground potential Vss by the operation of the current mirror composed of the diode-connected N channel MOS transistor MN_MIR of the bias circuit and the N channel MOS transistor MNI21 of the source line potential control circuit. Since the level is set, the current of the cell array is reduced to such an extent that the stored data of the cell array (cell_array) is not destroyed.

《Deep standby state》
In the deep standby state of the SRAM module shown in FIG. 26, the control signal ibiase is set to a high level, the control signal rsb1 and the control signal rs2 are set to a low level and a high level, respectively, and the peripheral circuit power switch PESW is turned off. The bias circuit is turned off, the deep standby switch MN2 is turned on, and the N-channel MOS transistor MNI21 is turned off. Therefore, the operating current of the cell array (cell_array) of the SRAM module can be greatly reduced.

[Embodiment 13]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 13 >>
FIG. 27 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the thirteenth embodiment of the present invention.

  The semiconductor integrated circuit according to the thirteenth embodiment of the present invention shown in FIG. 27 differs from the semiconductor integrated circuit according to the twelfth embodiment of the present invention shown in FIG. 26 only in the following points.

  That is, the first difference is that the parallel connection between the active power switch SW1 and the N-channel MOS transistor MNI21 in the source line control circuit of the semiconductor integrated circuit according to the twelfth embodiment of the present invention shown in FIG. The source line control circuit of the semiconductor integrated circuit according to the thirteenth embodiment of the present invention is replaced with a single N-channel MOS transistor MN23.

  Further, the second difference is that a P-channel MOS transistor MP_HOLD is added to the source line control circuit of the semiconductor integrated circuit according to the thirteenth embodiment of the present invention shown in FIG. 27, and the source and control of the P-channel MOS transistor MP_HOLD are controlled. The gate and drain are connected to the power supply voltage Vdd, the control signal rsb1, and the control gate of the N-channel MOS transistor MN23, respectively.

《Active state》
In the active state of the SRAM module shown in FIG. 27, the control signal cnt and the control signal rsb1 are set to a high level and a high level, respectively, and the power switch PWSW is turned on. Accordingly, the local power line vssm is set to the ground potential Vss, the peripheral circuit power switch PESW is also turned on, and the peripheral circuit (peripheral) is activated. Further, the output signal of the CMOS inverter INV_PASS is set to the low level by the high level control signal rsb1, and the P channel MOS transistor MP_HOLD and the N channel MOS transistor MN23 are turned on. As a result, the potential of the cell array source line arvss is set to the ground potential Vss, the cell array (cell_array) is also activated, and the SRAM module shown in FIG. 27 can perform the write operation or read operation.

<Standby state>
In the standby state of the SRAM module shown in FIG. 27, first, the control signal ibiase is set to the low level, and the P-channel MOS transistor MP_ICNT is controlled to be in the ON state by the bias circuit. Further, the control signal cnt, the control signal rsb1, and the control signal rs2 are respectively set to a high level, a low level, and a low level, the power switch PWSW is turned on, the peripheral circuit power switch PESW is turned off, and the peripheral circuit (peripheral) ) Is set to the standby state. The low level control signal rsb1 causes the output signal of the CMOS inverter INV_PASS to be at a high level, the P channel MOS transistor MP_HOLD is turned off, and both the P channel MOS transistor and the N channel MOS transistor connected in parallel with the CMOS transfer switch PASSSTR are turned on. It becomes. Therefore, the potential of the cell array source line arvss is slightly higher than the ground potential Vss by the operation of the current mirror composed of the diode-connected N channel MOS transistor MN_MIR of the bias circuit and the N channel MOS transistor MN23 of the source line potential control circuit. Since it is set to a high level, the current of the cell array is reduced to such an extent that the stored data of the cell array (cell_array) is not destroyed.

《Deep standby state》
In the deep standby state of the SRAM module shown in FIG. 27, the control signal ibiase is set to a high level, the control signal rsb1 and the control signal rs2 are set to a low level and a high level, respectively, and the peripheral circuit power switch PESW is turned off. The bias circuit is turned off, the deep standby switch MN2 is turned on, and the N-channel MOS transistor MN23 is turned off. Therefore, the operating current of the cell array (cell_array) of the SRAM module can be greatly reduced.

[Embodiment 14]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 14 >>
FIG. 28 is a diagram showing a configuration of each SRAM module of three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the fourteenth embodiment of the present invention.

  The semiconductor integrated circuit according to the fourteenth embodiment of the present invention shown in FIG. 28 differs from the semiconductor integrated circuit according to the thirteenth embodiment of the present invention shown in FIG. 27 only in the following points.

  That is, the difference is that a voltage monitor circuit (voltage_monotor) and a voltage dividing circuit (Rdd, Rref, Rss) are added to the source line control circuit of the semiconductor integrated circuit according to the fourteenth embodiment of the present invention shown in FIG. That is.

  The three voltage dividing resistors Rdd, Rref, Rss of the voltage dividing circuit are connected in series between the power supply voltage Vdd and the local power supply line vssm, and the potential difference of the intermediate voltage dividing resistor Rref is one of the voltage monitor circuits (voltage_monotor). Supplied to the differential input terminal. Furthermore, the potential difference between the power supply voltage Vdd of the cell array (cell_array) and the cell array source line arvss is supplied to the other differential input terminal of the voltage monitor circuit (voltage_monotor).

  Therefore, in the standby state, the voltage monitor circuit (voltage_monotor) compares the potential difference between the power supply voltage Vdd of the cell array (cell_array) and the cell array source line arvss with the potential difference of the intermediate voltage dividing resistor Rref. The voltage level of the control signal ibiase of the control gate of the P-channel MOS transistor MP_ICNT of the bias circuit is controlled so as to match. That is, the output control signal ibiase generated from the comparison output terminal out of the voltage monitor circuit (voltage_monotor) is supplied to the control gate of the P-channel MOS transistor MP_ICNT of the bias circuit.

  Furthermore, the voltage monitor circuit (voltage_monotor) can also detect a short circuit state between the power supply voltage Vdd of the cell array (cell_array) and the cell array source line arvss. In this short circuit state, the potential difference between the power supply voltage Vdd of the cell array (cell_array) and the cell array source line arvss is significantly lower than the potential difference of the intermediate voltage dividing resistor Rref. The detection result of the short-circuit state can be generated from the other output terminal Vout of the voltage monitor circuit (voltage_monotor).

[Embodiment 15]
<< Configuration of Semiconductor Integrated Circuit of Fifteenth Embodiment >>
FIG. 29 is a diagram showing a configuration of each SRAM module of three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the fifteenth embodiment of the present invention.

  The semiconductor integrated circuit according to the fifteenth embodiment of the present invention shown in FIG. 29 is different from the semiconductor integrated circuit according to the fourteenth embodiment of the present invention shown in FIG. 28 only in the following points.

  That is, the difference is that in the source line control circuit of the semiconductor integrated circuit according to the fifteenth embodiment of the present invention shown in FIG. 29, the source line control circuit of the semiconductor integrated circuit according to the fourteenth embodiment of the present invention shown in FIG. This is that the voltage dividing resistor Rss on the lower side of the voltage dividing circuit is replaced with an N-channel MOS transistor SW_REF and a CMOS inverter INV_REF.

  That is, in the source line control circuit of the semiconductor integrated circuit according to the fifteenth embodiment of the present invention shown in FIG. 29, the N-channel MOS transistor SW_REF is interposed between the voltage dividing resistor Rref in the middle of the voltage dividing circuit and the local power supply line vssm. The drain and source paths are connected. The control gate of the N-channel MOS transistor SW_REF is connected to the output terminal of the CMOS inverter INV_REF, and the control signal rsb1 is supplied to the input terminal of the CMOS inverter INV_REF.

  Therefore, in the active state of the SRAM module shown in FIG. 29, the control signal rsb1 is set to a high level, the N-channel MOS transistor SW_REF is turned off, and the current consumption of the voltage dividing circuit is reduced. In the standby state and the deep standby state, the control signal rsb1 is set to a low level, the N-channel MOS transistor SW_REF is turned on, and an operating current is supplied to the voltage dividing resistor Rref in the middle of the voltage dividing circuit.

[Embodiment 16]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 16 >>
FIG. 30 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the sixteenth embodiment of the present invention.

  The semiconductor integrated circuit according to the sixteenth embodiment of the present invention shown in FIG. 30 differs from the semiconductor integrated circuit according to the eleventh embodiment of the present invention shown in FIG. 25 only in the following points.

  That is, the difference is that in the semiconductor integrated circuit according to the sixteenth embodiment of the present invention shown in FIG. 30, resistor RN2, P-channel MOS transistor MP_ICNT and N-channel connected in series between power supply voltage Vdd and local power supply line vssm The bias circuit including the MOS transistor MN_MIR is shared by the plurality of source line control circuits of the plurality of SRAM modules Module 1 and 2. The plurality of SRAM modules Modules 1 and 2 are first and second SRAM modules (SRAM 1 and 2), second and third SRAM modules (SRAM 2 and 3), and first and third SRAM modules. SRAM modules (SRAMs 1 and 3).

  In the semiconductor integrated circuit according to the sixteenth embodiment of the present invention shown in FIG. 30, a plurality of cell array source lines arvss1, 2 of a plurality of cell arrays (cell_array) of a plurality of SRAM modules Modules 1, 2 and a local power supply line vssm are provided. N channel MOS transistor MNI1 and deep standby switch MNI2 are connected in series. The N-channel MOS transistor MNI1 and the deep standby switch MNI2 connected in series are shared by a plurality of source line control circuits of a plurality of cell arrays (cell_array) of a plurality of SRAM modules Module1 and SRAM2. The control gate of this shared N-channel MOS transistor MNI1 is connected to the N-channel MOS transistor MN_MIR of the bias circuit in the form of a current mirror. Thus, in the semiconductor integrated circuit according to the sixteenth embodiment of the present invention shown in FIG. 30, since the bias circuit shares a plurality of SRAM modules, the number of bias circuits and the bias current can be reduced. it can.

[Embodiment 17]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 17 >>
FIG. 31 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the seventeenth embodiment of the present invention.

  The semiconductor integrated circuit according to the seventeenth embodiment of the present invention shown in FIG. 31 is different from the semiconductor integrated circuit according to the sixteenth embodiment of the present invention shown in FIG. 30 only in the following points.

  That is, the first difference is that, in the source line control circuit of the semiconductor integrated circuit according to the seventeenth embodiment of the present invention shown in FIG. 31, the deep standby switch MNI2 of the source line control circuit of FIG. The source of the MOS transistor MNI1 is directly connected to the local power supply line vssm.

  The second difference is that in the semiconductor integrated circuit according to the seventeenth embodiment of the present invention shown in FIG. 31, the cell array source line arvss1 of the cell array (cell_array) of the first SRAM module Module1 and the drain of the N-channel MOS transistor MNI1. The drain / source path of the first deep standby switch MNS_M1 is connected between the cell array source line arvss2 of the cell array (cell_array) of the second SRAM module Module2 and the drain of the N-channel MOS transistor MNI1. This means that the drain / source path of the standby switch MNS_M2 is connected.

  In the deep standby state of the first SRAM module Module1, the control signal rsb2 is set to a low level and is connected between the cell array source line arvss1 of the cell array (cell_array) of the first SRAM module Module1 and the drain of the N-channel MOS transistor MNI1. The first deep standby switch MNS_M1 thus turned off is turned off. In the deep standby state of the second SRAM module Module2, the control signal rsb3 is set to a low level, and is connected between the cell array source line arvss2 of the cell array (cell_array) of the second SRAM module Module2 and the drain of the N-channel MOS transistor MNI1. The second deep standby switch MNS_M2 thus set is turned off.

[Embodiment 18]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 18 >>
FIG. 32 shows a structure of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the eighteenth embodiment of the present invention.

  The semiconductor integrated circuit according to the eighteenth embodiment of the present invention shown in FIG. 32 differs from the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 14 only in the following points.

  That is, the first difference is that a deep standby switch composed of P-channel MOS transistors connected between the power supply voltage Vdd and the cell array (cell_array) is composed of a plurality of P-channel MOS transistors MPSW1... MPSWm. It is that.

  The second difference is that the plurality of P-channel MOS transistors MPSW1... MPSWm constituting the deep standby switch are a plurality of cell array source lines arvdd1 arranged in the column direction (complementary bit line pair direction) of the cell array (cell_array). ... is connected to arvddm. Each cell array source line of the plurality of cell array source lines arvdd1... Arvddm is connected to a plurality of memory cells (MC) arranged in the column direction (complementary bit line pair direction) of the cell array (cell_array).

  A third difference is that a plurality of control signals rspb1... Rspbm are supplied to a plurality of control gates of the plurality of P-channel MOS transistors MPSW1.

  The current during standby of all the memory cells (MC) included in one cell array (cell_array) can be limited by one resistor RN1 and one diode-connected MOS transistor MN1 of the source line control circuit. It is.

  At the time of deep standby, the memory cells (MC) of the cell array source line connected to the P channel MOS transistors in the OFF state of the plurality of P channel MOS transistors MPSW1... MPSWm by the high level control signals of the plurality of control signals rspb1. The current can be cut off.

[Embodiment 19]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 19 >>
FIG. 33 shows a structure of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the nineteenth embodiment of the present invention.

  The semiconductor integrated circuit according to the nineteenth embodiment of the present invention shown in FIG. 33 is different from the semiconductor integrated circuit according to the eighteenth embodiment of the present invention shown in FIG. 32 only in the following points.

  That is, the difference is that each SRAM module of the semiconductor integrated circuit according to the nineteenth embodiment of the present invention shown in FIG. 33 is the same as each SRAM module of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. The two-column multiplex method is adopted. Therefore, in each SRAM module shown in FIG. 33, two pairs of complementary bit lines are connected to each selector (SELECTOR [1]... [N]).

  Between the first cell array source line arvdd1 of the memory cell (MC) connected to the first complementary bit line pair on the left side connected to each selector (SELECTOR [1]... [N]) and the power supply voltage Vdd. Is connected to the drain / source path of the first P-channel MOS transistor MPSW1 of the deep standby switch to which the first control signal rspb1 is supplied to the control gate. When the first control signal rspb1 is set to a low level, the first P-channel MOS transistor MPSW1 is turned on, and when the first control signal rspb1 is set to a high level, the first P-channel MOS transistor MPSW1 is Turns off. Further, the second cell array source line arvdd2 of the memory cell (MC) connected to the second complementary bit line pair on the right side connected to each selector (SELECTOR [1]... [N]) and the power supply voltage Vdd. In between, the drain / source path of the second P-channel MOS transistor MPSW2 of the deep standby switch to which the second control signal rspb2 is supplied is connected to the control gate. When the second control signal rspb2 is set to a low level, the second P-channel MOS transistor MPSW2 is turned on, and when the second control signal rspb2 is set to a high level, the second P-channel MOS transistor MPSW2 is Turns off.

  However, in the nineteenth embodiment of the present invention shown in FIG. 33, as in the eighteenth embodiment of the present invention shown in FIG. 32, all the memory cells (MC) included in one cell array (cell_array) are in standby. The current can be limited by one resistor RN1 and one diode-connected MOS transistor MN1 of the source line control circuit.

[Embodiment 20]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 20 >>
FIG. 34 is a diagram showing the configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twentieth embodiment of the present invention.

  The semiconductor integrated circuit according to the twentieth embodiment of the present invention is not shown in FIG. 34, but is similar to the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. The line and the local power line of the first SRAM module (SRAM 1) are shared by the first local power line vssl21. The local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are shared by the second local power supply line vssm22. The first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1). Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  Further, in the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the twentieth embodiment of the present invention, the peripheral circuit power switch PESW21 is connected between the peripheral circuit (peripheral) and the first local power supply line vssl21, and the cell array. A source line potential control circuit described below is connected between the cell array source line arvss21 of (cell_array) and the first local power supply line vssl21. Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). A source line potential control circuit described below is connected between the two local power supply lines vssm22. Further, in the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the third SRAM module (SRAM3). A source line potential control circuit described below is connected between the two local power supply lines vssm22.

<< Source line potential control circuit >>
As shown in FIG. 34, the source line potential control circuit of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twentieth embodiment of the present invention is the first source line potential. A control circuit and a second source line potential control circuit are included.

  The first source line potential control circuit includes a resistor RN1, a diode-connected N-channel MOS transistor MN1, and a deep standby switch MN2 between the cell array source line arvss and the local power supply line vssm. The parallel connection of the resistor RN1 and the diode-connected N-channel MOS transistor MN1 and the deep standby switch MN2 are connected in series, and a deep standby control signal rcut1 is supplied to the control gate of the deep standby switch MN2. In the deep standby state, the deep standby control signal rcut1 is set to a low level, and the deep standby switch MN2 is turned off. Note that the P-well of the diode-connected N-channel MOS transistor MN1 is connected to the source.

  The second source line potential control circuit includes a resistor RN2, a diode-connected N-channel MOS transistor MN3, and a deep standby switch MN4 between the cell array source line arvss and the local power supply line vssm. The parallel connection of the resistor RN2 and the diode-connected N-channel MOS transistor MN3 and the deep standby switch MN4 are connected in series, and a deep standby control signal rcut2 is supplied to the control gate of the deep standby switch MN4. In the deep standby state, the deep standby control signal rcut2 is set to a low level, and the deep standby switch MN4 is turned off. The P well of the diode-connected N-channel MOS transistor MN3 is connected to the local power supply line Vssm.

[Embodiment 21]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 21 >>
FIG. 35 shows a structure of each SRAM module of the three SRAM modules (SRAMs 1, 2, and 3) included in the semiconductor integrated circuit according to the twenty-first embodiment of the present invention.

  The semiconductor integrated circuit according to the twenty-first embodiment of the present invention is not shown in FIG. 35, but is similar to the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. The line and the local power line of the first SRAM module (SRAM 1) are shared by the first local power line vssl21. The local power supply line of the second SRAM module (SRAM2) and the local power supply line of the third SRAM module (SRAM3) are shared by the second local power supply line vssm22. The first power switch PWSW21 connected between the shared first local power supply line vssl21 and the ground potential Vss is shared by the logic circuit (logic) and the first SRAM module (SRAM1). Furthermore, the second power switch PWSW22 and the third power switch PWSW23 connected between the shared second local power supply line vssm22 and the ground potential Vss are connected to the second SRAM module (SRAM2) and the third SRAM. It is shared with the module (SRAM 3).

  In the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the twenty-first embodiment of the present invention shown in FIG. 35, the peripheral circuit power switch PESW21 is provided between the peripheral circuit (peripheral) and the first local power supply line vssl21. Are connected, and an active power switch SW21 and a ground-side source line potential control circuit described below are connected between the cell array source line arvss21 and the first local power supply line vssl21 of the cell array (cell_array). Yes. Also in the second SRAM module (SRAM2), the peripheral circuit power switch PESW22 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss22 of the cell array (cell_array) is connected to the second SRAM module (SRAM2). An active power switch SW22 and a ground-side source line potential control circuit described below are connected between the local power line vssm22. In the third SRAM module (SRAM3), the peripheral circuit power switch PESW23 is connected between the peripheral circuit (peripheral) and the second local power supply line vssm22, and the cell array source line arvss23 of the cell array (cell_array) is connected to the second SRAM module (SRAM3). An active power switch SW23 and a ground side source line potential control circuit described below are connected between the local power line vssm22.

  Furthermore, in the first SRAM module (SRAM1) of the semiconductor integrated circuit according to the twenty-first embodiment of the present invention shown in FIG. 35, there is an active connection between the cell array source line arvdd21 of the cell array (cell_array) and the power supply voltage Vdd. The power switch SWP21 is connected to a source line potential control circuit on the power source side described below. Also in the second SRAM module (SRAM2), an active power switch SWP22 and a power source side source line potential control circuit described below are provided between the cell array source line arvdd22 of the cell array (cell_array) and the power supply voltage Vdd. It is connected. Further, in the third SRAM module (SRAM3), an active power switch SWP23 and a power source side source line potential control circuit described below are provided between the cell array source line arvdd23 of the cell array (cell_array) and the power supply voltage Vdd. It is connected.

《Ground side source line potential control circuit》
As shown in FIG. 35, the source line potential control circuit on the ground side of each SRAM module of the three SRAM modules (SRAM1, 2, 3) included in the semiconductor integrated circuit according to the twenty-first embodiment of the present invention is a cell array source. A resistor RN1, a diode-connected N-channel MOS transistor MN1, and a deep standby switch MN2 are included between the line arvss and the local power supply line vssm. The parallel connection of the resistor RN1 and the diode-connected N-channel MOS transistor MN1 and the deep standby switch MN2 are connected in series, and the control signal rs2 is supplied to the control gate of the deep standby switch MN2. In the deep standby state, the control signal rs2 is set to a low level, and the deep standby switch MN2 is turned off. Note that the P well of the diode-connected N-channel MOS transistor MN1 is connected to the local power supply line vssm.

<< Power source side source line potential control circuit >>
As shown in FIG. 35, the source line potential control circuit on the power supply side of each of the three SRAM modules (SRAMs 1, 2, and 3) included in the semiconductor integrated circuit according to the twenty-first embodiment of the present invention is a cell array source. A resistor RP1, a diode-connected P-channel MOS transistor MP1, and a deep standby switch MP2 are included between the line arvdd and the power supply voltage Vdd. The parallel connection of the resistor RP1 and the diode-connected P-channel MOS transistor MP1 and the deep standby switch MP2 are connected in series, and the control signal rsp2 is supplied to the control gate of the deep standby switch MP2. In the deep standby state, the control signal rsp2 is set to a high level, and the deep standby switch MP2 is turned off. The N well of the diode-connected P-channel MOS transistor MP1 is connected to the power supply voltage Vdd.

《Active state》
In the active state of the SRAM module shown in FIG. 35, the control signal cnt, the control signal rs1, the control signal rs2, the control signal rsp1, and the control signal rsp2 are set to high level, high level, high level, low level, and low level, respectively.

  Therefore, the power switch PWSW, the peripheral circuit power switch PESW21, the active power switches SW1 and SWP1 are turned on, the deep standby switch MN2 of the ground side source line potential control circuit is turned on, and the power source side source line potential control circuit The deep standby switch MP2 is turned on.

  Accordingly, the local power supply line vssm is set to the ground potential Vss, and the peripheral circuit power switch PESW is also turned on, so that the peripheral circuit (peripheral) is activated. Furthermore, the potential of the power supply side cell array source line arvdd is set to the power supply voltage Vdd, the potential of the ground side cell array source line arvss is set to the ground potential Vss, and the cell array (cell_array) is also activated, as shown in FIG. It is possible to execute a write operation or a read operation of the SRAM module shown.

<Standby state>
In the standby state of the SRAM module shown in FIG. 35, the control signal cnt, control signal rs1, control signal rs2, control signal rsp1, and control signal rsp2 are set to high level, low level, high level, high level, and low level, respectively.

  Accordingly, the power switch PWSW, the peripheral circuit power switch PESW21, and the active power switches SW1 and SWP1 are turned off, and the peripheral circuit (peripheral) is set to the standby state. Further, the deep standby switch MN2 of the ground side source line potential control circuit is turned on, and the deep standby switch MP2 of the power source side source line potential control circuit is turned on. Further, in the ground side source line potential control circuit, the potential of the cell array source line arvss is set to a level slightly higher than the ground potential Vss by the diode operation of the N channel MOS transistor MN1, and in the source side potential source line control circuit, the P channel is set. By the diode operation of the MOS transistor MP1, the cell array current is reduced to such an extent that the potential of the cell array source line arvdd is set to a level slightly lower than the power supply voltage Vdd and the data held in the cell array (cell_array) is not destroyed.

《Deep standby state》
In the deep standby state of the SRAM module shown in FIG. 35, the control signal cnt, the control signal rs1, the control signal rs2, the control signal rsp1, and the control signal rsp2 are set to high level, low level, low level, high level, and high level, respectively. The

  Accordingly, the power switch PWSW, the peripheral circuit power switch PESW21, and the active power switches SW1 and SWP1 are turned off. Also, the deep standby switch MN2 of the ground side source line potential control circuit is turned off, and the deep standby switch MP2 of the power source side source line potential control circuit is turned off. As a result, the operating current of the cell array (cell_array) of the SRAM module can be greatly reduced.

[Embodiment 22]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 22 >>
FIG. 36 shows a structure of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twenty-second embodiment of the present invention.

  The semiconductor integrated circuit according to the twenty-second embodiment of the present invention shown in FIG. 36 differs from the semiconductor integrated circuit according to the twenty-first embodiment of the present invention shown in FIG. 34 only in the following points.

  That is, the difference is that each SRAM module of the semiconductor integrated circuit according to the twentieth embodiment of the present invention shown in FIG. 36 has a cell of each SRAM module of the semiconductor integrated circuit according to the twentieth embodiment of the present invention shown in FIG. The resistor RN2, the diode-connected N-channel MOS transistor MN3, and the deep standby switch MN4 of the second source line potential control circuit connected between the array source line arvss and the local power supply line vssm are omitted.

[Embodiment 23]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 23 >>
FIG. 37 is a diagram showing a configuration of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twenty-third embodiment of the present invention.

  The semiconductor integrated circuit according to the twenty-third embodiment of the present invention shown in FIG. 37 is different from the semiconductor integrated circuit according to the twenty-second embodiment of the present invention shown in FIG. 36 only in the following points.

  That is, the difference is that diode connection N of the source line potential control circuit of each SRAM module of the three SRAM modules (SRAM 1, 2, 3) included in the semiconductor integrated circuit according to the twenty-third embodiment of the present invention shown in FIG. The P well of the channel MOS transistor MN1 is connected to the local power supply line vssm, not the source.

[Embodiment 24]
<< Configuration of Semiconductor Integrated Circuit of Embodiment 24 >>
FIG. 1 shows an example of the configuration of a semiconductor integrated circuit according to a twenty-fourth embodiment of the present invention incorporating three SRAM modules (SRAMs 1, 2, and 3) according to any one of the first to twenty-third embodiments of the present invention. FIG.

  A semiconductor chip of the semiconductor integrated circuit shown in FIG. 1 includes a first central processing unit (CPU 1) and a second central processing unit (CPU 2) constituting a multiprocessor, and a moving picture of MPEG (Moving Picture Expert Group) 2. A video processing unit (Video) and an audio processing unit (Audio) for image encoding / decoding processing are included.

  Each of the first central processing unit (CPU1) and the second central processing unit (CPU2), the video processing unit (Video), and the audio processing unit (Audio) is the first to the present inventions described above. The three SRAM modules (SRAMs 1, 2, 3) according to any of the twenty-third embodiments are built in, and each unit has a built-in SRAM module (SRAM 1, 2, 3) depending on the operation state of each unit. The amount of data stored in the deep standby state changes.

  The semiconductor integrated circuit according to the twenty-fourth embodiment of the present invention shown in FIG. 1 can suitably cope with such a change in the amount of stored data in the deep standby state.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 11 or the fourth embodiment of the present invention shown in FIG. 18, the second SRAM module (SRAM2) and the third SRAM module (SRAM3). One of the second power switch PWSW22 and the third power switch PWSW23 connected between the second local power supply line vssm22 and the ground potential Vss shared with each other can be omitted.

  Still further, for example, the present invention is not limited to the semiconductor integrated circuit used for the moving image encoding / decoding processing shown in FIG. The present invention can be applied to various system-on-chip (SoC) that can be used for various applications such as a D converter and a microcontroller incorporating a D / A converter.

logic ... logic circuit peripheral ... cell_array ... memory cell array arvss, arvdd ... cell array source line Vdd ... power supply voltage Vss ... ground potential Vssm ... local power supply line arvss_control ... cell array source potential control circuit PWSW ... power supply switch PESW ... peripheral circuit power switch SW1 ... Power switch RN ... Resistance MN ... MOS transistor MSW, MPSW ... Deep standby switch SRAM 1, 2, 3 ... SRAM module RSCNT ... Control register CONTROL ... Control unit WORD_DRIVER ... Word driver bb, bt ... Complementary bit line pair wl ... Word line MC ... Memory cell SELECTOR ... Selector SA ... Sense amplifier MNDL, MNDR The drive transistor MPUL, MPUR ... load transistor MNSL, MNSR ... transfer transistor

Claims (9)

A cell array having a plurality of memory cells;
A first power line connected to the cell array;
A second power line connected to the first potential;
A third power line connected to the second potential;
A first electrode connected to the first power supply line; a second electrode connected to the second power supply line; and a control gate, wherein the first and second electrodes are electrically connected. 1N channel transistor,
A third electrode connected to the first power supply line; a fourth electrode connected to a control gate of the first N-channel transistor; and a control gate; and electrically connecting the third and fourth electrodes. A second N-channel transistor to be
A fifth electrode connected to the second power supply line; a sixth electrode connected to the control gate of the first N-channel transistor; and a control gate; and the fifth and sixth electrodes A third N-channel transistor to be conductive;
A seventh electrode connected to the third power supply line; an eighth electrode connected to the control gate of the first N-channel transistor; and a control gate; A P-channel transistor to conduct,
Each of the plurality of memory cells includes
A fourth N-channel transistor having a source electrode connected to the first power supply line;
A fifth N-channel transistor having a source electrode connected to the first power line, a drain electrode connected to the control gate of the fourth N-channel transistor, and a control gate connected to the drain electrode of the fourth N-channel transistor; Have
Each of the control gates of the second and third N-channel transistors and the P-channel transistor receives a signal for turning each transistor on and a signal for turning it off.   2. The semiconductor device according to claim 1, wherein the control gate of the first N-channel transistor is electrically connected to a drain electrode of the third N-channel transistor regardless of whether the second N-channel transistor is on or off. .   3. The semiconductor device according to claim 2, wherein the control gate of the first N-channel transistor is electrically connected to a drain electrode of the third N-channel transistor regardless of whether the P-channel transistor is on or off.   2. The semiconductor device according to claim 1, wherein the control gate of the first N-channel transistor is electrically connected to a drain electrode of the third N-channel transistor regardless of whether the P-channel transistor is on or off.   2. The semiconductor device according to claim 1, wherein a first operation state for turning off the first N-channel transistor can be set by turning on the third N-channel transistor.   By setting the third N-channel transistor in the off state and the second N-channel transistor in the on state, a second operation state for electrically connecting the control gate of the first N-channel transistor and the first electrode is set. The semiconductor device according to claim 5, which is possible.   The semiconductor device according to claim 6, wherein a third operation state in which the first N-channel transistor is turned on can be set by turning off the third N-channel transistor and turning on the P-channel transistor. A cell array having a plurality of memory cells;
A first power line connected to the cell array;
A second power line connected to the first potential;
A third power line connected to the second potential;
A first electrode connected to the first power supply line; a second electrode connected to the second power supply line; and a control gate, wherein the first and second electrodes are electrically connected. 1N channel transistor,
A third electrode connected to the first power supply line; a fourth electrode connected to a control gate of the first N-channel transistor; and a control gate; and electrically connecting the third and fourth electrodes. A second N-channel transistor to be
A fifth electrode connected to the second power supply line; a sixth electrode connected to the control gate of the first N-channel transistor; and a control gate; and the fifth and sixth electrodes A third N-channel transistor to be conductive;
A seventh electrode connected to the third power supply line; an eighth electrode connected to the control gate of the first N-channel transistor; and a control gate; A P-channel transistor to conduct,
Each of the plurality of memory cells includes
A fourth N-channel transistor having a source electrode connected to the first power supply line;
A fifth N-channel transistor having a source electrode connected to the first power line, a drain electrode connected to the control gate of the fourth N-channel transistor, and a control gate connected to the drain electrode of the fourth N-channel transistor; Have
The control gate of the first N-channel transistor is a semiconductor electrically connected to the source electrode of the third N-channel transistor without any transistor having an electrode connected to the control gate of the P-channel transistor apparatus. A cell array having a plurality of memory cells;
A first power line connected to the cell array;
A second power line connected to the first potential;
A third power line connected to the second potential;
A first electrode connected to the first power supply line; a second electrode connected to the second power supply line; and a control gate, wherein the first and second electrodes are electrically connected. 1N channel transistor,
A third electrode connected to the first power supply line; a fourth electrode connected to a control gate of the first N-channel transistor; and a control gate controlled based on a control signal; A second N-channel transistor for conducting the first electrode and the fourth electrode;
A fifth electrode connected to the second power supply line; a sixth electrode connected to the control gate of the first N-channel transistor; and a control gate; and the fifth and sixth electrodes A third N-channel transistor to be conductive;
A seventh electrode connected to the third power supply line; an eighth electrode connected to the control gate of the first N-channel transistor; and a control gate controlled based on the control signal; A P-channel transistor for conducting the seventh and eighth electrodes,
Each of the plurality of memory cells includes
A fourth N-channel transistor having a source electrode connected to the first power supply line;
A fifth N-channel transistor having a source electrode connected to the first power line, a drain electrode connected to the control gate of the fourth N-channel transistor, and a control gate connected to the drain electrode of the fourth N-channel transistor; Have
The semiconductor device wherein the control gate of the first N-channel transistor is electrically connected to the source electrode of the third N-channel transistor without passing through the second N-channel transistor.

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