JP2014203862A - Ceramic electronic component and method for manufacturing the same - Google Patents

Ceramic electronic component and method for manufacturing the same Download PDF

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JP2014203862A
JP2014203862A JP2013076556A JP2013076556A JP2014203862A JP 2014203862 A JP2014203862 A JP 2014203862A JP 2013076556 A JP2013076556 A JP 2013076556A JP 2013076556 A JP2013076556 A JP 2013076556A JP 2014203862 A JP2014203862 A JP 2014203862A
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electrode
electronic component
ceramic electronic
ceramic
ceramic body
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淳 大槻
Jun Otsuki
淳 大槻
由起人 山下
Yukihito Yamashita
由起人 山下
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Panasonic Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a ceramic electronic component that is easily mounted, has sufficient strength, and exhibits high accuracy, even when being reduced in size.SOLUTION: A ceramic electronic component includes: a ceramic body 11 formed by simultaneously firing a ceramic element assembly and an internal electrode 12; an external electrode 13 provided at both end portions of the ceramic body 11. In the ceramic electronic component, a relation of 0.35<L1/L0<0.45 is satisfied, where, when an L direction is a direction in which both end surfaces provided with the external electrode 13 face each other, L0 represents a length of the ceramic electronic component in the L direction, and L1 represents a length of the external electrode 13 in the L direction on a surface 11a serving as a mounting surface of the ceramic electronic component.

Description

本発明は、各種電子機器に用いられる面実装型セラミック電子部品およびその製造方法に関するものである。   The present invention relates to a surface mount ceramic electronic component used in various electronic devices and a method for manufacturing the same.

近年電子機器の小型高性能化により、各種電子部品においても小型高性能な面実装型部品が要求されている。たとえば温度補償用のチップサーミスタにおいても、小型低背化高精度化が要求されている。このため図5のように、サーミスタを構成するセラミック素体の間に内部電極2を形成し、同時焼成したセラミックボディ1の端面に内部電極2と電気的に接続された外部電極3を、導電ペーストを塗布し焼き付けることで形成したものが用いられてきた。   In recent years, as electronic devices have become smaller and higher performance, various electronic components have been required to have small and high performance surface mount components. For example, chip thermistors for temperature compensation are also required to be small, low profile and high precision. For this reason, as shown in FIG. 5, the internal electrode 2 is formed between the ceramic bodies constituting the thermistor, and the external electrode 3 electrically connected to the internal electrode 2 is electrically connected to the end face of the simultaneously fired ceramic body 1. What was formed by apply | coating and baking a paste has been used.

なお、この出願の発明に関連する先行技術文献情報としては、例えば、特許文献1が知られている。   As prior art document information related to the invention of this application, for example, Patent Document 1 is known.

特開2004−311676号公報Japanese Patent Laid-Open No. 2004-311676

上記従来のチップサーミスタで小型化したものを、実装してリフロー半田付けしようとすると、チップ立ちが発生しやすくなってくる。さらにチップサーミスタにおいて小型低背化すると、その抵抗値は内部電極間の抵抗値だけでなく、内部電極と対向する側の外部電極との間の抵抗値も全体の抵抗値に影響を与えるため、高精度化することが難しかった。   When the miniaturized chip thermistor is mounted and reflow soldered, chip standing tends to occur. Furthermore, when the chip thermistor is reduced in size and height, the resistance value is not only the resistance value between the internal electrodes, but also the resistance value between the internal electrode and the external electrode on the opposite side affects the overall resistance value. It was difficult to improve accuracy.

本発明はこの課題を解決するものであり、小型低背、高精度で実装しやすいセラミック電子部品を提供することを目的とする。   The present invention solves this problem, and an object of the present invention is to provide a ceramic electronic component that is small and low in profile and easy to mount with high accuracy.

本発明は上記課題を解決するために、セラミック素体と内部電極とを同時焼成してなるセラミックボディと、このセラミックボディの両端部に設けられた外部電極とを備えてなるセラミック電子部品であって、外部電極を設けた両端面が対向する方向をL方向として、セラミックボディのL方向の長さをL0、セラミック電子部品の実装面となる面における外部電極のL方向の長さをL1としたとき、0.35<L1/L0<0.45としたものである。   In order to solve the above-mentioned problems, the present invention provides a ceramic electronic component comprising a ceramic body formed by simultaneously firing a ceramic body and internal electrodes, and external electrodes provided at both ends of the ceramic body. Then, the direction in which both end surfaces provided with the external electrodes are opposed to each other is L direction, the length of the ceramic body in the L direction is L0, and the length of the external electrode on the surface to be the mounting surface of the ceramic electronic component is L1 Then, 0.35 <L1 / L0 <0.45.

上記構成により、このセラミック電子部品を実装してリフロー半田付けするときに、実装面側の外部電極により実装基板側に引っ張られる力が強くなり、チップ立ちを発生しにくくすることができる。   With the above configuration, when this ceramic electronic component is mounted and reflow soldered, the force pulled to the mounting substrate side by the external electrode on the mounting surface side becomes strong, and the chip standing can be made difficult to occur.

本発明の一実施の形態におけるチップサーミスタの断面図Sectional drawing of the chip thermistor in one embodiment of this invention 本発明の一実施の形態におけるチップサーミスタの斜視図The perspective view of the chip thermistor in one embodiment of the present invention 本発明の一実施の形態における別のチップサーミスタの断面図Sectional drawing of another chip | tip thermistor in one embodiment of this invention 本発明の一実施の形態におけるチップサーミスタの製造方法を示す図The figure which shows the manufacturing method of the chip | tip thermistor in one embodiment of this invention. 従来のチップサーミスタの断面図Cross section of conventional chip thermistor

以下、本発明の一実施の形態におけるセラミック電子部品について、具体的にチップサーミスタを例として、図面を参照しながら説明する。   Hereinafter, a ceramic electronic component according to an embodiment of the present invention will be described with reference to the drawings, taking a chip thermistor as an example.

図1は本発明の一実施の形態におけるチップサーミスタの断面図、図2は同斜視図であって、Mn、Ni、Co等の酸化物を主成分とするセラミックボディ11の内層にPdからなり、お互いに対向するように内部電極12が設けられている。セラミックボディ11の両端部には内部電極12に電気的に接続された外部電極13が設けられている。   FIG. 1 is a cross-sectional view of a chip thermistor according to an embodiment of the present invention, and FIG. 2 is a perspective view thereof. The inner layer of a ceramic body 11 whose main component is an oxide such as Mn, Ni, Co, etc. is made of Pd. The internal electrodes 12 are provided so as to face each other. External electrodes 13 electrically connected to the internal electrode 12 are provided at both ends of the ceramic body 11.

このチップサーミスタの外形は、長さ約0.4mm、幅約0.2mm、高さ約0.2mmとなっている。ここで外部電極13を設けた両端面11bが対向する方向をL方向として、実装面となる面11aの外部電極13のL方向の長さ(L1)を約0.16mmとしている。   The outer shape of this chip thermistor is about 0.4 mm in length, about 0.2 mm in width, and about 0.2 mm in height. Here, the direction in which both end surfaces 11b on which the external electrodes 13 are provided is opposed to the L direction, and the length (L1) in the L direction of the external electrode 13 on the surface 11a serving as the mounting surface is about 0.16 mm.

セラミック電子部品が小型化されてくると、その高さが大きさと比較して高くなっていき、半田リフロー時にチップ立ちが発生しやすくなる。このチップ立ちは半田が溶けてきたときにその表面張力により、セラミック電子部品の両端面の方向に引っ張り合う力が働く。この力のバランスが崩れた時にチップ立ちが発生してしまう。これに対して本実施の形態では、L1を大きくしているため、半田の表面張力が実装基板方向にも働くため、チップ立ちが発生しにくくなっている。この効果を得るためには、セラミック電子部品のL方向の長さをL0として、0.35<L1/L0<0.45とすることが望ましい。L1/L0が0.35以下となるとチップ立ちを抑える効果が小さくなり、L1/L0が0.45以上となると外部電極間隔が小さくなりすぎ、ショートの発生、あるいは漏れ電流による抵抗値の変化等が発生する可能性があるためである。   When ceramic electronic components are miniaturized, the height of the ceramic electronic components becomes higher than the size, and chip standing tends to occur during solder reflow. In this chip standing, when the solder melts, the surface tension causes a pulling force in the direction of both end faces of the ceramic electronic component. When this force balance is lost, chip standing occurs. On the other hand, in this embodiment, since L1 is increased, the surface tension of the solder also works in the direction of the mounting substrate, so that chip standing is less likely to occur. In order to obtain this effect, it is desirable that the length of the ceramic electronic component in the L direction is L0, and 0.35 <L1 / L0 <0.45. When L1 / L0 is 0.35 or less, the effect of suppressing the chip standing is reduced, and when L1 / L0 is 0.45 or more, the interval between the external electrodes becomes too small, causing a short circuit or a change in resistance value due to leakage current, etc. This is because there is a possibility of occurrence.

なお、この現象はセラミック電子部品の大きさが小さくなってくるとその自重が小さくなってくるため、L0が0.6mm以下のものについて特にその効果を発揮することができる。   This phenomenon is particularly effective when L0 is 0.6 mm or less because the weight of the ceramic electronic component decreases as the size of the ceramic electronic component decreases.

以上の構成を実現するために、外部電極13は、セラミックボディ11の両端面11bに設けられた端面電極15と、このチップサーミスタの実装面となる面11aのセラミックボディ11の両端面11bに沿って設けられた下面電極14と、端面電極15と下面電極14とを覆うように設けられためっき電極層16とにより構成することが望ましい。   In order to realize the above configuration, the external electrode 13 is provided along the end face electrodes 15 provided on the both end faces 11b of the ceramic body 11 and the both end faces 11b of the ceramic body 11 on the face 11a to be the mounting surface of the chip thermistor. It is desirable that the lower electrode 14 is provided, and the plating electrode layer 16 is provided so as to cover the end face electrode 15 and the lower electrode 14.

ここで内部電極12および下面電極14の厚さは、約1.5μm、内部電極12間の厚さは約50μm、端面電極15の厚さは約15μm、めっき電極層16の厚さは、Niが約1.5μm、Snが約2.5μmとなっている。   Here, the thickness of the internal electrode 12 and the bottom electrode 14 is about 1.5 μm, the thickness between the internal electrodes 12 is about 50 μm, the thickness of the end face electrode 15 is about 15 μm, and the thickness of the plating electrode layer 16 is Ni Is about 1.5 μm and Sn is about 2.5 μm.

セラミックボディ11の両端面11bには端面電極15が設けられており、それぞれの内部電極12に電気的に接続されている。このチップサーミスタの実装面となるセラミックボディ11の面11aの両端面11bに沿って下面電極14が設けられており、この下面電極14はそれぞれの端面電極15に電気的に接続されている。下面電極14は内部電極12と同じ材料を用い、セラミックボディ11と内部電極12を同時焼成するときに、同時に焼成して形成している。さらに端面電極15および下面電極14の上にNiおよびSnのめっき電極層16が形成されており、これにより外部電極13を構成している。また実装面側の外部電極13の外電長さ(L1)は約0.16mmとなっており、図2のように、セラミックボディ11の側面11cには、端面電極の一部が回りこんだものを除いて実質的に外部電極が形成されていない。   End face electrodes 15 are provided on both end faces 11 b of the ceramic body 11 and are electrically connected to the respective internal electrodes 12. A lower surface electrode 14 is provided along both end surfaces 11b of the surface 11a of the ceramic body 11 serving as a mounting surface of the chip thermistor, and the lower surface electrode 14 is electrically connected to each end surface electrode 15. The lower electrode 14 is formed by using the same material as that of the internal electrode 12 and simultaneously firing the ceramic body 11 and the internal electrode 12. Further, a plated electrode layer 16 of Ni and Sn is formed on the end face electrode 15 and the lower face electrode 14, thereby constituting the external electrode 13. The external electrode length (L1) of the external electrode 13 on the mounting surface side is about 0.16 mm. As shown in FIG. 2, a part of the end surface electrode wraps around the side surface 11c of the ceramic body 11. Except for, the external electrode is substantially not formed.

以上のように構成したチップサーミスタと従来のように外部電極を塗布して形成したチップサーミスタとを比較してみる。従来の方法で外電長さを約0.16mmにしようとすると、外部電極の間隔が小さくなりすぎて安定して形成できなかった。そこで例えば約0.1mmにした結果で見ると、端面側での厚さが約20μm、上下面および側面11cでの厚さが約10μmとなった。この上にさらにNi約1.5μm、Sn約2.5μmのめっき電極層を形成すると、高さ方向での外部電極の厚さは合計約28μmとなる。これに対して本実施の形態では、約5.5μmとなる。このように従来に比べて20μm以上(セラミックボディの厚さの10%以上)外部電極による厚さを低減することができる。すなわち所定の厚さにしようとすると、セラミックボディの厚さを10%以上厚くすることができ、抗折強度を高めることができる。   A comparison is made between the chip thermistor configured as described above and a chip thermistor formed by applying an external electrode as in the prior art. If the external electric length is made to be about 0.16 mm by the conventional method, the interval between the external electrodes becomes too small to be stably formed. Therefore, for example, when the thickness is about 0.1 mm, the thickness on the end surface side is about 20 μm, and the thickness on the upper and lower surfaces and the side surface 11c is about 10 μm. If a plating electrode layer of Ni of about 1.5 μm and Sn of about 2.5 μm is further formed thereon, the thickness of the external electrode in the height direction is about 28 μm in total. On the other hand, in this embodiment, it is about 5.5 μm. In this way, the thickness due to the external electrode can be reduced by 20 μm or more (10% or more of the thickness of the ceramic body) compared to the conventional case. That is, if it is going to be a predetermined thickness, the thickness of the ceramic body can be increased by 10% or more, and the bending strength can be increased.

また、従来のような塗布による外部電極では、その厚さが大きくなり、セラミックボディとの隙間も大きくなるため、衝撃が加わった場合破壊されやすくなる。これに対し、本実施の形態では、実装面側の外部電極13をフラットにすることができ、さらに面積が大きくなっているため、外部からの衝撃に対しても強いものとなっている。   In addition, the conventional external electrode by coating has a large thickness and a large gap with the ceramic body, so that it is easily broken when an impact is applied. On the other hand, in the present embodiment, the external electrode 13 on the mounting surface side can be flattened and the area is increased, so that it is strong against external impacts.

さらにチップサーミスタでは、その抵抗値は基本的には内部電極間の抵抗値で決まるが、内部電極とそれに対向する外部電極との間の漏れ電流による抵抗値への影響も付加される。そのため外電長さがばらつくと、内部電極とそれに対向する外部電極との距離がばらつき、これが全体としての抵抗値のばらつきの要因となる。従来のように外部電極を塗布により形成すると外電長さにばらつきが発生しやすい。これに対して本実施の形態では、下面電極14を印刷によりパターン形成し、同時焼成することにより、外電長さのばらつきを抑えることができる。   Further, in the chip thermistor, the resistance value is basically determined by the resistance value between the internal electrodes, but the influence on the resistance value due to the leakage current between the internal electrode and the external electrode opposed thereto is also added. Therefore, when the external power length varies, the distance between the internal electrode and the external electrode facing the internal electrode varies, and this causes a variation in resistance value as a whole. If the external electrode is formed by coating as in the prior art, variations in the external power length are likely to occur. On the other hand, in the present embodiment, variations in the external power length can be suppressed by patterning the bottom electrode 14 by printing and performing simultaneous firing.

また、従来の方法では、側面側にも外部電極が形成されるため、特に小型化が進むと、内部電極と側面との距離も小さくなっていくため、側面の外部電極との漏れ電流も発生する。本実施の形態では、セラミックボディ11の側面11cには、端面電極の一部が回りこんだものを除いて、実質的に外部電極が形成されていないため、内部電極12と側面11cとの間には漏れ電流は発生しない。   In addition, since the external electrode is formed on the side surface in the conventional method, the distance between the internal electrode and the side surface decreases as the miniaturization progresses. To do. In the present embodiment, since the external electrode is not substantially formed on the side surface 11c of the ceramic body 11 except for a part of the end surface electrode that is wrapped around, the space between the internal electrode 12 and the side surface 11c is not formed. There is no leakage current.

以上のように本実施の形態では、漏れ電流による全体の抵抗値への影響を大幅に低減することができ、高精度のチップサーミスタを得ることができる。   As described above, in this embodiment, the influence of the leakage current on the entire resistance value can be greatly reduced, and a highly accurate chip thermistor can be obtained.

なお上記実施の形態では、下面電極14をセラミックボディ11の実装面となる面11aのみに設けたが、図3のように実装面とは反対側の面にも同じ大きさの下面電極14を設けても良い。このようにすることにより、外部電極13の厚さはやや厚くなるが、上下面を区別する必要がなくなるため、製造工程あるいは実装時に工程を簡略化することができる。   In the above embodiment, the lower surface electrode 14 is provided only on the surface 11a to be the mounting surface of the ceramic body 11, but the lower surface electrode 14 having the same size is also provided on the surface opposite to the mounting surface as shown in FIG. It may be provided. By doing so, the thickness of the external electrode 13 is slightly increased, but it is not necessary to distinguish between the upper and lower surfaces, so that the process can be simplified during the manufacturing process or mounting.

次に本発明のチップサーミスタの製造方法について説明する。   Next, the manufacturing method of the chip thermistor of the present invention will be described.

まず出発原料Mn34、Co34、Fe23、Al23の酸化物粉末を混合、乾燥した後、仮焼、粉砕してMn34を主成分とする負の抵抗特性を有する機能セラミック材料を得る。次に、この機能セラミック材料の粉末に有機バインダー、溶剤を加えてセラミックスラリーを作製する。 First, oxide powders of starting raw materials Mn 3 O 4 , Co 3 O 4 , Fe 2 O 3 , and Al 2 O 3 are mixed and dried, then calcined and pulverized to obtain a negative electrode containing Mn 3 O 4 as a main component. A functional ceramic material having resistance characteristics is obtained. Next, an organic binder and a solvent are added to the powder of the functional ceramic material to produce a ceramic slurry.

次にこのセラミックスラリーを用いてドクターブレード法等により所定厚みのグリーンシートを得る。さらにスクリーン印刷法を用いてスクリーンのメッシュ開口部にPdの内部電極ペーストを充填しグリーンシートに内部電極ペーストを塗布して内部電極12となる導電体層を形成する。   Next, using this ceramic slurry, a green sheet having a predetermined thickness is obtained by a doctor blade method or the like. Further, using a screen printing method, a Pd internal electrode paste is filled into the mesh openings of the screen, and the internal electrode paste is applied to the green sheet to form a conductor layer that becomes the internal electrode 12.

次に図4(a)のように、内部電極12となる導電体層を形成したグリーンシート17aを所定枚数積層し、その上下に導電体層を形成していないグリーンシート17bを所定枚数重ね、さらにその上下に内部電極を形成するための内部電極ペーストと同じペーストで、下面電極14となる電極パターンを形成したグリーンシート17cを重ね、これを圧着して積層ブロックを形成する。   Next, as shown in FIG. 4A, a predetermined number of green sheets 17a on which a conductor layer to be the internal electrode 12 is formed are stacked, and a predetermined number of green sheets 17b on which the conductor layer is not formed are stacked. Further, a green sheet 17c on which an electrode pattern to be the lower surface electrode 14 is formed with the same paste as the internal electrode paste for forming the internal electrodes on the upper and lower sides thereof is stacked and pressure-bonded to form a stacked block.

次に図4(a)の切断線に沿って積層ブロックを切断しチップ化する。さらにチップの両端面11bに内部電極12の端部を露出させた後、脱バインダー、1200℃〜1300℃で焼成を順次行って図4(b)のようなセラミック焼結体のセラミックボディ11を得る。続いてセラミックボディ11の両端面11bに、下面電極14に電気的に接続される程度のCu粉体とガラスフリットを含有した導電ペーストを塗布して800℃〜900℃で焼付けを行うことにより端面電極15を形成し、図4(c)のようになる。さらにこの端面電極15および下面電極14に、Ni約1.5μm、Sn約2.5μmのめっき電極層16を形成することにより外部電極13を構成し、図4(d)のような長さ約0.4mm、幅約0.2mm、高さ約0.2mmのチップサーミスタを得る。   Next, the laminated block is cut along the cutting line of FIG. Further, after exposing the end portions of the internal electrodes 12 to the both end faces 11b of the chip, the binder is removed, and firing is sequentially performed at 1200 ° C. to 1300 ° C., so that the ceramic body 11 of the ceramic sintered body as shown in FIG. obtain. Subsequently, the both end surfaces 11b of the ceramic body 11 are coated with a conductive paste containing Cu powder and glass frit that is electrically connected to the lower surface electrode 14, and baked at 800 ° C. to 900 ° C. An electrode 15 is formed, as shown in FIG. Further, an external electrode 13 is formed by forming a plated electrode layer 16 of Ni of about 1.5 μm and Sn of about 2.5 μm on the end face electrode 15 and the lower face electrode 14, and has a length of about about 4 mm as shown in FIG. A chip thermistor having a width of about 0.4 mm, a width of about 0.2 mm, and a height of about 0.2 mm is obtained.

以上のように外部電極13を形成することにより、外部電極13は端面と上下面にのみ形成し、側面には形成しないようにすることができる(但し端面に塗布したときに側面側の端に滲んだものは除く)。また上下面に形成した下面電極14は印刷によって形成しているため外電長さを一定にすることができる。また端面電極15も下面電極14と電気的に接続される程度に塗布するため、塗布量を少なくすることができ、外形への影響を最小限にすることができる。   By forming the external electrode 13 as described above, the external electrode 13 can be formed only on the end surface and the upper and lower surfaces and not on the side surface (however, when applied to the end surface, Excludes bleeding.) Further, since the lower surface electrodes 14 formed on the upper and lower surfaces are formed by printing, the external power length can be made constant. Further, since the end face electrode 15 is also applied to such an extent that it is electrically connected to the lower face electrode 14, the amount of application can be reduced, and the influence on the outer shape can be minimized.

本発明に係るセラミック電子部品は、小型化しても、高精度で実装しやすいセラミック電子部品を提供するものであり、産業上有用である。   The ceramic electronic component according to the present invention provides a ceramic electronic component that is easy to mount with high accuracy even if it is downsized, and is industrially useful.

11 セラミックボディ
11a 実装面となる面
11b 端面
11c 側面
12 内部電極
13 外部電極
14 下面電極
15 端面電極
16 めっき電極層
17a 内部電極となる導電体層を形成したグリーンシート
17b 導電体層を形成していないグリーンシート
17c 下面電極となる電極パターンを形成したグリーンシート
DESCRIPTION OF SYMBOLS 11 Ceramic body 11a The surface used as a mounting surface 11b End surface 11c Side surface 12 Internal electrode 13 External electrode 14 Bottom electrode 15 End surface electrode 16 Plating electrode layer 17a Green sheet 17b which formed the conductor layer used as an internal electrode The conductor layer is formed No green sheet 17c Green sheet on which an electrode pattern to be the bottom electrode is formed

Claims (6)

セラミック素体と内部電極とを同時焼成してなるセラミックボディと、このセラミックボディの両端部に設けられた外部電極とを備えてなるセラミック電子部品であって、前記外部電極を設けた両端面が対向する方向をL方向として、前記セラミック電子部品の前記L方向の長さをL0、前記セラミック電子部品の実装面となる面における前記外部電極の前記L方向の長さをL1としたとき、0.35<L1/L0<0.45としたことを特徴とするセラミック電子部品。 A ceramic electronic component comprising a ceramic body formed by simultaneously firing a ceramic body and internal electrodes, and external electrodes provided at both ends of the ceramic body, wherein both end surfaces provided with the external electrodes are When the facing direction is the L direction, the length of the ceramic electronic component in the L direction is L0, and the length of the external electrode on the surface to be the mounting surface of the ceramic electronic component is L1. Ceramic electronic parts characterized by satisfying .35 <L1 / L0 <0.45. 前記L1が0.6mm以下であることを特徴とする請求項1記載のセラミック電子部品。 The ceramic electronic component according to claim 1, wherein the L1 is 0.6 mm or less. 前記外部電極は、前記セラミック電子部品の実装面となる面の前記両端面に接する下面電極と、前記セラミックボディの両端面に設けられ、前記内部電極と前記下面電極とに電気的に接続された端面電極と、前記端面電極および前記下面電極を覆うめっき電極層で構成されたことを特徴とする請求項1記載のセラミック電子部品。 The external electrode is provided on a lower surface electrode in contact with the both end surfaces of a surface to be a mounting surface of the ceramic electronic component, and on both end surfaces of the ceramic body, and is electrically connected to the internal electrode and the lower surface electrode. 2. The ceramic electronic component according to claim 1, comprising an end face electrode and a plating electrode layer covering the end face electrode and the lower face electrode. 前記下面電極は、前記セラミック素体および前記内部電極と同時に焼成されたものであることを特徴とする請求項3記載のセラミック電子部品。 4. The ceramic electronic component according to claim 3, wherein the lower surface electrode is fired simultaneously with the ceramic body and the internal electrode. 前記下面電極は、前記セラミックボディの対向する上下の面に形成されていることを特徴とする請求項1記載のセラミック電子部品。 The ceramic electronic component according to claim 1, wherein the lower surface electrodes are formed on upper and lower surfaces of the ceramic body that face each other. 内部電極となる導電体層を形成したグリーンシートと、下面電極となる導電体層を形成したグリーンシートとを積層して積層ブロックを形成する工程と、前記積層ブロックを切断してチップ化して焼成することによりセラミックボディを得る工程と、前記セラミックボディの両端面に、前記内部電極および前記下面電極に電気的に接続する端面電極を形成する工程と、前記下面電極および前記端面電極を覆うめっき電極層を設けることにより外部電極を形成する工程とを備え、前記セラミックボディの前記L方向の長さをL0、前記セラミック電子部品の実装面となる面における前記外部電極の前記L方向の長さをL1としたとき、0.35<L1/L0<0.45となるように外部電極を形成することを特徴とするセラミック電子部品の製造方法。 A step of forming a laminated block by laminating a green sheet having a conductor layer to be an internal electrode and a green sheet having a conductor layer to be a bottom electrode, and cutting the laminated block into chips to be fired A step of obtaining a ceramic body, a step of forming end face electrodes electrically connected to the internal electrode and the lower face electrode on both end faces of the ceramic body, and a plating electrode covering the lower face electrode and the end face electrode Forming an external electrode by providing a layer, the length in the L direction of the ceramic body is L0, and the length in the L direction of the external electrode on the surface to be the mounting surface of the ceramic electronic component is When L1 is set, external electrodes are formed so that 0.35 <L1 / L0 <0.45. Method.
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