JP2014191837A - Nonvolatile memory cell and nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile memory cell and a nonvolatile memory which do not require a selection transistor, need only small occupied area, and include a bipolar resistance element such as MTJ element.SOLUTION: A nonvolatile memory cell comprises: a resistance change element R in which an ohmic value changes in different directions depending on an energization direction; and a bidirectional threshold element causing current with the same polarity as a voltage to flow therethrough when the voltage of an absolute value equal to or higher than a threshold voltage is applied. The resistance change element R and the bidirectional threshold element are connected in series between a bit line BL and a source line SL. The threshold element includes antiparallel-connected diodes D1 and D2.

Description

  The present invention relates to a nonvolatile memory cell using a resistance change element and a nonvolatile memory including the nonvolatile memory cell.

  In recent years, a resistance change type memory for storing data using a resistance change type element has attracted attention as a next-generation non-volatile memory in place of a flash memory or a DRAM that has become limited in miniaturization. Examples of the resistance change element include MRAM (Magnetoretic Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistance Random Access Memory). The thing that is. A memory using such a resistance variable element does not require a complicated process like a flash memory, is compatible with a standard logic process, is suitable for miniaturization, and operates at a low voltage. The future is promising. An element configuration, characteristics, and array configuration of a memory using this type of variable resistance element are disclosed in Patent Document 1 or Non-Patent Document 1, for example.

  FIGS. 14A and 14B are diagrams showing the configuration and operation of a nonvolatile memory cell using a typical MTJ (Magnetic Tunnel Junction) element as a variable resistance element. FIG. 14C is a diagram showing an equivalent circuit of a nonvolatile memory cell using the circuit shown in FIGS. 14A and 14B.

As shown in FIGS. 14A and 14B, the MTJ element is composed of a pinned layer having a constant magnetic direction, a tunnel barrier film (insulating film), and a free layer whose magnetic direction changes. As shown in FIG. 14A, when a current in the direction from the free layer to the pinned layer is passed, the magnetization direction of the free layer becomes the same as that of the pinned layer, the MTJ element becomes low resistance, and data “0” is stored. It becomes a state. Conversely, as shown in FIG. 14B, when a current in the direction from the pinned layer toward the free layer is passed, the magnetization direction of the free layer is opposite to that of the pinned layer, the MTJ element becomes high resistance, and data “1” "Is stored.

When a nonvolatile memory cell is configured with such an MTJ element, as illustrated in FIGS. 14A and 14B, an N-channel selection transistor T1 serves as a switch for selecting the MTJ element. Connected in series. The nonvolatile memory cell shown in FIG. 14C includes a resistance variable element R1 and an N-channel selection transistor T1. Here, the resistance variable element R1 is the MTJ element shown in FIGS. 14 (a) and 14 (b). In the resistance variable element R1, there is a free layer on the tip side of the arrow, and a pinned layer on the rear end side. Therefore, when a current in the direction opposite to the arrow in FIG. 14C is passed through the resistance variable element R1, the resistance variable element R1 is reduced in resistance, and when a current in the same direction as the arrow is passed through the resistance variable element R1, The resistance variable element R1 has a high resistance.

In the example shown in FIG. 14C, the bit line BL is connected to the free layer of the variable resistance element R1, which is an MTJ element, and the source line SL is connected to the source of the N-channel selection transistor T1. Then, a voltage corresponding to the write data is applied between the bit line BL and the source line SL, a predetermined row selection voltage is applied to the N channel selection transistor T1 via the word line WL, and the N channel selection transistor T1 is turned on. As a result, a current is passed through the resistance variable element R1, and data “1” or “0” is written to the resistance variable element R1. The configuration of such a nonvolatile memory cell is disclosed in Patent Document 1, for example.

  FIG. 15 is a diagram illustrating a cross-sectional structure of a conventional nonvolatile memory cell array composed of nonvolatile memory cells as shown in FIGS. 14 (a) and 14 (b). In the example shown in FIG. 15, two N-channel selection transistors T1 shown in FIGS. 14A and 14B are formed on a semiconductor substrate. The gates of two N-channel selection transistors T1 constituting one nonvolatile memory cell are word lines WL. The sources of these N-channel selection transistors T1 are connected to the source line SL of the second metal layer 2M via the contact hole CS, the first metal layer 1M, the via V1 between the first layer and the second layer. The common drain of the two N-channel selection transistors T1 is connected to the pin layer of the MTJ element through the contact hole CS, and the free layer of the MTJ element is a bit line formed by the second metal layer 2M through the via V1. Connected to BL.

  FIG. 16 shows an operation example of the nonvolatile memory cell shown in FIGS. 14 and 15. When “0” is written to the MTJ element, a selection voltage of 1.2 V is applied to the gate of the N-channel selection transistor of the nonvolatile memory cell via the word line WL, 1.2 V is applied to the bit line BL, and the source line SL Is given 0V. As a result, a current of about 49 μA in the direction from the free layer to the pinned layer flows through the MTJ element of the nonvolatile memory cell, the MTJ element becomes low resistance, and “0” is stored. On the other hand, when “1” is written to the MTJ element of a desired nonvolatile memory cell, a selection voltage WL of 1.2 V is applied to the gate of the N-channel transistor of the nonvolatile memory cell, 0 V is applied to the bit line BL, and the source line Apply 1.2V to SL. As a result, a current of about 49 μA in the direction from the pinned layer to the free layer flows through the MTJ element of the nonvolatile memory cell, the MTJ element becomes high resistance, and “1” is stored.

  When data is read from a desired nonvolatile memory cell, a selection voltage WL of 1.2 V is applied to the gate of the N-channel transistor of the nonvolatile memory cell, 0.15 V is applied to the bit line BL, and 0 V is applied to the source line SL. give. Then, a current flowing from the bit line BL to the MTJ element of the nonvolatile memory cell is detected. When the MTJ element stores “0” and has a low resistance, a current of about 15 μA flows through the MTJ element. On the other hand, when the MTJ element stores “1” and has a high resistance, a current of about 10 μA flows through the MTJ element. Therefore, it is possible to determine whether the MTJ element stores “0” or “1” by detecting the current flowing into the MTJ element and comparing it with a threshold value.

  Note that the configuration of such a nonvolatile memory cell array and the operating conditions of the nonvolatile memory cells constituting the nonvolatile memory cell array are disclosed in Non-Patent Document 2, for example.

JP 2009-187631 A JP 2002-8369 A Special table 2007-536680 gazette

ISSCC Digest of Technical Papers, pp. 258, Feb. 2010. IEICE IEICE technical report ICEC Technical Report ICD2010-7 p35-p40

  In order to increase the memory capacity, it is effective to reduce the number of elements of the nonvolatile memory cell. Therefore, Patent Document 2 proposes a cross-point type memory in which a selection transistor is omitted and a memory cell is configured by only one resistor in order to reduce the area (see FIG. 3 of Patent Document 2). a) (b) (c)). Patent Document 3 also proposes a similar cross-point type memory (see FIGS. 46 to 48 of Patent Document 3). However, the configuration described in Patent Document 2 has a problem in that unnecessary sneak current flows to other nonvolatile memory cells when the nonvolatile memory cells are accessed, resulting in an increase in current consumption. In addition, when a bipolar resistance element such as an MTJ element is used as a memory element of a nonvolatile memory cell, it is necessary to pass a bidirectional current to the nonvolatile memory cell at the time of writing. The technique for doing this is not disclosed in Patent Document 2. The same applies to Patent Document 3, which does not disclose a technique that enables a bipolar resistance element to be used as a storage element of a nonvolatile memory cell.

  The present invention has been made in view of the above-described circumstances, and a non-volatile memory cell that does not require a selection transistor and occupies a small area and can be configured by a bipolar resistance element such as an MTJ element. And it aims at providing a non-volatile memory.

  The present invention relates to a resistance variable element whose resistance value changes in a different direction depending on the energization direction, and a bidirectional device that allows a current having the same polarity as that voltage to pass when a voltage whose absolute value is equal to or greater than a threshold voltage is applied. Provided is a non-volatile memory cell comprising a threshold element connected in series.

  According to the nonvolatile memory cell and the nonvolatile memory using the nonvolatile memory cell, the absolute value of the voltage applied to the resistance variable element and the threshold element connected in series is equal to or higher than the threshold voltage of the threshold element, and By selecting less than twice the threshold voltage, current wraparound to the non-volatile memory other than the desired non-volatile memory cell in the non-volatile memory is avoided, and data writing and data reading only to the desired non-volatile memory cell are performed. Can be realized.

1 is a circuit diagram showing a configuration of a nonvolatile memory cell according to a first embodiment of the present invention. FIG. It is a figure which illustrates the voltage-current characteristic of the threshold element of the non-volatile memory cell. It is a figure which shows the operating condition of the non-volatile memory cell. It is a circuit diagram which shows the structure of the non-volatile memory cell which is 2nd Embodiment of this invention. It is a circuit diagram which shows a structure and operation | movement of the non-volatile memory cell array which is 3rd Embodiment of this invention. It is a figure which shows the operation condition of "0" write of the embodiment. It is a figure which shows the operation condition of "1" write of the embodiment. It is a circuit diagram which shows a structure and operation | movement of the non-volatile memory cell array which is 4th Embodiment of this invention. It is a figure which shows the operation condition of "0" write of the embodiment. It is a figure which shows the operation condition of "1" write of the embodiment. It is a circuit diagram which shows the structure of the non-volatile memory which is 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the row decoder in the same embodiment. It is a circuit diagram which shows the structure of the non-volatile memory which is 6th Embodiment of this invention. It is a figure which shows the structure and operation | movement of an MTJ element. It is a figure which illustrates the cross-sectional structure of the non-volatile memory cell using an MTJ element. It is a figure which shows the operating condition of the non-volatile memory cell.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the transistor refers to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor; field-effect transistor having a metal-oxide film-semiconductor structure).

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a nonvolatile memory cell according to the first embodiment of the present invention. The nonvolatile memory cells are arranged in a matrix in the nonvolatile memory cell array of the nonvolatile memory, and the source lines SL wired along each row of the matrix and the bits wired along each column, respectively. Arranged at the intersection with the line BL. As shown in FIG. 1, the nonvolatile memory cell is formed by connecting a resistance variable element R and a threshold element composed of diodes D1 and D2 connected in antiparallel to each other in series between a bit line BL and a source line SL. Is. As the resistance variable element R, a bipolar variable resistance element similar to that used for MRAM, PRAM, ReRAM, or the like can be used. In the illustrated example, the resistance variable element R is an MTJ element used in MRAM. The free layer of the MTJ element, which is the resistance variable element R, is connected to the bit line BL, and the pinned layer is connected to a common connection point between the cathode of the diode D1 and the anode of the diode D2. The anode of the diode D1 and the cathode of the diode D2 are commonly connected to the source line SL.

  FIG. 2 is a diagram showing voltage-current characteristics of a threshold element composed of diodes D1 and D2. In FIG. 2, the horizontal axis indicates a voltage VN−VSL obtained by subtracting the potential VSL of the source line SL from the potential VN of the node N between the resistance variable element R and the threshold element, and the vertical axis indicates the source line from the node N. The electric current which flows toward SL is shown. In this example, the forward voltage of the diodes D1 and D2 is the threshold voltage of the threshold element. In a region where the absolute value of the voltage VN−VSL is equal to or lower than the threshold voltage (about 0.6 V in the illustrated example), the current I is zero. However, in a region where the voltage VN−VSL is positive and larger than the threshold voltage (in this case, the forward voltage of the diode D2), the forward current of the diode D2 flows through the threshold element. Further, in a region where the voltage VN−VSL is negative and the absolute value thereof is larger than the threshold voltage (in this case, the forward voltage of the diode D1), the forward current of the diode D1 flows through the threshold element.

  FIG. 3 is a diagram showing operating conditions of the nonvolatile memory cell according to the present embodiment. As shown in FIG. 3, in the case of “0” writing, 1.2 V is applied to the bit line BL and 0 V is applied to the source line SL. In this case, the diode D2 is turned on, a voltage of about 0.7 V is applied between the node N and the source line SL, and a voltage of about 0.5 V is applied to the resistance variable element R between the bit line BL and the node N. Is done. As a result, a forward current from the free layer to the pinned layer flows through the resistance variable element R, resulting in a low resistance, and “0” is written. On the other hand, when “1” is written, 0 V is applied to the bit line BL and 1.2 V is applied to the source line SL. In this case, the diode D1 is turned on, a voltage of about −0.7V is applied between the node N and the source line SL, and a voltage of about −0.5V is applied to the resistance variable element R between the bit line BL and the node N. Applied. As a result, a current in the reverse direction from the pinned layer to the free layer flows through the resistance variable element R, the resistance is increased, and “1” is written.

  When data is read, 0.7V is applied to the bit line BL and 0V is applied to the source line SL. In this case, the diode D2 is turned on, a voltage of about 0.7 V is applied between the node N and the source line SL, and a voltage of about 0.1 V is applied to the resistance variable element R between the bit line BL and the node N. Is done. At this time, the current flowing between the bit line BL and the source line SL is detected, and the data stored in the resistance variable element R is determined by comparing with a predetermined threshold value. That is, when the current flowing between the bit line BL and the source line SL is larger than the threshold, it is determined that the resistance of the resistance change element R is low and data “0” is stored. When the current flowing between the lines SL is smaller than the threshold, it is determined that the resistance of the resistance variable element R is high and data “1” is stored.

  In FIG. 3, “0” non-write and “1” non-write refer to the non-volatile memory cell when a non-volatile memory cell other than the non-volatile memory cell in the non-volatile memory cell array is a write target, for example. Operating conditions. When "0" is not written, a voltage having the same polarity as that when "0" is written is applied between the bit line BL and the source line SL. However, since the absolute value of the applied voltage does not exceed the threshold voltage of the threshold element, the nonvolatile Current does not flow through the memory cell and "0" is not written. The same applies to “1” non-write. The details of “0” non-write and “1” non-write will be clarified in a third embodiment described later.

  As described above, according to this embodiment, it is possible to write data to the variable resistance element R and read data from the variable resistance element R without using a switching element for selection such as a transistor. It is.

Second Embodiment
FIG. 4 is a circuit diagram showing a configuration of a nonvolatile memory cell according to the second embodiment of the present invention. In the first embodiment, the threshold element is constituted by diodes D1 and D2 connected in antiparallel, but in the present embodiment, the threshold element is constituted by a Zener diode DZ. Also in the present embodiment, the same effect as in the first embodiment can be obtained by setting the breakdown voltage of the Zener diode DZ to about 0.6 V that is the forward voltage of the diode.

<Third Embodiment>
FIG. 5 is a circuit diagram showing the configuration and operation of a nonvolatile memory cell array according to the third embodiment of the present invention. This nonvolatile memory cell array is constituted by the nonvolatile memory cells (FIG. 1) of the first embodiment. Here, in order to simplify the description, a nonvolatile memory cell array composed of 4-bit nonvolatile memory cells M00, M01, M10, and M11 will be described as an example. Bit lines BL0 and BL1 and source lines SL0 and SL1 are wired in the nonvolatile memory cell array. The nonvolatile memory cell M00 is at the intersection of the source line SL0 and the bit line BL0, the nonvolatile memory cell M01 is at the intersection of the source line SL0 and the bit line BL1, and the nonvolatile memory cell M10 is at the intersection of the source line SL1 and the bit line BL0. At the intersection, the nonvolatile memory cells M11 are arranged at the intersection between the source line SL1 and the bit line BL1, respectively.

  5A shows a case where “0” is written into the nonvolatile memory cell M00, FIG. 5B shows a case where “1” is written into the nonvolatile memory cell M00, and FIG. 5C shows a nonvolatile memory cell M00. The state of each part when reading data from is shown. FIG. 6 shows the operation condition for “0” write, and FIG. 7 shows the operation condition for “1” write.

When “0” is written in the nonvolatile memory cell M00, the following voltage application is performed.
a. A positive voltage between the bit line BL0 connected to the nonvolatile memory cell M00 to be written and the source line SL0 that is not less than the threshold voltage VF of the threshold element of the nonvolatile memory cell and not more than twice the threshold voltage VF Apply.
b. The same voltage as that applied to the bit line BL0 connected to the nonvolatile memory cell M00 to be written is applied to the source lines SL1 other than the source line SL0 connected to the nonvolatile memory cell M00 to be written.
c. Bit lines BL1 other than the bit line BL0 connected to the nonvolatile memory cell M00 to be written are opened, or the voltage of the bit line BL0 and the voltage of the source line SL0 connected to the nonvolatile memory cell M00 to be written And a voltage difference between the voltage of the bit line BL0 and the voltage of the bit line BL0 is equal to or lower than the threshold voltage VF and a voltage difference of the voltage of the source line SL0 is equal to or lower than the threshold voltage VF.

  Specifically, as shown in FIGS. 5A and 6, when “0” is written to the nonvolatile memory cell M00, the bit line BL0 is set to 1.2V and the bit line BL1 is set to open or 0.6V. The source line SL0 is set to 0V, and the source line SL1 is set to 1.2V.

  Here, paying attention to the nonvolatile memory cell M00, since BL0 = 1.2V and SL0 = 0V, as indicated by the solid line arrow, along the current path of bit line BL0 → resistance change element R → diode D2 → source line SL0. Thus, a positive voltage of 0.5 V is applied to the resistance variable element R. As a result, the resistance variable element R of the nonvolatile memory cell M00 has a low resistance because a current flows from the free layer to the pinned layer in the forward direction, and “0” is written.

  On the other hand, paying attention to the nonvolatile memory cells M01 and M11, since SL1 = 1.2V and SL0 = 0V, the source line SL1 → the diode D1 of the nonvolatile memory cell M11 and the resistance change element R → The current tends to flow through the current path of the bit line BL1 → the resistance variable element R and the diode D2 → the source line SL0 of the nonvolatile memory cell M01.

  However, when the bit line BL1 is open, the forward voltage VF = 0.6V of the diode D1 of the nonvolatile memory cell M11 and the forward voltage VF of the diode D2 of the nonvolatile memory cell M01 in this current path = 0.6V. Is equal to the voltage 1.2V between the source lines SL1 and SL0, the diode D1 of the nonvolatile memory cell M11 and the diode D2 of the nonvolatile memory cell M01 are both turned off, and no current flows in this current path. .

  In this case, the nonvolatile memory cell M11 is connected between the source line SL1 and the bit line BL1, although the voltage of the source line SL1 is higher than the voltage of the bit line BL1 as in the case of “1” writing. Since the voltage is insufficient, “1” is not written. This is referred to as “1” non-writing. The nonvolatile memory cell M01 has a voltage between the bit line BL1 and the source line SL0 although the voltage of the bit line BL1 is higher than the voltage of the source line SL0 as in the case of “0” writing. Since there is a shortage, “0” is not written. This is called non-writing of “0”.

  Regarding the nonvolatile memory cell M10, since SL1 = 1.2V and BL0 = 1.2V, the diodes D1 and D2 are turned off and are not selected.

  In the above example, “0” is written by setting the voltage V (BL−SL) applied between the bit line BL and the source line SL of the nonvolatile memory cell to be written to 1.2V. However, in order to avoid the occurrence of the sneak current to the non-write target nonvolatile memory cell and perform “0” write only to the write target non-volatile memory cell, VF ≦ V (BL−SL) ≦ 2VF. Thus, the voltage V (BL-SL) may be determined.

When “1” is written in the nonvolatile memory cell M00, the following voltage application is performed.
a. An absolute value that is not less than the threshold voltage VF of the threshold element of the nonvolatile memory cell and not more than twice the threshold voltage VF is between the bit line BL0 and the source line SL0 connected to the nonvolatile memory cell M00 to be written. Apply a negative voltage.
b. The same voltage as that applied to the bit line BL0 connected to the nonvolatile memory cell M00 to be written is applied to the source lines SL1 other than the source line SL0 connected to the nonvolatile memory cell M00 to be written.
c. Bit lines BL1 other than the bit line BL0 connected to the nonvolatile memory cell M00 to be written are opened, or the voltage of the bit line BL0 and the voltage of the source line SL0 connected to the nonvolatile memory cell M00 to be written And a voltage difference between the voltage of the bit line BL0 and the voltage of the bit line BL0 is equal to or lower than the threshold voltage VF and a voltage difference of the voltage of the source line SL0 is equal to or lower than the threshold voltage VF.

  Specifically, as shown in FIGS. 5B and 7, the bit line BL0 is set to 0V, the source line SL0 is set to 1.2V, the bit line BL1 is opened, and the source line SL1 is set to 0V. In this case, since a current flows through the nonvolatile memory cell M00 and a voltage of −0.5 V is applied to the resistance change element R, “1” writing is performed.

  On the other hand, when paying attention to the nonvolatile memory cell M01, SL0 = 1.2V and SL1 = 0V, so that a current path via the nonvolatile memory cells M01 and M11 is generated between the source lines SL0 and SL1 as indicated by broken line arrows. However, since the sum of the forward voltage of the diode D1 of the nonvolatile memory cell M01 and the forward voltage of the diode D2 of the nonvolatile memory cell M11 in this current path matches the voltage of 1.2 V between the source lines SL0 and SL1, Both diodes D1 and D2 are turned off. For this reason, no current flows through the nonvolatile memory cells M01 and M11, the nonvolatile memory cell M01 is not written to “1”, and the nonvolatile memory cell M11 is not written to “0”.

  The nonvolatile memory cell M10 is not selected because BL0 = 0V and SL1 = 0V.

  In the above example, “0” is written by setting the voltage V (SL−BL) applied between the source line SL and the bit line BL of the nonvolatile memory cell to be “1” written to 1.2V. However, VF ≦ V (SL−BL) ≦ 2VF is satisfied in order to perform “1” writing only to the nonvolatile memory cell to be written without erroneously writing to the nonvolatile memory cell that is not to be written. The voltage V (SL-BL) may be determined as follows.

When reading data from the nonvolatile memory cell M00, the following voltage application is performed.
a. An absolute value that is not less than the threshold voltage VF of the threshold element of the nonvolatile memory cell and not more than twice the threshold voltage VF is between the bit line BL0 and the source line SL0 connected to the nonvolatile memory cell M00 to be read. Apply a positive voltage.
b. The source line SL1 other than the source line SL0 connected to the nonvolatile memory cell M00 to be read has an intermediate voltage between the voltage of the bit line BL0 connected to the nonvolatile memory cell M00 to be read and the voltage of the source line SL0. The voltage difference between the voltage of the bit line BL0 and the voltage of the bit line BL0 is equal to or lower than the threshold voltage VF, and the voltage difference from the voltage of the source line SL0 is equal to or lower than the threshold voltage VF.
c. Bit lines BL1 other than the bit line BL0 connected to the nonvolatile memory cell M00 to be written are opened.
Specifically, as shown in FIG. 5C, the bit line BL0 is set to 0.7V, the source line SL0 is set to 0V, the bit line BL1 is opened, and the source line SL1 is set to 0.6V. In this case, the voltage applied to both ends of the resistance change element R of the nonvolatile memory cell M00 is approximately 0.1 V, and a current corresponding to the storage state of “0” and “1” of the resistance change element flows. .

  In this example, the voltage V (BL-SL) between the bit line BL and the source line SL connected to the nonvolatile memory cell to be read is set to 0.7 V. In order to accurately detect only the current flowing through the nonvolatile memory cell to be read without being turned on, the voltage V (BL-SL) should be determined so as to satisfy VF ≦ V (BL−SL) ≦ 2VF. Good.

  In the above description, the bit line (bit line BL1 in the above example) connected to the non-selected nonvolatile memory cell is opened. Instead of opening, the nonvolatile memory to be written or read is used. Even when a bias voltage (0.6 V in the writing example) corresponding to 1/2 of the voltage V (BL-SL) between the bit line BL and the source line SL connected to the cell is applied to the non-selected bit line Can be obtained. Further, when the bit line BL1 is fixed at 0.6V, the voltage is more stable than when the bit line BL1 is opened, and thus there is an advantage that the nonvolatile memory cell array can be speeded up.

  As described above, according to the present embodiment, a cross-point memory using a diode can be provided even in a nonvolatile memory using a bidirectional resistance change element such as an MRAM.

<Fourth embodiment>
FIG. 8 is a circuit diagram showing the configuration and operation of a nonvolatile memory cell array according to the fourth embodiment of the present invention. More specifically, FIG. 8A shows a case where “0” is written in the nonvolatile memory cell M00, FIG. 8B shows a case where “1” is written in the nonvolatile memory cell M00, and FIG. The state of each part when reading data from the non-volatile memory cell M00 is shown. FIG. 9 shows the operation condition for “0” write, and FIG. 10 shows the operation condition for “1” write.

  In the third embodiment, it is necessary to charge / discharge unselected source lines to 1.2 V or 0 V, respectively, with write data “0” and “1”, and the power consumption of charging / discharging the source lines is large. . In the fourth embodiment of the present invention, the power consumption for charging and discharging the source line is reduced.

  The difference between the third embodiment and the fourth embodiment is the bias voltage applied to the non-selected source line SL1 at the time of data writing. In the present embodiment, when “0” is written to the nonvolatile memory cell M00, a voltage between the voltage applied to the bit line BL0 connected to the nonvolatile memory cell M00 and the voltage applied to the source line SL0 is selected as a non-selected source. Give to the line. Specifically, when the voltage applied to the bit line BL0 connected to the nonvolatile memory cell M00 to be written is VBL and the voltage applied to the source line SL0 is VSL, the bias voltage VCOM = (VBL + VSL) / 2 is not Give to the selected source line. For example, as shown in FIGS. 8A and 9, BL0 = 1.2V, BL1 = 0.6V, SL0 = 0V, and SL1 = 0.6V.

  In this case, in the nonvolatile memory cell M00, a current flows from the bit line BL0 to the source line SL0 along the current path indicated by the solid line arrow, and “0” is written in the nonvolatile memory cell M00.

  As for the non-selected nonvolatile memory cells M01, M10, and M11, the current tends to flow along the current path indicated by the broken-line arrow. However, since only 0.6 V is applied to the nonvolatile memory cells, The diodes D1 and D2 of the memory cell are turned off, and “0” is not written to the nonvolatile memory cells M01 and M10, and “1” is not written to the nonvolatile memory cell M11.

  Next, when “1” is written in the nonvolatile memory cell M00, a voltage for fixing the non-selected source line is determined within a range satisfying the condition of VF ≦ VCOM ≦ 2VF. For example, FIG. 8B and FIG. As shown, BL0 = 0V, BL1 = 0.6V, SL0 = 1.2V, and SL1 = 0.6V. In this case, a current flows from the source line SL0 to the bit line BL0 along the current path indicated by the solid arrow in the nonvolatile memory cell M00, and “1” is written in the nonvolatile memory cell M00.

  With respect to the nonvolatile memory cells M01, M10, and M11, current tends to flow along the current path along the broken-line arrow, but since only 0.6V is applied to each nonvolatile memory cell, The diodes D1 and D2 of the memory cell are turned off. As a result, the non-volatile memory cells M01 and M10 are “1” non-write, and the non-volatile memory cell M11 is “0” non-write.

  Next, when data is read from the nonvolatile memory cell M00, BL0 = 0.7V, SL0 = 0V, BL1 = 0.6V, and SL1 = 0.6V. In this case, the voltage applied across the resistance variable element R of the nonvolatile memory cell M00 is approximately 0.1 V, and a current corresponding to “0” or “1” stored in the resistance variable element R is present. It flows to the nonvolatile memory cell M00.

  In this example, the voltage V (BL−SL) between the bit line BL0 connected to the nonvolatile memory cell M00 and the source line SL0 is 0.6V, but the voltage V (BL−SL) is VF ≦ V ( BL-SL) should be determined within a range satisfying the condition of 2VF.

  As described above, according to the present embodiment, selective writing and selection with respect to one nonvolatile memory cell are performed by always biasing a non-selected source line and a non-selected bit line to a constant voltage of 0.6V. Reading can be performed, and the charge / discharge current of the non-selected source line can be greatly reduced.

<Fifth Embodiment>
FIG. 11 is a circuit diagram showing a configuration example of a nonvolatile memory according to the fifth embodiment of the present invention. In FIG. 11, a non-volatile memory cell array 100 is a memory array composed of non-volatile memory cells according to the first embodiment. The nonvolatile memory cell array 100 includes a source line SLj (j = 0 to m) composed of m + 1 rows, a bit line BLk (k = 0 to n) composed of n + 1 columns, and intersections of these source lines and bit lines. Are configured by non-volatile memory cells Mjk (j = 0 to m, k = 0 to n).

  The row decoder 200 outputs a row selection signal SELj and a row selection inversion signal SELjB (j = 0 to m) corresponding to each source line SLj (j = 0 to m) of the nonvolatile memory cell array 100 based on the row address. Circuit.

  FIG. 12 is a diagram showing a circuit configuration for one row of the row decoder 200. As shown in FIG. 12, the circuit corresponding to one row j in the row decoder 200 includes a coincidence detection circuit 201 that outputs a signal at L level when the row address indicates row j, and an H level at other times. The inverter 202 that inverts and outputs the output signal of the coincidence detection circuit 201 is configured. The output signal of the coincidence detection circuit 201 is the row selection inversion signal SELjB, and the output signal of the inverter 202 is the row selection signal SELj.

  The selection switch 300 is a switch that selects the source line SLj according to the row selection signal SELj and the row selection inversion signal SELjB (j = 0 to m) output from the row decoder 200. The selection switch 300 includes source line selection transistors SSj and SSjB (j = 0 to m) connected to the source lines SLj (j = 0 to m). These source line selection transistors SSj and SSjB (j = 0 to m) are N-channel transistors, and a row selection signal SELj and a row selection inversion signal SELjB (j = 0 to m) are applied to each gate. The source line selection transistor SSj corresponding to a certain row j is turned on when the selection signal SELj is at the H level, and applies the write voltage VDIN to the source line SLj corresponding to the row j. Further, the source line selection transistor SSjB corresponding to a certain row j is turned on when the row selection inversion signal SELjB is at the H level, and applies the bias voltage VCOM to the source line SLj corresponding to the row j.

  The column decoder 400 outputs a column selection signal COLk and a column selection inversion signal COLkB (k = 0 to n) corresponding to each column k (k = 0 to n) of the nonvolatile memory cell array 100 based on the column address.

  The column gate switch 500 includes bit line selection transistors CGNk and CGPk (k = 0 to n) connected to the bit lines BLk (k = 0 to n), respectively. Here, the bit line selection transistor CGNk (k = 0 to n) is an N-channel transistor, and a column selection signal COLk (k = 0 to n) is applied to each gate thereof. The bit line selection transistor CGPk (k = 0 to n) is a P-channel transistor, and a column selection inversion signal COLkB (k = 0 to n) is applied to each gate thereof.

  The column decoder 400 sets the column selection signal COLk corresponding to the column k indicated by the column address to the H level and the selection inversion signal COLkB to the L level, and turns on the bit line selection transistor CGNk and the P channel transistor CGPk corresponding to the column k. The bit line BLk corresponding to the column k is connected to the data line DL. The column decoder 400 sets the column selection signal COLj ′ to the L level and the column selection inversion signal COLk′B to the H level for the column k ′ (≠ k) other than the column k corresponding to the column address, and the column k The bit line selection transistors CGNk 'and CGPk' corresponding to 'are turned off.

  The bias circuit 600 is a bias circuit that biases the bit line. Bias circuit 600 includes an N channel transistor PRk (k = 0 to n) connected to bit line BLk (k = 0 to n), an inverter 502 and an inverter 503 having a level shift function. A precharge signal PRE is applied to each gate of N channel transistor PRk (k = 0 to n) via inverters 502 and 503. The N-channel transistor PRk (k = 0 to n) is turned on when the precharge signal PRE becomes H level, and supplies the bias voltage VCOM (0.6 V) to the bit line BLk (k = 0 to n). The power supply circuit 700 is a circuit that generates the bias voltage VCOM (= 0.6 V).

The write control circuit 800 is a circuit that receives a write control signal WE and input data Din, and controls writing and reading of the nonvolatile memory. The write driver 900 is a circuit that supplies a voltage corresponding to the write data Din to the data line DL and the bit line connected thereto. The write driver 900 is a three-state driver having an output disable function. At the time of data reading, the write driver 900 is in an output disabled state and is disconnected from the data line DL. The source driver 1000 is a circuit for supplying a write voltage VIN corresponding to the write data Din to the source line SLj (j = 0 to m). The sense amplifier 1100 is an amplifier that detects and amplifies a minute current difference of the data line DL at the time of reading. The output circuit 1200 is a circuit that outputs output data Dout to the outside of the chip based on the output signal of the sense amplifier 1100.
The above is the configuration of the present embodiment.

Next, the operation of this embodiment will be described.
First, the operation when “0” is written to the nonvolatile memory cell M00 will be described. In the initial state, WE = L. Further, the precharge signal PR is at the H level, all the N-channel transistors PRk (k = 0 to n) are turned on, and all the bit lines BLk (k = 0 to n) are precharged to about 0.6V. Has been. In the initial state, the row decoder 200 sets all selection signals SELj (j = 0 to m) to L level and all selection inversion signals SELjB (j = 0 to m) to H level. Therefore, the bias voltage VCOM (= 0.6 V) is applied to all the source lines SLj (j = 0 to m).

  In the write mode, the write control signal WE is set to the H level. In the case of “0” write, write data Din = “0” is given to the write control circuit 800. Based on the write data Din = “0”, the write control circuit 800 outputs the write voltage VDIN = 0V from the source driver SD and outputs the voltage 1.2V from the write driver WD to the data line DL.

  When the nonvolatile memory cell M00 is selected by the row address and the column address, the row decoder 200 sets the row selection signal SEL0 to the H level and the row selection inversion signal SEL0B to the L level. As a result, the write voltage VDIN is applied to the source line SL0, and SL0 = 0V. The row decoder 200 sets the row selection signal SELj to the L level and the row selection inversion signal SELjB to the H level for the non-selected rows j = 1 to m. As a result, the bias voltage VCOM = 0.6 V is applied to the source line SLj (j = 1 to m) in the non-selected row.

  On the other hand, the column decoder 400 sets the column selection signal COL0 to H level and the column selection inversion signal COL0B to L level. As a result, the bit line BL0 is selected and connected to the data line DL, and 1.2V is supplied to the bit line BL0.

  In this way, 1.2 V is supplied to the bit line BL0 to which the nonvolatile memory cell M00 is connected and 0 V is supplied to the source line SL0, and a current flows through the resistance variable element R of the nonvolatile memory cell M00. As a result, the resistance variable element R of the nonvolatile memory cell M00 becomes low resistance, and “0” is written.

  At this time, 0.6 V is applied to the unselected source lines SLk (k = 1 to m), and the bit line selection transistors CGNk and CGPk connected to the unselected bit lines BLk (k = 1 to n). (K = 1 to n) is off. Here, before entering the write mode, the precharge voltage VCOM = 0.6 V is applied to all the bit lines. In the write mode, each bit line connected to a nonvolatile memory cell other than the nonvolatile memory cell M00 is opened. Therefore, in the write mode, the nonvolatile memory cells other than the nonvolatile memory cell M00 are in the non-write state.

  When writing “1” to the nonvolatile memory cell M00, the write control circuit 800 outputs the write voltage VDIN = 1.2V from the source driver SD based on the write data Din = “1”, and the voltage 0V from the write driver WD. Is output to the data line DL. Therefore, the bit line BL0 to which the nonvolatile memory cell M00 is connected is 0V, and the source line SL0 is 1.2V. As a result, “1” is written in the nonvolatile memory cell M00.

  Next, an operation of reading data from the nonvolatile memory cell M00 will be described. In the read mode, the write control WE is at the L level. The write control circuit 800 outputs 0 V from the source driver SD and disconnects the write driver WD from the data line DL in response to the write control WE becoming L level.

  When the read target is the nonvolatile memory cell M00, the voltage 0V output from the source driver SD is applied to the source line SL0, and the bit line BL0 is connected to the data line DL. 0.7 V is supplied to the data line DL by a bias circuit (not shown) in the sense amplifier 1100.

  Here, when the variable resistance element R of the nonvolatile memory cell M00 stores “0”, that is, when it has a low resistance, a large amount of current flows through the nonvolatile memory cell M00, and the sense amplifier 1100 reads data. It is determined that the data is “0”. Further, since the resistance change element R of the nonvolatile memory cell M00 stores “1” and the resistance is high, the flowing current is small, and thus the sense amplifier 1100 determines that the read data is “1”. . The output circuit 1200 outputs the determination result of the sense amplifier 1100 as read data Dout.

  In the above write operation and read operation, the non-selected source line is set to 0.6V, and the non-selected bit line is set to 0.6V. Therefore, the diodes D1 and D2 of the non-selected nonvolatile memory cells M01 to Mmn are The nonvolatile memory cells M01 to Mmn are turned off and turned off.

  As described above, according to the present embodiment, since 0.6 V is always applied to the non-selected source line and bit line, it is possible to eliminate the charge / discharge current every time the address is switched, and to reduce the power consumption. Can be realized.

<Sixth Embodiment>
FIG. 13 is a circuit diagram showing a configuration of a nonvolatile memory according to the sixth embodiment of the present invention. The nonvolatile memory according to the present embodiment is the one in which the precharge circuit 600 is deleted and a bias of 0.6 V is supplied from the column gate switch 550 to the non-selected bit line in the fifth embodiment (FIG. 11). It is.

  The column gate switch 550 includes an N channel transistor CGk (k = 0 to n) interposed between the bit line BLk (k = 0 to n) and the data line DL, and a bit line BLk (k = 0 to n). n) and an N-channel transistor CGkB (k = 0 to n) interposed between the output terminal of the power supply circuit 700 and the n-channel transistor CGkB. Here, column selection signal COLk (k = 0 to n) output from column decoder 400 is applied to each gate of N channel transistor CGk (k = 0 to n). A column selection inversion signal COLkB (k = 0 to n) output from the column decoder 400 is applied to each gate of the N channel transistor CGkB (k = 0 to n).

  In the initial state, the column decoder 400 sets all the column selection signals COLk (k = 0 to n) to L level and all the column selection inversion signals COLkB (k = 0 to n) to H level. As a result, the N-channel transistor CGk (k = 0 to n) is turned off, the N-channel transistor CGkB (k = 0 to n) is turned on, and the bias voltage VCOM = 0.6 V output from the power supply circuit 700 is applied to the N-channel transistor CGkB ( The voltage is applied to the bit line BLk (k = 0 to n) via k = 0 to n).

  For example, during a write operation to the nonvolatile memory cell M00, the column decoder 400 sets the column selection signal COL0 to H level, the column selection signal COLk (k = 1 to n) to L level, the column selection inversion signal COL0B to L level, and column selection. The inversion signal COLkB (k = 1 to n) is set to the H level. As a result, the bit line selection transistor CG0 is turned on, the bit line selection transistor CGk (k = 1 to n) is turned off, the bit line selection transistor CG0B is turned off, and the N-channel transistor CGkB (k = 1 to n) is turned on. As a result, the bit line BL0 is connected to the data line DL, the bias voltage VCOM = 0.6 V output from the power supply circuit 700 is applied to the bit line BLk (k = 1 to n), and data is written to the nonvolatile memory cell M00. Is done.

  In the fifth embodiment (FIG. 11), the bias voltage is supplied to the non-selected bit line from the precharge circuit, but the non-selected bit line is set to floating during the write operation and the read operation. Here, when the diodes D1 and D2 in the nonvolatile memory cell Mjk are diodes (Schottky diodes, amorphous diodes, etc.) manufactured on a metal wiring, this type of diode has many defects, as shown in FIG. There is a possibility that a leak current flows even when a firm diode characteristic cannot be obtained and the applied voltage is equal to or lower than the forward voltage VF. Therefore, as in the fifth embodiment, in the method in which the bit line is precharged and the unselected bit line is opened during the write operation and the read operation, it is biased to 0.6 V by the leakage current of the diodes D1 and D2. There is also a concern that the voltage of the bit line will drop. However, in the present embodiment, the bias voltage VCOM is applied to the unselected bit lines during the write operation and the read operation. Therefore, even if a leakage current of the diodes D1 and D2 occurs during the writing operation and the reading operation, the leakage current does not reduce the voltage of the non-selected bit line, and no operational problem occurs.

  In the sixth embodiment (FIG. 13), the decoder 300 and the column switch 550 are configured by analog switches composed of N-channel transistors. However, the N-channel transistor is similar to the column gate switch 500 of the fifth embodiment (FIG. 11). Alternatively, a CMOS analog switch composed of a P channel transistor may be used. In this case, there is an advantage that a voltage drop due to the threshold value of the N-channel transistor does not occur.

R... Variable resistance element, D1, D2... Diode, DZ... Zener diode, Mjk (j = 0 to m, k = 0 to n)... Nonvolatile memory cell, SLj (j = 0 to m) ... Source line, BLk (k = 0 to n)... Bit line, 100... Nonvolatile memory cell array, 200 ... Row decoder, 300 ... Select switch, SSj and SSjB (j = 0 to m). Source line selection transistor, 400... Column decoder, 500, 550... Column gate switch, CGNk (k = 0 to n), CGk (k = 0 to n), CGkB (k = 0 to n). Transistor, CGPk (k = 0 to n): P-channel transistor, 600: Precharge circuit, 700: Power supply circuit, 800: Write control circuit, 900: Write driver, 1000 ... Sudoraiba, 1100 ...... sense amplifier, 1200 ...... output circuit.

Claims (15)

  A resistance variable element whose resistance value changes in a different direction depending on the energization direction, and a bidirectional threshold element that allows a current having the same polarity as the voltage to pass when a voltage whose absolute value is equal to or greater than the threshold voltage is applied. A non-volatile memory cell characterized by being connected in series.   2. The nonvolatile memory cell according to claim 1, wherein the threshold element includes two diodes connected in antiparallel to each other.   The nonvolatile memory cell according to claim 1, wherein the threshold element is configured by a Zener diode having a breakdown voltage near a forward voltage. At the time of data writing, both ends of the resistance variable element and the threshold element connected in series have a polarity corresponding to the write data, and are equal to or higher than the threshold voltage of the threshold element and twice the threshold voltage. A write voltage having the following absolute value is applied:
At the time of data reading, a voltage having an absolute value that is not less than the threshold voltage of the threshold element and not more than twice the threshold voltage is applied to both ends of the resistance variable element and the threshold element connected in series. The nonvolatile memory cell according to claim 1, wherein the nonvolatile memory cell is a non-volatile memory cell. Multiple source lines,
A plurality of bit lines intersecting the plurality of source lines;
A plurality of nonvolatile memory cells provided corresponding to respective intersections of the plurality of source lines and the plurality of bit lines, each having a resistance change whose resistance value varies in a different direction depending on the energization direction Bit line and source line that have a type element and a bidirectional threshold element that allows a current having the same polarity as that voltage to pass when a voltage having an absolute value equal to or greater than the threshold voltage is applied. A non-volatile memory comprising a non-volatile memory cell array having a plurality of non-volatile memory cells formed by connecting the variable resistance element and the threshold element in series therebetween.   At the time of data writing, when the threshold voltage of the threshold element is VF, the bit line and the source line connected to the nonvolatile memory cell to be written have a polarity corresponding to the write data, and A voltage V (BL-SL) having an absolute value satisfying VF ≦ | V (BL−SL) | ≦ 2VF is set, and at the time of data reading, a bit line and a source connected to a nonvolatile memory cell to be read And a control means for setting a voltage V (BL-SL) having a predetermined polarity and having an absolute value satisfying VF ≦ | V (BL−SL) | ≦ 2VF between the lines. The nonvolatile memory according to claim 5.   The control means sets the same voltage as the voltage of the bit line connected to the nonvolatile memory cell to be written to a source line other than the source line connected to the nonvolatile memory cell to be written. The nonvolatile memory according to claim 6.   The control means is configured such that the source line other than the source line connected to the nonvolatile memory cell to be read is intermediate between the voltage of the bit line connected to the nonvolatile memory cell to be read and the voltage of the source line. A voltage is set such that a voltage difference from the voltage of the bit line is equal to or lower than a threshold voltage VF and a voltage difference from the voltage of the source line is equal to or lower than the threshold voltage VF. Item 7. The nonvolatile memory according to Item 6.   9. The control unit according to claim 6, wherein when the data is written or read, the bit line other than the bit line connected to the nonvolatile memory cell to be written or read is opened. The non-volatile memory according to claim 1.   The control means is connected to a nonvolatile memory cell to be written or read with respect to a bit line other than the bit line connected to the nonvolatile memory cell to be written or read at the time of data writing or data reading. The voltage difference between the bit line voltage and the source line voltage is a threshold voltage VF or less and the voltage difference from the source line voltage is a threshold voltage. The non-volatile memory according to claim 6, wherein a voltage that is equal to or lower than the voltage VF is set.   The control means is configured such that the voltage and source of the bit line connected to the nonvolatile memory cell to be written to or read from the source line other than the source line connected to the nonvolatile memory cell to be written to or read from are controlled. A voltage that is in the middle of the line voltage, the voltage difference with the bit line voltage being equal to or less than the threshold voltage VF, and the voltage difference with the source line voltage being less than or equal to the threshold voltage VF is set. The non-volatile memory according to claim 6.   The control means is connected to a nonvolatile memory cell to be written or read with respect to a bit line other than the bit line connected to the nonvolatile memory cell to be written or read at the time of data writing or data reading. A voltage difference between the bit line voltage and the source line voltage, the voltage difference from the bit line voltage being equal to or less than the threshold voltage VF, and the voltage difference from the source line voltage being The nonvolatile memory according to claim 11, wherein a voltage that is equal to or lower than the threshold voltage VF is set. A non-volatile memory cell array and control means;
The nonvolatile memory cell array includes:
Multiple source lines,
A plurality of bit lines intersecting the plurality of source lines;
A plurality of nonvolatile memory cells provided corresponding to respective intersections of the plurality of source lines and the plurality of bit lines, each having a resistance change whose resistance value varies in a different direction depending on the energization direction Bit line and source line that have a type element and a bidirectional threshold element that allows a current having the same polarity as that voltage to pass when a voltage having an absolute value equal to or greater than the threshold voltage is applied. A plurality of nonvolatile memory cells formed by connecting the resistance variable element and the threshold element in series between the nonvolatile memory cell,
When writing data to one nonvolatile memory cell in the nonvolatile memory cell array, the control means corresponds to write data between a bit line and a source line connected to the nonvolatile memory cell to be written. A voltage V (BL-SL) having polarity and having an absolute value satisfying the condition of VF ≦ | V (BL−SL) | ≦ 2VF when the threshold voltage of the threshold element is VF, When reading data from one nonvolatile memory cell in the nonvolatile memory cell array, the bit line and the source line connected to the nonvolatile memory cell to be read have a predetermined polarity and VF ≦ | V (BL−SL) | ≦ 2VF The voltage V (BL−SL) having an absolute value satisfying the condition of the condition is set, and writing or reading A source line and a bit line other than a source line and a bit line connected to a non-volatile memory to be read or to be read, and a bit line voltage and a source line connected to a non-volatile memory cell to be written or read And a voltage difference between the voltage of the bit line and the voltage of the bit line is equal to or lower than the threshold voltage VF, and a voltage difference from the voltage of the source line is equal to or lower than the threshold voltage VF. A non-volatile memory characterized by being fixed to. A precharge circuit that applies the bias voltage to all the bit lines of the nonvolatile memory cell array during a period in which a write operation or a read operation is not performed;
In the write operation or the read operation, the control unit opens all the bit lines other than the bit lines connected to the nonvolatile memory cell to be written or read, thereby setting the bit lines. The nonvolatile memory according to claim 13, wherein the nonvolatile memory is fixed to the bias voltage.   The control means provides a bias voltage output from the power supply circuit to all the bit lines other than the bit line connected to the nonvolatile memory cell to be written or read at the time of the write operation or the read operation, 14. The nonvolatile memory according to claim 13, wherein the bit lines are fixed to the bias voltage.

Images