JP2014167983A - Circuit board for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board for a semiconductor device which prevents solder flow between solder joint planned parts and misalignment of elements without forming a resist film in the circuit board where the semiconductor elements are soldered.SOLUTION: Semiconductor elements 11 are soldered to a circuit board 1 for a semiconductor device. An Ni plating layer 4 is formed on a surface of a circuit layer 3. Solder joint planned parts 5, to which the semiconductor elements 11 are soldered, and an altered part 6 altered by laser radiation are disposed adjacent to each other in a plane direction on the Ni plating layer 4.

Description

  The present invention relates to a circuit board used in a semiconductor device and to which a semiconductor element such as an LED is soldered.

  When a semiconductor element is soldered to a circuit board having a circuit layer made of copper or aluminum, a Ni plating layer is formed on the surface of the circuit layer in order to improve solder wettability on the surface of the circuit layer. In addition, when soldering a plurality of semiconductor elements on a circuit layer, a Ni plating layer is provided only on the part to which the semiconductor elements are soldered in order to prevent the solder material from flowing and the semiconductor element from being displaced. For example, a method of forming a solder resist layer in a portion where a semiconductor element is not soldered after a Ni plating layer is formed on the entire surface of a circuit layer or the like is known.

In Patent Document 1, a two-layer surface treatment layer is formed on a conductive base material, and laser light is irradiated between an electrical contact portion and a terminal portion joined to another substrate by solder joining. A contact is disclosed in which the surface treatment layer is removed, and the underlying surface treatment layer exposed by this removal is oxidized to prevent the solder from spreading into the electrical contact portion.
Patent Document 2 describes that a resist film is formed by forming a coating film on the surface of a base material and then exposing it by irradiating a laser.
Patent Document 3 discloses a partial plating method in which a resist is coated on the surface of a material to be plated, a resist at a portion where plating is necessary is removed by laser irradiation, and after the plating is performed at the removed portion, another resist is removed. Yes.

Japanese Patent No. 4445014 JP-T-2001-511137 JP 2001-223313 A

By the way, when forming a resist film by screen printing, the positioning accuracy tends to be lowered due to the occurrence of misalignment caused by the elongation of the screen printing plate. In addition, it is difficult to improve the dimensional accuracy due to bleeding or splashing of the resist ink. In the resist film by screen printing, the practical minimum width is limited to 300 μm, and it is difficult to cope with a fine pattern called a fine line.
When a solder resist layer is formed, if the heat treatment is performed in the air for curing the resist layer, the Ni plating surface may be oxidized and the solder wettability may be impaired.

If only a necessary part is processed by laser irradiation as described in each patent document, the part can be formed with high dimensional accuracy. However, in the technique described in Patent Document 1, a plurality of parts are previously formed on a conductive base material. It is necessary to form a layer, and the techniques described in Patent Document 2 and Patent Document 3 require both steps of forming a resist film and removing the resist film.
Further, the method of removing the resist film by laser irradiation has a problem that the removed resist film is scattered and adheres to the plated surface, resulting in poor bonding.

  The present invention has been made in view of such circumstances, and in a circuit board for soldering a semiconductor element, without causing a resist film, a solder flow between elements to be soldered or an element misalignment occurs. An object of the present invention is to provide a circuit board for a semiconductor device that can prevent the above.

  The circuit board for a semiconductor device of the present invention is a circuit board for a semiconductor device to which a semiconductor element is soldered, and a Ni plating layer is formed on the surface of the circuit layer, and the semiconductor element is formed on the Ni plating layer. The solder joint planned part to be soldered and the altered part by laser irradiation are arranged adjacent to each other in the surface direction.

The altered portion formed by laser irradiation on a part of the Ni plating layer is a part of the Ni plating layer that has become an oxide or hydroxide due to the heat at the time of laser irradiation, resulting in poor solder wettability. Yes. For this reason, when soldering a semiconductor element to a solder joint planned part, it is prevented that the solder spreads in the altered part adjacent to the solder joint planned part. Therefore, the semiconductor element can be soldered in a state of being accurately positioned on the solder joint planned portion without being shifted from the solder joint planned portion.
In this case, the altered portion formed by laser irradiation on a part of the Ni plating layer is not formed by removing a part of the Ni plating layer, the resist film, or the like. Work such as formation and removal of the film is not required, and there is no problem that the removal material of the resist film adheres to the Ni plating layer.

In the circuit board for a semiconductor device of the present invention, a plurality of the solder joint planned portions may be formed, and the altered portion may be formed so as to block between the solder joint planned portions.
A plurality of semiconductor elements can be soldered at a desired interval by an altered portion between them, and solder flow to the altered portion can be reliably prevented, so that each semiconductor element can be accurately positioned even if the width is reduced. It is possible to achieve a fine pitch.

  In the circuit board for a semiconductor device of the present invention, the Ni plating layer was measured by Auger electron spectroscopy under the conditions of acceleration voltage: 5 kV, beam current: 5 nA, raster region: 20 μm, surface inclination angle with respect to the beam incident direction: 30 °. Regarding the Ni content, the Ni content in the solder joint planned portion is 45 at% or more, and the Ni content in the altered portion is preferably 5 at% to 12 at%.

If the Ni content in the altered portion is less than 5 at%, the amount of Ni scattered by the laser irradiation increases, and the scattered Ni adheres to the surface of the solder joint planned portion, which may deteriorate the solder wettability as the Ni plating layer. . If the Ni content of the altered part exceeds 12 at%, the degree of alteration is small, and when using flux or the like during soldering, the altered part is removed, and the solder gets wet and the effect of preventing flow is obtained. There is a risk of disappearing.
If the Ni content of the Ni plating layer in the solder joint planned portion is less than 45 at%, the solder wettability is impaired, and there is a risk of causing a joint failure of the element.

  According to the circuit board for a semiconductor device of the present invention, the altered portion due to laser irradiation provided between the planned joining portions in the Ni plating layer prevents the solder from spreading from the planned solder joining portion. It is possible to reliably prevent occurrence of a positional deviation of the attached element and to solder the semiconductor element in a state of being positioned with high accuracy. Moreover, since it forms by changing a part of Ni plating layer, while work | work is easy, it does not inhibit the solder wettability of the solder joint planned part.

It is a longitudinal cross-sectional view which shows one Embodiment of the circuit board for semiconductor devices of this invention. It is a top view of the circuit board of FIG. It is a top view which shows a part of sample used in the case of a test.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
In a circuit board 1 for a semiconductor device according to an embodiment, a circuit layer 3 made of a metal plate is bonded to a surface of a ceramic substrate 2 in a laminated state, and a Ni plating layer 4 is formed on the surface of the circuit layer 3. On the surface of the plating layer 4, the solder joint planned portion 5 and the altered portion 6 are formed adjacent to each other in the surface direction.
The ceramic substrate 2 is not particularly limited, but AlN, Si ₃ N ₄ , Al ₂ O ₃ , SiC, or the like is used. As the metal plate constituting the circuit layer 3, copper or a copper alloy, aluminum or an aluminum alloy is used. The circuit layer 3 is bonded to the ceramic substrate 2 by a method such as brazing, soldering, diffusion bonding, or a transient liquid phase bonding method (TLP bonding method: Transient Liquid Phase Diffusion Bonding).
The Ni plating layer 4 may be either an electroless Ni plating layer or an electrolytic Ni plating layer. In the case of electroless plating, Ni-P plating containing P in a range of up to 10% by mass is also applicable. These are collectively referred to as Ni plating. The thickness of the Ni plating layer 4 is preferably 2 μm to 7 μm. When aluminum or an aluminum alloy is used for the circuit layer 3, a zincate treatment is performed as a base treatment before Ni plating.

A plurality of semiconductor elements 11 are soldered onto the circuit layer 3 on the circuit board 1, and the solder joint planned portions 5 to which the semiconductor elements 11 are to be soldered are arranged at predetermined intervals. An altered portion 6 is formed between the planned solder joint portions 5 that are disposed and are adjacent to each other. In the example shown in FIG. 1, two solder joint planned portions 5 are formed on the Ni plating layer 4, and the altered portion 6 is formed between the two solder joint planned portions 5.
This altered portion 6 is formed by irradiating a portion between the solder joint planned portions 5 in the Ni plating layer 4 with a laser, so that a part of the Ni plating layer 4 is oxidized (NiO) or hydroxide (by a heat at the time of laser irradiation). Ni (OH) ₂ ). For this reason, the solder joint scheduled portion 5 is excellent in solder wettability, which is an original characteristic of the Ni plating layer 4, whereas the deteriorated portion 6 has poor solder wettability.

  When solder is applied on the circuit layer 3 of the circuit board 1 configured as described above, the solder adheres to each solder joint planned portion 5 and the solder wettability occurs in the altered portion 6 between the solder joint planned portions 5. Due to the poor nature, solder is not applied, and the solder on the solder joint planned portions 5 arranged on both sides of the solder is prevented from spreading at the boundary with the altered portion 6. When the semiconductor element 11 is mounted on the solder (on the solder joint planned portion 5) and the reflow process is performed, the solder on the solder joint planned portion 5 is melted and the semiconductor element 11 is joined. The molten solder is prevented from flowing out beyond the boundary between the solder joint planned portion 5 and the altered portion 6, and therefore the semiconductor element 11 is joined in a state where the semiconductor element 11 is accurately positioned on the solder joint planned portion 5. can do. Reference numeral 12 in FIG. 1 denotes a solder layer formed between the Ni plating layer 4 and the semiconductor element 11 in the solder joint planned portion 5.

The altered portion 6 is formed by forming a Ni plating layer 4 on the surface of the circuit layer 3 and then irradiating with a laser so as to block between the solder joint planned portions 5.
Various lasers such as a gas laser such as a carbon dioxide laser and a solid-state laser such as a YAG laser can be used for this laser irradiation. You may use harmonics, such as a 2nd harmonic and a 3rd harmonic, with respect to a fundamental wave.
If the power of the laser on the surface of the Ni plating layer 4 is too large, scattering of Ni in the Ni plating layer 4 increases and the amount of remaining Ni decreases. If the power is small, the alteration effect will be poor. The specific laser power varies depending on the type of laser to be used. For example, the Ni plating layer 4 is irradiated with a laser at a frequency of 10 W, a focal length of 50 mm, and a frequency of 50 kHz by a double wave of a YAG laser. These focal positions may be made to coincide with the surface of the Ni plating layer 4 or may be irradiated in a shifted state as long as it is within a range from the surface of the Ni plating layer 4 to several hundred μm.

The Ni content of the altered portion 6 formed by this laser irradiation is specified by Auger electron spectroscopy (AES) analysis. The acceleration voltage is 5 kV, the beam current is 5 nA, the raster region is 20 μm, and the surface tilt angle with respect to the beam incident direction is: The Ni content when measured under the condition of 30 ° is set to 5 at% to 12 at%.
When the Ni content in the altered portion 6 is less than 5 at%, the amount of Ni scattered by the laser irradiation increases, and the scattered Ni adheres to the surface of the Ni plating layer other than the altered portion 6 (that is, the solder joint planned portion 5). There is a risk. Since the scattered matter is an oxide or hydroxide that Ni is altered by laser irradiation, if it is attached to the solder joint planned portion 5, the solder wettability as the Ni plating layer is deteriorated.
On the other hand, when the Ni content of the altered portion 6 exceeds 12 at%, the degree of alteration is small, and when the flux or the like is used during soldering, the altered portion 6 is removed and the solder gets wet and prevents flow. The effect may not be obtained.
The Ni content of the solder joint planned portion 5 is preferably 45 at% or more. If the Ni content of the solder joint planned portion 5 is less than 45 at%, the solder wettability is impaired and the semiconductor element 11 may be poorly joined.

A test conducted for confirming the effect of the present invention will be described.
A sample in which electroless Ni—P plating (P concentration: 1% by mass to 3% by mass) was formed on an aluminum plate with a thickness of 5 μm was prepared. The surface of the Ni plating layer of this sample was irradiated with laser light. As shown in FIG. 3, a laser beam is irradiated in a linear shape of a predetermined length to form an altered portion 6 having a width W of 0.15 mm, and the linear altered portion 6 is opened with a gap G of 0.15 mm. A plurality were formed. A space between the altered portions 6 is a solder joint planned portion 5.
The laser used was a double wave of the YAG laser, the output was 10 W, the focal length was 50 mm, and the frequency was 50 kHz. The Ni plating layer 4 was irradiated with this laser while changing the focal position and the processing speed. Table 1 shows the focal position and processing speed at that time. The focal position was described as a focal shift with respect to the surface of the Ni plating layer 4. When the surface of the Ni plating layer 4 and the focal position coincide with each other, the focal shift is 0 μm.

These samples were subjected to solder evaluation and AES analysis.
For solder evaluation, a solder ball made of Pb-10 mass% Sn having a diameter of 0.5 mm is placed so as to straddle the solder joint planned portion 5 and the altered portion 6 and is heated to 360 ° C. in a nitrogen atmosphere (93% N2 + 7% H2). The solder was melted by heating, and the solder wettability and the solder flow prevention effect were evaluated.
The solder wettability was evaluated based on the solder wetting spread rate based on the degree of solder spreading on the solder joint planned portion 5 after melting the solder ball in the planned joint portion 5.
Solder wetting spread rate = (DH) / D × 100 (%)
(D: Solder ball diameter, H: Height after solder wetting)
When the solder wetting spread rate was 60% or more, it was judged that the solder wetting was good (◯).
The solder flow prevention effect is evaluated by the area ratio of the solder adhering to the deteriorated portion 6 after the solder ball is melted. The area ratio of the solder adhering to the deteriorated portion 6 is within 5%. Less than% is Δ, and 20% or more is ×.
In the AES analysis, in order to remove the adsorbed gas component on the surface of the Ni plating layer 4, after sputtering with argon gas for 1 minute, acceleration voltage: 5 kV, beam current: 5 nA, raster region: 20 μm, surface tilt angle with respect to the beam incident direction : Measured at 30 °. As indicated by A in FIG. 3, the solder joint planned portion 5 and the altered portion 6 were measured at three locations, and the average value was obtained.
These results are shown in Table 1.

  As is apparent from Table 1, in the examples, the Ni content of the altered portion 6 is 5 at% to 12 at%, and the Ni content of the solder joint planned portion 5 is 45 at% or more, both of which are solder wettability and solder flow. The prevention effect was also good. On the other hand, in Example 13, the solder wettability of the solder joint planned portion 5 is worse than that in Examples 1-12. This is presumably because the Ni content of the altered portion 6 is 4 at% or less, the Ni amount scattered by the laser irradiation is large, and it adheres to the solder joint planned portion 5. In Example 14, the solder adhered on the altered portion 6, which is considered to be because the alteration effect due to laser irradiation was not sufficient.

In addition, this invention is not limited to the said embodiment, A various change can be added in the range which does not deviate from the meaning of this invention.
In the embodiment, the altered portion is formed between a plurality of planned solder joint portions so as to cut off between the planned solder joint portions. However, the present invention is not limited to this configuration. The invention can be applied, and an altered portion may be provided so as to surround the periphery of the solder joint planned portion.

DESCRIPTION OF SYMBOLS 1 Circuit board for semiconductor devices 2 Ceramic substrate 3 Circuit layer 4 Ni plating layer 5 Solder joint planned part 6 Alteration part 11 Semiconductor element 12 Solder layer

Claims (3)

  A circuit board for a semiconductor device to which a semiconductor element is soldered, wherein a Ni plating layer is formed on the surface of the circuit layer, and a solder joint planned portion to which the semiconductor element is soldered to the Ni plating layer, A circuit board for a semiconductor device, wherein the altered portion by laser irradiation is arranged in a state adjacent to the surface direction.   2. The circuit board for a semiconductor device according to claim 1, wherein a plurality of the solder joint planned portions are formed, and the altered portion is formed so as to block between the solder joint planned portions.   The Ni content of the Ni plating layer measured by Auger electron spectroscopy under the conditions of acceleration voltage: 5 kV, beam current: 5 nA, raster region: 20 μm, and surface tilt angle with respect to the beam incident direction is 30 °. 3. The circuit board for a semiconductor device according to claim 1, wherein the Ni content is 45 at% or more, and the Ni content of the altered portion is 5 at% to 12 at%.

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