JP2014165242A - Semiconductor element mounting substrate and manufacturing method of the same - Google Patents
Semiconductor element mounting substrate and manufacturing method of the same Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 119
- 239000000758 substrate Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000007747 plating Methods 0.000 claims abstract description 121
- 238000005530 etching Methods 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims description 26
- 238000007789 sealing Methods 0.000 abstract description 39
- 239000011347 resin Substances 0.000 abstract description 38
- 229920005989 resin Polymers 0.000 abstract description 38
- 230000007547 defect Effects 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 16
- 230000000052 comparative effect Effects 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000004090 dissolution Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
本発明は、表面側にハーフエッチング加工を施した半導体素子搭載用基板を用いて、表面側に半導体素子を実装し樹脂封止した後、裏面側をエッチング加工して半導体素子搭載用基板の不要な部分を除去するようにして半導体パッケージを製造するのに用いられる半導体素子搭載用基板及びその製造方法に関する。 The present invention eliminates the need for a semiconductor element mounting substrate by mounting a semiconductor element on the front surface side using a semiconductor element mounting substrate that has been subjected to half-etching on the front surface side, sealing the resin, and then etching the back surface side. The present invention relates to a semiconductor element mounting substrate used for manufacturing a semiconductor package by removing a necessary portion and a method for manufacturing the same.
半導体パッケージは、多ピン化、小型化、薄化の要求から、半田ボールを使用したＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケージや半導体素子の下にアウターリードを配置したＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）等のさまざまなパッケージが出現している。 Semiconductor packages come in various types such as BGA (Ball Grid Array) packages using solder balls and CSP (Chip Size Package) in which outer leads are arranged under the semiconductor elements, in response to demands for multi-pin, miniaturization and thinning. A package has appeared.
その中でも、比較的安価で上記要求に対応できる方法として、金属材料であるリードフレームを利用したＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ−ｌｅａｄ）タイプのパッケージがある。 Among them, there is a QFN (Quad Flat Non-lead) type package using a lead frame that is a metal material as a method that can meet the above-mentioned requirements at a relatively low cost.
これは、金属材料を用いて、中央に形成されたパッドに半導体素子を搭載し、その周辺にエリアアレイ状に、表面側は半導体素子とワイヤで繋ぐワイヤボンディング部となり、その裏面側は外部接続部となる導体端子部を有する半導体パッケージである。この導体端子部の上下（表裏）面をワイヤボンディング部と外部接続端子部にそれぞれ使用することにより、多ピン化、小型化、薄化を実現している。 This uses a metal material to mount a semiconductor element on a pad formed in the center, in the form of an area array around it, the front side becomes a wire bonding part connecting the semiconductor element and the wire, and the back side is an external connection It is a semiconductor package which has a conductor terminal part used as a part. By using the upper and lower (front and back) surfaces of the conductor terminal portion for the wire bonding portion and the external connection terminal portion, respectively, a large number of pins, miniaturization, and thinning are realized.
そして特許文献１には、金属材料としてリードフレーム用の銅材に貴金属のめっきを施す工程と、裏面に耐エッチングレジスト膜を成形した後、表面のめっき層をエッチングマスクとして用いてハーフエッチング加工する工程と、上記リードフレーム材に所望の半導体素子を搭載し、半導体素子と金属めっき層をワイヤボンディングする工程と、樹脂封止する工程と、リードフレーム材の裏面に形成した耐エッチングレジストを除去し、貴金属めっき層をエッチングマスクとして使用して裏面をエッチング加工して外部接続部を独立させる工程を有する半導体パッケージの製造方法が示されている。
特許文献１に記載されているように、ハーフエッチング加工によって柱状形状に形成された半導体素子搭載用基板のワイヤボンディング部や半導体素子搭載部は、封止樹脂により被覆された後、エッチング加工を行い最終的に半導体パッケージとして形成される。しかし、前記ハーフエッチングにより形成される柱状形状部分が封止樹脂により被覆されるため、ワイヤボンディング部の反対面が外部接続部となる導体端子が封止樹脂から抜け落ちたり一部が剥がれたりする問題を抱えている。
As described in
そして特に導体端子であるワイヤボンディング部は、封止樹脂と接触する面積が小さいことから、前述した抜け落ちの問題が発生しやすく、金属板をハーフエッチング加工する際に柱状形状の側面に凹部を形成することで封止樹脂との密着性を向上させるようにしている。 In particular, the wire bonding part, which is a conductor terminal, has a small area in contact with the sealing resin, so the above-mentioned problem of dropout is likely to occur, and a recess is formed on the side surface of the columnar shape when half-etching a metal plate. By doing so, it is trying to improve adhesiveness with sealing resin.
しかし、エッチングの特性からコーナー部（角部）は直線部に比べて溶解速度が速くなり、同じ時間エッチング加工した場合はコーナー部がより多く溶解される。そのため、コーナー部の側面は、ボンディング用めっき直下の銅まで溶解が進み凹部が形成され難く直線的な形状に近づくとともに一部ボンディング用めっきの欠けが生じ、端子形状不具合を引き起こす。逆に、コーナー部の凹部形成を優先してエッチング加工を行うと端子の直線部の側面のエッチング量が不足し凹部が形成され難いことから、端子コーナー部と直線部の両方の側面に凹部を同時に形成することは困難である。特に、ハーフエッチング深さの5倍以上の長さとなる直線部および多角形端子の長辺／短辺＞1.33の長辺部においては、柱状形状の側面に凹部が形成され難い。 However, due to the characteristics of etching, the corner portion (corner portion) has a higher dissolution rate than the straight portion, and more corner portions are dissolved when etching is performed for the same time. For this reason, the side surface of the corner portion is melted up to the copper immediately below the bonding plating, and it is difficult to form a recess and approaches a linear shape. Conversely, if etching is performed with priority given to the formation of recesses in the corners, the amount of etching on the side surfaces of the straight portions of the terminals is insufficient and it is difficult to form recesses. It is difficult to form at the same time. In particular, in the straight portion having a length of 5 times or more of the half etching depth and the long side portion of the polygon terminal having a long side / short side> 1.33, it is difficult to form a recess on the side surface of the columnar shape.
したがって、平面形状が四角形状で１辺が０．５ｍｍ程度でコーナー半径０．１〜０．１５ｍｍ程度のワイヤボンディング部は、その直線部に比べてコーナー部がハーフエッチング加工での溶解速度が速くなるため、四角形状の一部が欠損する事態が生じ、柱状形状の加工側面に均一な凹部が形成されず上下方向に直線的な形状となってしまう。そのため、このことが封止樹脂との密着性が低下する原因となっていた。 Therefore, the wire bonding portion having a square shape with a square shape of about 0.5 mm on one side and a corner radius of about 0.1 to 0.15 mm has a faster dissolution rate in the half etching process than the straight portion. Therefore, a situation in which a part of the quadrangular shape is lost occurs, and a uniform concave portion is not formed on the processed side surface of the columnar shape, and a linear shape is formed in the vertical direction. Therefore, this has been a cause of a decrease in adhesion with the sealing resin.
また、導体端子が封止樹脂から抜け落ちることを防止するために側面に十分な深さの凹部が形成されるようにエッチングを行うと、場合によってはワイヤボンディング部のめっき直下の金属板である銅まで溶解され、めっきの一部がバリとなったり欠損したりする事態が生じることもあった。 In addition, if etching is performed so that a concave portion with a sufficient depth is formed on the side surface to prevent the conductor terminal from falling off the sealing resin, in some cases, copper which is a metal plate directly under the plating of the wire bonding portion In some cases, a part of the plating becomes burrs or is lost.
一方、ワイヤボンディング部が円形形状の場合は全体が同一曲率となっているので多角形状の場合と異なり一箇所が集中して溶解されることはないが、側面に十分な深さの凹部が形成されるようにエッチングを行うと、多角形状の場合と同様にワイヤボンディング部のめっき直下の金属板である銅まで溶解されてしまいめっきの一部がバリとなったり、欠損したりする事態が生じることがあった。 On the other hand, when the wire bonding part has a circular shape, the entire surface has the same curvature, so unlike the polygonal shape, one point is not concentrated and melted, but a recess with a sufficient depth is formed on the side surface. When etching is performed as described above, copper, which is a metal plate immediately below the plating of the wire bonding portion, is dissolved as in the polygonal shape, and a part of the plating becomes burrs or is lost. There was a thing.
また、半導体素子搭載部はワイヤボンディング部と比べればその平面形状は大きいが、パッド部は四角形でサイドの直線部分が長いため、金属板をハーフエッチング加工するとこの部分は側面に凹部が形成されないで垂直な平面となる。したがって、封止樹脂との接着面積はワイヤボンディング部と比べれば大きいが、垂直な平面であるため結果としてそれほど大きな密着力を得ることはできていない。 In addition, the planar shape of the semiconductor element mounting part is larger than that of the wire bonding part, but the pad part is square and the side straight part is long. Therefore, when the metal plate is half-etched, this part does not have a concave part on the side. It becomes a vertical plane. Therefore, although the bonding area with the sealing resin is larger than that of the wire bonding portion, since it is a vertical plane, as a result, a great adhesion force cannot be obtained.
そこで本発明は、かかる事情に鑑みてなされたものであり、ワイヤボンディング部の一部が欠損する事態や、封止樹脂とワイヤボンディング部や半導体素子搭載部の密着性が低下することを防止した半導体素子搭載用基板を提供することを目的とする。 Therefore, the present invention has been made in view of such circumstances, and has prevented a situation in which a part of the wire bonding portion is lost and a decrease in the adhesion between the sealing resin and the wire bonding portion or the semiconductor element mounting portion. An object is to provide a substrate for mounting a semiconductor element.
上記目的を達成するために、本発明の半導体素子搭載用基板は、表面側に半導体素子の実装とワイヤボンディングをして前記表面側を樹脂封止した後、裏面側からのエッチング加工によって半導体素子搭載用基板の不要な部分を除去するようにして半導体パッケージを製造するのに用いられる金属板製の半導体素子搭載用基板であって、前記金属板の前記表面側に、ハーフエッチング加工により上面の平面形状が円形形状としたワイヤボンディング部となる柱状形状が形成され、前記柱状形状の側面は凹部を有するとともに、前記柱状形状の上面には前記円形形状より小さなエリアにワイヤボンディング用のめっきが形成され、また同じ面に、ハーフエッチング加工により上面の平面形状が略四角形形状で各辺には部分的に円弧となる形状を有して半導体素子搭載部となる略角柱状形状が形成され、前記略角柱状形状の側面は部分的に凹部を有するとともに、前記略角柱状形状の上面には前記略四角形形状より小さなエリアにめっきが形成されていることを特徴とする。 In order to achieve the above object, a semiconductor element mounting substrate according to the present invention includes mounting a semiconductor element on the front surface side and wire bonding, sealing the front surface side with resin, and then etching the semiconductor element from the back surface side. A semiconductor element mounting substrate made of a metal plate used for manufacturing a semiconductor package by removing an unnecessary portion of the mounting substrate, wherein the upper surface of the metal plate is half-etched on the surface side. A columnar shape that is a wire bonding portion having a circular planar shape is formed, the side surface of the columnar shape has a recess, and a plating for wire bonding is formed on an upper surface of the columnar shape in an area smaller than the circular shape. In addition, on the same surface, the shape of the top surface is a substantially square shape by half-etching, and each side has a circular arc shape. Thus, a substantially prismatic shape to be a semiconductor element mounting portion is formed, and a side surface of the substantially prismatic shape has a concave portion partially, and an upper surface of the substantially prismatic shape is plated in an area smaller than the substantially rectangular shape. Is formed.
また、本発明においては、前記金属板の前記裏面側には、半導体パッケージの外部接続端子となる部分に、前記ワイヤボンディング用と同じ構成のめっきが矩形形状に形成されていることが好ましい。 In the present invention, it is preferable that a plating having the same configuration as that for the wire bonding is formed in a rectangular shape on a portion to be an external connection terminal of the semiconductor package on the back surface side of the metal plate.
また、本発明においては、前記ワイヤボンディング用のめっきの外周には、前記柱状形状の上面が露出していることが好ましい。 In the present invention, it is preferable that an upper surface of the columnar shape is exposed on an outer periphery of the wire bonding plating.
また、本発明においては、前記ワイヤボンディング用のめっきは円形形状であり、前記柱状形状の上面の円形形状の半径は、前記ワイヤボンディング部の半径より１０μｍ以上大きいことが好ましい。 In the present invention, the plating for wire bonding has a circular shape, and the radius of the circular shape of the upper surface of the columnar shape is preferably 10 μm or more larger than the radius of the wire bonding portion.
あるいは、本発明の半導体素子搭載用基板は、表面側に半導体素子の実装とワイヤボンディングをして前記表面側を樹脂封止した後、裏面側からのエッチング加工によって半導体素子搭載用基板の不要な部分を除去するようにして半導体パッケージを製造するのに用いられる金属板製の半導体素子搭載用基板であって、前記金属板の前記表面側に、ハーフエッチング加工により上面の平面形状をコーナーの半径がハーフエッチング深さの２倍以上の大きさを有する四角形以上の多角形形状としたワイヤボンディング部となる柱状形状が形成され、前記柱状形状の側面は凹部を有するとともに、前記柱状形状の上面には前記多角形形状より小さなエリアにワイヤボンディング用のめっきが形成され、また同じ面に、ハーフエッチング加工により上面の平面形状が略四角形形状で各辺には部分的に円弧となる形状を有して半導体素子搭載部となる略角柱状形状が形成され、前記略角柱状形状の側面は部分的に凹部を有するとともに、前記略角柱状形状のパッド部上面には前記略四角形形状より小さなエリアにめっきが形成されていることを特徴とする。 Alternatively, the semiconductor element mounting substrate according to the present invention eliminates the need for the semiconductor element mounting substrate by etching from the back side after mounting the semiconductor element on the front side and wire bonding and sealing the surface side with resin. A substrate for mounting a semiconductor element made of a metal plate used for manufacturing a semiconductor package by removing a portion thereof, wherein a planar shape of an upper surface is formed on the surface side of the metal plate by a half-etching process, and a radius of a corner Is formed into a square or more polygonal wire bonding portion having a size more than twice the half-etching depth, the side surface of the columnar shape has a recess, and the top surface of the columnar shape is In the area smaller than the polygonal shape, the wire bonding plating is formed, and on the same surface, half-etching is performed. The planar shape of the surface is a substantially quadrangular shape, and each side has a partially arcuate shape to form a substantially prismatic shape serving as a semiconductor element mounting portion, and the side surface of the substantially prismatic shape is partially recessed And a plating is formed on an upper surface of the substantially prismatic pad portion in an area smaller than the substantially rectangular shape.
また、本発明においては、前記金属板の反対側である裏面側には、半導体パッケージの外部接続端子となる部分に、前記ワイヤボンディング用と同じ構成のめっきが矩形形状に形成されていることが好ましい。 Further, in the present invention, on the back side opposite to the metal plate, a plating having the same configuration as that for the wire bonding is formed in a rectangular shape on a portion to be an external connection terminal of the semiconductor package. preferable.
また、本発明においては、前記ワイヤボンディング用のめっきの外周には、前記柱状形状の上面が露出していることが好ましい。 In the present invention, it is preferable that an upper surface of the columnar shape is exposed on an outer periphery of the wire bonding plating.
また、本発明においては、前記ワイヤボンディング用のめっきは円形形状若しくは前記柱状形状と相似形状であり、めっきが円形状の場合は前記柱状形状の上面の多角形状に対して内接する円を想定すると、その円の半径は前記ワイヤボンディング用のめっきの半径より１０μｍ以上大きく、めっきが円形状以外の場合はボンディング用めっきの外周に対し１０μｍ以上の大きさで前記柱状形状の上面が露出していることが好ましい。 In the present invention, the plating for wire bonding is a circular shape or a shape similar to the columnar shape. When the plating is circular, a circle inscribed with respect to the polygonal shape of the upper surface of the columnar shape is assumed. The radius of the circle is larger than the radius of the wire bonding plating by 10 μm or more. When the plating is not circular, the upper surface of the columnar shape is exposed with a size of 10 μm or more with respect to the outer periphery of the bonding plating. It is preferable.
一方、本発明の半導体素子搭載用基板の製造方法は、表面側に半導体素子の実装とワイヤボンディングをして前記表面側を樹脂封止した後、裏面側からのエッチング加工によって半導体素子搭載用基板の不要な部分を除去するようにして半導体パッケージを製造するのに用いられる金属板製の半導体素子搭載用基板の製造方法であって、前記金属板の前記表面側にワイヤボンディング用及び半導体素子搭載用のめっきを形成する工程と、前記金属板の前記表面側に形成したワイヤボンディング用及び半導体素子搭載用のめっきより広い範囲を覆うレジストマスクを形成する工程と、前記表面側の前記レジストマスクから露出している前記金属板をハーフエッチング加工し、側面に凹部が形成されたワイヤボンディング用の柱状形状と、側面に部分的に凹部が形成された半導体素子搭載用の略角柱状形状のパッド部とを形成する工程を含むことを特徴とする。 On the other hand, in the method for manufacturing a semiconductor element mounting substrate of the present invention, after mounting the semiconductor element on the front surface side and wire bonding and sealing the front surface side with resin, the semiconductor element mounting substrate is etched by the back surface side. A method of manufacturing a substrate for mounting a semiconductor element made of a metal plate used for manufacturing a semiconductor package by removing unnecessary portions of the metal plate, for wire bonding and mounting the semiconductor element on the surface side of the metal plate Forming a resist mask covering a wider area than the plating for wire bonding and semiconductor element mounting formed on the surface side of the metal plate, and the resist mask on the surface side The exposed metal plate is half-etched and has a columnar shape for wire bonding in which a concave portion is formed on the side surface, and a side surface. Min to characterized in that it comprises a step of forming a pad portion of a substantially prismatic shape of the semiconductor element mounting in which a recess is formed.
また、本発明においては、前記レジストマスクは、ワイヤボンディング用のめっき部分では上面の平面形状が円形形状であり、半導体素子搭載用のめっき部分では上面の平面形状が略四角形形状で各辺は部分的に円弧となる形状を有していることが好ましい。 In the present invention, the resist mask has a circular shape on the upper surface in the plated portion for wire bonding, and the planar shape on the upper surface in the plated portion for mounting the semiconductor element has a substantially rectangular shape and each side is a partial shape. It is preferable to have a circular arc shape.
また、本発明においては、前記レジストマスクは、ワイヤボンディング用のめっき部分では上面の平面形状が四角形以上の多角形状であってコーナーの半径が前記ハーフエッチング加工によるエッチング深さの２倍以上の大きさであり、半導体素子搭載用のパッド部のめっき部分では上面の平面形状が略四角形形状で各辺は部分的に円弧となる形状を有していることが好ましい。 Further, in the present invention, the resist mask has a polygonal shape having a square upper surface in the plated portion for wire bonding, and has a corner radius larger than twice the etching depth by the half etching process. In addition, in the plated portion of the pad portion for mounting the semiconductor element, it is preferable that the planar shape of the upper surface has a substantially rectangular shape and each side has a shape that is partially circular.
ハーフエッチング加工を行うワイヤボンディング部となる柱状形状の上面の平面形状を円形形状にすることで、柱状形状を形成するハーフエッチング加工の条件が同じ条件となり、全周囲が同じ凹部を有する側面となる柱状形状となり、封止樹脂との密着性が低下することを防止できる。また、ワイヤボンディング用のめっきより上面の円形形状を大きくすることによりワイヤボンディング用のめっきの一部がバリとなったり欠損したりする事態を防止できる。 By making the planar shape of the upper surface of the columnar shape to be a wire bonding part to be half-etched into a circular shape, the conditions of the half-etching process for forming the columnar shape are the same conditions, and the entire periphery becomes a side surface having the same recess. It becomes columnar shape and it can prevent that adhesiveness with sealing resin falls. Moreover, by making the circular shape of the upper surface larger than the wire bonding plating, it is possible to prevent a part of the wire bonding plating from becoming burrs or missing.
その上、ハーフエッチング加工を行う半導体素子搭載部となる略角柱状形状の上面の平面形状は部分的に円弧を有する略四角形形状にすることで、略角柱状形状を形成するハーフエッチング加工時に円弧部分が凹部を有する側面となり側面が直線的な平面とならないため、封止樹脂との密着性が低下することを防止できる。また、略角柱状形状のパッド部上面となる略四角形形状よりめっきを小さくしたのでめっきの一部がバリとなったり欠損したりする事態を防止できる。 In addition, the planar shape of the upper surface of the substantially prismatic shape that becomes the semiconductor element mounting portion to be half-etched is formed into a substantially quadrangular shape having a partial arc, so that an arc is formed during the half-etching process that forms the substantially prismatic shape. Since the portion becomes a side surface having a recess and the side surface does not become a linear plane, it is possible to prevent the adhesiveness with the sealing resin from being lowered. Further, since the plating is made smaller than the substantially rectangular shape that is the upper surface of the substantially prismatic pad portion, it is possible to prevent a situation where a part of the plating becomes burrs or is lost.
また、ワイヤボンディング部となる柱状形状の上面の平面形状を、コーナーの半径がハーフエッチング深さの２倍以上の大きさを有する四角形形状とすることで、コーナー部のハーフエッチング加工溶解速度を直線部に近づけられ、四角形形状の一部が欠損する事態を防止して、柱状形状の側面に凹部を有する半導体素子搭載用基板を得ることが可能となる。また、ワイヤボンディング用のめっきより上面の四角形形状を大きくすることによりワイヤボンディング用のめっきの一部がバリとなったり欠損したりする事態を防止できる。 In addition, the planar shape of the upper surface of the columnar shape that becomes the wire bonding portion is a quadrangular shape in which the corner radius is twice or more the half etching depth, so that the half etching processing dissolution rate of the corner portion is linear. It is possible to obtain a semiconductor element mounting substrate having a concave portion on the side surface of the columnar shape by preventing a situation where a part of the quadrangular shape is lost. Further, by making the upper surface square shape larger than the wire bonding plating, it is possible to prevent a part of the wire bonding plating from becoming burrs or missing.
更に、平面形状において、コーナー部が直角である四角形形状に対し、五角形以上の多角形形状にすることでコーナーを形成する角度が大きくなり角部と直線部とのハーフエッチング加工溶解速度差を小さくできるので、全周囲が同じ凹部を有した側面の柱状形状となり、柱状形状の側面に凹部を有する半導体素子搭載用基板を得ることが可能となる。 Furthermore, in the planar shape, the angle at which the corner is formed becomes larger by making the polygon shape more than a pentagon with respect to the rectangular shape with a right corner, and the difference in the half etching processing dissolution rate between the corner and the straight portion is reduced. Therefore, it becomes possible to obtain a semiconductor element mounting substrate having a columnar shape with side surfaces having the same recesses on the entire periphery and having recesses on the side surfaces of the columnar shape.
以下、本発明の半導体素子搭載用基板及びその製造方法の一例を図面を参照して説明する。
本発明の半導体素子搭載用基板は、厚さ０．１ｍｍ〜０．１５ｍｍの銅合金を金属板として使用する。
Hereinafter, an example of a semiconductor element mounting substrate and a method for manufacturing the same according to the present invention will be described with reference to the drawings.
The substrate for mounting a semiconductor element of the present invention uses a copper alloy having a thickness of 0.1 mm to 0.15 mm as a metal plate.
まず、金属板表面の異物や不純物を取り除く前処理を行い、両面にレジスト層を形成する。通常は市販されているドライフィルムレジストをラミネーターを用いて貼着する。 First, a pretreatment is performed to remove foreign substances and impurities on the surface of the metal plate, and a resist layer is formed on both sides. Usually, a commercially available dry film resist is attached using a laminator.
そして、表面側（半導体素子搭載面側）と裏面側（外部接続部側）に必要なめっきを形成するためのレジストマスクを形成する。このレジストマスクの形成は、一般的な方法であり、所定のパターンが形成された露光用マスクを用いてレジスト層を露光し、現像することで両面にレジストマスクを形成する。次に形成したレジストマスクの開口部から露出している金属板に、一般的なめっき前処理を行って必要なめっきを形成し、レジストマスクを剥離する。 Then, a resist mask for forming necessary plating on the front surface side (semiconductor element mounting surface side) and the back surface side (external connection portion side) is formed. The formation of the resist mask is a general method, and the resist layer is exposed and developed using an exposure mask on which a predetermined pattern is formed, thereby forming a resist mask on both sides. Next, general plating pretreatment is performed on the metal plate exposed from the opening of the formed resist mask to form necessary plating, and the resist mask is peeled off.
次に、めっきが形成された金属板の両面に再びレジスト層を形成し、表面側は、必要な半導体素子搭載用基板のパターンであって形成しためっきより広い範囲を覆うレジストマスクを形成し、裏面側は全面を覆うレジストマスクを形成する。 Next, a resist layer is again formed on both surfaces of the metal plate on which the plating is formed, and a resist mask is formed on the surface side to cover a wider area than the formed plating, which is a pattern of a necessary semiconductor element mounting substrate, A resist mask covering the entire surface is formed on the back side.
この表面側のレジストマスクは、上記したように形成しためっきより広い範囲を覆うようにするが、具体的には、柱状形状を形成してワイヤボンディング部となる部分のレジストマスクは、上面の平面形状が、円形または楕円形、あるいはコーナーの半径がハーフエッチング深さの２倍以上の大きさを有する四角形以上の多角形状のワイヤボンディング部となるようにレジストマスクを形成する。 The resist mask on the surface side covers a wider area than the plating formed as described above. Specifically, the resist mask in a portion that forms a columnar shape and becomes a wire bonding portion is a flat surface on the upper surface. The resist mask is formed so that the wire bonding portion has a circular or elliptical shape, or a rectangular or more polygonal shape in which the corner radius is twice or more the half etching depth.
また、半導体素子搭載部となる略角柱状形状を形成してパッド部となる部分のレジストマスクは、上面の平面形状が部分的に円弧を有する略四角形形状のパッド部となるようにレジストマスクを形成する In addition, the resist mask in the portion that forms the substantially prismatic shape to be the semiconductor element mounting portion and becomes the pad portion is the resist mask so that the planar shape of the upper surface is a substantially quadrangular pad portion having a partial arc. Form
このワイヤボンディング部となる部分のレジストマスクとパッド部となる部分のレジストマスクは、ハーフエッチング加工によって金属板を溶解処理した際に先に形成したワイヤボンディング部やパッド部のめっきより金属板の表面が広く残るように設定する。そうすることで、めっきの一部がバリとなったり欠損したりして後工程で不具合を生じることを防止することができる。 The resist mask of the part that becomes the wire bonding part and the resist mask of the part that becomes the pad part are formed on the surface of the metal plate by plating the wire bonding part and the pad part that are formed first when the metal plate is dissolved by half etching. Set to remain wide. By doing so, it can prevent that a part of plating becomes a burr | flash or lose | deletes and produces a malfunction in a post process.
次に金属板をハーフエッチング加工するが、金属板の厚さの半分程度から７０％程度の深さまでハーフエッチングを行う。このハーフエッチングの程度は、後工程で行われる裏面側からのエッチングを考慮して任意に選択可能である。 Next, the metal plate is half-etched. Half-etching is performed from about half the thickness of the metal plate to a depth of about 70%. The degree of this half-etching can be arbitrarily selected in consideration of the etching from the back side that is performed in a later step.
表面側からハーフエッチング加工をすることにより、図１（１）に示すように金属板１０がエッチングされることによりワイヤボンディング部１となる箇所は、側面に凹部４を有する柱状形状５が形成され、柱状形状５の上面は上面の平面形状よりも小さなエリアにワイヤボンディング用のめっき１’が形成されたワイヤボンディング部１となり、下面は外部接続用のめっきが形成された外部接続部２となる。
By performing half-etching from the front surface side, a
また、半導体素子搭載部３となる箇所にも部分的に側面に凹部６を有する略角柱状形状７が形成され、略角柱状形状７の上面は上面の平面形状よりも小さなエリアに半導体素子搭載用のめっき３’が形成された略四角形形状のパッド部８となる。
In addition, a substantially
このハーフエッチング加工により柱状形状５が形成され、また柱状形状５の側面には凹部４が形成され、封止樹脂との密着性を確保される。さらにこのハーフエッチング加工により略角柱状形状７も形成され、また略角柱状形状７の側面には円弧部分９に凹部６が形成され、封止樹脂との密着性が確保される。そして、レジストマスクを剥離することにより、本発明の半導体素子搭載用基板となる。
The
そして、図１（２）に示すように、半導体素子２０を搭載し、ワイヤ２１でワイヤボンディングを行い、封止樹脂３０で封止した後、裏面側からエッチング加工を行って導体端子１１となる柱状形状５とパッド部８となる略角柱状形状７を独立させて、個々の半導体パッケージに切断して半導体パッケージが得られる。
Then, as shown in FIG. 1B, the
図１（３）は、上記工程により製作された本発明の半導体素子搭載用基板の平面図の一部を示したものであり、図示したようにワイヤボンディング部１はめっき１’部分よりも柱状形状５上面の平面部の方が一回り大きくなっている。また、略角柱状形状７の半導体素子搭載部３も、めっき３’部分よりもパッド部８上面となる部分の方が一回り大きくなっている。
FIG. 1 (3) shows a part of a plan view of the semiconductor element mounting substrate of the present invention manufactured by the above process. As shown, the
なお、ワイヤボンディング部１の柱状形状５の上面の平面形状とめっき１’の形状は図１（３）に示す形状に限るものではなく、例えば図２に示すような形状であってもよい。（１）は平面形状とめっき双方とも楕円形状のもの、（２）は平面形状とめっき双方とも四角形状のもの、（３）は平面形状が五角形状でめっきが円形形状のもの、（４）は平面形状が六角形状でめっきが円形形状の例を示したものである。
Note that the planar shape of the upper surface of the
また、半導体素子搭載部３の略角柱状形状５のパッド部８上面の略四角形形状は図１（３）に示す形状に限るものではなく、例えば図３に示すような形状であってもよい。（１）はサイドの直線部分に長さが半円未満の円弧を連続させて設けたもの、（２）はサイドの直線部分に長さが半円未満の円弧を間隔をあけて設けたもの、（３）はサイドの直線部分及びコーナー部分に長さが半円以上の円弧を連続させて設けたもの、（４）はサイドの直線部分及びコーナー部分に長さが半円以上の円弧を間隔をあけて設けたものである。
Further, the substantially square shape of the upper surface of the
（実施例１）
金属板として、厚さ０．１２５ｍｍの銅系合金材（古河電気工業株式会社製ＥＦＴＥＣ６４−Ｔ）を用いて、両面にドライフィルムレジスト（旭化成イーマテリアルズ株式会社製ＡＱ−２５５８）をラミネートした。
Example 1
As a metal plate, a dry film resist (AQ-2558 manufactured by Asahi Kasei E-Materials Co., Ltd.) was laminated on both sides using a 0.125 mm thick copper-based alloy material (EFTEC64-T manufactured by Furukawa Electric Co., Ltd.).
そして、表面側のワイヤボンディング部に形成するめっきエリアを直径０．５ｍｍの円形、半導体素子搭載部に形成するめっきエリアは角部に半径０．２ｍｍとなる４ｍｍ□の四角形状、そして裏面側の外部接続部に形成するめっきエリアは、従来と同じ角部が半径０．１ｍｍとなる０．５ｍｍ□の四角形状、パッド部の部位にも角部が半径０．１ｍｍとなる４ｍｍ□の四角形状が開口されるレジストマスクを形成するようなパターンで両面に露光を行い、現像してめっきが必要な部分が開口されたレジストマスクを形成した。 The plating area formed on the wire bonding portion on the front side is a circle having a diameter of 0.5 mm, the plating area formed on the semiconductor element mounting portion is a 4 mm square shape having a radius of 0.2 mm at the corner, and the back surface side The plating area to be formed in the external connection part is a 0.5 mm square shape with a radius of 0.1 mm as in the conventional case, and a 4 mm square shape with a corner radius of 0.1 mm at the pad portion. The resist mask was opened on both sides with a pattern that would form a resist mask with an opening, and developed to form a resist mask having openings where plating is required.
次に、形成したレジストマスクの開口部から露出している金属板に、酸化膜等を除去するめっき前処理を行い、Ｎｉを１μｍ、Ｐｄを０．０７μｍ、Ａｕを０．００３μｍの厚さで順次めっきを施し、レジストマスクを剥離した。 Next, the metal plate exposed from the opening of the formed resist mask is subjected to a pre-plating process for removing an oxide film and the like, with a thickness of 1 μm for Ni, 0.07 μm for Pd, and 0.003 μm for Au. Sequential plating was performed, and the resist mask was peeled off.
次に、めっきが形成された金属板の両面に、前述と同じドライフィルムレジストをラミネートし、裏面側は全面を覆うレジストマスクとした。また、表面側は、形成しためっきより半径で５０μｍ大きく覆うようにレジストマスクを形成した。また、半導体素子搭載部については図３（１）に示すようにサイドの直線部分に半径０．７ｍｍの円弧が連続して形成されるようにレジストマスクを形成した。 Next, the same dry film resist as described above was laminated on both surfaces of the metal plate on which plating was formed, and the back side was used as a resist mask covering the entire surface. Further, a resist mask was formed on the surface side so as to cover the formed plating by 50 μm larger in radius. As for the semiconductor element mounting portion, a resist mask was formed so that an arc having a radius of 0.7 mm was continuously formed in the straight line portion of the side as shown in FIG.
次に、液温４０℃のエッチング液を用いて、スプレー圧０．１〜０．２ＭＰａで２分間エッチング加工を行い、表面側から約８０μｍの深さまでハーフエッチング加工を行い、ワイヤボンディング部となる柱状形状と半導体素子搭載部となる略角柱状形状を形成した。 Next, using an etching solution having a liquid temperature of 40 ° C., etching is performed for 2 minutes at a spray pressure of 0.1 to 0.2 MPa, and half-etching is performed from the surface side to a depth of about 80 μm to form a wire bonding portion. A columnar shape and a substantially prismatic shape serving as a semiconductor element mounting portion were formed.
得られたワイヤボンディング部となる柱状形状の側面に形成された凹部の深さは平均１８μｍであった（図５（１）参照）。また、半導体素子搭載部となる略角柱状形状の円弧部分の側面にも平均１２μｍの凹部が形成された。少なくとも１０μｍ以上の凹部が柱状形状と略角柱状形状の側面に形成されていることから、樹脂封止後の密着強度は十分に確保されていると判断した。また、めっきの一部がバリとなったり欠損したりした箇所はなかった。 The average depth of the recesses formed on the side surfaces of the columnar shape to be the wire bonding portion was 18 μm (see FIG. 5 (1)). In addition, concave portions having an average of 12 μm were also formed on the side surface of the substantially prismatic arc portion serving as the semiconductor element mounting portion. Since the recesses of at least 10 μm or more were formed on the side surfaces of the columnar shape and the substantially prismatic shape, it was determined that the adhesion strength after resin sealing was sufficiently ensured. Moreover, there was no location where a part of the plating became burrs or was missing.
その後、両面のレジストマスクを剥離することで本発明の半導体素子搭載用基板が得られた。 Then, the semiconductor element mounting substrate of the present invention was obtained by peeling off the resist masks on both sides.
この半導体素子搭載用基板に、銀ペーストを用いて半導体素子を搭載し、直径２０μｍのボンディングワイヤで半導体素子のバンプとワイヤボンディング部を接続した。その後エポキシ系の封止樹脂を用いて樹脂封止した後、アルカリ性の銅エッチング液で裏面側に形成しためっき層をエッチングマスクとしてエッチング処理した。 A semiconductor element was mounted on the semiconductor element mounting substrate using a silver paste, and the bump of the semiconductor element and the wire bonding portion were connected with a bonding wire having a diameter of 20 μm. Then, after sealing with an epoxy-based sealing resin, an etching process was performed using the plating layer formed on the back side with an alkaline copper etching solution as an etching mask.
その後、ダイシング工程にて個々のパッケージサイズに裁断し、得られた半導体パッケージのパッド剥がれ及び導体端子の抜け落ちを確認したところ不良の発生は無かった。 Then, it cut | judged to the individual package size at the dicing process, and there was no generation | occurrence | production of a defect, when the peeling of the pad of the obtained semiconductor package and the removal of the conductor terminal were confirmed.
（実施例２）
実施例１と同様に、両面にめっきが形成され、両面にレジスト層を形成した材料を用いて、裏面側は全面を覆うレジストマスクとし、表面側には、ワイヤボンディング部として形成した直径０．５ｍｍの円形形状のめっきと同じ中心の直径が０．５３ｍｍの円が内接する四角形で０．２ｍｍのコーナー半径となるレジストマスクを形成した。同様に０．６ｍｍの円が内接する五角形と六角形で０．２ｍｍのコーナー半径となるレジストマスクを形成したものを準備した。半導体素子搭載部については実施例１と同じ形状のレジストマスクを形成した。
(Example 2)
Similar to Example 1, using a material in which plating is formed on both surfaces and a resist layer is formed on both surfaces, the back side is a resist mask covering the entire surface, and the surface side is formed with a diameter of 0. A resist mask having a corner radius of 0.2 mm and a quadrangle inscribed by a circle having a center diameter of 0.53 mm and the same center as that of the 5 mm circular plating was formed. Similarly, a pentagon and a hexagon in which a circle of 0.6 mm is inscribed and a resist mask having a corner radius of 0.2 mm were prepared. For the semiconductor element mounting portion, a resist mask having the same shape as in Example 1 was formed.
これらを実施例１と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さは、全て平均１５〜１８μｍであった。少なくとも１０μｍ以上の凹部が柱状形状と略角柱状形状の側面に形成されていることから、樹脂封止後の密着強度は十分に確保されていると判断した。また、めっきの一部がバリとなったり欠損したりした箇所はなかった。 These were half-etched from the surface side to a depth of about 80 μm as in Example 1 to form a columnar shape and a substantially prismatic shape. The depths of the recesses formed on the side surfaces of the obtained columnar shape were all 15 to 18 μm on average. Since the recesses of at least 10 μm or more were formed on the side surfaces of the columnar shape and the substantially prismatic shape, it was determined that the adhesion strength after resin sealing was sufficiently ensured. Moreover, there was no location where a part of the plating became burrs or was missing.
（実施例３）
実施例１と同様に、両面にめっきが形成され、両面にレジスト層を形成した材料を用いて、裏面側は全面を覆うレジストマスクとし、表面側には実施例１と同様に形成しためっきより半径で５０μｍ大きく覆うようにレジストマスクを形成した。なお、半導体素子搭載部については図３（２）に示すようにサイドの直線部分に半径０．７ｍｍの円弧が間隔をおいて形成されるようにレジストマスクを形成したものと、図３（３）に示すようにサイドの直線部分及びコーナー部分に半径０．３ｍｍの円弧が連続して形成されるようにレジストマスクを形成したものと、図３（４）に示すようにサイドの直線部分及びコーナー部分に半径０．３ｍｍの円弧が間隔をおいて形成されるようにレジストマスクを形成したものとを準備した。
(Example 3)
As in Example 1, using a material in which plating is formed on both sides and a resist layer is formed on both sides, the back side is a resist mask that covers the entire surface, and the surface side is the same as in Example 1 A resist mask was formed so as to cover a large radius of 50 μm. As for the semiconductor element mounting portion, as shown in FIG. 3 (2), a resist mask is formed so that arcs with a radius of 0.7 mm are formed at intervals on the side straight portions, and FIG. 3), a resist mask is formed so that arcs with a radius of 0.3 mm are continuously formed at the side straight portions and corner portions, and the side straight portions and the corner portions as shown in FIG. A resist mask was prepared so that arcs with a radius of 0.3 mm were formed at corners at intervals.
これらを実施例１と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた略角柱状形状の側面の円弧部分に形成された凹部の深さは、全て平均１２〜１５μｍであった。少なくとも１０μｍ以上の凹部が柱状形状と略角柱状形状の側面に形成されていることから、樹脂封止後の密着強度は十分に確保されていると判断した。また、めっきの一部がバリとなったり欠損したりした箇所はなかった。 These were half-etched from the surface side to a depth of about 80 μm as in Example 1 to form a columnar shape and a substantially prismatic shape. The average depths of the recesses formed in the arc portions of the side surfaces of the obtained substantially prismatic shape were all 12-15 μm on average. Since the recesses of at least 10 μm or more were formed on the side surfaces of the columnar shape and the substantially prismatic shape, it was determined that the adhesion strength after resin sealing was sufficiently ensured. Moreover, there was no location where a part of the plating became burrs or was missing.
（実施例４）
両面に実施例１と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側は形成しためっきより半径で１０μｍ大きく覆うようにレジストマスクを形成した以外は実施例１と同様にした。
Example 4
A material in which the same plating as in Example 1 was formed on both surfaces and a resist layer was formed on both surfaces was used. Example 1 was the same as Example 1 except that the back side was a resist mask covering the entire surface and the front side was formed so as to cover 10 μm larger in radius than the formed plating.
これを実施例１と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さは、平均１５〜１８μｍであった。少なくとも１０μｍ以上の凹部が柱状形状と略角柱状形状の側面に形成されていることから、樹脂封止後の密着強度は十分に確保されていると判断した。また、実施例１と同様にめっきの一部がバリとなったり欠損したりした箇所はなかった。 This was half-etched from the surface side to a depth of about 80 μm as in Example 1 to form a columnar shape and a substantially prismatic shape. The depth of the recesses formed on the side surfaces of the obtained columnar shape was 15 to 18 μm on average. Since the recesses of at least 10 μm or more were formed on the side surfaces of the columnar shape and the substantially prismatic shape, it was determined that the adhesion strength after resin sealing was sufficiently ensured. Further, as in Example 1, there was no spot where a part of the plating became burrs or was missing.
（実施例５）
両面に実施例２と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側はワイヤボンディング部として形成した直径０．５ｍｍの円形形状のめっきと同じ中心の直径が０．５２ｍｍの円が内接する四角形で０．２ｍｍのコーナー半径となるレジストマスクを形成した以外は実施例２と同様にした。
(Example 5)
A material in which the same plating as in Example 2 was formed on both surfaces and a resist layer was formed on both surfaces was used. The back side is a resist mask that covers the entire surface, and the front side is the same square as the 0.5 mm diameter circular plating formed as a wire bonding part. Example 2 was performed except that a resist mask was formed.
これを実施例２と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さは、平均１５〜１８μｍであった。少なくとも１０μｍ以上の凹部が柱状形状と略角柱状形状の側面に形成されていることから、樹脂封止後の密着強度は十分に確保されていると判断した。また、実施例２と同様にめっきの一部がバリとなったり欠損したりした箇所はなかった。 This was half-etched from the surface side to a depth of about 80 μm as in Example 2 to form a columnar shape and a substantially prismatic shape. The depth of the recesses formed on the side surfaces of the obtained columnar shape was 15 to 18 μm on average. Since the recesses of at least 10 μm or more were formed on the side surfaces of the columnar shape and the substantially prismatic shape, it was determined that the adhesion strength after resin sealing was sufficiently ensured. Further, as in Example 2, there was no spot where a part of the plating became burrs or was missing.
（実施例６）
両面に実施例２と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側はワイヤボンディング部として形成した直径０．５ｍｍの円形形状のめっきと同じ中心の直径が０．５３ｍｍの円が内接する四角形で０．１６ｍｍのコーナー半径となるレジストマスクを形成した以外は実施例２と同様にした。
(Example 6)
A material in which the same plating as in Example 2 was formed on both surfaces and a resist layer was formed on both surfaces was used. The back side is a resist mask that covers the entire surface, and the front side is the same square as the 0.5 mm diameter circular plating formed as a wire bonding part. Example 2 was performed except that a resist mask was formed.
これを実施例２と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さは、平均１５〜１８μｍであった。少なくとも１０μｍ以上の凹部が柱状形状と略角柱状形状の側面に形成されていることから、樹脂封止後の密着強度は十分に確保されていると判断した。また、実施例２と同様にめっきの一部がバリとなったり欠損したりした箇所はなかった。 This was half-etched from the surface side to a depth of about 80 μm as in Example 2 to form a columnar shape and a substantially prismatic shape. The depth of the recesses formed on the side surfaces of the obtained columnar shape was 15 to 18 μm on average. Since the recesses of at least 10 μm or more were formed on the side surfaces of the columnar shape and the substantially prismatic shape, it was determined that the adhesion strength after resin sealing was sufficiently ensured. Further, as in Example 2, there was no spot where a part of the plating became burrs or was missing.
（実施例７）
両面に実施例２と同じめっきが形成され、両面に実施例２と同じレジストマスクを形成した材料を用いた。
(Example 7)
A material in which the same plating as in Example 2 was formed on both surfaces and the same resist mask as in Example 2 was formed on both surfaces was used.
これを実施例２と同じ方法により表面側から約１００μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さは、平均１７〜２０μｍであった。少なくとも１０μｍ以上の凹部が柱状形状と略角柱状形状の側面に形成されていることから、樹脂封止後の密着強度は十分に確保されていると判断した。また、実施例２と同様にめっきの一部がバリとなったり欠損したりした箇所はなかった。 This was half-etched from the surface side to a depth of about 100 μm by the same method as in Example 2 to form a columnar shape and a substantially prismatic shape. The depth of the recesses formed on the side surfaces of the obtained columnar shape was 17 to 20 μm on average. Since the recesses of at least 10 μm or more were formed on the side surfaces of the columnar shape and the substantially prismatic shape, it was determined that the adhesion strength after resin sealing was sufficiently ensured. Further, as in Example 2, there was no spot where a part of the plating became burrs or was missing.
（比較例１）
実施例１と同じ、厚さ０．１２５ｍｍの銅系合金材の両面にドライフィルムレジストをラミネートし、表面側にワイヤボンディング部に形成するめっきエリアを直径０．５ｍｍの円形、半導体素子搭載部に形成するめっきエリアは角部に半径０．１ｍｍとなる４ｍｍ□の四角形状、そして裏面側の外部接続部に形成するめっきエリアは、同じ角部が半径０．１ｍｍとなる０．５ｍｍ□の四角形状、パッド部の部位にも角部が半径０．１ｍｍとなる４ｍｍ□の四角形状が開口されるレジストマスクを形成した。
形成したレジストマスクの開口部から露出している金属板１に、めっき前処理を行い、Ｎｉ、Ｐｄ、Ａｕを順次めっきし、レジストマスクを剥離した。
(Comparative Example 1)
As in Example 1, a dry film resist is laminated on both surfaces of a 0.125 mm thick copper-based alloy material, and a plating area formed on the wire bonding portion on the surface side is a circular shape with a diameter of 0.5 mm, on the semiconductor element mounting portion The plating area to be formed is a 4 mm square with a radius of 0.1 mm at the corner, and the plating area to be formed at the external connection on the back side is a 0.5 mm square with a radius of 0.1 mm. A resist mask having a 4 mm square shape with a corner having a radius of 0.1 mm was also formed in the shape and the pad portion.
The
次に、めっきが形成された金属板の両面に、前述と同じドライフィルムレジストをラミネートし、裏面側は全面を覆うレジストマスクとした。また、表面側は、形成しためっきを丁度覆うようにレジストマスクを形成した。そして、実施例１と同じエッチング条件で、表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。 Next, the same dry film resist as described above was laminated on both surfaces of the metal plate on which plating was formed, and the back side was used as a resist mask covering the entire surface. In addition, a resist mask was formed on the surface side so as to just cover the formed plating. Then, under the same etching conditions as in Example 1, half-etching was performed from the surface side to a depth of about 80 μm to form a columnar shape and a substantially prismatic shape.
得られたワイヤボンディング部となる柱状形状の側面に形成された凹部の深さは平均４μｍで、部分的には凹部が無く、角部および直線部には上面（表面側）のめっきに欠損部も確認され、樹脂封止後の端子密着強度を得るには不十分であると判断できた（図５（２）参照）。また、半導体素子搭載部となる略角柱状形状の側面は垂直であり、樹脂封止後の密着強度を得るには不十分であると判断できた。 The depth of the concave portions formed on the side surfaces of the columnar shape to be the obtained wire bonding portion is an average of 4 μm, and there is no concave portion in part, and the corner portion and the straight portion are defective in the plating on the upper surface (surface side). It was also confirmed, and it was judged that it was insufficient to obtain the terminal adhesion strength after resin sealing (see FIG. 5 (2)). Moreover, it was judged that the side surface of the substantially prismatic shape serving as the semiconductor element mounting portion was vertical, which was insufficient for obtaining the adhesion strength after resin sealing.
（比較例２）
両面に実施例１と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側は形成しためっきより半径で７μｍ大きく覆うようにレジストマスクを形成した以外は実施例１と同様にした。
(Comparative Example 2)
A material in which the same plating as in Example 1 was formed on both surfaces and a resist layer was formed on both surfaces was used. Example 1 was the same as Example 1 except that the back side was a resist mask covering the entire surface and the front side was formed so as to cover the surface with a radius of 7 μm larger than the formed plating.
これを実施例１と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さは、平均１５〜１８μｍであった。しかし、めっきの一部が欠損していた。したがって、樹脂封止後の密着強度は十分に確保されないと判断した。 This was half-etched from the surface side to a depth of about 80 μm as in Example 1 to form a columnar shape and a substantially prismatic shape. The depth of the recesses formed on the side surfaces of the obtained columnar shape was 15 to 18 μm on average. However, a part of the plating was missing. Therefore, it was judged that the adhesion strength after resin sealing was not sufficiently ensured.
（比較例３）
両面に実施例２と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側はワイヤボンディング部として形成した直径０．５ｍｍの円形形状のめっきと同じ中心の直径が０．５１ｍｍの円が内接する四角形で０．２ｍｍのコーナー半径となるレジストマスクを形成した以外は実施例２と同様にした。
(Comparative Example 3)
A material in which the same plating as in Example 2 was formed on both surfaces and a resist layer was formed on both surfaces was used. The back side is a resist mask that covers the entire surface, and the front side is the same square as the 0.5 mm diameter circular plating formed as a wire bonding part. Example 2 was performed except that a resist mask was formed.
これを実施例２と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さは、平均１２〜１８μｍであった。しかし、めっきの一部が欠損していた。したがって、樹脂封止後の密着強度は十分に確保されないと判断した。 This was half-etched from the surface side to a depth of about 80 μm as in Example 2 to form a columnar shape and a substantially prismatic shape. The depth of the concave portions formed on the side surfaces of the obtained columnar shape was 12 to 18 μm on average. However, a part of the plating was missing. Therefore, it was judged that the adhesion strength after resin sealing was not sufficiently ensured.
（比較例４）
両面に実施例２と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側はワイヤボンディング部として形成した直径０．５ｍｍの円形形状のめっきに外接する一辺が０．５ｍｍでコーナー半径が０．２ｍｍの四角形のレジストマスクを形成した以外は実施例２と同様にした。
(Comparative Example 4)
A material in which the same plating as in Example 2 was formed on both surfaces and a resist layer was formed on both surfaces was used. The back side is a resist mask that covers the entire surface, and the front side is a square resist mask that is 0.5mm in diameter and 0.2mm in corner radius that circumscribes a 0.5mm diameter circular plating formed as a wire bonding part. The procedure was the same as in Example 2 except that.
これを実施例２と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さは、平均５〜１２μｍであった。部分的には凹部の深さが浅く、また角部および直線部には上面（表面側）のめっきに欠損部も確認され、樹脂封止後の端子密着強度を得るには不十分であると判断できた This was half-etched from the surface side to a depth of about 80 μm as in Example 2 to form a columnar shape and a substantially prismatic shape. The depth of the recesses formed on the side surfaces of the obtained columnar shape was 5 to 12 μm on average. In part, the depth of the recesses is shallow, and the corners and straight parts are also missing in the plating on the upper surface (surface side), which is insufficient to obtain the terminal adhesion strength after resin sealing. I was able to judge
（比較例５）
両面に実施例２と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側はワイヤボンディング部として形成した直径０．５ｍｍの円形形状のめっきと同じ中心の直径が０．５３ｍｍの円が内接する四角形で０．１０ｍｍのコーナー半径となるレジストマスクを形成した以外は実施例２と同様にした。
(Comparative Example 5)
A material in which the same plating as in Example 2 was formed on both surfaces and a resist layer was formed on both surfaces was used. The back side is a resist mask that covers the entire surface, and the front side is the same square as the 0.5 mm diameter circular plating formed as a wire bonding part. Example 2 was performed except that a resist mask was formed.
これを実施例２と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状はコーナー部が一部欠損してめっきにも欠損部が確認された。また側面に形成された凹部の深さは、平均４〜１２μｍであり、樹脂封止後の端子密着強度を得るには不十分であると判断できた。 This was half-etched from the surface side to a depth of about 80 μm as in Example 2 to form a columnar shape and a substantially prismatic shape. As for the obtained columnar shape, a corner part partly lacked and the defect part was confirmed also in plating. Moreover, the depth of the recessed part formed in the side surface is 4-12 micrometers on average, and it has been judged that it is insufficient for obtaining the terminal adhesion strength after resin sealing.
（比較例６）
両面に実施例２と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側はワイヤボンディング部として形成した直径０．５ｍｍの円形形状のめっきと同じ中心の直径が０．５３ｍｍの円が内接する四角形でコーナーは直角であるレジストマスクを形成した以外は実施例２と同様にした。
(Comparative Example 6)
A material in which the same plating as in Example 2 was formed on both surfaces and a resist layer was formed on both surfaces was used. The back side is a resist mask that covers the entire surface, and the front side is a quadrangle in which a circle with a center diameter of 0.53 mm is inscribed, and the corners are at right angles, as with a 0.5 mm diameter circular plating formed as a wire bonding part. The same procedure as in Example 2 was performed except that a mask was formed.
これを実施例２と同じく表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状はコーナー部が一部欠損してめっきにも欠損部が確認された。また側面に形成された凹部の深さは、平均２〜１２μｍであり、樹脂封止後の端子密着強度を得るには不十分であると判断できた。 This was half-etched from the surface side to a depth of about 80 μm as in Example 2 to form a columnar shape and a substantially prismatic shape. As for the obtained columnar shape, a corner part partly lacked and the defect part was confirmed also in plating. Moreover, the depth of the recessed part formed in the side surface was 2-12 micrometers on average, and it was judged that it was inadequate to obtain the terminal contact | adhesion intensity | strength after resin sealing.
（比較例７）
両面に実施例２と同じめっきが形成され、両面に実施例２とレジスト層を形成した材料を用いた。
(Comparative Example 7)
The same plating as Example 2 was formed on both surfaces, and a material in which Example 2 and a resist layer were formed on both surfaces was used.
これを実施例２と同じ方法で表面側から約１１０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた柱状形状の側面に形成された凹部の深さが平均１８〜２５μｍあり、めっきの一部が欠損していた。 This was half-etched from the surface side to a depth of about 110 μm by the same method as in Example 2 to form a columnar shape and a substantially prismatic shape. The average depth of the recesses formed on the side surfaces of the obtained columnar shape was 18 to 25 μm, and a part of the plating was missing.
（比較例８）
両面に実施例１と同じめっきが形成され、両面にレジスト層を形成した材料を用いた。裏面側は全面を覆うレジストマスクとし、表面側は半導体素子搭載部についてはサイドの直線部分には円弧を形成せずにサイドが直線状に形成されるようにレジストマスクを形成以外は実施例１と同様にした。
(Comparative Example 8)
A material in which the same plating as in Example 1 was formed on both surfaces and a resist layer was formed on both surfaces was used. Example 1 except that the back side is a resist mask that covers the entire surface, and the front side is a resist mask that is formed so that the side is formed in a straight line without forming an arc in the straight part of the side for the semiconductor element mounting portion And so on.
これを実施例１と同じエッチング条件で、表面側から約８０μｍの深さまでハーフエッチング加工を行い、柱状形状と略角柱状形状を形成した。得られた半導体素子搭載部となる略角柱状形状はめっきの一部がバリとなったり欠損したりした箇所はなかったが、側面が垂直で凹部がなく、樹脂封止後の密着強度を得るには不十分であると判断できた。 This was half-etched from the surface side to a depth of about 80 μm under the same etching conditions as in Example 1 to form a columnar shape and a substantially prismatic shape. The substantially prismatic shape to be the semiconductor element mounting portion obtained did not have a part where plating partially became burrs or chipped, but the side surface was vertical and there was no recess, and the adhesion strength after resin sealing was obtained. It was judged that this was insufficient.
１ ワイヤボンディング部
１’ めっき
２ 外部接続部
３ 半導体素子搭載部
３’ めっき
４ 凹部
５ 柱状形状
６ 凹部
７ 略角柱状形状
８ パッド部
９ 円弧部分
１０ 金属板
１１ 導体端子
２０ 半導体素子
２１ ワイヤ
３０ 封止樹脂
DESCRIPTION OF
Claims (11)
前記金属板の前記表面側に、ハーフエッチング加工により上面の平面形状が円形形状としたワイヤボンディング部となる柱状形状が形成され、前記柱状形状の側面は凹部を有するとともに、前記柱状形状の上面には前記円形形状より小さなエリアにワイヤボンディング用のめっきが形成され、
また同じ面に、ハーフエッチング加工により上面の平面形状が略四角形形状で各辺には部分的に円弧となる形状を有して半導体素子搭載部となる略角柱状形状が形成され、前記略角柱状形状の側面は部分的に凹部を有するとともに、前記略角柱状形状のパッド部上面には前記略四角形形状より小さなエリアにめっきが形成されていることを特徴とする半導体素子搭載用基板。 After the semiconductor element is mounted and wire-bonded on the front surface side and the front surface side is resin-sealed, an unnecessary portion of the semiconductor element mounting substrate is removed by etching from the back surface side to manufacture a semiconductor package. A semiconductor element mounting substrate made of a metal plate used for
A columnar shape is formed on the surface side of the metal plate to be a wire bonding portion whose planar shape on the upper surface is circular by half-etching, and the side surface of the columnar shape has a recess, and on the upper surface of the columnar shape. Is formed by plating for wire bonding in an area smaller than the circular shape,
In addition, a substantially square columnar shape serving as a semiconductor element mounting portion is formed on the same surface by a half-etching process so that the planar shape of the upper surface is a substantially rectangular shape and each side has a partially arcuate shape. A substrate for mounting a semiconductor element, wherein a side surface of the columnar shape has a recess partly, and a plating is formed on an upper surface of the pad portion of the substantially prismatic shape in a smaller area than the substantially rectangular shape.
前記金属板の前記表面側に、ハーフエッチング加工により上面の平面形状をコーナーの半径がハーフエッチング深さの２倍以上の大きさを有する四角形以上の多角形形状としたワイヤボンディング部となる柱状形状が形成され、前記柱状形状の側面は凹部を有するとともに、前記柱状形状の上面には前記多角形状より小さなエリアにワイヤボンディング用のめっきが形成され、
また同じ面に、ハーフエッチング加工により上面の平面形状が略四角形形状で各辺には部分的に円弧となる形状を有して半導体素子搭載部となる略角柱状形状が形成され、前記略角柱状形状の側面は部分的に凹部を有するとともに、前記略角柱状形状のパッド部上面には前記略四角形形状より小さなエリアにめっきが形成されていることを特徴とする半導体素子搭載用基板。 After the semiconductor element is mounted and wire-bonded on the front surface side and the front surface side is resin-sealed, an unnecessary portion of the semiconductor element mounting substrate is removed by etching from the back surface side to manufacture a semiconductor package. A semiconductor element mounting substrate made of a metal plate used for
On the surface side of the metal plate, a columnar shape serving as a wire bonding portion in which a planar shape of the upper surface is formed by half-etching, and a corner radius is more than twice the half-etching depth and is a quadrilateral or more polygonal shape The side surface of the columnar shape has a recess, and the upper surface of the columnar shape is formed with a plating for wire bonding in an area smaller than the polygonal shape,
In addition, a substantially square columnar shape serving as a semiconductor element mounting portion is formed on the same surface by a half-etching process so that the planar shape of the upper surface is a substantially rectangular shape and each side has a partially arcuate shape. A substrate for mounting a semiconductor element, wherein a side surface of the columnar shape has a recess partly, and a plating is formed on an upper surface of the pad portion of the substantially prismatic shape in a smaller area than the substantially rectangular shape.
前記金属板の前記表面側にワイヤボンディング用及び半導体素子搭載用のめっきを形成する工程と、
前記金属板の前記表面側に形成したワイヤボンディング用及び半導体素子搭載用のめっきより広い範囲を覆うレジストマスクを形成する工程と、
前記表面側の前記レジストマスクから露出している前記金属板をハーフエッチング加工し、側面に凹部が形成されたワイヤボンディング用の柱状形状と、側面に部分的に凹部が形成された半導体素子搭載用の略角柱状形状のパッド部とを形成する工程を含むことを特徴とする半導体素子搭載用基板の製造方法。 After the semiconductor element is mounted and wire-bonded on the front surface side and the front surface side is resin-sealed, an unnecessary portion of the semiconductor element mounting substrate is removed by etching from the back surface side to manufacture a semiconductor package. A method of manufacturing a semiconductor element mounting substrate made of a metal plate used for
Forming a wire bonding and semiconductor element mounting plating on the surface side of the metal plate;
Forming a resist mask covering a wider area than plating for wire bonding and semiconductor element mounting formed on the surface side of the metal plate;
The metal plate exposed from the resist mask on the front surface side is half-etched to provide a wire bonding columnar shape with a concave portion on the side surface, and a semiconductor element mounting portion on which the concave portion is partially formed on the side surface And a step of forming a substantially prismatic pad portion. A method of manufacturing a semiconductor element mounting substrate.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004007022A (en) * | 2003-09-30 | 2004-01-08 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2006310570A (en) * | 2005-04-28 | 2006-11-09 | Aoi Electronics Co Ltd | Semiconductor device |
| JP2007150372A (en) * | 2007-03-15 | 2007-06-14 | Mitsui High Tec Inc | Semiconductor device and method of manufacturing same |
| JP2009302095A (en) * | 2008-06-10 | 2009-12-24 | Seiko Epson Corp | Semiconductor device and method for manufacturing the same |
| JP2012193946A (en) * | 2011-02-28 | 2012-10-11 | Jfe Steel Corp | Air preheating device and exhaust air recirculating device |
| JP2013016624A (en) * | 2011-07-04 | 2013-01-24 | Renesas Electronics Corp | Semiconductor device and manufacturing method of the same |
| JP2014049718A (en) * | 2012-09-04 | 2014-03-17 | Sumitomo Metal Mining Co Ltd | Semiconductor device manufacturing method, semiconductor element mounting substrate used therefor and manufacturing method of the same |
-
2013
- 2013-02-22 JP JP2013033087A patent/JP6168589B2/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004007022A (en) * | 2003-09-30 | 2004-01-08 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2006310570A (en) * | 2005-04-28 | 2006-11-09 | Aoi Electronics Co Ltd | Semiconductor device |
| JP2007150372A (en) * | 2007-03-15 | 2007-06-14 | Mitsui High Tec Inc | Semiconductor device and method of manufacturing same |
| JP2009302095A (en) * | 2008-06-10 | 2009-12-24 | Seiko Epson Corp | Semiconductor device and method for manufacturing the same |
| JP2012193946A (en) * | 2011-02-28 | 2012-10-11 | Jfe Steel Corp | Air preheating device and exhaust air recirculating device |
| JP2013016624A (en) * | 2011-07-04 | 2013-01-24 | Renesas Electronics Corp | Semiconductor device and manufacturing method of the same |
| JP2014049718A (en) * | 2012-09-04 | 2014-03-17 | Sumitomo Metal Mining Co Ltd | Semiconductor device manufacturing method, semiconductor element mounting substrate used therefor and manufacturing method of the same |
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