JP2014147407A - Slot machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a slot machine capable of improving the security on a random number circuit to be mounted.SOLUTION: A slot machine comprises an update monitoring circuit 537 capable of monitoring the occurrence of the abnormality of the frequency of a random number clock signal to update the numerical data held by numerical value holding means of a 16-bit random number circuit 508b, and the update state of the numerical data held by the numerical value holding means. A main control part 41 sets the monitor of the random number circuit before the timing for extracting numerical data (of a random value) from the random number circuit.

Description

  The present invention relates to a slot machine capable of generating a predetermined winning according to a display result of a variable display device capable of variably displaying a plurality of types of identification information each identifiable.

  A slot machine generally includes a variable display device having a plurality of (usually three) reels on which a plurality of types of symbols as identification information are drawn on the outer periphery, and first, a bet number is determined by a player's BET operation. The reels start to rotate when the start operation is performed with the set number of bets set, and the rotation is stopped by operating a stop button provided corresponding to each reel. When all reels stop rotating, a winning combination is generated when a predetermined winning symbol combination (for example, 7-7-7, hereinafter referred to as a symbol combination) is arranged on the winning line. To do. Winning is possible on condition that the internal lottery performed simultaneously with the start operation is won.

  Some slot machines of this type are equipped with a random number circuit for generating random values used for games such as the lottery processing related to the internal lottery. For example, Patent Document 1 describes that a slot machine is configured to be equipped with a random number circuit, and that a malfunction in a random number clock generation circuit of the random number circuit mounted in the slot machine can be detected.

JP-A-2005-192916

  In the slot machine described in Patent Document 1, the occurrence of abnormality in the frequency of the random number clock signal can be monitored by detecting the malfunction of the random number clock generation circuit of the random number circuit. However, the update state of numerical data that the random number circuit updates as a random number value cannot be monitored, and it may not be said that security measures are sufficient for the random number circuit mounted in the slot machine.

  The present invention has been made paying attention to such problems, and an object of the present invention is to provide a slot machine capable of improving the security related to a random number circuit to be mounted.

In order to solve the above-described problem, a slot machine according to claim 1 of the present invention provides:
A variable display device capable of starting a game by setting a predetermined number of bets for one game using a game value (medal), and capable of variably displaying a plurality of types of identification information each of which can be identified A slot machine (slot machine 1) in which one game is completed when a display result is derived to (reels 2L, 2C, 2R) and a winning can be generated according to the display result of the variable display device. ,
A game control means (main control unit 41) for controlling a game, incorporating a random number circuit (random number circuit 508b) for generating numerical data to be a random value;
A start operation means (start switch 7) operated when starting the game;
With
The random number circuit (random number circuit 508b) includes numerical value holding means (hard latch random number value register) for holding numerical data updated when the start operation means (start switch 7) is operated,
The game control means includes
When the operation of the start operation means (start switch 7) is detected in a state where a game can be started (a state where a specified number of bets is set), the value is held by the numerical value holding means (hard latch random number value register) Pre-determining means (internal lottery) for determining whether or not to allow the occurrence of winning using the numerical data that has been made,
Occurrence of abnormality in the frequency of a random number clock signal (external clock frequency abnormality) for updating numerical data held by the numerical value holding means (hard latch random number value register), and the numerical value holding means (hard latch random number value register) Random number circuit monitoring means (update monitoring circuit 537) capable of monitoring the update state (update abnormality) of the numerical data held by
Random number circuit setting means for setting a monitoring target by the random number circuit monitoring means (update monitoring circuit 537) (setting of monitoring frequency according to the setting value of bits 1-0 of the random number clock monitoring setting (KRCS) in the program management area) When,
Including
The random number circuit setting means performs setting related to monitoring by the random number circuit monitoring means before the timing of extracting numerical data from the random number circuit (the main control unit 41 sets the random number circuit when the slot machine 1 is turned on. 508b is set in hardware, and then the user program is started)
It is characterized by that.
According to this feature, since the occurrence of abnormality in the frequency of the random number clock signal can be monitored and the update state of the numerical data can be monitored, the security of the random number circuit installed in the slot machine can be improved. In addition, it is possible to increase the fairness of the game because it is determined whether or not the winning is permitted by the predetermining means using the numerical data generated by the highly secure random number circuit.

The slot machine according to means 1 of the present invention is the slot machine according to claim 1,
The random number circuit (random number circuit 508b) can generate a plurality of types of numerical data (random numbers generated by the channels RL0 to RL3),
The game control means (main control unit 41) is advantageous to the player (the number of times that a successful outcome that will increase the number of ART games is derived) separately from the prior determination means (internal lottery). ) To determine the degree of advantage (successful lottery)
The advantage determining means is a numerical data of a type different from the numerical data (random numbers generated by the channel RL0) used by the prior determining means (internal lottery) among the numerical data generated by the random number circuit (random number circuit 508b). The advantage is determined using (channel RL2).
According to this feature, the numerical data generated by the random number circuit can be used for determination by the advantage determining means. At this time, since numerical data different from the pre-determining means is used, it is possible to prevent the numerical data used by the pre-deciding means and the numerical data used by the advantage determining means from being synchronized.

The slot machine according to means 2 of the present invention is the slot machine according to claim 1 or means 1, wherein
The random number circuit (random number circuit 508b) can generate a plurality of types of numerical data (random numbers generated by the channels RL0 to RL3),
The game control means includes
Delay state control means (control of the freeze state by the main control unit 41) for controlling the game state to a delay state (freeze state) that delays the progress of the game over a predetermined period;
Special fluctuation control means (reel production control by the main control unit 41) for performing special fluctuation control (reel production) of the plurality of variable display areas (reels 2L, 2C, 2R) in the delay state (freeze state);
Special variation determination means (freeze lottery, success number lottery, success notice lottery) for making a determination regarding the special variation control (reel production),
Including
The special variation determining means uses the special data using a different kind of numerical data (random numbers generated by the channels RL1 to 3) than the numerical data (random numbers generated by the channel RL0) used by the prior determination means (internal lottery). It is characterized by making decisions regarding fluctuation control (reel production).
According to this feature, the numerical data generated by the random number circuit can be used for determination by the special variation determination means. At this time, since numerical data different from the pre-determining means is used, it is possible to prevent the numerical data used by the pre-determining means and the numerical data used by the special variation determining means from being synchronized.

The slot machine according to means 3 of the present invention is the slot machine according to claim 1, means 1 or 2,
The variable display device includes a plurality of variable display areas (reels 2L, 2C, and 2R) that can be variably displayed by periodically moving a plurality of types of identification information (designs) that can be individually identified in a predetermined order. Can derive the display result,
When the display result is derived to all of the plurality of variable display areas (reels 2L, 2C, 2R), one game is completed. As a result of one game, the plurality of variable display areas (reels 2L, 2C, 2R) are completed. ), A slot machine (slot machine 1) in which a winning can be generated according to the combination of the display results derived to each of
Production control means (sub control unit 91) for controlling production based on control information (command) transmitted from the game control means (main control unit 41);
Derivation operation means (stop switches 8L, 8C, 8R) each operated when deriving display results to the plurality of variable display areas (reels 2L, 2C, 2R);
With
The game control means includes
When it is determined that the identification information (symbol) is moved at a specified speed for all of the plurality of variable display areas (reels 2L, 2C, 2R) after starting the game. Effective reception state control means for effectively receiving that the derivation operation means (stop switches 8L, 8C, 8R) has been operated;
When the derivation operation means (stop switches 8L, 8C, 8R) is operated in the valid acceptance state (a state where the stop operation is valid), the derivation operation means is supported based on the determination result of the prior determination means Derivation control means for performing derivation control (reel stop control) for deriving the display result to the variable display area
Delay state control means (freeze state control) for controlling to a delay state (freeze state) that delays the progress of the game over a predetermined period;
In the delay state (freeze state), the relative positional relationship of the identification information among the plurality of variable display areas (reels 2L, 2C, 2R) is a specific positional relationship (for example, “black 7” is aligned on a straight line. Special fluctuation control means for performing special fluctuation control (reel effect) for performing fluctuation control of the plurality of variable display areas (reels 2L, 2C, 2R) so as to be in a positional relationship),
After performing the special variation control (reel effect) in the delay state (freeze state), the variable display regions (reels 2L, 2C, and 2R) all have a variation stopped state or a speed different from the specified speed. Specific state control means for controlling to a specific state (stop state) that is one of the states in which the identification information (symbol) is moved,
All of the plurality of variable display areas (reels 2L, 2C, 2R) are controlled by the specific state control means to the specific state (stop state) for all of the plurality of variable display areas (reels 2L, 2C, 2R). First moving speed changing means for changing the moving speed of the identification information (symbol) in any one of the variable display areas (left reel) toward the specified speed when is in the specific state (stopped state). ,
After the specific state control means controls all of the plurality of variable display areas (reels 2L, 2C, 2R) to the specific state (stopped state), at least one of the variable display areas (reel 2L / reels 2L, 2C) ) Is in the steady state (constant speed rotation), the moving speed in any variable display area (reel 2C / reel 2R) that has not yet been in the steady state (constant speed rotation) is defined. Second moving speed changing means for changing the speed,
All of the plurality of variable display areas (reels 2L, 2C, 2R) are controlled by the specific state control means to the specific state (stop state) for all of the plurality of variable display areas (reels 2L, 2C, 2R). When the steady state (constant speed rotation) is reached, the special acceptance post-fluctuation valid acceptance state control means (enabling the acceptance of the stop operation after the freeze state) to be the valid acceptance state (a state in which the stop operation is valid);
Specific time determining means for randomly determining a specific time (time based on left, middle, and right reel timer values) until the second moving speed changing means changes the moving speed;
Including
The second moving speed changing means determines that the variable display area (reel 2L / reel 2C) that last changed the moving speed has reached the steady state (constant speed rotation), and then moves the moving speed. The variable display area (reel 2C / reel 2R) is changed when the specific time (setting of the left, middle and right reel timer values) determined by the specific time determination means has elapsed. Change the moving speed of reel 2C / reel 2R),
The specific time determining means is the second moving speed changing means before the first moving speed changing means changes the moving speed (before starting the rotation of the left reel which starts rotating first). Determine all the specific times used (time based on left, middle and right reel timer values),
The game control means (main control unit 41) is configured such that after the specific time determining means determines the specific time (time based on left, middle, and right reel timer values), the first moving speed changing means is The specific time (time based on the timer values for the left, middle, and right reels) determined by the specific time determination means before changing the moving speed (before starting the rotation of the left reel that starts rotating first) Specific time specific control information transmitting means for transmitting specific time specific control information (reel delay command) to the effect control means (sub-control unit 91).
According to this feature, since the special variation control for performing variation control of the plurality of variable display regions is performed so that the relative positional relationship of the identification information among the plurality of variable display regions becomes the specific positional relationship, the variable display region In the display mode, it is possible to produce an effect with impact, and after special variation control, the movement of the identification information of all the variable display areas is temporarily stopped or the moving speed is different from the specified speed, and then any variable display is performed. After the area moving speed changes toward the specified speed, the time until the moving speed of the next variable display area changes randomly changes, so that the moving speed of the identification information of all variable display areas changes to the specified speed. The relative positional relationship of the identification information among the plurality of variable display areas, which are in the specific positional relationship by the special variation control, is determined when the steady state is determined and the effective reception state is obtained. Because it is a dam positional relationship, even if special fluctuation control with specific positional relation is performed, there is no regularity that does not occur if special fluctuation control is not performed, and special fluctuation control is not performed. By doing so, the gaming performance of the slot machine in which the display result is derived by the technical intervention by the player is not impaired.

A slot machine according to means 4 of the present invention is the slot machine according to claim 1, means 1 or 2,
The variable display device includes a plurality of variable display areas (reels 2L, 2C, and 2R) that can be variably displayed by periodically moving a plurality of types of identification information (designs) that can be individually identified in a predetermined order. Can derive the display result,
When the display result is derived to all of the plurality of variable display areas (reels 2L, 2C, 2R), one game is completed. As a result of one game, the plurality of variable display areas (reels 2L, 2C, 2R) are completed. ), A slot machine (slot machine 1) in which a winning can be generated according to the combination of the display results derived to each of
Production control means (sub control unit 91) for controlling production based on control information (command) transmitted from the game control means (main control unit 41);
Derivation operation means (stop switches 8L, 8C, 8R) each operated when deriving display results to the plurality of variable display areas (reels 2L, 2C, 2R);
With
The game control means includes
When it is determined that the identification information (symbol) is moved at a specified speed for all of the plurality of variable display areas (reels 2L, 2C, 2R) after starting the game. Effective reception state control means for effectively receiving that the derivation operation means (stop switches 8L, 8C, 8R) has been operated;
When the derivation operation means (stop switches 8L, 8C, 8R) is operated in the valid acceptance state (a state where the stop operation is valid), the derivation operation means is supported based on the determination result of the prior determination means Derivation control means for performing derivation control (reel stop control) for deriving the display result to the variable display area
Delay state control means (freeze state control) for controlling to a delay state (freeze state) that delays the progress of the game over a predetermined period;
In the delay state (freeze state), the relative positional relationship of the identification information among the plurality of variable display areas (reels 2L, 2C, 2R) is a specific positional relationship (for example, “black 7” is aligned on a straight line. Special fluctuation control means for performing special fluctuation control (reel effect) for performing fluctuation control of the plurality of variable display areas (reels 2L, 2C, 2R) so as to be in a positional relationship),
After performing the special variation control (reel effect) in the delay state (freeze state), the variable display regions (reels 2L, 2C, and 2R) all have a variation stopped state or a speed different from the specified speed. Specific state control means for controlling to a specific state (stop state) that is one of the states in which the identification information (symbol) is moved,
All of the plurality of variable display areas (reels 2L, 2C, 2R) are controlled by the specific state control means to the specific state (stop state) for all of the plurality of variable display areas (reels 2L, 2C, 2R). First moving speed changing means for changing the moving speed of the identification information (symbol) in any one of the variable display areas (left reel) toward the specified speed when is in the specific state (stopped state). ,
After the specific state control means controls all of the plurality of variable display areas (reels 2L, 2C, 2R) to the specific state (stopped state), at least one of the variable display areas (reel 2L / reels 2L, 2C) ) Is in the steady state (constant speed rotation), the moving speed in any variable display area (reel 2C / reel 2R) that has not yet been in the steady state (constant speed rotation) is defined. Second moving speed changing means for changing the speed,
All of the plurality of variable display areas (reels 2L, 2C, 2R) are controlled by the specific state control means to the specific state (stop state) for all of the plurality of variable display areas (reels 2L, 2C, 2R). When the steady state (constant speed rotation) is reached, the special acceptance post-fluctuation valid acceptance state control means (enabling the acceptance of the stop operation after the freeze state) to be the valid acceptance state (a state in which the stop operation is valid);
Specific time determining means for randomly determining a specific time (time based on left, middle, and right reel timer values) until the second moving speed changing means changes the moving speed;
Including
The second moving speed changing means is configured to change the moving speed after the variable display area (reel 2L / reel 2C) that has changed the moving speed last starts changing the moving speed. From the specific time (time based on the left, middle, and right reel timer values) determined by the specific time determination means (reel 2C / reel 2R) and the specific state (stop state) to the steady state (constant speed) The moving speed of the variable display area (reel 2C / reel 2R) is changed when a time obtained by adding a predetermined arrival time (acceleration time) sufficient to reach (rotation) has elapsed,
The specific time determining means is the second moving speed changing means before the first moving speed changing means changes the moving speed (before starting the rotation of the left reel which starts rotating first). Determine all the specific times used (time based on left, middle and right reel timer values),
The game control means (main control unit 41) is configured such that after the specific time determining means determines the specific time (time based on left, middle, and right reel timer values), the first moving speed changing means is The specific time (time based on the timer values for the left, middle, and right reels) determined by the specific time determination means before changing the moving speed (before starting the rotation of the left reel that starts rotating first) Specific time specific control information transmitting means for transmitting specific time specific control information (reel delay command) to the effect control means (sub-control unit 91).
According to this feature, since the special variation control for performing variation control of the plurality of variable display regions is performed so that the relative positional relationship of the identification information among the plurality of variable display regions becomes the specific positional relationship, the variable display region In the display mode, it is possible to produce an effect with impact, and after special variation control, the movement of the identification information of all the variable display areas is temporarily stopped or the moving speed is different from the specified speed, and then any variable display is performed. After the area moving speed changes toward the specified speed, the time until the moving speed of the next variable display area changes randomly changes, so that the moving speed of the identification information of all variable display areas changes to the specified speed. The relative positional relationship of the identification information among the plurality of variable display areas, which are in the specific positional relationship by the special variation control, is determined when the steady state is determined and the effective reception state is obtained. Because it is a dam positional relationship, even if special fluctuation control with specific positional relation is performed, there is no regularity that does not occur if special fluctuation control is not performed, and special fluctuation control is not performed. By doing so, the gaming performance of the slot machine in which the display result is derived by the technical intervention by the player is not impaired.

A slot machine according to means 5 of the present invention is the slot machine according to claim 1, means 1 or 2,
The variable display device includes a plurality of variable display areas (reels 2L, 2C, and 2R) that can be variably displayed by periodically moving a plurality of types of identification information (designs) that can be individually identified in a predetermined order. Can derive the display result,
When the display result is derived to all of the plurality of variable display areas (reels 2L, 2C, 2R), one game is completed. As a result of one game, the plurality of variable display areas (reels 2L, 2C, 2R) are completed. ), A slot machine (slot machine 1) in which a winning can be generated according to the combination of the display results derived to each of
Production control means (sub control unit 91) for controlling production based on control information (command) transmitted from the game control means (main control unit 41);
Derivation operation means (stop switches 8L, 8C, 8R) each operated when deriving display results to the plurality of variable display areas (reels 2L, 2C, 2R);
With
The game control means includes
When it is determined that the identification information (symbol) is moved at a specified speed for all of the plurality of variable display areas (reels 2L, 2C, 2R) after starting the game. Effective reception state control means for effectively receiving that the derivation operation means (stop switches 8L, 8C, 8R) has been operated;
When the derivation operation means (stop switches 8L, 8C, 8R) is operated in the valid acceptance state (a state where the stop operation is valid), the derivation operation means is supported based on the determination result of the prior determination means Derivation control means for performing derivation control (reel stop control) for deriving the display result to the variable display area
Delay state control means (freeze state control) for controlling to a delay state (freeze state) that delays the progress of the game over a predetermined period;
In the delay state (freeze state), the relative positional relationship of the identification information among the plurality of variable display areas (reels 2L, 2C, 2R) is a specific positional relationship (for example, “black 7” is aligned on a straight line. Special fluctuation control means for performing special fluctuation control (reel effect) for performing fluctuation control of the plurality of variable display areas (reels 2L, 2C, 2R) so as to be in a positional relationship),
After performing the special variation control (reel effect) in the delay state (freeze state), the variable display regions (reels 2L, 2C, and 2R) all have a variation stopped state or a speed different from the specified speed. Specific state control means for controlling to a specific state (stop state) that is one of the states in which the identification information (symbol) is moved,
After the specific state control means controls all of the plurality of variable display areas (reels 2L, 2C, 2R) to the specific state (stopped state), the variable display area (reel) in the specific state (stopped state) A moving speed changing means for changing the moving speed of the identification information (symbol) toward the specified speed (constant speed rotation);
All of the plurality of variable display areas (reels 2L, 2C, 2R) are controlled by the specific state control means to the specific state (stop state) for all of the plurality of variable display areas (reels 2L, 2C, 2R). When the steady state (constant speed rotation) is reached, the special acceptance post-fluctuation valid acceptance state control means (enabling the acceptance of the stop operation after the freeze state) to be the valid acceptance state (a state in which the stop operation is valid);
A specific time (time based on the timer values for the left, middle, and right reels) until the movement speed of the variable display area corresponding to each of the plurality of variable display areas (reels 2L, 2C, 2R) is changed from a predetermined range. A specific time determining means for determining at random;
The moving speed changing means is controlled to the specific state (stopped state) for all of the plurality of variable display areas (reels 2L, 2C, 2R) by the specific state control means, and then the plurality of variable display areas (reels) 2L, 2C, 2R) corresponding to any variable display area (reel) when the specific time determined by the specific time determination means (time based on the left, middle, and right reel timer values) has elapsed. Changing the moving speed of the variable display area corresponding to the specific time (the reel timer value is 0),
The specific time determining means may be configured to change the plurality of variable display areas (before the rotation of the reel that starts rotating first) before the moving speed changing means changes the moving speed of any of the variable display areas. Determining all the specific times (time based on the timer values for the left, middle and right reels) corresponding to the reels 2L, 2C, 2R),
In the game control means, after the specific time determining means determines the specific time (time based on the left, middle, and right reel timer values), the moving speed changing means causes the movement of any one of the variable display areas. The specific time (time based on the left, middle, and right reel timer values) determined by the specific time determination means can be specified before the speed is changed (before the rotation of the reel that starts rotating first). Specific time specific control information transmitting means for transmitting specific time specific control information (reel delay command) to the effect control means (sub-control unit 91) is further included.
According to this feature, since the special variation control for performing variation control of the plurality of variable display regions is performed so that the relative positional relationship of the identification information among the plurality of variable display regions becomes the specific positional relationship, the variable display region In the display mode, an impactful presentation can be performed, and after special variation control, the movement of the identification information of all the variable display areas is temporarily stopped or set to a moving speed different from the specified speed, and then each variable display is performed. Effective when it is judged that the moving speed of the identification information of all variable display areas has become the specified speed and has reached the steady state by the time until the moving speed of the identification information of the area changes toward the specified speed at random. Since the relative positional relationship of the identification information of the plurality of variable display areas that are in a specific positional relationship by the special variation control becomes a random positional relationship when the acceptance state is entered, Even if special variation control with fixed position relation is performed, there is no regularity that does not occur if special variation control is not performed, and technical intervention by the player by performing special variation control Thus, the gaming property of the slot machine for deriving the display result is not impaired.

A slot machine according to means 6 of the present invention is the slot machine according to claim 1, means 1 or 2,
The variable display device includes a plurality of variable display areas (reels 2L, 2C, and 2R) that can be variably displayed by periodically moving a plurality of types of identification information (designs) that can be individually identified in a predetermined order. Can derive the display result,
When the display result is derived to all of the plurality of variable display areas (reels 2L, 2C, 2R), one game is completed. As a result of one game, the plurality of variable display areas (reels 2L, 2C, 2R) are completed. ), A slot machine (slot machine 1) in which a winning can be generated according to the combination of the display results derived to each of
Production control means (sub control unit 91) for controlling production based on control information (command) transmitted from the game control means (main control unit 41);
Derivation operation means (stop switches 8L, 8C, 8R) each operated when deriving display results to the plurality of variable display areas (reels 2L, 2C, 2R);
With
The game control means includes
When it is determined that the identification information (symbol) is moved at a specified speed for all of the plurality of variable display areas (reels 2L, 2C, 2R) after starting the game. Effective reception state control means for effectively receiving that the derivation operation means (stop switches 8L, 8C, 8R) has been operated;
When the derivation operation means (stop switches 8L, 8C, 8R) is operated in the valid acceptance state (a state where the stop operation is valid), the derivation operation means is supported based on the determination result of the prior determination means Derivation control means for performing derivation control (reel stop control) for deriving the display result to the variable display area
Delay state control means (freeze state control) for controlling to a delay state (freeze state) that delays the progress of the game over a predetermined period;
In the delay state (freeze state), the relative positional relationship of the identification information among the plurality of variable display areas (reels 2L, 2C, 2R) is a specific positional relationship (for example, “black 7” is aligned on a straight line. Special fluctuation control means for performing special fluctuation control (reel effect) for performing fluctuation control of the plurality of variable display areas (reels 2L, 2C, 2R) so as to be in a positional relationship),
After performing the special variation control (reel effect) in the delay state (freeze state), the variable display regions (reels 2L, 2C, and 2R) all have a variation stopped state or a speed different from the specified speed. Specific state control means for controlling to a specific state (stop state) that is one of the states in which the identification information (symbol) is moved,
All of the plurality of variable display areas (reels 2L, 2C, 2R) are controlled by the specific state control means to the specific state (stop state) for all of the plurality of variable display areas (reels 2L, 2C, 2R). First moving speed changing means for changing the moving speed of the identification information (symbol) in any one of the variable display areas (left reel) toward the specified speed when is in the specific state (stopped state). ,
After the specific state control means controls all of the plurality of variable display areas (reels 2L, 2C, 2R) to the specific state (stopped state), at least one of the variable display areas (reel 2L / reels 2L, 2C) ) Is in the steady state (constant speed rotation), the moving speed in any variable display area (reel 2C / reel 2R) that has not yet been in the steady state (constant speed rotation) is defined. Second moving speed changing means for changing the speed,
All of the plurality of variable display areas (reels 2L, 2C, 2R) are controlled by the specific state control means to the specific state (stop state) for all of the plurality of variable display areas (reels 2L, 2C, 2R). When the steady state (constant speed rotation) is reached, the special acceptance post-fluctuation valid acceptance state control means (enabling the acceptance of the stop operation after the freeze state) to be the valid acceptance state (a state in which the stop operation is valid);
A specific time (time based on the timer values for the left, middle, and right reels) until the movement speed of the variable display area corresponding to each of the plurality of variable display areas (reels 2L, 2C, 2R) is changed from a predetermined range. A specific time determining means for determining at random;
Including
The first moving speed changing means changes the moving speed after the specific state control means controls the variable display areas (reels 2L, 2C, 2R) to the specific state (stopped state). The variable display area (left reel) when a specific time (time based on the timer values for the left, middle, and right reels) determined by the specific time determination means has elapsed with respect to the variable display area (left reel) Change the moving speed of
The second moving speed changing means changes the moving speed of the variable display area (reel 2L / reel 2C) that last changed the moving speed, and then changes the moving speed. The variable display area (reel 2C / reel 2R) when a specific time (time based on the timer values for the left, middle, and right reels) determined by the specific time determination means has elapsed for (reel 2C / reel 2R). )
The specific time determining means is the second moving speed changing means before the first moving speed changing means changes the moving speed (before starting the rotation of the left reel which starts rotating first). Determine all the specific times used (time based on left, middle and right reel timer values),
The game control means (main control unit 41) is configured such that after the specific time determining means determines the specific time (time based on left, middle, and right reel timer values), the first moving speed changing means is The specific time (time based on the timer values for the left, middle, and right reels) determined by the specific time determination means before changing the moving speed (before starting the rotation of the left reel that starts rotating first) Specific time specific control information transmitting means for transmitting specific time specific control information (reel delay command) to the effect control means (sub-control unit 91).
According to this feature, since the special variation control for performing variation control of the plurality of variable display regions is performed so that the relative positional relationship of the identification information among the plurality of variable display regions becomes the specific positional relationship, the variable display region In the display mode, after the special variation control, the movement of the identification information of all the variable display areas is temporarily stopped or the moving speed is different from the specified speed, and then the variable display area is first set. The time until the moving speed of the identification information of the variable display area is changed, the moving speed of the identification information of one of the variable display areas changes toward the specified speed, and then the moving speed of the identification information of the variable display area is changed. When the movement time of the identification information of all the variable display areas becomes the specified speed and is determined to be in the steady state because it is changed randomly, special fluctuation control is performed. Since the relative positional relationship of the identification information between the variable display areas that have a more specific positional relationship becomes a random positional relationship, even when special variation control with a specific positional relationship is performed, special variation control is performed. If there is not, there will be no regularity that does not occur, and the game performance of the slot machine that causes the display result to be derived by technical intervention by the player by performing special variation control may be impaired Absent.

In the means 3, 4 and 6, the first moving speed changing means and the second moving speed changing means change the moving speed toward a specified speed. For example, if the specific state is a stopped state, It starts moving and accelerates toward the specified speed.If the specified state is slower than the specified speed, it accelerates toward the specified speed, and the specified state is faster than the specified speed. If there is, it is to decelerate toward the specified speed.
Further, in the means 3, 4 and 6, the first moving speed changing means changes the moving speed of the identification information in any variable display area toward the specified speed in any one of the variable display areas. The moving speed may be changed toward the specified speed, or the moving speed in any two or more variable display areas may be changed toward the specified speed.
In the means 3, 4 and 6, the second moving speed changing means changes the moving speed in any of the variable display areas not yet in the steady state toward the specified speed. The moving speed in any one of the variable display areas that are not in the state may be changed toward the specified speed, or the moving speed in any two or more variable display areas that are not in the steady state yet. May be configured to change toward the specified speed.
Further, in the means 5, the movement speed changing means changes the movement speed toward a specified speed, for example, if the specific state is a stop state, the movement is started and accelerated toward the specified speed. If the specified state is slower than the specified speed, acceleration is performed toward the specified speed. If the specified state is higher than the specified speed, the vehicle is decelerated toward the specified speed.

It is a front view of the slot machine of Example 1 to which the present invention was applied. It is a perspective view which shows the internal structure of a slot machine. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of a main control part. It is a figure which shows an example of the address map in a main control part. It is a figure which illustrates the main part of a program management area. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the correspondence of the setting data and operation | movement in a header (KHDR). It is a figure which shows an example of the setting content in a program code end address (KPCE), a program code start address 2 (KPCS2), and a program code end address 2 (KPCE2). It is a figure which shows an example of the setting content in reset setting (KRES). It is a figure which shows an example of the setting content in 16 bit random number initial setting 1 (KRL1). It is a figure which shows an example of the setting content in 16 bit random number initial setting 2 (KRL2). It is a figure which shows an example of the setting content in 16 bit random number initial setting 3 (KRL3). It is a figure which shows an example of the setting content in 8-bit random number initial setting 1 (KRS1). It is a figure which shows an example of the setting content in 8-bit random number initial setting 2 (KRS2). It is a figure which shows an example of the setting content in security time setting (KSES). It is a figure which shows an example of the setting content in random number clock monitoring setting (KRCS). It is a figure which shows the structural example etc. of an internal information register. It is a block diagram which shows the example of 1 structure of an 8-bit random number circuit. It is a block diagram which shows one structural example of a 16-bit random number circuit. It is explanatory drawing which shows an example of a structure example and setting content of RL0 hard latch selection register 0 (RL0LS0). It is explanatory drawing which shows an example of a structure example and setting content of RL0 hard latch selection register 1 (RL0LS1). It is explanatory drawing which shows an example of a structure of a RLn hard latch selection register (RLnLS), and an example of a setting content. It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch selection register 0 (RSLS0). It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch selection register 1 (RSLS1). It is explanatory drawing which shows an example of a structure of RL interruption control register 0 (RLIC0), and an example of the setting content. It is explanatory drawing which shows an example of a structure example and setting content of RL interrupt control register 1 (RLIC1). It is explanatory drawing which shows an example of a structure of a RS interruption control register (RSIC), and an example of setting content. It is explanatory drawing which shows an example of a structure of a RLn maximum value setting register (RLnMX), and an example of the setting content. It is explanatory drawing which shows an example of a structure example of RSn maximum value setting register (RSnMX), and a setting content. It is explanatory drawing which shows an example of a structure example and setting content of a random number sequence change register (RDSC). It is explanatory drawing which shows an example of a structure example and setting content of a random number soft latch register (RDSL). It is explanatory drawing which shows an example of a structure of a random number soft latch flag register (RDSF), and an example of the setting content. It is explanatory drawing which shows an example of a structure of a RLn soft latch random number value register (RLnSV), and an example of setting content. It is explanatory drawing which shows an example of a structure example of RSn soft latch random number value register (RSnSV), and a setting content. It is explanatory drawing which shows an example of a structure of RL hard latch flag register 0 (RLHF0), and an example of the setting content. It is explanatory drawing which shows an example of a structure example and setting content of RL hard latch flag register 1 (RLHF1). It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch flag register (RSHF). It is explanatory drawing which shows an example of a structure of a RL0 hard latch random number value register m (RL0mHV), and an example of setting content. It is explanatory drawing which shows an example of a structure of a RL1 hard latch random number value register m (RL1mHV), and an example of setting content. It is explanatory drawing which shows an example of a structure of a RL2 hard latch random number value register m (RL2mHV), and an example of setting content. It is explanatory drawing which shows an example of a structure of a RL3 hard latch random number value register m (RL3mHV), and an example of the setting content. It is explanatory drawing which shows an example of a structure example of RSn hard latch random number value register (RSnHV), and a setting content. It is explanatory drawing for demonstrating the difference in the reset operation by the setting content by reset setting (KRES). It is explanatory drawing which shows the example of how to read the data stored in the internal RAM area. It is a flowchart which shows the control content of the starting process (main) which a main control part performs. It is a flowchart which shows the control content of the game process which a main control part performs. It is a flowchart which shows the control content of the random number acquisition process which a main control part performs. It is a flowchart which shows the control content of the internal lottery process which a main control part performs. It is a flowchart which shows the control content of the power interruption process (main) which a main control part performs. It is a figure for demonstrating the technical matter relevant to the kind of special combination, the symbol combination of a special combination, and a special combination. It is a figure for demonstrating the technical matter relevant to the kind of small combination, the symbol combination of a small combination, and a small combination. It is a figure for demonstrating the technical matter relevant to the kind of re-game player, the symbol combination of a re-game player, and a re-game player. It is a figure for demonstrating the technical matter relevant to the symbol combination of a transfer event, and a transfer event. It is a figure for demonstrating the transition of a gaming state. It is a figure which shows the outline | summary of a game state. It is a figure for demonstrating the combination of the lottery object combination read as a lottery object role for every game state. It is a figure for demonstrating the combination of the lottery object combination read as a lottery object role for every game state. It is a figure for demonstrating the combination of the lottery object combination read as a lottery object role for every game state. It is a figure for demonstrating the combination of the combination which a prize is permitted by a lottery object combination. It is a figure for demonstrating the reel control at the time of several re-game player winning. It is a figure for demonstrating the reel control at the time of several small part winning. It is a flowchart which shows the flow of ART control. It is a figure which shows the flow of the display change of the reel production | presentation and the liquid crystal display 51 accompanying it. It is a figure which shows the flow of the display change of the reel production | presentation and the liquid crystal display 51 accompanying it. It is a figure which shows the procedure of control of a reel effect. It is a figure which shows the modification of the determination method of the successful appearance in a reel production, and a failure appearance. It is a flowchart which shows the control content of the acceleration process after reel effect which the main control part performs. It is a figure which shows the outline | summary of the random number value for delay. It is a figure which shows the method of calculating the timer value for left, middle, and right reels from the random number value for left, middle, and right delay. It is a figure which shows the update method in the modification of the random value for left, middle, and right delay. It is a timing chart which shows the control situation at the time of applying the acceleration process after reel production. It is a flowchart which shows the control content of the modification 1 of the acceleration process after a reel effect which a main control part performs. It is a timing chart which shows the control condition at the time of applying the modification 1 of the acceleration process after a reel effect. It is a flowchart which shows the control content of the modification 2 of the post-reel effect acceleration process which a main control part performs. It is a timing chart which shows the control condition at the time of applying the modification 2 of the acceleration process after a reel effect. It is a flowchart which shows the control content of the modification 3 of the post-reel effect acceleration process which a main control part performs. It is a timing chart which shows the control situation at the time of applying the modification 3 of the acceleration process after a reel effect.

  A mode for carrying out a slot machine according to the present invention will be described below based on examples.

  An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. As shown in FIG. 2, a slot machine 1 according to the present embodiment includes a housing 1a having an open front surface and a side of the housing 1a. And a front door 1b pivotally supported at the end.

  Inside the casing 1a of the slot machine 1 of the present embodiment, as shown in FIG. 2, reels 2L, 2C and 2R (hereinafter referred to as a left reel, a middle reel and a right reel) in which a plurality of types of symbols are arranged on the outer periphery. ) Are juxtaposed in the horizontal direction, and as shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, 2R can be seen from the see-through window 3 provided on the front door 1b. Are arranged as follows.

  As shown in FIG. 3, on the outer periphery of the reels 2L, 2C, and 2R, “black 7”, “net 7 (shaded 7 in the figure)”, “white 7”, “BAR”, “replay”, A plurality of types of mutually distinguishable symbols such as “plum”, “watermelon”, “cherry”, “bell”, and “orange” are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in upper, middle, and lower three stages in the see-through window 3 provided in the approximate center of the reel panel 1c of the front door 1b.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and rotated by reel motors 32L, 32C, and 32R (see FIG. 4), so that the symbols of the reels 2L, 2C, and 2R are continuously formed in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R are reel sensors 33L, 33C, and 33R that detect a reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. , Is provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  At the position corresponding to each of the reels 2L, 2C, and 2R on the front door 1b, a horizontally-long rectangular see-through window 3 that allows the reels 2L, 2C, and 2R to be seen through from the front side is provided. The reels 2L, 2C, and 2R can be visually recognized from the player side.

  As shown in FIG. 1, on the front door 1b, there are a medal insertion portion 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player's own game value). The MAXBET switch 6 that is operated when setting the maximum bet number (3 in any game state in the present embodiment) among the specified number of bets determined according to the game state within the range. The settlement switch 10 that is operated when the medals stored as credits and the medals used for setting the number of bets are settled (the medals used for setting the credits and the number of bets are returned), and the game is started. Start switch 7 that is operated at the time, and stop switches 8L, 8C, and 8R that are operated when the rotation of the reels 2L, 2C, and 2R is stopped, respectively, for performance. Use the switch 56 are respectively provided so as to be operated by the player.

  In this embodiment, among the three reels 2L, 2C, and 2R that have started to rotate, the reel that stops first is referred to as a first stop reel, and the stop is referred to as a first stop. Similarly, the reel that stops second is called the second stop reel, the stop is called second stop, the reel that stops third is called the third stop reel, and the stop is the third stop. Alternatively, it is called final stop.

  Further, as shown in FIG. 1, the front door 1b shows a credit indicator 11 for displaying the number of medals stored as credits, the number of medals paid out due to the occurrence of a winning, and the contents when an error occurs. An auxiliary game indicator 12 for displaying an error code or the like, 1 BETLED 14 for informing that the bet number is set to 1 by lighting, 2 BETLED 15 for informing that the bet number is set to 2, and 3 betting numbers being set A 3BET LED 16 for notifying that the game has been performed, an insertion request LED 17 for notifying that a medal can be inserted by lighting, and a start valid LED 18 for notifying that the game start operation by operating the start switch 7 is effective. , Wait (reel rotation starts because a certain period has not elapsed since the start of the previous game Waiting to have state) in wait for notifying by lighting the effect that in LED 19, a game display section 13 in the replay LED20 is provided for informing it is provided by lighting the effect that during replay game, which will be described later.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying that the setting operation of the bet amount by the operation of the MAXBET switch 6 is valid, and stop switches 8L, 8C, The left, middle, and right stop valid LEDs 22L, 22C, and 22R (see FIG. 4) are provided inside the 8R to notify that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is valid by lighting. It has been.

  Further, below the stop switches 8L, 8C, and 8R on the front door 1b, a lower panel on which a title of the slot machine 1 and a payout table 1 to be described later are printed is provided.

  As shown in FIG. 2, a reset switch 23 (see FIG. 4) for detecting a reset operation for releasing an error state described later and a stop state described later by a predetermined key operation is provided inside the front door 1b. The setting value display 24 displays the setting value at that time while the setting value to be changed or the confirmation of the setting value is being confirmed, and the progress of the game is regulated until a reset operation is performed at the end of the BB described later. A stop switch 36a for selecting whether to enable / disable the stop function controlled to the state), automatic settlement processing at the end of BB described later (medal stored as credits is settled (returned) regardless of the player's operation) The automatic settlement switch 36b for selecting the validity / invalidity of the automatic settlement function to be controlled), and the flow path of medals inserted from the medal insertion section 4 are provided in the housing 1a, which will be described later. A flow path switching solenoid 30 (see FIG. 4) for selectively switching to either the upper tank 34a side or the medal payout exit 9 side, and a medal that has been inserted from the medal insertion unit 4 and has flowed to the hopper tank 34a side is detected. A medal selector 29 having an inserted medal sensor 31 (see FIG. 4) and a door open detection switch 25 (see FIG. 4) for detecting the open state of the front door 1b are provided.

  As shown in FIG. 2, the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R (see FIG. 4), and the reel reference positions of the reels 2L, 2C, and 2R are detected inside the housing 1a. A reel unit 2 including possible reel sensors 33L, 33C, and 33R (see FIG. 4), an external output board 1000 (see FIG. 4) for outputting an external output signal, and a medal inserted from the medal insertion unit 4 are stored. A hopper tank 34a, a hopper motor 34b for paying out medals stored in the hopper tank 34a from the medal payout opening 9 (see FIG. 4), and a payout sensor 34c for detecting the medals paid out by driving the hopper motor 34b (see FIG. 4). 4) and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, there is provided a full sensor 35a (see FIG. 4) consisting of a pair of conductive members spaced left and right provided at a height capable of detecting a predetermined amount of stored medal. The amount of medals stored in the interior when the member is electrically connected by contacting the medal stored in the overflow tank 35 exceeds a predetermined amount, that is, the overflow tank is full. Can be detected.

  As shown in FIG. 2, a function key switch 37 for switching to a setting change state or a setting confirmation state is provided on the front surface of the power supply box 100, and functions as a reset switch for canceling an error state or a stop state in normal times. In the setting change state, a reset / setting switch 38 that functions as a setting switch for changing a setting value of a winning probability (outtake rate) of internal lottery described later, and a power source that is operated when turning on / off the power source A switch 39 is provided.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or a bet number is set using credits. To use the credit, the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the winning line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the state where the game can be started. Become. In the present embodiment, when the prescribed number of bets is set to three regardless of the gaming state and the prescribed number of bets is set, the pay line LN becomes valid. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In this embodiment, as shown in FIG. 1, only the winning line LN set across the symbols arranged in the horizontal direction in the middle stage of the reel 2L, the middle stage of the reel 2C, the middle stage of the reel 2R, that is, the middle stage, is used as the winning line. It has been established. In this embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

  In the present embodiment, invalid lines LM1 to LM1-4 are set apart from the winning line LN in order to make it easy to recognize that the winning line LN has a combination of symbols constituting the winning line. The invalid lines LM1 to LM4 are not determined based on the combination of symbols aligned with the invalid lines LM1 to LM4. When the combination of symbols constituting a specific prize is arranged on the winning line LN, the invalid line LM1 to LM4. When a combination of symbols (for example, bell-bell-bell) is awarded when the winning line LN is aligned with any of the LM1 to LM4, the symbols constituting the particular winning line LN It is easy to recognize that the combination is complete. In this embodiment, as shown in FIG. 1, an invalid line LM1 and a lower stage of the reel 2L, which are set across the symbols arranged horizontally in the upper stage of the reel 2L, the upper stage of the reel 2C, the upper stage of the reel 2R, that is, the upper stage. , The lower stage of the reel 2C, the lower stage of the reel 2R, that is, the invalid line LM2 set across the symbols arranged horizontally in the lower stage, the upper stage of the reel 2L, the middle stage of the reel 2C, the lower stage of the reel 2R, that is, the lower side There are four types of invalid lines LM3 set across straddling symbols LM3, lower stage of reel 2L, middle stage of reel 2C, upper stage of reel 2R, that is, invalid line LM4 set straddling to the right. It is defined as.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  Then, when all the reels 2L, 2C, 2R are stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a role) is displayed on the reels 2L, 2C, 2R on the winning line LN. If the game stops as a result, a winning occurs, and a predetermined number of medals are given to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, when the combination of symbols accompanying the transition of the gaming state on the winning line LN is stopped as a display result of each reel 2L, 2C, 2R, the gaming state according to the combination of symbols is shifted. .

  In the present embodiment, a configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, a configuration using four or more reels may be used. In a configuration using two or more reels, a winning determination may be made based on a combination of display results derived for all two or more reels.

  In the slot machine 1 according to the present embodiment, after the game is started and the reels 2L, 2C, and 2R are rotated and the symbols start to change, any one of the stop switches 8L, 8C, and 8R is operated. When this is done, the rotation of the reels corresponding to the stop switches 8L, 8C, 8R is stopped, and the symbols are stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

  The reels 2L, 2C and 2R rotate 80 times per minute, and 80 × 21 (the number of symbols per reel) = 1680 frames, so the maximum of 4 symbols is drawn in 190 ms. Will be able to. In other words, the symbols that can be selected as the stop symbols are the symbols that are displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols that are four frames ahead of them, for a total of five symbols.

  For this reason, for example, when any one of the stop switches 8L, 8C, 8R is operated and the symbol displayed on the lower stage of the reel corresponding to the stop switch is used as a reference, the symbol from the symbol to four frames ahead is used. Since the symbols can be displayed in the lower row, in each of the reels 2L, 2C, 2R, when any one of the stop switches 8L, 8R is operated, the symbol displayed in the middle row of the reel corresponding to the stop switch. The symbols arranged within 5 frames including can be displayed on the winning line.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the game control board 40 are generated. It is supplied to the production control board 90 connected through the. In addition, a command transmission line from the main control unit 41 to the sub control unit 91, which will be described later, and a power supply line for supplying power from the game control board 40 to the effect control board 90 are connected via a single cable and connector. Are connected to each other, and all the connectors that connect these cables and the respective boards are connected to each other so that the respective parts on the side of the effect control board 90 can operate and receive commands from the main control part 41. Become. For this reason, unless the command transmission line for transmitting a command from the main control unit 41 is connected to the effect control board 90, power is not supplied to the effect control board 90, and only the effect control board 90 side operates. There is no end to it. The power supply line for supplying power to the effect control board is directly connected from the power supply board 101 to the effect control board 90 without going through the game control board 40, and the power supply board 101 directly supplies power to the effect control board 90. May be supplied.

  Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

  On the game control board 40, the above-described MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, stop switch 36a, automatic settlement switch 36b, insertion medal sensor 31, door open The detection switch 25 and reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, setting key switch 37, and reset / setting switch 38 are connected via the power supply board 101. Detection signals from these connected switches are input.

  Further, the game control board 40 includes the credit indicator 11, the game auxiliary indicator 12, 1-3 BET LEDs 14-16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, the BET switch valid LED 21, the left The middle and right stop valid LEDs 22L, 22C and 22R, the set value display 24, the flow path switching solenoid 30, the reel motors 32L, 32C and 32R are connected, and the hopper motor 34b described above is connected via the power supply board 101. These electrical components are connected, and are driven based on control of a main control unit 41 (described later) mounted on the game control board 40.

  The game control board 40 includes a main control unit 41, a control clock generation circuit 42, a random number clock generation circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, and a power interruption detection circuit. 48 and a reset circuit 49 are mounted.

  The main control unit 41 is composed of a one-chip microcomputer, and includes a ROM 41b for storing a game control (game progress control) program and the like, a RAM 41c used as a work memory, and a CPU 41a for performing a control operation according to the program. In addition to performing processing related to the progress of the game, each part of the control circuit mounted on the game control board 40 is controlled directly or indirectly.

  The main control unit 41 further includes random number circuits 508a and 508b that generate hardware random numbers (random numbers generated by the hardware circuit).

  In addition, since the CPU 41a executes control according to the program stored in the ROM 41b in the main control unit 41, hereinafter, the main control unit 41 (or CPU 41a) will execute (or perform processing) specifically. Is that the CPU 41a executes control according to the program. The same applies to the sub-control unit 91 described later. However, as will be described later, when the power to the slot machine 1 is turned on or a system reset occurs, the main control unit 41 sets the internal reset operation, the random number circuits 508a and 508b, and the register according to the setting contents of the program management area. The main control unit 41 executes this setting operation by hardware without using a program.

  The RAM 41c is a backup RAM as a nonvolatile storage means that is partially or entirely backed up by a backup power source. That is, even if the power supply to the slot machine 1 is stopped, a part or all of the contents of the RAM 41c is stored for a predetermined period (until the backup power supply cannot be supplied because the capacitor as the backup power supply is discharged). . And when it recovers after a power failure etc. arises, based on the data, it becomes possible to recover a control state before the occurrence of a power failure etc. In the present embodiment, the entire RAM 41c is backed up.

  The control clock generation circuit 42 generates a control clock CCLK serving as an oscillation signal having a predetermined frequency outside the main control unit 41. The control clock CCLK generated by the control clock generation circuit 42 is supplied to the clock circuit 502 via, for example, a control external clock terminal of the main control unit 41 as shown in FIG. The random number clock generation circuit 43 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the main control unit 41. The random number clock RCLK generated by the random number clock generation circuit 43 is supplied to the random number circuits 508a and 508b via a random number external clock terminal (RCK terminal) of the main control unit 41 as shown in FIG. Is done. As an example, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 may be set to be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42. Alternatively, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 may be higher than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42.

  In the present embodiment, a case where the dedicated random number clock RCLK is input from the random number clock generation circuit 43 to the random number circuits 508a and 508b is shown, but the present invention is not limited thereto. For example, instead of using a dedicated clock, the control clock CCLK from the control clock generation circuit 42 may be input to the random number circuits 508 a and 508 b inside the main control unit 41. In this case, for example, a random number counter (random number generation circuits 525a and 525b to be described later) built in the random number circuits 508a and 508b may be updated using a signal obtained by dividing the control clock CCLK. In this case, the random number clock generation circuit 43 may not be provided on the game control board 40.

  The switch detection circuit 44 takes in detection signals input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits them to the main control unit 41. The motor drive circuit 45 transmits the motor drive signal output from the main control unit 41 to the reel motors 32L, 32C, and 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40. The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1 and outputs a voltage drop signal indicating that to the main control unit 41 when a voltage drop is detected. The reset circuit 49 provides a system reset signal to the main control unit 41 in a state where the power is unstable, such as when the power is turned on or when the power is turned off.

  FIG. 5 shows a configuration example of the main control unit 41 mounted on the game control board 40. The main control unit 41 shown in FIG. 5 is a one-chip microcomputer, and the main control unit 41 shown in FIG. 5 is an external bus interface 501, a clock circuit 502, a verification block 503, and a unique information storage circuit 504. , An arithmetic circuit 505, a reset / interrupt controller 506, a CPU (Central Processing Unit) 56, a ROM (Read Only Memory) 54, a RAM (Random Access Memory) 55, a free-run counter circuit 507, and a random number circuit 508a. 508b, a timer circuit 509, an interrupt controller 510, a parallel input port 511, a serial communication circuit 512, a parallel output port 513, and an address decoding circuit 514.

  In addition, the random number circuits mounted on the main control unit 41 include an 8-bit random number circuit 508a that generates an 8-bit random number and a 16-bit random number circuit 508b that generates a 16-bit random number. In the example shown in FIG. 5, an 8-bit random number circuit 508a and a 16-bit random number circuit 508b for generating a 16-bit random number are illustrated one by one. However, the main control unit 41 includes an 8-bit random number circuit 508a and a 16-bit random number circuit 508a. The 16-bit random number circuit 508b for generating 16-bit random numbers is mounted on each of four circuits (four channels). In this embodiment, the four channels of the 8-bit random number circuit 508a may be expressed as RS0 to RS3, respectively, and the four channels of the 16-bit random number circuit 508b may be expressed as RL0 to RL3, respectively.

  The reset / interrupt controller 506 also includes an out-of-designated area prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit that monitors whether the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when it is detected that the user program is executed outside the designated area. The watchdog timer 506b has a function of generating a time-out signal for each set period.

  FIG. 6 shows an example of an address map in the main control unit 41. As shown in FIG. 6, the area from address 0000H to address 2FFFH is allocated to the ROM 41b of the main control unit 41 and includes a program code / data area (an area for storing user programs and data) and a program management area. . FIG. 7 shows an example of the usage and contents of the main part of the program management area in the ROM 41b. The area from address F000H to address F3FFH is allocated to the RAM 41c of the main control unit 41. An area from address FE00H to address FEBFH is a built-in register area assigned to the built-in register of the main control unit 41. 8 to 10 show examples of uses and contents of the main part of the built-in register area. The area from the address FED0H to the address FEFDH is an XCS / XCSE decode area allocated to the address decode circuit 514.

  The program management area is a storage area for storing information necessary for the main control unit 41 to perform various settings such as internal reset operation settings and random number circuits 508a and 508b during system reset. As shown in FIG. 7, the program management area includes a header (KHDR), a program code end address (KPCE), a program code start address 2 (KPCS2), a program code end address 2 (KPCE2), a reset setting (KRES), 16-bit random number initial setting 1 (KRL1), 16-bit random number initial setting 2 (KRL2), 16-bit random number initial setting 3 (KRL3), 8-bit random number initial setting 1 (KRS1), 8-bit random number initial setting 2 (KRS2), Security time setting (KSES), random number clock monitoring setting (KRCS), and the like are included. As shown in FIGS. 8 to 10, the built-in register area includes an internal information register (CIF), various registers used in the random number circuits 508a and 508b, and the like.

  The header (KHDR) stored in the program management area indicates the setting of an 8-byte code string indicating the start of the program management area and the reading setting of internal data in the main control unit 41. FIG. 11 illustrates the correspondence between the setting data and the operation in the header (KHDR). Here, the main control unit 41 can set a ROM read prevention function and a bus output mask function. The ROM read prevention function is a function for permitting or prohibiting the read operation for the data stored in the ROM 41b included in the main control unit 41, and the read data stored in the ROM 41b cannot be read in a state where the read prohibition is set. The bus output mask function is used for address bus output, data bus output, and control signal output in the external bus interface 501 when an external device connected to the external bus interface 501 makes a read request for internal data of the main control unit 41. This function disables reading of internal data from an external device by applying a mask. As shown in FIG. 11, in accordance with setting data set as an 8-byte code string indicating the start of the program management area, the operation combinations of the ROM read prevention function and the bus output mask function are set to be different. Of the setting data shown in FIG. 11, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data.

  The program code end address (KPCE) stored in the program management area indicates the setting of the final address of the program code area that continues from 0000H of the user program. FIG. 12A shows an example of setting contents in the program code end address (KPCE).

  In this embodiment, two program code areas can be set in the program code / data area from address 0000H to address 2FBFH. Specifically, the first program code area can be set as an area from address 0000H to the address set by the program code end address (KPCE), and the second program code area is the program code start It can be set as an area from the address set by address 2 (KPCS2) to the address set by program code end address 2 (KPCE2). Hereinafter, the program code stored in the first program code area is also referred to as program code 1, and the program code stored in the second program code area is also referred to as program code 2.

  As shown in FIG. 12A, the lower address of the final address of the program code 1 is set in the address 2FD3H of the program code end address (KPCE). In addition, the upper address of the final address of the program code 1 is set in the address 2FD4H.

  Program code start address 2 (KPCS2) stored in the program management area indicates the setting of the start address of the second program code area when the user program is divided into two blocks. FIG. 12B shows an example of setting contents at the program code start address 2 (KPCS2).

  As shown in FIG. 12B, the lower address of the head address of the program code 2 is set in the address 2FD5H of the program code start address 2 (KPCS2). In addition, the upper address of the head address of the program code 2 is set in the address 2FD6H. If the program code area is not divided into two, 0000H may be set to address 2FD5H and address 2FD6H of program code start address 2 (KPCS2).

  The program code end address 2 (KPCE2) stored in the program management area indicates the setting of the final address of the second program code area when the user program is divided into two blocks. FIG. 12C shows an example of setting contents in the program code end address 2 (KPCE2).

  As shown in FIG. 12C, the lower address of the final address of the program code 2 is set in the address 2FD7H of the program code end address 2 (KPCE2). In addition, the upper address of the final address of the program code 2 is set in the address 2FD8H. If the program code area is not divided into two, 0000H may be set to address 2FD7H and address 2FD8H of program code end address 2 (KPCE2).

  The setting contents of the program code end address (KPCE), the program code start address 2 (KPCS2), and the program code end address 2 (KPCE2) shown in FIG. 12 are executed correctly in the designated area by the IAT circuit 506a. Referenced when monitoring whether or not. That is, the IAT circuit 506a designates from 0000H to the address indicated by the program code end address (KPCE) or from the address indicated by the program code start address 2 (KPCS2) to the address indicated by the program code end address 2 (KPCE2). It is determined whether or not the user program is being executed within the range, and an IAT signal is output based on the detection that the user program is being executed outside the specified range.

  The reset setting (KRES) stored in the program management area indicates an internal reset operation or operation permission / prohibition setting of the watchdog timer (WDT) 506b. FIG. 13 shows an example of setting contents in the reset setting (KRES).

  Bit [7] of reset setting (KRES) is reset internally when a time-out signal is input from watchdog timer (WDT) 506b or when an IAT occurs (when an IAT signal is input from IAT circuit 506a) It shows the setting of the operation when this occurs. In the example shown in FIG. 13, if the bit value in the reset setting (KRES) bit [7] is “0”, a user reset occurs when a time-out signal or an IAT signal is input. On the other hand, if the bit value in the reset setting (KRES) bit [7] is “1”, a system reset occurs when a time-out signal or an IAT signal is input.

  Bit [6] of the reset setting (KRES) indicates the setting of the activation method of the watchdog timer (WDT) 506b. In the example shown in FIG. 13, if the bit value of the reset setting (KRES) bit [6] is “0”, the watch is automatically activated based on the transition to the user mode when a reset occurs regardless of the user program. The dog timer (WDT) 506b is activated and time measurement is started. On the other hand, if the bit value in bit [6] of the reset setting (KRES) is “1”, the watchdog timer (WDT) 506b is activated by the software (user program) after the transition to the user mode. Measurement starts.

Bit [5-4] of the reset setting (KRES) indicates the setting of the reference clock signal of the watchdog timer (WDT) 506b. In the example illustrated in FIG. 13, when “00” is set in the bit [5-4] of the reset setting (KRES), 2 ¹⁵ × TSCLK is selected as the reference clock signal. Further, when “01” is set in the reset setting (KRES) bit [5-4], 2 ¹⁹ × TSCLK is selected as the reference clock signal. Further, when “10” is set in the bit [5-4] of the reset setting (KRES), 2 ²² × TSCLK is selected as the reference clock signal. Further, when “11” is set in the bit [5-4] of the reset setting (KRES), 2 ²⁵ × TSCLK is selected as the reference clock signal. SCLK indicates an internal system clock of the main control unit 41, and TSCLK indicates 1 / SCLK.

Bits [3-0] of the reset setting (KRES) indicate the setting of the timeout time of the watchdog timer (WDT) 506b. Specifically, the time-out period of the watchdog timer (WDT) 506b is set to the reference clock selected by the bit [5-4] of the reset setting (KRES) using the bits [3-0] of the reset setting (KRES). It is a value obtained by multiplying the set value. For example, when “1000” is set to the bit [3-0] of the reset setting (KRES) (that is, the value “8” is set), “00” is set to the bit [5-4] of the reset setting (KRES). When set, the timeout time is 2 ¹⁵ × TSCLK × 8, and when reset setting (KRES) bit [5-4] is set to “01”, the timeout time is 2 ¹⁹ × TSCLK × 8. When the reset setting (KRES) bit [5-4] is set to “10”, the timeout time is 2 ²² × TSCLK × 8, and the reset setting (KRES) bit [5-4] is set to “11”. If you set ", the timeout time is ^{2 25} × TSCLK × 8. Further, when “1111” is set to the bit [3-0] of the reset setting (KRES) (that is, the value “15” is set), “00” is set to the bit [5-4] of the reset setting (KRES). When set, the timeout time is 2 ¹⁵ × TSCLK × 15. When the reset setting (KRES) bit [5-4] is set to “01”, the timeout time is 2 ¹⁹ × TSCLK × 15. When the reset setting (KRES) bit [5-4] is set to “10”, the timeout time is 2 ²² × TSCLK × 15, and the reset setting (KRES) bit [5-4] is set to “11”. If set to "the timeout time is ^{2 25} × TSCLK × 15. FIG. 13 also shows specific examples of timeout values when the internal system clock is 10.0 MHz and 12.0 MHz.

  When setting not to use the watchdog timer (WDT) 506b, as shown in FIG. 13, it is only necessary to set “0000” in bits [3-0] of the reset setting (KRES). However, even if the reset setting (KRES) bit [3-0] is set to “0000” and the watchdog timer (WDT) 506b is disabled, the reset setting (KRES) bit By setting the value of [7], it is possible to set whether to perform system reset or user reset.

  16-bit random number initial setting 1 (KRL1), 16-bit random number initial setting 2 (KRL2), and 16-bit random number initial setting 3 (KRL3) stored in the program management area indicate settings of the 16-bit random number circuit 508b. FIG. 14 shows an example of setting contents in 16-bit random number initial setting 1 (KRL1). FIG. 15 shows an example of setting contents in 16-bit random number initial setting 2 (KRL2). Further, FIG. 16 shows an example of setting contents in 16-bit random number initial setting 3 (KRL3).

  First, the setting contents in 16-bit random number initial setting 1 (KRL1) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 1 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 14, if the bit value of the bit “7” of the 16-bit random number initial setting 1 (KRL1) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. As a result, the 16-bit random number circuit 508b of channel 1 is activated. On the other hand, if the bit value in bit “7” of 16-bit random number initial setting 1 (KRL1) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 1 is activated.

  Bit “6” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 1. In the example shown in FIG. 14, if the bit value of bit “6” of 16-bit random number initial setting 1 (KRL1) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 16-bit random number initial setting 1 (KRL1) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  In this embodiment, the random number clock RCLK generated by the random number clock generation circuit 43 already described is input via the random number external clock terminal (RCK terminal), and the random number clock RCLK is divided by two. The signal is used as an update clock. The same applies to the 16-bit random number circuit 508b and the 8-bit random number circuit 508a of other channels.

  Bit “5-4” of 16-bit random number initial setting 1 (KRL1) indicates whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 1. In the example shown in FIG. 14, if the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is not changed. . If the bit value in bit “5-4” of 16-bit random number initial setting 1 (KRL1) is “01”, the random number sequence updated by 16-bit random number circuit 508b of channel 1 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 0 among the 16-bit random number circuit 508b of 4 channels. In the example shown in FIG. 14, if the bit value in the bit “3” of the 16-bit random number initial setting 1 (KRL1) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. Is activated, the channel 0 16-bit random number circuit 508b is activated. On the other hand, if the bit value in bit “3” of 16-bit random number initial setting 1 (KRL1) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 0 is activated.

  Bit “2” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 0. In the example illustrated in FIG. 14, if the bit value in the bit “2” of the 16-bit random number initial setting 1 (KRL1) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 1 (KRL1) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bits “1-0” of 16-bit random number initial setting 1 (KRL1) indicate whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 0. In the example shown in FIG. 14, if the bit value in the bit “1-0” of 16-bit random number initialization 1 (KRL1) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of channel 0 is not changed. . If the bit value in bits “1-0” of 16-bit random number initialization 1 (KRL1) is “01”, the random number sequence updated by the 16-bit random number circuit 508b of channel 0 is changed by software (user program). it can. If the bit value in the bit “1-0” of the 16-bit random number initial setting 1 (KRL1) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 0 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 16-bit random number initial setting 1 (KRL1) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 0 is automatically started from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Next, setting contents in 16-bit random number initial setting 2 (KRL2) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 3 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 15, if the bit value in bit “7” of 16-bit random number initial setting 2 (KRL2) is “0”, the maximum random number is set by software (user program) after shifting to the user mode. Is activated, the 16-bit random number circuit 508b of channel 3 is activated. On the other hand, if the bit value in bit “7” of 16-bit random number initial setting 2 (KRL2) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 3 is activated.

  Bit “6” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 3. In the example shown in FIG. 15, if the bit value of bit “6” of 16-bit random number initialization 2 (KRL2) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 16-bit random number initial setting 2 (KRL2) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bit “5-4” of 16-bit random number initial setting 2 (KRL2) indicates whether or not the random number sequence updated by the 16-bit random number circuit 508b of channel 3 is changed. In the example shown in FIG. 15, if the bit value in the bit “5-4” of the 16-bit random number initialization 2 (KRL2) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is not changed. . If the bit value in bit “5-4” of 16-bit random number initialization 2 (KRL2) is “01”, the random number sequence updated by 16-bit random number circuit 508b of channel 3 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 16-bit random number initial setting 2 (KRL2) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in bit “5-4” of 16-bit random number initialization 2 (KRL2) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of channel 3 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 2 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 15, if the bit value in the bit “3” of the 16-bit random number initial setting 2 (KRL2) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. Is activated, the 16-bit random number circuit 508b of channel 2 is activated. On the other hand, if the bit value in the bit “3” of the 16-bit random number initial setting 2 (KRL2) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 2 is activated.

  Bit “2” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 2. In the example shown in FIG. 15, if the bit value of bit “2” of 16-bit random number initial setting 2 (KRL2) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 2 (KRL2) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bits “1-0” of 16-bit random number initial setting 2 (KRL2) indicate whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 2. In the example shown in FIG. 15, if the bit value in the bit “1-0” of 16-bit random number initialization 2 (KRL2) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is not changed. . If the bit value in bit “1-0” of 16-bit random number initialization 2 (KRL2) is “01”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is changed by software (user program). it can. If the bit value in bit “1-0” of 16-bit random number initialization 2 (KRL2) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is automatically updated from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 16-bit random number initial setting 2 (KRL2) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 2 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Next, setting contents in 16-bit random number initial setting 3 (KRL3) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 3 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value at bit “7” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “7” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the main control unit 41 is used as the start value for the first round of random number update. The value set to is used. Since the ID number of the main control unit 41 is different for each chip, it is possible to make it difficult to predict the update timing of the random number by using a value based on the ID number as the start value, and aim for the update timing of the random number. Thus, it is possible to prevent acts that illegally generate jackpots. The ID number itself may be used as a value based on the ID number, or a predetermined calculation (for example, a value obtained by adding or subtracting a predetermined value) may be used for the ID number.

  Bit “6” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 3 is changed at every system reset. In the example shown in FIG. 16, if the bit value in bit “6” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in bit “6” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  Bit “5” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 2 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value at bit “5” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “5” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the main control unit 41 is used as the start value for the first round of random number update. The value set to is used.

  Bit “4” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 2 is changed at every system reset. In the example shown in FIG. 16, if the bit value in bit “4” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in bit “6” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  Bit “3” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 1 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value in bit “3” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “3” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the main control unit 41 is used as the start value for the first round of random number update. The value set to is used.

  Bit “2” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 1 is changed at every system reset. In the example shown in FIG. 16, if the bit value in bit “2” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  Bit “1” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 0 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value at bit “1” of 16-bit random number initialization 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value of the bit “1” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the main control unit 41 is used as the start value for the first round of random number update. The value set to is used.

  Bit “0” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 0 is changed at every system reset. In the example shown in FIG. 16, if the bit value in bit “0” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in bit “0” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  The 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) stored in the program management area indicate settings of the 8-bit random number circuit 508a. FIG. 17 shows an example of setting contents in the 8-bit random number initial setting 1 (KRS1). FIG. 18 shows an example of setting contents in the 8-bit random number initial setting 2 (KRS2).

  First, the setting contents in 8-bit random number initial setting 1 (KRS1) will be described with reference to FIG. Bit “7” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 1 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 17, if the bit value in the bit “7” of the 8-bit random number initial setting 1 (KRS1) is “0”, after entering the user mode, the maximum random number value is set by software (user program). As a result, the 8-bit random number circuit 508a of channel 1 is activated. On the other hand, if the bit value in the bit “7” of the 8-bit random number initial setting 1 (KRS1) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 8-bit random number circuit 508a of channel 1 is activated.

  Bit “6” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 1. In the example shown in FIG. 17, if the bit value of bit “6” of 8-bit random number initial setting 1 (KRS1) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 8-bit random number initial setting 1 (KRS1) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bit “5-4” of 8-bit random number initial setting 1 (KRS1) indicates whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 1. In the example shown in FIG. 17, if the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is not changed. . If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of channel 1 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 0 out of the 4-channel 8-bit random number circuit 508a. In the example shown in FIG. 17, if the bit value in the bit “3” of the 8-bit random number initial setting 1 (KRS1) is “0”, after entering the user mode, the maximum random number value is set by software (user program). As a result, the 8-bit random number circuit 508a of channel 0 is activated. On the other hand, if the bit value in the bit “3” of the 8-bit random number initial setting 1 (KRS1) is “1”, regardless of the user program, it is automatically based on the transition to the user mode when a reset occurs. Then, the 8-bit random number circuit 508a of channel 0 is activated.

  Bit “2” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 0. In the example shown in FIG. 17, if the bit value in the bit “2” of the 8-bit random number initial setting 1 (KRS1) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 8-bit random number initial setting 1 (KRS1) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bits “1-0” of 8-bit random number initial setting 1 (KRS1) indicate whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 0. In the example shown in FIG. 17, if the bit value in the bit “1-0” of the 8-bit random number initial setting 1 (KRS1) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 0 is not changed. . If the bit value in bits “1-0” of 8-bit random number initial setting 1 (KRS1) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of channel 0 is changed by software (user program). it can. If the bit value in the bit “1-0” of the 8-bit random number initial setting 1 (KRS1) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 0 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in bits “1-0” of the 8-bit random number initial setting 1 (KRS1) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of channel 0 is automatically started from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Next, setting contents in the 8-bit random number initial setting 2 (KRS2) will be described with reference to FIG. Bit “7” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 3 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 18, if the bit value in the bit “7” of the 8-bit random number initial setting 2 (KRS2) is “0”, after the transition to the user mode, the maximum random number is set by software (user program). Is activated, the 8-bit random number circuit 508a of channel 3 is activated. On the other hand, if the bit value in the bit “7” of the 8-bit random number initial setting 2 (KRS2) is “1”, regardless of the user program, it is automatically based on the transition to the user mode when a reset occurs. Then, the 8-bit random number circuit 508a of channel 3 is activated.

  Bit “6” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the update clock of the 8-bit random number circuit 508a of the channel 3. In the example shown in FIG. 18, if the bit value of bit “6” of 8-bit random number initial setting 2 (KRS2) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 8-bit random number initial setting 2 (KRS2) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is obtained. Used as an update clock.

  Bit “5-4” of 8-bit random number initial setting 2 (KRS2) indicates whether or not the random number sequence updated by the 8-bit random number circuit 508a of channel 3 is changed. In the example shown in FIG. 18, if the bit value in the bit “5-4” of the 8-bit random number initialization 2 (KRS2) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is not changed. . If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is automatically updated from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is automatically started from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 2 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 18, if the bit value in the bit “3” of the 8-bit random number initial setting 2 (KRS2) is “0”, after the transition to the user mode, the maximum random number is set by software (user program). Is activated, the channel 2 8-bit random number circuit 508a is activated. On the other hand, if the bit value in the bit “3” of the 8-bit random number initial setting 2 (KRS2) is “1”, regardless of the user program, it is automatically based on the transition to the user mode when a reset occurs. Then, the 8-bit random number circuit 508a of channel 2 is activated.

  Bit “2” of 8-bit random number initial setting 2 (KRS2) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 2. In the example shown in FIG. 18, if the bit value of bit “2” of 8-bit random number initial setting 2 (KRS2) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 8-bit random number initial setting 2 (KRS2) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is obtained. Used as an update clock.

  Bits “1-0” of 8-bit random number initial setting 2 (KRS2) indicate whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 2. In the example shown in FIG. 18, if the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 2 is not changed. . If the bit value in bits “1-0” of the 8-bit random number initial setting 2 (KRS2) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of channel 2 is changed by software (user program). it can. Further, if the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 2 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 2 is automatically set from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Note that the 8-bit random number circuit 508a does not have a function for setting a start value as shown in FIG. 16, unlike the 16-bit random number circuit 508b.

  The security time setting (KSES) stored in the program management area indicates a time setting for extending the security mode. FIG. 19 shows an example of setting contents in the security time setting (KSES).

  Bit [7-6] of the security time setting (KSES) indicates the setting of the time for extending the security mode time at random. In the example shown in FIG. 19, when “01” is set in the bit [7-6] of the security time setting (KSES), the short mode is set as a mode for extending the security mode time at random. Specifically, when the internal system clock is 10.0 MHz, the time in the range of 0 to 0.816 ms is randomly extended, and when the internal system clock is 12.0 MHz, the range of 0 to 0.51 ms. The time is extended randomly. Further, when “10” is set in the bit [7-6] of the security time setting (KSES), the middle mode is set as a mode in which the security mode time is randomly extended. When the system clock is 10.0 MHz, the time in the range of 0 to 26.112 ms is randomly extended, and when the internal system clock is 12.0 MHz, the time in the range of 0 to 16.32 ms is randomly selected. Extended. Further, when “11” is set in the bit [7-6] of the security time setting (KSES), the long mode is set as a mode for randomly extending the security mode time. When the system clock is 10.0 MHz, the time in the range of 0 to 855.584 ms is randomly extended, and when the internal system clock is 12.0 MHz, the time in the range of 0 to 522.24 ms is randomly selected. Extended.

  When setting so as not to perform random extension of the security mode time, as shown in FIG. 19, “00” may be set in bits [7-6] of the security time setting (KSES).

Bit [5] of the security time setting (KSES) indicates the setting of the reference clock signal for the time for fixing and extending the security mode time. In the example shown in FIG. 19, when “0” is set in bit [5] of the security time setting (KSES), 2 ²² × TSCLK is selected as the reference clock signal. When “1” is set in bit [5] of the security time setting (KSES), 2 ²⁴ × TSCLK is selected as the reference clock signal.

Bits [4-0] of the security time setting (KSES) indicate a time setting for extending the security mode time in a fixed manner. Specifically, the fixed extension time of the security mode time is the set value set by the bit [4-0] of the security time setting (KSES) to the reference clock selected by the bit [5] of the security time setting (KSES). Is the value multiplied by. For example, when “00001” is set in the bit [4-0] of the security time setting (KSES) (that is, the value “1” is set), “0” is set in the bit [5] of the security time setting (KSES). When set, the fixed extension time is 2 ²² × TSCLK × 1, and when “1” is set in bit [5] of the security time setting (KSES), the fixed extension time is 2 ²⁴ × TSCLK × 1. It becomes. Further, when “01000” is set in the bit [4-0] of the security time setting (KSES) (that is, the value “8” is set), “0” is set in the bit [5] of the security time setting (KSES). When set, the fixed extension time is 2 ²² × TSCLK × 8, and when “1” is set to bit [5] of the security time setting (KSES), the fixed extension time is 2 ²⁴ × TSCLK × 8. It becomes. Also, when “10000” is set to the bit [4-0] of the security time setting (KSES) (that is, the value “16” is set), “0” is set to the bit [5] of the security time setting (KSES). When set, the fixed extension time is 2 ²² × TSCLK × 16, and when the security time setting (KSES) bit [5] is set to “1”, the fixed extension time is 2 ²⁴ × TSCLK × 16. It becomes. Further, when “11111” is set to the bit [4-0] of the security time setting (KSES) (that is, the value “31” is set), “0” is set to the bit [5] of the security time setting (KSES). When set, the fixed extension time is 2 ²² × TSCLK × 31. When “1” is set to bit [5] of the security time setting (KSES), the fixed extension time is 2 ²⁴ × TSCLK × 31. It becomes. FIG. 19 also shows specific examples of fixed extension time values when the internal system clock is 10.0 MHz and 12.0 MHz.

  When setting so that the security mode time is not fixedly extended, “00000” may be set to bits [4-0] of the security time setting (KSES) as shown in FIG.

  As shown in FIG. 19, the security mode time is randomly extended by setting bit [7-6] of security time setting (KSES) and fixed extension by setting of bit [5-0] of security time setting (KSES). The extension can be set in two ways. And the addition time of the time set by these two types of methods becomes the extension time of the final security mode time.

  The random number clock monitoring setting (KRCS) stored in the program management area indicates the setting of the monitoring frequency of the external clock signal input from the random number external clock terminal (RCK terminal). FIG. 20 shows an example of setting contents in the random number clock monitoring setting (KRCS).

  Bit [7-2] of the random number clock monitoring setting (KRCS) is a fixed bit (that is, a bit that is not particularly used for setting), and all bits are always set to “0”.

Bits [1-0] of the random number clock monitoring setting (KRCS) are input clocks when an external clock signal input from the random number external clock terminal (RCK terminal) is selected as a clock for updating the random number. The setting of the frequency used as the detection target of frequency anomalies is shown. In the example shown in FIG. 20, when “00” is set in bits [1-0] of the random number clock monitoring setting (KRCS), the monitoring frequency is set to less than the frequency of SCLK (internal system clock). When “01” is set in bits [1-0] of the random number clock monitoring setting (KRCS), the monitoring frequency is set to less than the frequency of SCLK (internal system clock) / 2. Further, when "10" is set to bits [1-0] of the random number clock monitoring settings (KRCS) sets the frequency lower than the SCLK (internal system clock) / ^{2 2} as the monitoring frequency. Further, when "11" is set to bits [1-0] of the random number clock monitoring settings (KRCS) sets the SCLK frequency lower than the (internal system clock) / ^{2 3} as a monitoring frequency.

  When an abnormality in the monitoring frequency of the external clock signal input from the random number external clock terminal (RCK terminal) is detected, “1” is set in bit 3 of the internal information register (CIF) described later.

  In this embodiment, the main control unit 41 has a function of detecting an abnormal operation (external clock frequency abnormality) of the 16-bit random number circuit 508b out of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b. . Specifically, the main control unit 41 is set in the random number clock monitoring setting (KRCS) when the external clock signal input from the random number external clock terminal (RCK terminal) is selected as the random number update clock. Based on the monitored frequency, it is detected whether or not the frequency of the external clock signal has decreased, and when the frequency of the external clock signal has been decreased (external clock frequency abnormality), an internal information register (CIF) (to be described later) ) Is set to “1”.

  Further, the main control unit 41 has a function of monitoring the update state of the random number of the 16-bit random number circuit 508b, and when an abnormality is detected in the update state (for example, the random number value is not updated with the same value or is normally disturbed). When the value of the random number is counted up one by one but the value of the random number is suddenly increased by 2 or more), the corresponding bit of bits 7 to 4 of the internal information register (CIF) Set “1” to.

  This embodiment shows a case where the monitoring frequency of the external clock signal to be monitored is set for detection of an abnormal operation of the 16-bit random number circuit 508b by setting using the random number clock monitoring setting (KRCS). However, it may be configured to be able to set whether or not to detect the external clock frequency abnormality itself, or to be able to set whether or not to detect the update abnormality itself. In this case, it may be configured such that the setting of whether or not the external clock frequency abnormality detection itself is performed and the setting of whether or not the update abnormality detection itself is performed can be performed independently. It is also possible to configure such that only can be enabled or disabled collectively.

  In order to be able to set whether or not to detect the external clock frequency abnormality itself or whether or not to detect the update abnormality itself, for example, it is set whether or not to start the random number circuit itself. If the random number circuit is set not to start, the external clock frequency abnormality detection and update abnormality detection cannot be performed effectively, so the external clock frequency abnormality detection and update abnormality detection are not performed. It can be said that. As described above, setting whether or not to detect the external clock frequency abnormality itself or whether or not to detect the update abnormality itself includes realizing whether or not to start the random number circuit itself. It is a concept.

  In the present embodiment, a dedicated random number clock RCLK is externally input from the random number clock generation circuit 43 to the random number circuits 508a and 508b. For example, the control clock from the control clock generation circuit 42 Even when a clock other than the dedicated random number clock RCLK is externally input, such as when CCLK is externally input, it is possible to detect an external clock frequency abnormality or update abnormality. Regarding detection of update abnormality in the random number circuit, other clocks such as a random number update using a dedicated random number clock RCLK from the random number clock generation circuit 43 and a control clock CCLK from the control clock generation circuit 42 are used. It may be configured so that it can be set only in either of the cases where random number is updated by using.

  Further, in this embodiment, the abnormality of the external clock frequency is detected, and the abnormality of the frequency of the internal system clock SCLK of the main control unit 41 is not particularly detected, for the following reason. That is, when the internal system clock SCLK is used for updating the random number, the operation of the CPU 41a itself should have stopped in a situation where an abnormality has occurred in the internal system clock SCLK. However, there is no case where only the update of the random number is stopped, and there is no possibility that some problem will occur. On the other hand, when an external clock signal is used for the random number update, there is a possibility that only the update of the random number is stopped even though the CPU 41a is operating, which may cause an adverse effect. It is.

  The external bus interface 501 provided in the main control unit 41 shown in FIG. 5 is an interface function between the external bus and the internal bus of the chip constituting the main control unit 41, a direction control function of the address bus, the data bus, and each control signal, etc. Is a bus interface. For example, the external bus interface 501 is connected to an external memory or an external input / output device externally attached to the main control unit 41, and transmits / receives address signals, data signals, various control signals, and the like to / from these external devices. Anything to do.

  The clock circuit 502 included in the main control unit 41 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EX by two. The generated internal system clock is output from the external output terminal (CLKO terminal) to the outside.

  The verification block 503 provided in the main control unit 41 has a function of connecting to an external verification machine and performing chip verification.

  The unique information storage circuit 504 included in the main control unit 41 is a circuit that stores a plurality of types of unique information serving as internal information of the main control unit 41, for example. As an example, the unique information storage circuit 504 stores three kinds of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 41b code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 41b, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41. The ID number is an 8-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41. Here, it is sufficient that the chip individual number can be read from the user program while the ID number cannot be read from the user program. The unique information storage circuit 504 may be included in the ROM 41b by using a predetermined area of the ROM 41b, for example. Alternatively, the unique information storage circuit 504 may be included in the CPU 41a by using, for example, a built-in register of the CPU 41a.

  An arithmetic circuit 505 provided in the main control unit 41 is a circuit that performs multiplication and division.

  The reset / interrupt controller 506 provided in the main control unit 41 is for controlling various reset and interrupt requests generated inside or outside the main control unit 41. The reset controlled by the reset / interrupt controller 506 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period. In this embodiment, a system reset is also generated when a watchdog timer (WDT) time-out signal is generated or when travel outside the specified area is prohibited (IAT) due to the reset setting (KRES). There are things to do. The user reset is a reset that occurs due to a predetermined factor, such as a watchdog timer (WDT) time-out signal or a non-designated area travel prohibition (IAT).

  Interrupts controlled by the reset / interrupt controller 506 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 41a is in the interrupt disabled state, and is an interrupt that is generated when a low level signal is input to the external non-maskable interrupt terminal XNMI (also used as the input port PI6) for a certain period. is there. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 41a, and multiple interrupts can be executed by setting priority. The cause of the maskable interrupt INT is that a low level signal is input to the external maskable interrupt terminal XINT (also used as the input port PI5) for a certain period, a time-out occurs in the timer circuit 509, the serial communication circuit 512 Multiple types of interrupt factors may be determined in advance, such as the occurrence of an interrupt factor due to data reception or data transmission, or the occurrence of an interrupt factor due to the acquisition of numeric data that is a random value in the random number circuits 508a and 508b. It ’s fine.

  The reset / interrupt controller 506 controls interrupts and manages resets using the internal information register CIF (address FE25H) among the built-in registers provided in the main control unit 41 as shown in FIGS. The internal information register CIF is a register for managing a reset factor generated immediately before, reading a random number update state, and a state of an input frequency when the random number update clock is an external clock.

  FIG. 21A shows a configuration example of the internal information register CIF. FIG. 21B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF. The internal information data RL3ER stored in the bit number [7] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL3 updated by the 16-bit random number circuit 508b of the channel 3. In the example shown in FIG. 21B, when the update abnormality of the 16-bit random number RL3 is not detected, the bit value of the internal information data RL3ER becomes “0”, whereas when the update abnormality of the 16-bit random number RL3 is detected. The bit value is “1”. The internal information data RL2ER stored in the bit number [6] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL2 updated by the 16-bit random number circuit 508b of the channel 2. In the example shown in FIG. 21B, when the update abnormality of the 16-bit random number RL2 is not detected, the bit value of the internal information data RL2ER becomes “0”, while when the update abnormality of the 16-bit random number RL2 is detected. The bit value is “1”. The internal information data RL1ER stored in the bit number [5] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL1 updated by the 16-bit random number circuit 508b of the channel 1. In the example shown in FIG. 21B, when the update abnormality of the 16-bit random number RL1 is not detected, the bit value of the internal information data RL1ER becomes “0”, whereas when the update abnormality of the 16-bit random number RL1 is detected. The bit value is “1”. The internal information data RL0ER stored in the bit number [4] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL0 updated by the 16-bit random number circuit 508b of the channel 0. In the example shown in FIG. 21B, when the update abnormality of the 16-bit random number RL0 is not detected, the bit value of the internal information data RL0ER becomes “0”, whereas when the update abnormality of the 16-bit random number RL0 is detected. The bit value is “1”. The bit number [7-4] of the internal information register CIF is set to “0” as an initial value.

  The internal information data RCER stored in the bit number [3] of the internal information register CIF is obtained when the external clock signal input from the random number external clock terminal (RCK terminal) is selected as the random number update clock. Indicates a frequency error in the external clock signal. In the example shown in FIG. 21B, when the frequency abnormality of the external clock signal is not detected, the bit value of the internal information data RCER becomes “0”, while when the frequency abnormality of the external clock signal is detected, The bit value is “1”. The bit number [3] of the internal information register CIF is set to “0” as an initial value.

  The internal information data SRSF stored in the bit number [2] of the internal information register CIF indicates that the reset factor generated immediately before is a system reset. In the example shown in FIG. 21B, when the reset factor immediately before is not a system reset (system reset has not occurred), the bit value of the internal information data SRSF is “0”, whereas when the system reset is in effect (system When the reset occurs), the bit value becomes “1”. The bit number [2] of the internal information register CIF is set to “1” as an initial value.

  The internal information data WDTF stored in the bit number [1] of the internal information register CIF indicates that the reset factor generated immediately before is a user reset due to the input of a time-out signal from the watchdog timer (WDT) 506b. In the example shown in FIG. 21B, when the reset factor immediately before is not a user reset by the timeout signal (user reset by the timeout signal has not occurred), the bit value of the internal information data WDTF becomes “0”, while the timeout occurs. When it is a user reset by a signal (a user reset is generated by a timeout signal), the bit value becomes “1”. The bit number [1] of the internal information register CIF is set to “0” as an initial value.

  Internal information data IATF stored in bit number [0] of internal information register CIF indicates that the reset factor generated immediately before is a user reset due to the input of an IAT generation signal from IAT circuit 506a. In the example shown in FIG. 21B, when the immediately preceding reset factor is not a user reset by the IAT generation signal (user reset has not occurred by the IAT generation signal), the bit value of the internal information data IATF becomes “0”. When the user reset is performed by the IAT generation signal (user reset is generated by the IAT generation signal), the bit value is “1”. The bit number [0] of the internal information register CIF is set to “0” as an initial value.

  The CPU 41a included in the main control unit 41 is a control CPU that executes game control in the slot machine 1 by executing a user program (game control processing program for game control) based on a control code read from the ROM 41b. . When such game control is executed, the CPU 41a reads fixed data from the ROM 41b, the variable data writing operation in which the CPU 41a writes various fluctuation data to the RAM 41c and temporarily stores them, and the CPU 41a is temporarily stored in the RAM 41c. A variable data reading operation for reading out various variable data being received, a receiving operation in which the CPU 41a receives input of various signals from the outside of the main control unit 41 via the external bus interface 501, the parallel input port 511, the serial communication circuit 512, and the like. However, a transmission operation for outputting various signals to the outside of the main control unit 41 through the external bus interface 501, the serial communication circuit 512, the parallel output port 513, and the like is also performed.

  The ROM 41b included in the main control unit 41 stores a control code indicating a user program (game control processing program for game control), fixed data, and the like.

  The RAM 41c included in the main control unit 41 provides a work area for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power source. That is, even if the power supply to the slot machine 1 is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period.

  The main control unit 41 is equipped with four channels of 8-bit free-run counters as the free-run counter circuit 507.

  The random number circuits 508a and 508b included in the main control unit 41 are circuits that generate numerical data that is a random value having a predetermined update range, such as an 8-bit random number or a 16-bit random number. In this embodiment, the hardware random number generated by the 16-bit random number circuit 508b among the random number circuits 508a and 508b is a random number for internal lottery described later, a random number for freeze lottery described later, and a random number for successful number lottery described later. Used. The CPU 41a is used for games by processing or updating various numerical data by software using a random counter different from the random number circuits 508a and 508b based on the numerical data extracted from the random number circuits 508a and 508b. Numerical data indicating all or part of the random number value may be counted. Alternatively, the CPU 41a may count (update) a part of numerical data indicating a random value such as a big hit determination random number by software without using the random number circuits 508a and 508b. As an example, the numerical data extracted by the CPU 41a from the random number circuits 508a and 508b serving as hardware is processed by software to update the numerical data indicating the random numbers for internal lottery, and other random values (for example, described later) The numerical data indicating the random number for freeze lottery and the random number for successful lottery to be described later may be updated by software using the random counter or the like by the CPU 41a.

  FIG. 22 is a block diagram illustrating a configuration example of the 8-bit random number circuit 508a. FIG. 23 is a block diagram illustrating a configuration example of the 16-bit random number circuit 508b. As shown in FIGS. 22 and 23, the 8-bit random number circuit 508a and the 16-bit random number circuit 508b are random number sequence change selection circuits 523a and 523b, random number generation circuits 525a and 525b, random number sequence change circuits 526a and 526b, and a maximum value. Comparing circuits 527a and 527b are provided. In addition to the components included in the 8-bit random number circuit 508a, the 16-bit random number circuit 508b includes a random number start value selection circuit 535, as shown in FIG. Further, as shown in FIG. 23, the 16-bit random number circuit 508b includes an update monitoring circuit 537 in addition to the components included in the 8-bit random number circuit 508a.

  In the example shown in FIG. 23, only the configuration of the circuit portion of the 16-bit random number circuit 508b is shown, and description of each register used by the 16-bit random number circuit 508b other than the random number sequence change register 522 and the maximum value setting register 524b is omitted. doing. Specifically, the 16-bit random number circuit 508b replaces the RS hard latch selection registers 528a and 528b shown in FIG. 22 with RL0 hard latch selection registers 0 (RL0LS0) to RL3 hard latch selection registers (RL3LS) shown in FIG. ), Instead of the RS0 hard latch random value register 529a to RS3 hard latch random value register 529d shown in FIG. 22, the RL0 hard latch random value register 0 (RL0HV0) to RL3 hard latch random value register shown in FIGS. 1 (RL3HV1) is used, and instead of the RS hard latch flag register 530 shown in FIG. 22, RL hard latch flag register 0 (RLHF0) to RL hard latch flag register 1 (RLHF1) shown in FIG. RS interrupt control register 531 Instead, the RL interrupt control register 0 (RLIC0) to the RL interrupt control register 1 (RLIC1) shown in FIG. 8 are used, and the RS0 soft latch random value register 533a to RS3 soft latch random value register 533d shown in FIG. RL0 soft latch random value register (RL0SV) to RL3 soft latch random value register (RL3SV) shown in FIG. The 16-bit random number circuit 508b uses the same register as the 8-bit random number circuit 508a for the random value soft latch register 532 and the random number soft latch flag register 534.

  The 8-bit random number circuit 508a is an 8-bit random number initial setting 521a (8-bit random number initial setting 1 (KRS1) and 8-bit random number initial setting 2 (KRS2) shown in FIG. 7) provided in the program management area already described. Operates according to the set contents.

  The 16-bit random number circuit 508b is a 16-bit random number initial setting 521b (16-bit random number initial setting 1 (KRL1) to 16-bit random number initial setting 2 (KRL2) shown in FIG. 7) provided in the program management area already described. Operates according to the set contents. In addition to the function of the 8-bit random number circuit 508a, the 16-bit random number circuit 508b sets the 16-bit random number initial setting 536 (16-bit random number initial setting 3 (KRL3) shown in FIG. 7). By operating according to the contents, it has a function of changing the start value of the random number value in the first round (see FIG. 16).

  Further, in the 16-bit random number circuit 508b, the random number generation circuit 525b includes an update monitoring circuit 537. In addition to the function of the 8-bit random number circuit 508a, the update monitoring circuit 537 operates to cause an external clock frequency abnormality and an update abnormality. (See FIG. 20). In this embodiment, the case where both the external clock frequency abnormality and the update abnormality are detected by one update monitoring circuit 537 is shown. However, the monitoring circuit for detecting the external clock frequency abnormality and the monitoring circuit for detecting the update abnormality are shown. And may be provided separately.

  The 8-bit random number circuit 508a may also be configured to include an update monitoring circuit so that an external clock frequency abnormality and an update abnormality of the 8-bit random number circuit 508a can be detected.

  The random number sequence change register 522 corresponds to the random number sequence change register RDSC included in the built-in register of the main control unit 41 as shown in FIG. As the random number sequence change register RDSC, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The maximum value setting registers 524a and 524b correspond to the RS0 maximum value setting register (RS0MX) to the RS3 maximum value setting register (RS3MX) included in the built-in registers of the main control unit 41 as shown in FIG. In the case of the 16-bit random number circuit 508b, it corresponds to the RL0 maximum value setting register (RL0MX) to the RL3 maximum value setting register (RL3MX)).

  The hard latch selection register 528a corresponds to the RS hard latch selection register 0 (RSLS0) included in the built-in register of the main control unit 41 as shown in FIG. The hard latch selection register 528b corresponds to the RS hard latch selection register 1 (RSLS1) included in the built-in register of the main control unit 41 as shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL0 hard latch selection register 0 (RL0LS0) to RL3 hard latch selection register 3 (RL3LS) shown in FIG.

  The RS0 hard latch random value registers 529a to RS3 hard latch random value registers 529d are RS0 hard latch random value registers (RS0HV) to RS3 hard latch random numbers included in the built-in registers of the main control unit 41 as shown in FIG. This corresponds to the register (RS3HV). In the case of the 16-bit random number circuit 508b, the RL0 hard latch random value register 0 (RL0HV0) to RL1 hard latch random value register 1 (RL1HV1) shown in FIG. 9 and the RL2 hard latch random value register 0 (RL2HV0) shown in FIG. ) To RL3 hard latch random number value register 1 (RL3HV1).

  The RS hard latch flag register 530 corresponds to the RS hard latch flag register (RSHF) shown in FIG. The 16-bit random number circuit 508b corresponds to RL hard latch flag register 0 (RLHF0) to RL hard latch flag register 1 (RLHF1) shown in FIG.

  The RS interrupt control register 531 corresponds to the RS interrupt control register (RSIC) shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL interrupt control register 0 (RLIC0) to the RL interrupt control register 1 (RLIC1) shown in FIG.

  The random number soft latch register 532 corresponds to the random number soft latch register (RDSL) shown in FIG. As the soft latch register RDSL, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The RS0 soft latch random value registers 533a to RS3 soft latch random value registers 533d correspond to the RS0 soft latch random value registers (RS0SV) to RS3 soft latch random value registers (RS3SV) shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL0 soft latch random number value (RL0SV) to the RL3 soft latch random value (RL3SV) shown in FIG.

  The random number soft latch flag register 534 corresponds to the random number soft latch flag register (RDSF) shown in FIG. As the random number soft latch flag register RDSF, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The random number sequence change selection circuits 523a and 523b follow the setting contents of the 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) shown in FIGS. 17 and 18 (in the case of the 16-bit random number circuit 508b). , According to the setting contents of 16-bit random number initial setting 1 (KRL1) and 16-bit random number initial setting 2 (KRL2) shown in FIG. 14 and FIG. , “Automatically change from the second lap” or “Automatically change from the first lap” is selected. Then, when any one of “change by software”, “automatic change from the second round” or “automatic change from the first round” is selected, the random number sequence changing circuits 526a and 526b receive random numbers according to the selection method. Change the column. Further, when “Do not change” is selected, control for changing the random number sequence is not performed.

  The random number sequence changing circuits 526a and 526b are circuits that can change the permutation of the numerical data generated by the random number generating circuits 525a and 525b in accordance with instructions from the random number sequence change selecting circuits 523a and 523b. For example, when “change by software” is instructed, the random number sequence change circuits 526a and 526b change the random number sequence updated by the random number generation circuits 525a and 525b by software (user program). In addition, for example, when “automatic change from the second round” is instructed, the random number sequence change circuits 526a and 526b automatically change the random number sequence updated by the random number generation circuits 525a and 525b from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. In addition, for example, when “automatic change from the first round” is instructed, the random number sequence change circuits 526a and 526b automatically change the random number sequence updated by the random number generation circuits 525a and 525b from the first round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed.

  The random number generation circuits 525a and 525b are constituted by, for example, an 8-bit counter (in the case of the 16-bit random number circuit 508b, a 16-bit counter), and the like, and predetermined numerical data can be updated based on an input of a random number update clock signal or the like. This circuit cyclically updates a predetermined range from a predetermined initial value to a predetermined final value. For example, the random number generation circuits 525a and 525b add one by one from the initial value set in the range from “0” to “255” in response to the falling edge in the random number update clock signal. The numerical data is counted up (in the case of the 16-bit random number circuit 508b, the numerical data is incremented by 1 from the initial value set within the range of “0” to “65535” to “65535”. Count up) Then, after counting up to “255”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The maximum value comparison circuits 527a and 527b follow the setting contents of the 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) shown in FIGS. 17 and 18 (in the case of the 16-bit random number circuit 508b, In accordance with the setting contents of 16-bit random number initial setting 1 (KRL1) and 16-bit random number initial setting 2 (KRL2) shown in FIGS. 14 and 15, the maximum value of the random number values generated by the random number generation circuits 525a and 525b is set.

  FIG. 24A shows a configuration example of the RL0 hard latch selection register 0 (RL0LS0). FIG. 24B shows an example of setting contents in each bit of data stored in the RL0 hard latch selection register 0 (RL0LS0). The data RL01RF stored in the bit number [7] of the RL0 hard latch selection register 0 (RL0LS0) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 1 (RL0HV1) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 24B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL01RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RL01RF is set to “0” as an initial value.

  In this embodiment, regarding the program management area and the register of the built-in register, specifically, by setting the corresponding bit in the program management area or the like to a value of “0” or “1”, the correspondence is made. The value of the bit to be read is read, and the read “0” or “1” value is written to the control register of the main control unit 41 by hardware, so that various settings are made. For example, for bit 7 of RL0 hard latch select register 0 (RL0LS0), if the value read from bit 7 is “0”, “0” is written to the control register of main control unit 41 in hardware. Thus, if the value is not read from the RL0 hard latch random value register 1 (RL0HV1), the next value is not latched. If the value read from the bit 7 is “1”, the main control unit 41 By writing “1” in hardware in the control register, the next value is latched without reading the value from the RL0 hard latch random value register 1 (RL0HV1). The same applies to each setting item in other program management areas and each bit of each register of the built-in register.

  The data RL01LS0 to RL01LS2 stored in the bit number [6-4] of the RL0 hard latch selection register 0 (RL0LS0) is input to the RL0 hard latch random number value register 1 (RL0HV1) according to which external terminal is input. It shows the setting of whether to import a value. In the example shown in FIG. 24B, when “000” is set in the bit number [6-4] of the RL0 hard latch selection register 0 (RL0LS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RL0 hard latch select register 0 (RL0LS0), the setting is invalid. In addition, the data RL01LS0 to RL01LS2 are set to “000” as an initial value.

  The data RL00RF stored in the bit number [3] of the RL0 hard latch selection register 0 (RL0LS0) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 0 (RL0HV0) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 24B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL00RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RL00RF is set to “0” as an initial value.

  The data RL00LS0 to RL00LS2 stored in the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0) is input to the RL0 hard latch random value register 0 (RL0HV0) by the external terminal input of the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 24B, when “000” is set in the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0), the setting is invalid. In addition, the data RL00LS0 to RL00LS2 is set to “000” as an initial value.

  FIG. 25A shows a configuration example of the RL0 hard latch selection register 1 (RL0LS1). FIG. 25B shows an example of setting contents in each bit of data stored in the RL0 hard latch selection register 1 (RL0LS1). The data RL03RF stored in the bit number [7] of the RL0 hard latch selection register 1 (RL0LS1) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 3 (RL0HV3) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 25B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL03RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RL03RF is set to “0” as an initial value.

  The data RL03LS0 to RL03LS2 stored in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1) is input to the RL0 hard latch random value register 3 (RL0HV3) according to which external terminal input the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 25B, when “000” is set in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1), the setting is invalid. The data RL03LS0 to RL03LS2 is set to “000” as an initial value.

  The data RL02RF stored in the bit number [3] of the RL0 hard latch selection register 1 (RL0LS1) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 2 (RL0HV2) by external terminal input. The setting of conditions is shown. In the example shown in FIG. 25B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL02RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RL02RF is set to “0” as an initial value.

  The data RL02LS0 to RL02LS2 stored in the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1) is input to the RL0 hard latch random value register 2 (RL0HV2) by the external terminal input of the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 25B, when “000” is set in the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1), the setting is invalid. The data RL02LS0 to RL02LS2 is set to “000” as an initial value.

  FIG. 26A shows a configuration example of the RLn hard latch selection register (RLnLS). FIG. 26B shows an example of setting contents in each bit of data stored in the RLn hard latch selection register (RLnLS). In FIG. 26, n takes a value from 0 to 3. Data RLn1RF stored in the bit number [7] of the RLn hard latch selection register (RLnLS) is a condition when the value of the 16-bit random number RLn is input to the RLn hard latch random value register 1 (RLnHV1) by an external terminal input. Shows the settings. In the example shown in FIG. 26B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RLn1RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RLn1RF is set to “0” as an initial value.

  The data RLn1LS0 to RLn1LS2 stored in the bit number [6-4] of the RLn hard latch selection register (RLnLS) is a value of the 16-bit random number RLn depending on which external terminal is input to the RLn hard latch random value register 1 (RLnHV1). Indicates whether to capture. In the example shown in FIG. 26B, when “000” is set in the bit number [6-4] of the RLn hard latch selection register (RLnLS), the PI0 terminal is selected and “001” is set. In this case, the PI1 terminal is selected. When “010” is set, the PI2 terminal is selected. When “011” is set, the PI3 terminal is selected. When “100” is set. When the PI4 terminal is selected and “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RLn hard latch selection register (RLnLS), the setting is invalid. The data RLn1LS0 to RLn1LS2 is set to “000” as an initial value.

  Data RLn0RF stored in the bit number [3] of the RLn hard latch selection register (RLnLS) is a condition when the value of the 16-bit random number RLn is input to the RLn hard latch random value register 0 (RLnHV0) by an external terminal input Shows the settings. In the example shown in FIG. 26B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RLn0RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RLn0RF is set to “0” as an initial value.

  The data RLn0LS0 to RLn0LS2 stored in the bit number [2-0] of the RLn hard latch selection register (RLnLS) is the value of the 16-bit random number RLn depending on which external terminal is input to the RLn hard latch random value register 0 (RLnHV0). Indicates whether to capture. In the example shown in FIG. 26B, when “000” is set in the bit number [2-0] of the RLn hard latch selection register (RLnLS), the PI0 terminal is selected and “001” is set. In this case, the PI1 terminal is selected. When “010” is set, the PI2 terminal is selected. When “011” is set, the PI3 terminal is selected. When “100” is set. When the PI4 terminal is selected and “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [2-0] of the RLn hard latch selection register (RLnLS), the setting is invalid. The data RLn0LS0 to RLn0LS2 is set to “000” as an initial value.

  FIG. 27A shows a configuration example of the RS hard latch selection register 0 (RSLS0). FIG. 27B shows an example of setting contents in each bit of data stored in the RS hard latch selection register 0 (RSLS0). Data RS1RF stored in the bit number [7] of the RS hard latch selection register 0 (RSLS0) is a condition for capturing the value of the 8-bit random number RS1 into the RS1 hard latch random value register (RS1HV) by an external terminal input. Shows the settings. In the example shown in FIG. 27B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS1RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RS1RF is set to “0” as an initial value.

  The data RS1LS0 to RS1LS2 stored in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0) is the value of the 8-bit random number RS1 depending on which external terminal is input to the RS1 hard latch random number value register (RS1HV). Indicates whether to capture. In the example shown in FIG. 27B, when “000” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0), the setting is invalid. In addition, the data RS1LS0 to RS1LS2 is set to “000” as an initial value.

  Data RS0RF stored in the bit number [3] of the RS hard latch selection register 0 (RSLS0) is a condition for taking the value of the 8-bit random number RS0 into the RS0 hard latch random value register (RS0HV) by inputting an external terminal Shows the settings. In the example shown in FIG. 27B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS0RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RS0RF is set to “0” as an initial value.

  The data RS0LS0 to RS0LS2 stored in the bit number [2-0] of the RS hard latch selection register 0 (RSLS0) is the value of the 8-bit random number RS0 depending on which external terminal input to the RS0 hard latch random value register (RS0HV). Indicates whether to capture. In the example shown in FIG. 27B, when “000” is set in the bit number [2-0] of the RS hard latch selection register 0 (RSLS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RS hard latch selection register 0 (RSLS0), the setting is invalid. In addition, the data RS0LS0 to RS0LS2 is set to “000” as an initial value.

  FIG. 28A shows a configuration example of the RS hard latch selection register 1 (RSLS1). FIG. 28B shows an example of setting contents in each bit of data stored in the RS hard latch selection register 1 (RSLS1). Data RS3RF stored in the bit number [7] of the RS hard latch selection register 1 (RSLS1) is a condition for taking the value of the 8-bit random number RS3 into the RS3 hard latch random number value register (RS3HV) by external terminal input Shows the settings. In the example shown in FIG. 28B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS3RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RS3RF is set to “0” as an initial value.

  The data RS3LS0 to RS3LS2 stored in the bit number [6-4] of the RS hard latch selection register 1 (RSLS1) is an 8-bit random number RS3 value depending on which external terminal is input to the RS3 hard latch random number value register (RS3HV). Indicates whether to capture. In the example shown in FIG. 28B, when “000” is set in the bit number [6-4] of the RS hard latch selection register 1 (RSLS1), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS1), the setting is invalid. In addition, the data RS3LS0 to RS3LS2 is set to “000” as an initial value.

  Data RS2RF stored in the bit number [3] of the RS hard latch selection register 1 (RSLS1) is a condition for taking the value of the 8-bit random number RS2 into the RS2 hard latch random value register (RS2HV) by inputting an external terminal Shows the settings. In the example shown in FIG. 28B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS2RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RS2RF is set to “0” as an initial value.

  The data RS2LS0 to RS2LS2 stored in the bit number [2-0] of the RS hard latch selection register 1 (RSLS1) is an 8-bit random number RS2 value depending on which external terminal is input to the RS2 hard latch random value register (RS2HV). Indicates whether to capture. In the example shown in FIG. 28B, when the bit number [2-0] of the RS hard latch selection register 1 (RSLS1) is set to “000”, the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RS hard latch selection register 1 (RSLS1), the setting is invalid. In addition, the data RS2LS0 to RS2LS2 is set to “000” as an initial value.

  FIG. 29A shows a configuration example of the RL interrupt control register 0 (RLIC0). FIG. 29B shows an example of setting contents in each bit of data stored in the RL interrupt control register 0 (RLIC0). The bit value of bit [7-6] of RL interrupt control register 0 (RLIC0) is always “0”.

  The data RL11IE stored in the bit number [5] of the RL interrupt control register 0 (RLIC0) is forbidden / permitted for interrupts caused by the random number value taken into the RL1 hard latch random number value register 1 (RL1HV1). Shows the settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL11IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL11IE is set to “0” as an initial value.

  The data RL10IE stored in the bit number [4] of the RL interrupt control register 0 (RLIC0) is forbidden / permitted for an interrupt caused by the random number value taken into the RL1 hard latch random number value register 0 (RL1HV0). Shows the settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL10IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL10IE is set to “0” as an initial value.

  The data RL03IE stored in the bit number [3] of the RL interrupt control register 0 (RLIC0) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL0 hard latch random number value register 3 (RL0HV3). Shows the settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL03IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL03IE is set to “0” as an initial value.

  The data RL02IE stored in the bit number [2] of the RL interrupt control register 0 (RLIC0) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL0 hard latch random number value register 2 (RL0HV2). Shows the settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL02IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL02IE is set to “0” as an initial value.

  The data RL01IE stored in the bit number [1] of the RL interrupt control register 0 (RLIC0) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL0 hard latch random value register 1 (RL0HV1). Shows the settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL01IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL01IE is set to “0” as an initial value.

  The data RL00IE stored in the bit number [1] of the RL interrupt control register 0 (RLIC0) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL0 hard latch random value register 0 (RL0HV0). Shows the settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL00IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL00IE is set to “0” as an initial value.

  FIG. 30A shows a configuration example of the RL interrupt control register 1 (RLIC1). FIG. 30B shows an example of setting contents in each bit of data stored in the RL interrupt control register 1 (RLIC1). The bit values of the bits [7-6] and [3-2] of the RL interrupt control register 1 (RLIC1) are always “0”.

  The data RL31IE stored in the bit number [5] of the RL interrupt control register 1 (RLIC1) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL3 hard latch random number value register 1 (RL3HV1). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL31IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL31IE is set to “0” as an initial value.

  The data RL30IE stored in the bit number [4] of the RL interrupt control register 1 (RLIC1) prohibits / permits an interrupt due to the fact that a random value is taken into the RL3 hard latch random value register 0 (RL3HV0). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL30IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL30IE is set to “0” as an initial value.

  The data RL21IE stored in the bit number [1] of the RL interrupt control register 1 (RLIC1) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL2 hard latch random number value register 1 (RL2HV1). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL21IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL21IE is set to “0” as an initial value.

  The data RL20IE stored in the bit number [0] of the RL interrupt control register 1 (RLIC1) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL2 hard latch random number value register 0 (RL2HV0). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL20IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL20IE is set to “0” as an initial value.

  FIG. 31A shows a configuration example of the RS interrupt control register (RSIC). FIG. 31B shows an example of setting contents in each bit of data stored in the RS interrupt control register (RSIC). The RS interrupt control register (RSIC) is a register that is used by both the 8-bit random number circuit 508a and the free-run counter circuit 507, and bits [7-4] of the RS interrupt control register (RSIC) are free-run. The settings related to the hard latch registers (FRC0 hard latch register (FR0HV) to FRC3 hard latch register (FR3HV)) used by the counter 507 are shown.

  The data RS3IE stored in the bit number [3] of the RS interrupt control register (RSIC) is set to disable / enable interrupts due to the fact that the RS3 hard latch random value register (RS3HV) has received a random value. Is shown. In the example shown in FIG. 31B, the bit value of the data RS3IE becomes “0” when the interrupt is disabled, whereas the bit value becomes “1” when the interrupt is enabled. . The data RS3IE is set to “0” as an initial value.

  The data RS2IE stored in the bit number [2] of the RS interrupt control register (RSIC) is set to disable / enable interrupts due to the fact that the random value is taken into the RS2 hard latch random number value register (RS2HV). Is shown. In the example shown in FIG. 31B, the bit value of the data RS2IE is “0” when interrupt is disabled, whereas the bit value is “1” when interrupt is enabled. . The data RS2IE is set to “0” as an initial value.

  The data RS1IE stored in the bit number [1] of the RS interrupt control register (RSIC) is set to disable / permit interrupts due to the fact that the random value is taken into the RS1 hard latch random number value register (RS1HV). Is shown. In the example shown in FIG. 31B, the bit value of the data RS1IE becomes “0” when the interrupt is disabled, whereas the bit value becomes “1” when the interrupt is enabled. . The data RS1IE is set to “0” as an initial value.

  The data RS0IE stored in the bit number [0] of the RS interrupt control register (RSIC) is set to disable / permit interrupts due to the fact that the random value is taken into the RS0 hard latch random number value register (RS0HV). Is shown. In the example shown in FIG. 31B, the bit value of the data RS0IE becomes “0” when the interrupt is disabled, whereas the bit value becomes “1” when the interrupt is enabled. . The data RS0IE is set to “0” as an initial value.

  FIG. 32A shows a configuration example of the RLn maximum value setting register (RLnMX). FIG. 32B shows an example of setting contents in each bit of data stored in the RLn maximum value setting register (RLnMX). In FIG. 32, n takes a value from 0 to 3. As shown in FIG. 32B, the maximum value of the 16-bit random number RLn is set in the data RLnMX15 to RLnMX0 stored in the bit number [15-0] of the RLn maximum value setting register (RLnMX).

  FIG. 33A shows a configuration example of the RSn maximum value setting register (RSnMX). FIG. 33B shows an example of setting contents in each bit of data stored in the RSn maximum value setting register (RSnMX). In FIG. 33, n takes a value from 0 to 3. As shown in FIG. 33B, the maximum value of the 8-bit random number RSn is set in the data RSnMX7 to RSnMX0 stored in the bit number [7-0] of the RSn maximum value setting register (RSnMX).

  FIG. 34A shows a configuration example of the random number sequence change register (RDSC). FIG. 34B shows an example of setting contents in each bit of data stored in the random number sequence change register (RDSC). Data RS3SC stored in the bit number [7] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of the 8-bit random number RS3. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RS3SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS3SC is set to “0” as an initial value.

  Data RS2SC stored in the bit number [6] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of the 8-bit random number RS2. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RS2SC becomes “0”, whereas when the random number sequence is set to be changed, the bit value Becomes “1”. The data RS2SC is set to “0” as an initial value.

  The data RS1SC stored in the bit number [5] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 8-bit random number RS1. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RS1SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS1SC is set to “0” as an initial value.

  Data RS0SC stored in bit number [4] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 8-bit random number RS0. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RS0SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS0SC is set to “0” as an initial value.

  Data RL3SC stored in bit number [3] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 16-bit random number RL3. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RL3SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL3SC is set to “0” as an initial value.

  The data RL2SC stored in the bit number [2] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 16-bit random number RL2. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RL2SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL2SC is set to “0” as an initial value.

  The data RL1SC stored in the bit number [1] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 16-bit random number RL1. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RL1SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL1SC is set to “0” as an initial value.

  Data RL0SC stored in bit number [0] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 16-bit random number RL0. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RL0SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL0SC is set to “0” as an initial value.

  FIG. 35A shows a configuration example of a random number soft latch register (RDSL). FIG. 35B shows an example of setting contents in each bit of data stored in the random number soft latch register (RDSL). Data RS3SL stored in bit number [7] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 8-bit random number RS3 into the RS3 soft latch random number value register (RS3SV). In the example shown in FIG. 35B, the bit value of the data RS3SL becomes “0” when the random number value is set not to be captured, while the bit value when the random number sequence is set to be changed. Becomes “1”. The data RS3SL is set to “0” as an initial value.

  Data RS2SL stored in the bit number [6] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 8-bit random number RS2 into the RS2 soft latch random number value register (RS2SV). In the example shown in FIG. 35B, when the random value is set not to be taken in, the bit value of the data RS2SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS2SL is set to “0” as an initial value.

  The data RS1SL stored in the bit number [5] of the random number soft latch register (RDSL) indicates a bit for taking the random value of the 8-bit random number RS1 into the RS1 soft latch random value register (RS1SV). In the example shown in FIG. 35B, when the random value is set not to be taken in, the bit value of the data RS1SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS1SL is set to “0” as an initial value.

  Data RS0SL stored in bit number [4] of the random number soft latch register (RDSL) indicates a bit for taking the random value of the 8-bit random number RS0 into the RS0 soft latch random value register (RS0SV). In the example shown in FIG. 35B, the bit value of the data RS0SL is “0” when the random number value is set not to be captured, while the bit value is set when the random number sequence is changed. Becomes “1”. The data RS0SL is set to “0” as an initial value.

  Data RL3SL stored in the bit number [3] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL3 into the RL3 soft latch random value register (RL3SV). In the example shown in FIG. 35B, the bit value of the data RL3SL becomes “0” when it is set not to take in the random number value, while the bit value when it is set to change the random number sequence. Becomes “1”. The data RL3SL is set to “0” as an initial value.

  Data RL2SL stored in the bit number [2] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL2 into the RL2 soft latch random number value register (RL2SV). In the example shown in FIG. 35B, when the random value is set not to be taken in, the bit value of the data RL2SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL2SL is set to “0” as an initial value.

  Data RL1SL stored in the bit number [1] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL1 into the RL1 soft latch random number value register (RL1SV). In the example shown in FIG. 35B, when the random value is set not to be taken in, the bit value of the data RL1SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL1SL is set to “0” as an initial value.

  Data RL0SL stored in the bit number [0] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL0 into the RL0 soft latch random value register (RL0SV). In the example shown in FIG. 35B, the bit value of the data RL0SL is “0” when the random value is set not to be captured, while the bit value is set when the random number sequence is set to be changed. Becomes “1”. The data RL0SL is set to “0” as an initial value.

  FIG. 36A shows a configuration example of a random number soft latch flag register (RDSF). FIG. 36B shows an example of setting contents in each bit of data stored in the random number soft latch flag register (RDSF). The data RS3SF stored in the bit number [7] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS3 soft latch random value register (RS3SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RS3SF is “0”, whereas when the random value has been captured, the bit value is “ 1 ". The data RS3SF is set to “0” as an initial value.

  The data RS2SF stored in the bit number [6] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS2 soft latch random value register (RS2SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RS2SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS2SF is set to “0” as an initial value.

  The data RS1SF stored in the bit number [5] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS1 soft latch random number value register (RS1SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RS1SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS1SF is set to “0” as an initial value.

  The data RS0SF stored in the bit number [4] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS0 soft latch random value register (RS0SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RS0SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS0SF is set to “0” as an initial value.

  The data RL3SF stored in the bit number [3] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL3 soft latch random value register (RL3SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RL3SF is “0”, while when the random value has been captured, the bit value is “0”. 1 ". The data RL3SF is set to “0” as an initial value.

  The data RL2SF stored in the bit number [2] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL2 soft latch random number value register (RL2SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RL2SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL2SF is set to “0” as an initial value.

  The data RL1SF stored in the bit number [1] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL1 soft latch random number value register (RL1SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RL1SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL1SF is set to “0” as an initial value.

  Data RL0SF stored in the bit number [0] of the random number soft latch flag register (RDSF) indicates that the random number value has been taken into the RL0 soft latch random number value register (RL0SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RL0SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL0SF is set to “0” as an initial value.

  FIG. 37A shows a configuration example of the RLn soft latch random value register (RLnSV). FIG. 37B shows an example of the contents stored in each bit of data stored in the RLn soft latch random value register (RLnSV). In FIG. 37, n takes a value from 0 to 3. As shown in FIG. 37B, the data RLnSV15 to RLnSV0 stored in the bit number [15-0] of the RLn soft latch random value register (RLnSV) are 16 bits taken by the random number soft latch register (RDSL). The value of the random number RLn is stored. When a random value is fetched, “1” is set in the corresponding bit of the random number soft latch flag register (RDSF).

  FIG. 38A shows a configuration example of the RSn soft latch random number value register (RSnSV). FIG. 38B shows an example of the contents stored in each bit of data stored in the RSn soft latch random value register (RSnSV). In FIG. 38, n takes a value from 0 to 3. As shown in FIG. 38B, the data RSnSV7 to RSnSV0 stored in the bit number [7-0] of the RSn soft latch random number register (RSnSV) are 8 bits taken by the random number soft latch register (RDSL). The value of the random number RSn is stored. When a random value is fetched, “1” is set in the corresponding bit of the random number soft latch flag register (RDSF).

  FIG. 39A shows a configuration example of the RL hard latch flag register 0 (RLHF0). FIG. 39B shows an example of setting contents in each bit of data stored in the RL hard latch flag register 0 (RLHF0). The bit value of bit [7-6] of the RL hard latch flag register 0 (RLHF0) is always “0”.

  The data RL11HF stored in the bit number [5] of the RL hard latch flag register 0 (RLHF0) indicates that the random number value is taken into the RL1 hard latch random value register 1. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL11HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL11HF is set to “0” as an initial value.

  The data RL10HF stored in the bit number [4] of the RL hard latch flag register 0 (RLHF0) indicates that a random value has been taken into the RL1 hard latch random value register 0. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL10HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL10HF is set to “0” as an initial value.

  The data RL03HF stored in the bit number [3] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 3. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL03HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL03HF is set to “0” as an initial value.

  The data RL02HF stored in the bit number [2] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 2. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL02HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL02HF is set to “0” as an initial value.

  The data RL01HF stored in the bit number [1] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 1. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL01HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL01HF is set to “0” as an initial value.

  The data RL00HF stored in the bit number [0] of the RL hard latch flag register 0 (RLHF0) indicates that a random value has been taken into the RL0 hard latch random value register 0. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL00HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL00HF is set to “0” as an initial value.

  FIG. 40A shows a configuration example of the RL hard latch flag register 1 (RLHF1). FIG. 40B shows an example of setting contents in each bit of data stored in the RL hard latch flag register 1 (RLHF1). The bit values of the bits [7-6] and [3-2] of the RL hard latch flag register 1 (RLHF1) are always “0”.

  Data RL31HF stored in the bit number [5] of the RL hard latch flag register 1 (RLHF1) indicates that a random number value has been taken into the RL3 hard latch random value register 1. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL31HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL31HF is set to “0” as an initial value.

  The data RL30HF stored in the bit number [4] of the RL hard latch flag register 1 (RLHF1) indicates that a random value has been taken into the RL3 hard latch random value register 0. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL30HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL30HF is set to “0” as an initial value.

  The data RL21HF stored in the bit number [1] of the RL hard latch flag register 1 (RLHF1) indicates that a random value has been taken into the RL2 hard latch random value register 1. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL21HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL21HF is set to “0” as an initial value.

  The data RL20HF stored in the bit number [1] of the RL hard latch flag register 1 (RLHF1) indicates that the random number value is taken into the RL2 hard latch random value register 0. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL20HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL20HF is set to “0” as an initial value.

  FIG. 41A shows a configuration example of the RS hard latch flag register (RSHF). FIG. 41B shows an example of setting contents in each bit of data stored in the RS hard latch flag register (RSHF). The RS hard latch flag register (RSHF) is a register that is used by both the 8-bit random number circuit 508a and the free-run counter circuit 507, and bits [7-4] of the RS hard latch flag register (RSHF) are The settings related to the hard latch registers (FRC0 hard latch register (FR0HV) to FRC3 hard latch register (FR3HV)) used by the free-run counter 507 are shown.

  The data RS3HF stored in the bit number [3] of the RS hard latch flag register (RSHF) indicates that the random number value is taken into the RS3 hard latch random value register (RS3HV). In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RS3HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS3HF is set to “0” as an initial value.

  The data RS2HF stored in the bit number [2] of the RS hard latch flag register (RSHF) indicates that the random value is taken into the RS2 hard latch random value register (RS2HV). In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RS2HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS2HF is set to “0” as an initial value.

  The data RS1HF stored in the bit number [1] of the RS hard latch flag register (RSHF) indicates that the random value has been taken into the RS1 hard latch random value register (RS1HV). In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RS1HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS1HF is set to “0” as an initial value.

  The data RS0HF stored in the bit number [0] of the RS hard latch flag register (RSHF) indicates that the random value is taken into the RS0 hard latch random value register (RS0HV). In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RS0HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS0HF is set to “0” as an initial value.

  FIG. 42A shows a configuration example of the RL0 hard latch random number value register m (RL0mHV). FIG. 42B shows an example of the contents stored in each bit of data stored in the RL0 hard latch random number value register m (RL0mHV). In FIG. 42, m takes a value from 0 to 3. As shown in FIG. 42B, the data RL0mHV15 to RL0mHV0 stored in the bit number [15-0] of the RL0 hard latch random number value register m (RL0mHV) are the 16-bit random number RL0 captured by the external terminal input. Stores the value. When a random value is fetched, “1” is set in the corresponding bit of the RL hard latch flag register 0 (RLHF0).

  FIG. 43A shows a configuration example of the RL1 hard latch random number value register m (RL1mHV). FIG. 43B shows an example of the contents stored in each bit of data stored in the RL1 hard latch random number value register m (RL1mHV). In FIG. 43, m takes a value from 0 to 3. As shown in FIG. 43B, the data RL1mHV15 to RL1mHV0 stored in the bit number [15-0] of the RL1 hard latch random number value register m (RL1mHV) are the 16-bit random number RL1 fetched by the external terminal input. Stores the value. When a random value is fetched, “1” is set in the corresponding bit of the RL hard latch flag register 0 (RLHF0).

  FIG. 44A shows a configuration example of the RL2 hard latch random number value register m (RL2mHV). FIG. 44B shows an example of the contents stored in each bit of data stored in the RL2 hard latch random number value register m (RL2mHV). In FIG. 44, m takes a value from 0 to 3. As shown in FIG. 44 (B), the data RL2mHV15 to RL2mHV0 stored in the bit number [15-0] of the RL2 hard latch random value register m (RL2mHV) is the 16-bit random number RL2 fetched by the external terminal input. Stores the value. When a random value is fetched, “1” is set in the corresponding bit of the RL hard latch flag register 1 (RLHF1).

  FIG. 45A shows a configuration example of the RL3 hard latch random number value register m (RL3mHV). FIG. 45B shows an example of the contents stored in each bit of data stored in the RL3 hard latch random number value register m (RL3mHV). In FIG. 45, m takes a value from 0 to 3. As shown in FIG. 45 (B), the data RL3mHV15 to RL3mHV0 stored in the bit number [15-0] of the RL3 hard latch random number register m (RL3mHV) are the 16-bit random number RL3 fetched by the external terminal input. Stores the value. When a random value is fetched, “1” is set in the corresponding bit of the RL hard latch flag register 1 (RLHF1).

  FIG. 46A shows a configuration example of the RSn hard latch random number value register (RSnHV). FIG. 46B shows an example of the contents stored in each bit of data stored in the RSn hard latch random number value register (RSnHV). In FIG. 46, n takes a value from 0 to 3. As shown in FIG. 46B, the data RSnHV7 to RSnHV0 stored in the bit number [70] of the RSn hard latch random number register (RLnHV) stores the value of the 8-bit random number RSn fetched by the external terminal input. Is done. When a random value is taken in, “1” is set in the corresponding bit of the RS hard latch flag register (RSHF).

  The timer circuit 509 included in the main control unit 41 illustrated in FIG. 5 is an 8-bit programmable timer, and the main control unit 41 includes three channels of 8-bit counters as the timer circuit 509. In this embodiment, it is possible to perform a real-time interrupt request and time measurement by using a timer circuit 509 and setting by a user program.

  The interrupt controller 510 provided in the main control unit 41 shown in FIG. 5 receives an external interrupt request from the PI5 / XINT terminal, or from a built-in peripheral circuit (for example, serial communication circuit 512, random number circuits 508a and 508b, timer circuit 509). This circuit controls interrupt requests.

  The parallel input port 511 provided in the main control unit 41 shown in FIG. 5 incorporates an 8-bit wide input-only port (PIP). Further, the parallel output port 513 provided in the main control unit 41 shown in FIG. 5 incorporates an output-only port (POP) having an 11-bit width.

  A serial communication circuit 512 included in the main control unit 41 illustrated in FIG. 5 is a circuit that performs asynchronous serial communication in input / output with respect to the outside. The main control unit 41 includes, as the serial communication circuit 512, a 1-channel circuit for both transmission and reception and a 3-channel circuit for transmission only.

  An address decoding circuit 514 provided in the main control unit 41 shown in FIG. 5 is a circuit for decoding each functional block in the main control unit 41 and a chip select signal that is a decoding signal for an external device. . In response to the chip select signal, the internal circuit of the main control unit 41 or the external device serving as a peripheral device is selectively operated effectively and can be accessed from the CPU 41a.

  In this embodiment, the main control unit 41 transmits various commands to the sub control unit 91 via the parallel output port 513. A command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and no command is sent from the sub control unit 91 toward the main control unit 41. In this embodiment, the command is transmitted to the sub-control unit 91 via the parallel output port 513, that is, the command is transmitted as a parallel signal, but via the serial communication circuit 512. A configuration in which a command is transmitted to the sub-control unit 91, that is, a configuration in which the command is transmitted as a serial signal may be employed.

  The main control unit 41 also receives detection states of various switches connected to the game control board 40 from the parallel input port 511. The main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from the parallel input port 511.

  Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In this embodiment, a timer interrupt process (main), which will be described later, is executed every time a time-out occurs in the timer circuit 509, that is, every fixed time interval (about 0.56 ms in this embodiment).

  The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt will occur at that point. It will be.

  The main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes as a basic process, and changes the detection state of the various switches. Execute a process that moves in stages. Further, the main control unit 41 executes a timer interrupt process (main) at regular time intervals (about 0.56 ms in this embodiment). In addition, the execution interval of the timer interrupt process (main) is set to a time longer than the sum of the time required to complete the repeated process according to the control state in the basic process and the execution time of the timer interrupt process (main) Therefore, the process that is repeated according to the control state between the current and next timer interrupt processes (main) is completed at least once.

  An effect switch 56 is connected to the effect control board 90, and a detection signal of the effect switch 56 is input.

  The effect control board 90 is connected to effect devices such as a liquid crystal display 51 (see FIG. 1), an effect LED 52, speakers 53 and 54, and the reel LED 55 described above, which are arranged on the front door 1b of the slot machine 1. These effect devices are driven based on control by a later-described sub-control unit 91 mounted on the effect control board 90.

  In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, effect effect LED 52, speakers 53 and 54, and reel LED 55. However, in addition to the sub-control unit 91, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output control unit may determine the output pattern of the effect device, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be performed. The output control of the rendering device is performed by both of the units.

  Further, in the present embodiment, the liquid crystal display 51, the effect effect LED 52, the speakers 53 and 54, and the reel LED 55 are exemplified as the effect device, but the effect device is not limited to these, for example, a mechanically driven display. A device or a mechanically driven item may be applied as the effect device.

  The effect control board 90 is composed of a microcomputer having a sub CPU 91a, ROM 91b, RAM 91c, and I / O port 91d, and a liquid crystal display connected to the effect control board 90, a sub control unit 91 for effect control. 51, a display control circuit 92 for performing display control, an LED driving circuit 93 for controlling driving of the effect LED 52 and the reel LED 55, an audio output circuit 94 for controlling audio output from the speakers 53, 54, when the power is turned on or from the sub CPU 91a The reset circuit 95 that gives a reset signal to the sub CPU 91a when the initialization command is not input for a predetermined time, the switch detection circuit 96 that detects the detection signal input from the effect switch 56 connected to the effect control board 90, and date information Clock device 97 for outputting time information including time information, and slot A power interruption detection circuit 98 that monitors a power supply voltage supplied to the thin 1 and outputs a voltage drop signal indicating that to the sub CPU 91a when a voltage drop is detected, and other circuits are mounted. The sub CPU 91a receives various commands transmitted from the game control board 40 and performs various controls for performing the effects, and directly or indirectly controls each part of the control circuit mounted on the effect control board 90. Control.

  The reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that gives the system reset signal to the main control unit 41 in the game control board 40. When the power is turned on, the sub control unit 91 It starts at an earlier stage than the unit 41. On the other hand, the power interruption detection circuit 98 has a voltage that outputs a voltage drop signal lower than the power interruption detection circuit 48 that outputs a voltage drop signal to the main control unit 41 in the game control board 40. The sub control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the number of input system clocks reaches a certain number, that is, every certain interval.

  Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time.

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and the data stored in the RAM 91c is held while the backup power is supplied.

  In the slot machine 1 of this embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to a set value in an internal lottery described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 41c is displayed as a display value on the setting value display 24, and the setting value can be changed by operating the reset / setting switch 38. Transition to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated one by one (when further operation is performed from the setting 6, the display returns to the setting 1). . When the start switch 7 is operated, the display value is determined as the set value. When the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 41c of the main control unit 41, and the state shifts to a state in which the game can proceed.

  In order to check the set value, after the game is over, the setting key switch 37 may be turned on in a state where the bet amount is not set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 41c is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by setting the setting key switch 37 to the off state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not the voltage drop signal from the power interruption detection circuit 48 is detected every time the timer interruption process (main) is executed. If the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process, the power interruption process (main) is executed. In the power interruption process (main), a register is saved in a stack of a RAM 41c, which will be described later, and data for destructive diagnosis (in this embodiment, 5AH) in which any bit is 1, that is, specific data other than 0 is stored in the RAM 41c. In addition to the storage, the RAM parity adjustment data is calculated so that the RAM parity based on the data stored in all areas of the RAM 41c becomes 0, and stored in the RAM 41c. The RAM parity is a value calculated as an exclusive OR of values stored in each bit of the corresponding area (all areas in this embodiment) of the RAM 41c. Therefore, if the RAM parity based on the data stored in all areas of the RAM 41c is 0, the RAM parity adjustment data is 0, and the RAM parity based on the data stored in all areas of the RAM 41c is 1. In this case, the RAM parity adjustment data is 1.

  The main control unit 41 calculates the RAM parity based on the data stored in all areas of the RAM 41c at the time of activation regardless of whether the system reset or the user reset, and the value of the data for destructive diagnosis And the processing state of the main control unit 41 is restored to the state before the power interruption based on the data stored in the RAM 41c on the condition that the RAM parity is 0 and the value of the data for destructive diagnosis is also correct. However, if the RAM parity is not 0 (in the case of 1) or the value of the destruction diagnosis data is not correct, it is determined that the RAM is abnormal, and the RAM abnormal error code is set in the register to control the RAM abnormal error state. However, the progress of the game is disabled. Unlike the normal error state, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the above-described setting change state. It will not be released until

  In this embodiment, all data stored in the RAM 41c is held by the backup power source even in the event of a power failure, and the main control unit 41 determines that the data in the RAM 41c is normal when the power is turned on. In addition, although the configuration is such that the control state before power interruption is restored based on the data stored in the RAM 41c, only the data necessary for the restoration of the control state during a power failure is backed up among the data stored in the RAM 41c and the power is turned on. It may be configured to return to the control state before power interruption based on the data backed up at the time.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player For example, it is not necessary to restore the state of all input ports to the state before power interruption.

  Next, initialization of the RAM 41c of the main control unit 41 will be described. The storage area of the RAM 41c of the main control unit 41 is divided into an important work, a non-saved work, a general work, a special work, an unused area, and a stack area.

  The important work is a work in which data such as various display devices and LED display data, I / O input / output data, game time counter, etc., which are inconvenient to be initialized are stored. The unsaved work is a work that holds the state of various switches, and a value is always set regardless of whether or not the data in the RAM 41c is destroyed at the time of activation. The general work is a work that stores data that can be initialized at the end of the BB, such as a stop control table, a stop symbol, the number of medals paid out, and the total number of medals paid out in the BB. The special work is a work that stores data such as various software random numbers that are initialized only before the setting is started. The unused area is an unused area in the storage area of the RAM 41c, and is initialized if any one of a plurality of initialization conditions described later is satisfied. The stack area is an area in which data saved from the register of the main control unit 41 is stored, and the unused stack area is one of a plurality of initialization conditions to be described later, like the unused area. However, if it is established, it will be initialized, but the in-use stack area is not initialized because the program continues.

  In this embodiment, the main control unit 41 stores the data in the RAM 41c when the setting key switch 37 is turned on, when a RAM error occurs, when the BB ends, or when the setting key switch 37 is turned off. When not being destroyed, when five initialization conditions at the end of one game are satisfied, four types of initializations that are initialized in accordance with each initialization condition are performed.

  Initialization 1 is an initialization performed when the setting key switch 37 is turned on at the time of startup and transitions to a setting change state, or initialization performed when a RAM abnormality error occurs. In the storage area of the RAM 41c, all areas (including the unused area and the unused stack area) except for the important work and the used stack area, that is, the area from the unsaved work to the unused stack area are initialized. The Initialization 2 is initialization performed at the end of the BB. In initialization 2, there are general work, unused area, and unused stack area in the storage area of the RAM 41c, that is, areas from the general work to the unused stack area. It is initialized. Initialization 3 is an initialization performed when the setting key switch 37 is off at the time of startup and the data in the RAM 41c is not destroyed. In the initialization 3, the unsaved work, the unused area, and the The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 41c are initialized.

  In this embodiment, initialization 1 is performed before the change of the setting change state. However, the initialization 1 is performed at the end of the setting change state, or both before the change of the setting change state and at the end of the setting change state. Also good.

  In the slot machine 1 of the present embodiment, as described above, the prescribed number of bets that can be set is determined according to the gaming state (RT0 to 5, RB, BB (RB)), and determined according to the gaming state. The game can be started on condition that the specified number of bets is set. In the present embodiment, the winning line LN is activated when a specified number of bets according to the gaming state are set.

  In the slot machine 1 of this embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line (in the present embodiment, all the pay lines are always enabled. The activated winning line is simply referred to as a winning line), and a winning combination is obtained when a combination of symbols called “comb” is arranged. The combination may be a combination of the same symbols or a combination including different symbols. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition to a game state advantageous to the player. Below, a small role and a re-playing role are collectively called a general role. In order for winning of each combination determined according to the gaming state to occur, it is necessary to win an internal lottery to be described later and set a winning flag of the combination in the RAM 41c.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until the combination of combinations permitted by the flag is complete, and is invalid in a game having the combination of combinations permitted. In other words, once the winning flag for a special role is won, even if the combination of characters allowed by the flag cannot be aligned, the winning flag is not invalidated and carried over to the next game. It becomes.

  Hereinafter, the internal lottery of the present embodiment will be described. In the internal lottery, it is determined whether or not the above winning combination is permitted before the display results of all the reels 2L, 2C, and 2R are derived and displayed (actually, when the start switch 7 is detected). To do. In the internal lottery, first, a random value for internal lottery (an integer from 0 to 65535) is acquired when the start switch 7 is detected. Specifically, the value generated by the channel RL0 of the random number circuit 508b and stored in the RL0 hard latch random value register 0 (RL0HV0) is set as the lottery work assigned to the RAM 41c. Then, for each combination determined according to the gaming state and whether or not the special combination is carried over, it is determined according to the numerical data stored in the lottery work, the current gaming state and RT type, the number of bets and the set value. It is performed according to the number of judgment values for each combination.

  As already described with reference to FIG. 24, the channel of the random number circuit 508b is based on the signal (latch signal) from either terminal according to the setting contents of bits 2-0 of the RL0 hard latch select register 0 (RL0LS0). Whether to latch the random number value in the RL0 hard latch random value register 0 (RL0HV0) of RL0 is set. In this embodiment, the detection signal from the start switch 7 is input to the set terminal as a latch signal, and the channel RL0 of the random number circuit 508b is operated at the timing when the start switch 7 is operated. The RL0 hard latch random number value register 0 (RL0HV0) in FIG.

  In the internal lottery, the number of judgment values determined in accordance with the role that is the subject of the internal lottery, the current gaming state, the current RT type and the set value are stored in a random number for internal lottery (the lottery work) When the result of addition overflows, it is determined that the winning combination is won. For this reason, a winning combination will be won with a probability (number of determination values / 65536) according to the number of determination values.

  If a winning combination of any combination is determined, a winning flag corresponding to the combination determined to be winning is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination is selected, only the general winning combination work is cleared.

  In the internal lottery of the present embodiment, the number of determination values of the lottery object combination is sequentially added to the internal lottery random value, and when the addition result overflows, it is determined that the combination is won. However, the number of determination values of the lottery target combination may be sequentially subtracted from the internal lottery random value, and when the result of the subtraction overflows, it may be determined that the combination is won.

  Further, in this embodiment, the number of determination values, which is the number of determination values determined to be winning, is determined for each lottery target role, and the number of determination values is sequentially added (subtracted) to the random number value for each lottery target role. In the case of overflow, the winning combination corresponding to the number of determination values is determined. However, for each lottery target role, a range of random values determined to be winning is determined, and the range to which the random value belongs It is good also as a structure which determines the winning of the role to perform.

  Next, stop control of the reels 2L, 2C, 2R will be described.

  The main control unit 41 refers to the table index and the table creation data stored in the ROM 41bA when the rotation of the reel starts and when the reel stops and the reel that is still rotating still remains. A stop control table is created for each reel that is rotating. When any of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the referred stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the table index, an index that indicates the start address of the area in which the data for table creation is stored, from the reference address when referring to the table index, according to the setting state of the winning flag by internal lottery (hereinafter referred to as internal winning state) Differences up to the address where the data is stored are registered. As a result, a difference corresponding to the internal winning state is acquired, and the corresponding index data can be acquired by adding the difference to the reference address. Even when the winning combinations are different, when the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes a stop control table indicating the number of sliding frames according to the stop operation position, and an address of the stop control table to be referred to according to the reel stop status.

  The stop control table referred to according to the reel stop status is whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, only the right reel is stopped, It may vary depending on whether the middle reel is stopped, the left and right reels are stopped, the middle and right reels are stopped, and if any reel is stopped, stop Since there may be differences depending on the stop position of the reels already completed, the address of the stop control table to be referenced for each situation is registered for each rotating reel, and based on the top address of the table creation data, It is possible to specify the address of the stop control table that should be referred to according to the status of each, and it is necessary according to each status from this specified address. And to be able to identify the stop control table. Even when the reel stop status and the stopped position of the stopped reel are different, when the same stop control table is applied, the same address may be registered as the address of the stop control table. In such a case, the same stop control table is referred to.

  The stop control table is data that can specify the number of sliding frames for each timing when the stop operation is performed. In the present embodiment, a stepping motor that makes one turn at a cycle of 336 steps (0 to 335) is used for the reel motors 32L, 32C, and 32R. That is, when the reel motors 32L, 32C, and 32R are driven in 336 steps, the reels 2L, 2C, and 2R make one round. Then, 21 areas (frames) divided every 16 steps (the number of steps that one symbol moves) are defined for one reel, and these areas are areas 0 to 20 from the reel reference position. A number is assigned. On the other hand, the number of symbols arranged on one reel is 21, and symbol numbers 0 to 20 from the reel reference position are assigned to symbols on each reel, so symbols 0 to 20 are assigned to each reel. , Area numbers 0 to 20 are assigned in order. In the stop control table, the number of sliding symbols for each area number is compressed and stored according to a predetermined rule, and the number of sliding symbols for each area number can be acquired by expanding the stop control table. Yes.

  As described above, the stop control table created by referring to the table index and the table creation data corresponds to the area number, and the area corresponding to each area number is the stop reference position (in this embodiment, the perspective window 3). Sliding frame when an operation of the stop switches 8L, 8C, 8R is detected at a timing (a timing in which the number of steps from the reel reference position is included in the range of the number of steps of each region number). It is a table with each number set.

  Next, the procedure for creating the stop control table will be described. First, at the start of reel rotation, the top address of the table creation data corresponding to the internal winning state of the game is acquired. Specifically, the table index is first referred to, index data corresponding to the internal winning state is obtained, table creation data is identified based on the obtained index data, and all reels are identified from the identified table creation data. The address of the stop control table for each reel corresponding to the state of rotation is acquired, and the stop control table for each reel stored at the acquired address is expanded to generate a stop control table for all reels.

  Further, when any one reel stops or any two reels stop, the index data acquired at the start of reel rotation, that is, the top address of the table creation data corresponding to the internal winning state of the game The table creation data is identified based on the table creation data, and the stop control table address of the unreacted reel corresponding to the stopped reel and the area number of the stop position of the reel is obtained from the identified table creation data. The stop control table for each stored reel is expanded to create a stop control table for the unstopped reels.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel, the control when the display result is derived to the corresponding reel is described. To explain, when any operation corresponding to the rotating reel is detected effectively among the stop switches 8L, 8C, 8R, the stop operation position is based on the number of steps from the reel reference position when the stop operation is detected. The number of sliding symbols corresponding to the area number of the specified stop operation position is acquired by referring to the stop control table of the reel where the stop operation is detected. Then, control is performed to rotate and stop the reel by the number of acquired sliding frames. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the acquired number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. As a result, the area corresponding to the area number that is the stop position ahead of the number of sliding frames from the area corresponding to the area number of the stop operation position where the stop operation is detected is the stop reference position (in this embodiment, the perspective window 3 It will stop in the lower symbol area).

  In the table index of this embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state, and further, one table creation data includes one reel. Only one address is stored as the address of the storage area of the stop control table corresponding to the stop status (and the stop position of the stopped reel). In other words, table creation data corresponding to one internal winning state in one gaming state and stop control tables corresponding to reel stop states (and stopped positions of stopped reels) are uniquely determined. The stop control table created with reference to is unique for one internal winning state in one gaming state and the reel stop status (and the stop position of the stopped reel). Therefore, when all of the gaming state, the internal winning state, and the reel stop status (and the stop position of the stopped reel) are the same, the reel is based on the same stop control table, that is, the same control pattern. The stop control is performed.

  Further, in this embodiment, a value of 0 to 4 is determined as the number of sliding frames, and the reel can be stopped by drawing a maximum of 4 symbols after detecting the stop operation. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In this embodiment, when any of the winning combinations is won, the winning combination is drawn to the maximum in the range of 4 frames on the winning line, and the non-winning winning combination is drawn so that it is not aligned on the winning line. A stop control table with a defined number of frames is created and reel stop control is performed. If no winning combination is selected, a stop control table with a determined number of sliding symbols that do not have any combination And stop control of the reel. As a result, when a stop operation is performed, if the winning combination can be stopped on the winning line in the drawing range of up to 4 frames, the control is performed so that the winning combination is stopped. The combination that has not been performed will be controlled to be stopped in a drawing range of a maximum of 4 frames.

  When a special role and a small role are elected at the same time, such as when a special role is elected while the special role has been carried over from before the previous game, the winning small role is the maximum in the range of 4 frames on the winning line. The number of sliding frames is fixed so that it can be drawn to the limit, and for the stop operation position where the selected small role cannot be drawn in the range of up to 4 frames in the winning line, the winning special role is in the range of 4 frames in the winning line Then, a stop control table in which the number of sliding frames is determined so as to be pulled in as much as possible is created, and reel stop control is performed. As a result, when a stop operation is performed, if it is possible to stop all the small roles that have been selected in the drawing range of up to 4 frames on the winning line and stop them, control is performed so that the winning combination is stopped. If you can't draw a small role that has been won in the drawing range of up to 4 frames on the line, if you can stop with a special role that has been won in the drawing range of up to 4 frames on the winning line, A control is performed to stop them in a uniform manner, and a winning combination that has not been won will be controlled to be stopped within a 4-frame pull-in range. That is, in such a case, priority is given to the control for aligning the small combination on the winning line over the special combination, and the special combination can be won only when the small combination cannot be drawn. When a special combination and a small combination can be withdrawn at the same time, only the small combination is drawn in, and the small combination is not aligned on the winning line at the same time as the special combination.

  In this example, when a special role is elected while the special role has been carried over from before the previous game, or when a special role and a small role are simultaneously elected, the special role and the small role are won simultaneously. If the selected special role is given priority over the selected special role, the special role is controlled on the winning line only when the small role cannot be withdrawn. When winning simultaneously, priority is given to the control for aligning the special role on the winning line over the small role, and the control for aligning the small role on the winning line may be performed only when the special role cannot be drawn.

  If a special player and a replaying player are elected at the same time, such as when a replaying player is elected while the special role has been carried over from before the previous game, when the stop operation is performed, In addition, a control is performed in which the symbols of the re-gamer are aligned and stopped within a drawing range of up to 4 frames. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer to be simultaneously elected are arranged at intervals of 5 symbols or less, that is, within 4 frames, for any of the reels 2L, 2C, and 2R. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games on the winning line has priority over the special game, and the re-games will always win. In the case where the special combination and the re-playing combination can be withdrawn at the same time, only the re-playing combination is drawn in, and the special combination is not arranged on the winning line at the same time as the re-playing combination.

  In this embodiment, after the rotation of the reels 2L, 2C, and 2R is started, the main control unit 41 rotates the reels for which the stop operation has not been detected yet until the operation of the stop switches 8L, 8C, and 8R is detected. Continuously, on the condition that the operation of the stop switches 8L, 8C, and 8R is detected, control is performed to stop the display result on the corresponding reel. Even if the reel rotation temporarily stops due to the occurrence of a reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is restarted. Control is performed to stop the display result of the corresponding reels on the condition that the rotation of the reels that have not been continued is continued and the operation of the stop switches 8L, 8C, and 8R is detected.

  In this embodiment, control is performed to stop the display result on the corresponding reel on condition that the operation of the stop switches 8L, 8C, and 8R is detected. However, the rotation of the reel is started. When a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is assumed that the stop operation has been performed, and automatic stop control is performed to automatically stop each reel. May be. In this case, since the reels are stopped without the player's operation, it is preferable to derive a display result that does not constitute any combination even if any combination is won.

  In the present embodiment, the main control unit 41 measures the game time, which is the time elapsed from the start of the reel rotation every time the reel starts rotating after the game starts. After a game is over, when a specified number of bets are set by inserting medals, etc., and the game start operation is enabled, the reel start of the previous game is started. If the game time that started timing from the time point is equal to or longer than a predetermined restriction time (4.1 seconds in this embodiment), that is, if the predetermined restriction time has elapsed since the reel rotation start time of the previous game, At that time, the reels in the game are started to rotate.

  On the other hand, after the end of one game, when a predetermined number of bets are set by inserting medals, etc., and when the game start operation is enabled, the reel rotation of the previous game is started. If the game time that started timing from the time is less than the predetermined regulation time, that is, if the predetermined regulation time has not elapsed since the reel rotation start time of the previous game, the reel rotation is not started at that time, It waits until the game time that has started timing from the start of reel rotation of the previous game reaches a predetermined regulation time, and when the predetermined regulation time is reached, rotation of the reel in the game is started.

  That is, when the predetermined regulation time has not elapsed since the start of reel rotation in the previous game, the main control unit 41 regulates the progress of the game until the predetermined regulation time elapses. The progress of the game is regulated so that the shortest time is not less than a predetermined regulation time.

  In this embodiment, if a predetermined regulation time has not elapsed since the start of reel rotation in the previous game, the progress of the game is regulated until the predetermined regulation time has elapsed, so that one game The configuration is such that the progress of the game is regulated so that the shortest time is not less than a predetermined regulation time. However, any configuration that restricts the progress of the game so that the minimum time of at least one game is not less than the prescribed regulation time may be used. If the game time is counted from one timing other than the start of reel rotation in one game (for example, at the end of the game), and a predetermined regulation time has passed by the same one timing in the next game While the game is allowed to proceed, if the predetermined regulation time has not elapsed before the same timing in the next game, the game does not proceed and the predetermined regulation time elapses To wait, that it allows progressive game when a predetermined restriction time period has passed, it may be configured to one game shortest time regulates the progress of the game to a predetermined restriction time or more.

  Next, commands that the main control unit 41 transmits to the sub control unit 91 will be described.

  In the present embodiment, the main control unit 41 sends to the sub-control unit 91 a number-of-insertion command, a credit command, an internal winning command, a freeze command, a preparation-out stop command, a preliminary-out stop command, a result-out stop command, Fluctuation restart command, reel delay command, reel rotation start command, reel stop command, winning number command, payout start command, payout end command, return command, gaming state command, RT information command, standby command, stop command, error command, A plurality of types of commands including a setting command, a setting confirmation command, a door command, and an operation detection command are transmitted.

  These commands consist of 1-byte type data indicating the command type and 1-byte extension data indicating the command content, and the sub-control unit 91 can determine the command type from the type data.

  The inserted number command is a command that can specify the number of inserted medals, that is, the number of medals used for setting the number of bets, and is a state from the end of the game (after changing the setting) to the start of the game. Or, when a prescribed number of bets is not set, a medal is inserted, or when the bet number is set by operating the MAXBET switch 6. The inserted number command is transmitted when the betting number setting operation is performed, so that it is possible to specify that the betting number setting operation has been performed by receiving the inserted number command.

  The credit command is a command that can specify the number of medals stored as credits, and is a state from the end of the game (after setting change) to the start of the game, and in a state where a predetermined number of bets is set, Sent when a medal is inserted and credits are added.

  The internal winning command is a command that can specify the internal lottery result, and is transmitted when the start switch 7 is operated to start the game. Further, since the internal winning command is transmitted when the start switch 7 is operated, it is possible to specify that the start switch 7 has been operated by receiving the internal winning command.

  The freeze command is a command that can specify whether or not to control the freeze state to be described later in the game, and when controlling to the freeze state, and is transmitted after the internal winning command.

  The ready-out stop command specifies whether the below-mentioned ready-out is stopped in the frozen state, and whether the later-out success is stopped by the operation of the start switch 7 or the later-out failure is stopped. This is a possible command, and is sent when the preparation is stopped in the freeze state.

  The advance notice stop command is a command that can specify that the advance notice that will be described later has been stopped, and is transmitted when the advance notice is derived after the successful outcome is derived in the freeze state.

  The result output stop command is a command that can specify that the success output or the failure output has been derived, and succeeds when the operation of the start switch 7 is detected in a state where the preparation output is stopped in the freeze state. It is transmitted when an outcome or failure outcome is derived, or when a certain amount of time passes and a success outcome or failure outcome is derived.

  The change restart command is a command that can specify that the change has started toward the preparation event after the success event has been derived. After the success event has been derived (if the notice event is derived) After that, it is transmitted when the change is started toward the preparation event.

  The reel delay command is a command that can specify the timing at which each reel starts to rotate, the timing at which the reel rotates at a constant speed, and the timing at which the stop operation becomes effective after the reel effect executed in the freeze state described later. Stores the timer values for the left, middle and right reels, which will be described later, which can specify the delay time of each reel, and each reel starts to rotate by taking into account the acceleration time of the reel on the sub-control unit 91 side. This is a command that can specify the timing, the timing of constant speed rotation, and the timing at which the stop operation becomes valid, and is transmitted before starting the rotation of the left reel that starts rotating first after the reel effect.

  The reel rotation start command is a command for notifying the start of reel rotation in a game that is not controlled in the freeze state, which will be described later, and is transmitted when the rotation of the reels 2L, 2C, and 2R is started.

  The reel stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, the area number of the corresponding reel stop operation position, and the area number of the corresponding reel stop position. And is transmitted each time stop control is performed in accordance with the stop operation of each reel. Since the reel stop command is transmitted when the stop switches 8L, 8C, and 8R are operated, it is possible to specify that the stop switches 8L, 8C, and 8R are operated by receiving the reel stop command. .

  The winning number command is a command that can specify the combination of symbols aligned on the winning line LN, whether or not a winning is received, the type of winning, and the number of medals to be paid out at the winning. Sent after.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals is started by paying out a prize or credit (including medals used for setting the number of bets). The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning and winning a credit is completed.

  The return command is a command indicating that the main control unit 41 has returned to the control state before the power interruption, and is transmitted when the main control unit 41 returns to the control state before the power interruption.

  The game state command is a command that can specify the current game state (in BB, in RB, or replay), and is transmitted when power is restored or when the game ends.

  The RT information command is a command that can specify the gaming state of the next game (any one of RT0 to RT5), and is transmitted at the end of the game.

  The standby command is a command indicating a transition to the standby state, and after one game is over, a credit (which was used for setting the bet number) is set when the transition to the standby state is made after a predetermined time without setting the bet number. (Including medals) is sent out after the medal payout is completed and the payout end command is sent.

  The stop command is a command indicating the occurrence or release of the stop state, and after the end of the BB, the stop command indicating the occurrence of the stop state is transmitted when the ending effect waiting time has elapsed, and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted.

  An error command is a command that indicates the occurrence or cancellation of an error condition and the type of error condition. When an error is determined and controlled to an error condition, an error command indicating the occurrence and type of the error condition is sent and reset. When the error state is canceled after the operation is performed, an error command indicating the cancellation of the error state is transmitted.

  The setting command is a command indicating the start or end of the setting change state and the setting value after the setting change. At the time of transition to the setting change state, a setting command indicating the start of the setting change state is transmitted, and when the setting change state ends. A setting command indicating the end of the setting change state and the setting value after the setting change is transmitted. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it can be specified that the control state of the main control unit 41 has been initialized by the setting command indicating the start of setting. .

  The setting confirmation command is a command that indicates the start or end of the setting confirmation state. A setting confirmation command that indicates the start of setting confirmation is transmitted when entering the setting confirmation state, and the setting confirmation end is indicated when the setting confirmation state ends. A confirmation command is sent.

  The door command is a command indicating the detection state of the door opening detection switch 25, that is, on (open state) / off (closed state), when the power is turned on, at the end of one game (after the game is over, the bet number of the next game) Sent before the setting of ”can be started), and when the detection state of the door opening detection switch 25 changes (from on to off, from off to on).

  The operation detection command is a command indicating the detection state (on / off) of the operation switches (MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R), and is transmitted periodically.

  Of these commands, commands other than the door command and the operation detection command are generated in the basic process, temporarily stored in the command queue provided in the RAM 41c, and transmitted in the command transmission process of the timer interrupt process (main) described above. The

  On the other hand, the door command is generated in the door monitoring process of the timer interrupt process (main) and stored in the door command storage area. The door command storage area stores a door command indicating the detection state of the door opening detection switch 25 at the time of power-on or at the end of one game, and when the detection state of the door opening detection switch 25 changes, A door command indicating the detection state is stored. Further, the door command stored in the door command storage area is not cleared even after the door command is transmitted, and is then overwritten by a newly stored door command. When the power is turned on or one game is finished, a door command transmission request 1 for requesting transmission of a door command stored in the door command storage area is set, and whether the door command transmission request 1 is set or whether the door is open is detected. When the detection state of the switch 25 changes, it is temporarily stored in the command queue provided in the RAM 41c and transmitted in the subsequent command transmission process of the timer interrupt process (main).

  The operation detection command is generated in the switch input determination process of the timer interrupt process (main), temporarily stored in the command queue provided in the RAM 41c, and then the command transmission process of the timer interrupt process (main). And sent.

  Next, the control of the effect performed by the sub control unit 91 based on the command transmitted from the main control unit 41 to the effect control board 90 will be described.

  When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

  The reception buffer is provided with an area capable of storing a maximum of 16 commands so that a plurality of commands can be accumulated.

  In the timer interrupt process (sub), the sub-control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. If an unprocessed command is stored, the sub-control unit 91 is the earliest. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, effect effect LED 52, speakers 53, 54, reel LED 55, etc. are controlled based on the control contents registered in the control pattern table. Performs output control of various rendering devices.

  In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the lighting effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED, etc. Control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 stores the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among these, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. Thereby, the production according to the production pattern and the progress of the game is executed.

  If the sub-control unit 91 receives a new command during the execution of an effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and changes to the newly received command. An effect based on the corresponding control pattern is executed. In other words, even if the production is not finished to the end, when a new command is received, the production that was being executed is canceled and a new command is received unless the received new command is not a command that triggers a new production. An effect based on the command is executed.

  In particular, in this embodiment, when the betting number setting operation is performed during the execution of the effect, that is, when the sub-control unit 91 receives the inserted number command indicating that the betting number is set, The production is to be canceled. For this reason, if the player wants to proceed to the next game rather than seeing the production to the end, the production is canceled and the next game can be started. There is no. Further, when a credit or betting amount adjustment operation is performed during the performance, that is, after the sub-control unit 91 receives a game state command indicating the end of the game, it receives an internal winning command indicating the start of the game. When the payout start command is received before, the effect being executed is stopped. Credits and bets are settled when the game is terminated. In such a case, by terminating the performance that is being executed, there is an intention to end the game, but the performance continues unnecessarily. It is designed not to be overwhelmed.

  When the internal winning command is received, the effect pattern is selected at a selection rate corresponding to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 stores the effect pattern in the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the registered selection rate, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

  Next, the operation of the main control unit 41 will be described. First, in this embodiment, as already described, whether a user reset or a system reset is generated when a time-out signal from the watchdog timer (WDT) 506b or an IAT signal from the IAT circuit 506a is generated. Is possible (see FIG. 13). FIG. 47 is an explanatory diagram for explaining a difference in the reset operation depending on the setting content in the reset setting (KRES).

  First, a case where a system reset is set to occur when a time-out signal from the watchdog timer (WDT) 506b or an IAT signal from the IAT circuit 506a is generated will be described with reference to FIG. In this case, as shown in FIG. 47A, when the slot machine 1 is turned on and the power supply is started, the main control unit 41 initializes all internal circuits including the CPU core. Then, according to the setting contents of the program management area, various settings of the main control unit 41 such as setting of the internal reset operation and setting of the random number circuits 508a and 508b are performed by hardware (step S1001). Specifically, the internal reset operation is set in accordance with the setting contents of the reset setting (KRES) shown in FIG. 13 in the program management area, or the 16-bit random number initial setting 1 (shown in FIGS. 14 to 18 in the program management area). The random number circuits 508a and 508b are set according to the setting contents of KRL1) to 8-bit random number initial setting 2 (KRS2). In the example shown in FIG. 47A, the main control unit 41 sets the system reset as the setting of the internal reset operation according to the setting contents of the program management area. The setting contents of the program management area are set in advance by the manufacturer (user) when the slot machine 1 is manufactured.

  When the various settings of the main control unit 41 are completed, the main control unit 41 shifts to the security mode and executes a security check (step S1002). In the security check executed in step S1002, the user program is authenticated. Specifically, it is recalculated whether the authentication code calculated based on the user program is correct. If the authentication code is correct, the process proceeds to step S1003. If the authentication code is not correct, the CPU 41a is stopped. As described above, the security mode time to be shifted to the security mode is variable according to the setting contents of the security time setting (KSES) shown in FIG. 19 of the program management area. Specifically, the security mode time is set by setting in step S1001 according to the setting contents of the security time setting (KSES) shown in FIG. 19 of the program management area. It is assumed that the authentication code is written in advance together with the user program by the manufacturer (user) of the slot machine 1 when writing into the built-in ROM 41b when the slot machine 1 is manufactured.

  When the security check is finished, the main control unit 41 shifts to the user mode and starts executing the user program. Specifically, execution of a start-up process (main) in FIG. 49 described later, a game process shown in FIG. 50, and the like is started.

  Next, it is assumed that a timeout signal from the watchdog timer (WDT) 506b and an IAT signal from the IAT circuit 506a are generated while the user program is being executed. In the example shown in FIG. 47A, since the system reset is set as the setting of the internal reset operation in step S1001, the system reset is generated based on the generation of the timeout signal or the IAT signal.

  Then, as in step S1001, the main control unit 41 initializes all internal circuits including the CPU core, sets internal reset operation, sets random number circuits 508a and 508b, etc. according to the setting contents of the program management area. Various settings of the main control unit 41 are performed by hardware (step S1005). When various settings of the main control unit 41 are completed, the main control unit 41 shifts to a security mode and executes a security check (step S1006), as in step S1002.

  When the security check is completed, the main control unit 41 shifts to the user mode and starts executing the user program as in step S1003. Specifically, the execution of the startup process (main) in FIG. 49 described later is started again.

  Thereafter, each time a time-out signal from the watchdog timer (WDT) 506b or an IAT signal from the IAT circuit 506a is generated, the operations in steps S1004 to S1007 are executed. In FIG. 47A, the specific processing contents of steps S1001 and S1002 and the specific processing contents of steps S1005 and S1006 are the same.

  Next, a case where a user reset is set to occur when a time-out signal from the watchdog timer (WDT) 506b or an IAT signal from the IAT circuit 506a is generated will be described with reference to FIG. In this case, as shown in FIG. 47B, when the slot machine 1 is turned on and the power supply is started, the main control unit 41 initializes all internal circuits including the CPU core. Then, according to the setting contents of the program management area, various settings of the main control unit 41 such as setting of the internal reset operation and setting of the random number circuits 508a and 508b are performed by hardware (step S1011). Specifically, the internal reset operation is set in accordance with the setting contents of the reset setting (KRES) shown in FIG. 13 in the program management area, or the 16-bit random number initial setting 1 (shown in FIGS. 14 to 18 in the program management area). The random number circuits 508a and 508b are set according to the setting contents of KRL1) to 8-bit random number initial setting 2 (KRS2). In the example shown in FIG. 47B, the main control unit 41 sets the user reset as the setting of the internal reset operation according to the setting contents of the program management area. The setting contents of the program management area are set in advance by the manufacturer (user) when the slot machine 1 is manufactured.

  When the various settings of the main control unit 41 are completed, the main control unit 41 shifts to the security mode and executes a security check (step S1012). In the security check executed in step S1012, the user program is authenticated. Specifically, it is recalculated whether the authentication code calculated based on the user program is correct. If the authentication code is correct, the process proceeds to step S1013. If the authentication code is not correct, the CPU 41a is stopped. As described above, the security mode time to be shifted to the security mode is variable according to the setting contents of the security time setting (KSES) shown in FIG. 19 of the program management area. Specifically, the security mode time is set by performing the setting in step S1011 according to the setting contents of the security time setting (KSES) shown in FIG. 19 of the program management area. It is assumed that the authentication code is written in advance together with the user program by the manufacturer (user) at the time of writing into the built-in ROM 41b when the slot machine 1 is manufactured.

  When the security check is finished, the main control unit 41 shifts to the user mode and starts executing the user program. Specifically, execution of a startup process (main) in FIG. 49 described later is started.

  Next, it is assumed that a timeout signal from the watchdog timer (WDT) 506b and an IAT signal from the IAT circuit 506a are generated while the user program is being executed. In the example shown in FIG. 47B, the user reset is generated based on the generation of the timeout signal or the IAT signal because the user reset is set as the setting of the internal reset operation in step S1011.

  When a user reset occurs, the various settings of the main control unit 41 in step S1011 and the security check in step S1012 are not executed. Among the internal circuits of the main control unit 41, the CPU core, timer circuit 509, free run counter The circuit 507, the arithmetic circuit 505, the parallel input port 511, the parallel output port 513, the serial communication circuit 512, the interrupt controller 510, and the like are initialized. Then, it returns to the top address of the user program as it is, and the execution of the user program is started again from the top address (step S1015). Specifically, the execution of the startup process (main) in FIG. 49 described later is started again.

  Thereafter, each time the time-out signal from the watchdog timer (WDT) 506b or the IAT signal from the IAT circuit 506a is generated, the operations in steps S1014 to S1015 are executed.

  In this embodiment, when the main control unit 41 reads data stored in the internal RAM area during execution of the user program, the main control unit 41 sets all upper and lower addresses of the internal RAM area in which the data is stored. Instead of designating, it is possible to designate only the lower part of the address and read the data. FIG. 48 is an explanatory diagram showing an example of how to read data stored in the internal RAM area. In this embodiment, data referred to by the user program is stored in the F000H to F0FFH areas of the built-in RAM area, and the upper address of the data storage area is always F0H. The main control unit 41 is provided with a dedicated register (Q register) for storing the upper address of the data storage area as a fixed value, and a fixed value F0H is set in the Q register.

  In the example shown in FIG. 48, the case where the data stored in the address F020H of the internal RAM area is read is shown. In this case, using the command LDQ for reading data using the Q register, only the lower address 20H is designated and the data read operation is performed (specifically, LDQ A, (20H) is executed). . Then, the CPU 41a specifies the upper address of the data storage area as F0H from the fixed value set in the Q register, specifies the lower address 20H specified by the LDQ instruction, and combines the upper and lower data storage areas. Is specified as F020H. Then, the CPU 41a reads the data a stored in the data storage area corresponding to the specified F020H and stores it in the register A.

  Note that the value of the Q register is initialized by hardware at the time of system reset and automatically set to the initial value F0H. For example, when power is supplied to the slot machine 1 and power supply is started, the lower 4 bits of the Q register are initialized to 0, and the upper 4 bits are inverted by an inverting circuit so that all values are 1. Thus, F0H is automatically set as the initial value of the Q register. As will be described later, in this embodiment, even when the execution of the user program is started, the process for setting the initial value F0H in the Q register is executed by the user program.

  The initial value of the Q register may be set only by hardware automatic setting performed when power is supplied to the slot machine 1 and power supply is started, or a user program executed at the start of the user program Only the setting by may be used.

  Next, a process executed according to the user program after the main control unit 41 executes the system check and then shifts to the user mode will be described. When the mode is shifted to the user mode, the main control unit 41 starts executing the start process (main).

  FIG. 49 is a flowchart showing the control content of the startup process (main) executed by the main control unit 41.

  In the start-up process (main), interrupts are first disabled (Sa1), and the parallel output port 513 and the built-in registers are initialized (Sa2, Sa3). Next, it is determined whether or not the voltage drop signal from the power interruption detection circuit 48 is detected, that is, whether or not the voltage is unstable (Sa4). If the voltage drop signal is detected, the voltage drop is detected. Wait until no signal is detected.

  If a voltage drop signal is not detected in step Sa4, the address of the program to be executed when an interrupt occurs is set in the I register (Sa5), access to the RAM 41c is permitted (Sa6), and the stack pointer is set ( Sa7), the initial value F0H is set in the Q register (Sa8). That is, the initial value F0H is set in the Q register at the timing when access to the RAM 41c is permitted.

  Next, the RAM parity of all the storage areas (including the unused area and the unused stack area) of the RAM 41c is calculated (Sa9), and it is determined whether or not the RAM parity is 0 (Sa10). If the power interruption interrupt processing (main) is normally performed, the RAM parity should be 0. If the RAM parity is not 0 in the step of Sa7, the data stored in the RAM 41c is not normal. In this case, the process proceeds to step Sa14.

  On the other hand, if the RAM parity is 0 in step Sa10, it is further determined whether or not the destructive diagnosis data is normal (Sa11). If power interruption interrupt processing (main) is performed normally, the data for destruction diagnosis should be set, and if the data for destruction diagnosis is not normal in step Sa11 (data for destruction diagnosis is power interruption) Since the data in the RAM 41c is not normal also in cases other than 5A (H) stored sometimes, the process proceeds to step Sa14.

  If it is determined in step Sa11 that the destructive diagnosis data is normal, the data in the RAM 41c is normal, so the destructive diagnosis data is cleared (Sa12), and the RAM 41c indicates that the data is normal. A normal flag is set in the RAM 41c (Sa13), and the process proceeds to step Sa14.

  In step Sa14, it is determined whether or not the setting key switch 37 is on. If the setting key switch 37 is on, the initializing process for initializing all storage areas in the RAM 41c except for the in-use stack area is performed. After executing the conversion 1 (Sa15), the interruption is permitted (Sa16), and the setting command indicating the setting start is set in the command queue (Sa17). The setting command set in step Sa17 is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main).

  After the step Sa17, the process proceeds to a setting change process controlled to a setting change state in which the setting value can be changed (Sa18). After the setting changing process is completed by setting a new setting value, the setting is terminated. The setting command shown is set in the command queue (Sa19), and the process proceeds to game processing. The setting command set in step Sa19 is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main).

  If the setting key switch 37 is off in step Sa14, it is determined whether or not the data in the RAM 41c is normal based on whether or not the RAM normal flag is set (Sa20), and the data in the RAM 41c is determined not to be normal. The initialization 1 similar to Sa15 is executed to initialize all the storage areas in the RAM 41c except the used stack area (Sa21), and interrupts are permitted (Sa22). Then, an error code indicating a RAM abnormality is set (Sa23), an error command indicating a RAM abnormality is set in the command queue (Sa24), and an error process, that is, a RAM abnormality error state is entered. The error command set in step Sa24 is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main). Also, unlike a normal error, a RAM abnormality error does not return to a state in which the game can proceed until a new set value is set.

  If it is determined in the step Sa20 that the data in the RAM 41c is normal, the stack pointer is initialized after performing initialization 3 for initializing the non-saved work, the unused area and the unused stack area in the RAM 41c (Sa25). Is restored to the state before power interruption (Sa26), and the return command is set in the command queue (Sa27). The return command set in step Sa27 is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main). Next, the input buffer for storing the input state of detection signals such as various switches input to the parallel input port 511 is initialized (Sa28), and the output state of the parallel output port 513 is restored to the state before power interruption ( Sa29), each register is restored to the state before the power interruption, that is, the state saved in the stack (Sa30), the interrupt is permitted (Sa31), and the process executed at the end before the power interruption is returned. .

  FIG. 50 is a flowchart showing the control contents of the game process executed by the main control unit 41.

  In the game process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a winning determination process (Sd4), a payout process (Sd5), and a game end process (Sd6) are sequentially executed. When the end-time process ends, the process returns to the BET process again.

  In the BET process in the step of Sd1, the process waits in a state where a bet number can be set, and a process for starting a game when a specified number of bets is set according to the gaming state and the start switch 7 is operated is executed. .

  In the internal lottery process in the step of Sd2, a process is performed for determining whether or not winning in each of the above-mentioned winning combinations is allowed based on the internal lottery random value latched when the start switch 7 is detected in the step of Sd1. In this internal lottery process, a winning flag is set in the RAM 41c based on the respective lottery results.

  In the reel rotation process in the step of Sd3, the process of rotating each reel 2L, 2C, 2R, and the operation of the stop switch 8L, 8C, 8R by the player is detected. A process for stopping the rotation is executed.

  In the winning determination process in the step Sd4, when it is determined in the step Sd3 that the rotation of all the reels 2L, 2C, and 2R is stopped, the winning is determined according to the display result derived for each reel 2L, 2C, and 2R. A process of determining whether or not it has occurred is executed.

  In the payout process in step Sd5, when it is determined that a prize is generated in step Sd4, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd6, a process of setting a gaming state in preparation for the next game is executed.

  In the game process, a command is set in the command queue in accordance with the progress control of the game, and is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main). Yes.

  FIG. 51 is executed when an operation of the start switch 7, that is, a change of the start switch 7 from off to on is detected in a state where the game can be started in the BET process executed in the step Sd1 by the main control unit 41. It is a flowchart which shows the control content of a random number acquisition process.

  In the random number acquisition process, interrupts are first set to be prohibited (Se1), and the start switch 7 is thus operated in a state where the game can be started. By executing the power interruption process (main) without acquiring the random number value that has been acquired, it is possible to prevent the game from starting even though the random number value has not been acquired at the time of power recovery.

  Next, it is determined whether or not another switch is on (Se2). If any switch is on, interrupt is permitted (Se4), and the operation of the start switch 7 in the BET process is detected. Return to the waiting state.

  If none of the other switches are on in the step of Se2, the specified number of bets set in the RAM 41c is further referred to, and whether the value of the BET counter assigned to the RAM 41c is the specified number, that is, the game It is determined whether or not the number of bets serving as a start condition is set (Se3).

  If the value of the BET counter is not the specified number in the step of Se3, the interruption is permitted (Se4) and the process returns to the state of waiting for the detection of the operation of the start switch 7 in the BET process.

  If the value of the BET counter is a specified number in the step of Se3, it is determined whether or not a random number abnormality is detected (Se5).

  The main control unit 41 has a function of detecting an operation abnormality (external clock frequency abnormality and update abnormality) of the random number circuit 508b. When an external clock frequency abnormality is detected, the bit of the internal information register (CIF) When “1” is set to 3 and an abnormal update is detected, “1” is set to the corresponding bit among bits 7 to 4 of the internal information register (CIF). Yes. For this reason, in the step of Se5, it is determined whether or not a random number abnormality is detected based on whether or not “1” is set in any of the values of the internal information register (CIF) bit 3 and bits 7 to 4. It ’s fine.

  If a random number abnormality is detected in step Se5, an error code indicating random number abnormality is set in the register (Se6), an error command indicating random number abnormality is set in the command queue (Se7), and an interrupt is issued. Permit (Se8) and shift to error processing. The error command set in the step of Se7 is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main). Similarly to the RAM abnormality error, the random abnormality error does not return to a state in which the game can proceed until a new set value is set.

  When no random number abnormality is detected in the step of Se5, the value stored in the RL0 hard latch random number register 0 (RL0HV0) of the random number circuit 508b, that is, the disturbance latched at the timing when the start switch 7 is operated. A numerical value is set in the lottery work assigned to the RAM 41c (Se9), an interruption is permitted (Se10), and a setting at the start of the game is performed (Se11). Then, after the step of Se11, the BET process is terminated and the process returns to the flowchart of FIG. That is, the process proceeds to the internal lottery process in step Sd2.

  FIG. 52 is a flowchart showing the control content of the internal lottery process executed by the main control unit 41 in step Sd2.

  In the internal lottery process, first, the random number set for the lottery work is set in the register (Sf1), and the first lottery target combination corresponding to the current gaming state and RT is set (Sf2).

  Next, the number of determination values corresponding to the current game state, RT, and set value of the set lottery target combination is acquired (Sf3), and the acquired determination value number is added to the value set in the register (Sf4). Then, it is determined whether or not the value after the addition has overflowed, that is, whether or not the total number of random numbers (65536) has been exceeded (Sf5).

  If the value after the addition has overflowed in the step of Sf5, the winning flag of the corresponding winning combination, that is, the currently selected lottery object winning combination is set in the internal winning flag storing work (Sf6), and the internal lottery process is performed. When the game ends, the process returns to the game process shown in FIG. 50 and proceeds to the reel rotation process.

  When the value after the addition does not overflow in the step of Sf5, it is determined whether or not the determination of all the lottery target combinations according to the current gaming state and RT is completed (Sf7), and all the lottery targets If the determination of the combination has not ended, the next lottery target combination is set, and the process returns to step Sf3.

  If all the lottery target combinations have been determined in step Sf7, the internal lottery process is terminated, the process returns to the game process shown in FIG. 50, and the process proceeds to the reel rotation process.

  FIG. 53 is a flowchart showing the control contents of the power interruption process (main) executed in response to the power interruption detected in the timer interrupt process (main) by the main control unit.

  In the power interruption process (main), first, all registers that may be in use are saved in the stack area (Sm1). Although the value of the I register described above is used, it is not saved here because the same fixed value is always set with the initialization at the time of startup.

  Next, destruction diagnosis data (5A (H) in this embodiment) is set (Sm2), and the parallel output port 513 is initialized (Sm3). Next, the RAM parity adjustment data is calculated and set in the RAM 41c so that the exclusive OR of all the storage areas (including the unused area and the unused stack area) of the RAM 41c becomes 0 (Sm4). Access is prohibited (Sm5), and loop processing starts.

  In the loop processing, the process waits in a state where the output state of the voltage drop signal is monitored (Sm6). In this state, when the voltage drop signal is not input, it is determined that the voltage has been restored, and the program is started from the startup process (main). On the other hand, when the voltage drops while the voltage drop signal is input, the operation is stopped internally.

  When the power supply is stopped by the above process, the power interruption process (main) is executed, the destruction diagnosis data and the RAM parity adjustment data are stored in the backup RAM, the RAM access is disabled, and the output The port is cleared.

  In this embodiment, after completion of processing such as generation of check data (destructive diagnosis data and RAM parity adjustment data) and output port clear in the power supply processing (main), input of a voltage drop signal is repeatedly confirmed. Although the process shifts to a power-off waiting loop, it may not be configured to confirm the input of such a voltage drop signal. In this case, for example, the watchdog timer (WTD) 506b is set to be activated by the user program, and the watchdog timer (WTD) 506b is activated when entering the power-off waiting loop. When the power supply is not completely cut off and the voltage value of the power supply does not drop completely, a reset by a time-out signal from the watchdog timer (WTD) 506b may be generated.

  Also, in this embodiment, it is confirmed whether or not a power-off signal is input when the power to the slot machine 1 is turned on. If it is input, the infinite loop is entered, and the voltage drop signal is input to the infinite loop. In this configuration, the infinite loop is continued until there is no more input. In such a configuration, the watchdog timer (WTD) 506b is activated when entering the infinite loop in the same manner as described above, and the same processing is performed. You may comprise so that it may perform.

  If the watchdog timer (WTD) 506b is set to be activated (except for the watchdog timer (WTD) 506b activated only in the power-off waiting loop as described above), it is normal. The CPU 41a is programmed to output a signal for clearing the watchdog timer (WTD) 506b so as not to time out when the CPU 41a is operating. Specifically, it is programmed to write a value for clearing in a WDT clear register (not shown) provided in the built-in register area.

  In this embodiment, the RAM 41c is backed up by a backup power source (the contents of the RAM 41c are preserved for a predetermined period even when the power supply to the slot machine 1 is stopped). In the present embodiment, both the destruction diagnosis data and the RAM parity adjustment data based on the contents of the RAM 41c when the voltage drop signal is output in the power interruption process (main) are stored in the backup area of the RAM 41c. After the power supply to the slot machine 1 is stopped, when the power supply is restored within a predetermined period, the main control unit 41 changes its control state to the power according to the data stored in the RAM 41c by the activation process (main). It is possible to return to the state immediately before the supply is stopped. If the power supply stop period exceeds a predetermined period, the RAM parity does not become 0, or even if the RAM parity becomes 0, the destruction diagnosis data is damaged. In this case, the storage area of the RAM 41c Among these, initialization 1 is executed to initialize all the storage areas except the used stack area.

  In this way, the data for returning the control state relating to the game of the main control unit 41 to the state immediately before the power supply is stopped is surely stored in the RAM 41c by the power interruption process (main) (preparation process for power supply stop). Saved in. Therefore, even if the power is cut off due to a power failure or the like, if the power is restored within a predetermined period, the control state related to the game of the main control unit 41 can be returned to the state immediately before the power supply is stopped.

  If the voltage drop signal is turned off after the power interruption process (main), the process returns to the first step of the user mode (startup process (main)). In this case, since the power interruption process (main) is normally executed, the control state recovery process is executed by the activation process (main). Therefore, when the voltage drop signal is turned off after executing the power interruption process (main), the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the process related to the progress of the game is not stopped, and the process related to the progress of the game is automatically continued.

  In this embodiment, a predetermined event occurs during execution of a predetermined process (game process, timer interrupt process (main)) (an IAT signal is input from the IAT circuit 506a, a time-out signal is output from the watch dog timer (WDT) 506b). ), The stored contents of the RAM 41c (backup RAM) are initialized. Specifically, when an IAT signal is input from the IAT circuit 506a or a time-out signal is input from the watchdog timer (WDT) 506b during execution of the game process or timer interrupt process (main), the power interruption process (main) is performed. Without being executed, a system reset or a user reset (see steps S1004 and S1014 in FIG. 47) will occur. Then, after a system reset occurs, a security check is performed, and then the process shifts to the user mode in step S1007, and the start-up process (main) shown in FIG. 49 is started again. After a user reset occurs, in step S1015 Returning to the top of the user program, the execution of the startup process (main) shown in FIG. 49 is started again. However, since neither the RAM adjustment data nor the destruction diagnosis data is set, the startup process (main) is started. Thus, it is determined that the RAM is abnormal, and initialization 1 is executed to initialize all the storage areas except the used stack area among the storage areas of the RAM 41c.

  The “predetermined process” is a process that is executed in a state where a game is enabled after the setting change process and the recovery process are executed in the startup process (main) when the power to the slot machine 1 is turned on. Yes, as described above, specifically, game processing and timer interrupt processing (main) are applicable. However, when the power interruption process (main) is being executed due to the power supply voltage drop, it is excluded from the predetermined process.

  Further, in this embodiment, when a predetermined event occurs after executing the power interruption process (main) (the IAT signal is input from the IAT circuit 506a and the time-out signal is input from the watchdog timer (WDT) 506b), the RAM 41c ( Based on the stored contents of the backup RAM), a recovery process for restoring the control state to the state before the power interruption is executed. Specifically, when the power interruption process (main) is executed based on the input of the voltage drop signal and the loop process is executed, the IAT signal from the IAT circuit 506a or the watchdog timer (WDT) When a time-out signal is input from 506b (however, when an IAT signal is input from the IAT circuit 506a, it is a case where a program outside the designated area is being executed for some reason. This corresponds to a case where an IAT signal is sent from the IAT circuit 506a after transitioning to the loop process of the power interruption process (main), and a system reset or a user reset based on the input of an IAT signal or a timeout signal (step of FIG. 47) S1004 and S1014) are generated. Then, after a system reset occurs, a security check is executed, and then in step S1007, the mode is shifted to the user mode and the start process (main) is started again. After a user reset occurs, the top of the user program is started in step S1015. The execution of the startup process (main) is started again, but since both the RAM adjustment data and the destruction diagnosis data are set, it is determined that the RAM 41c is normal in the startup process (main). Then, the recovery process is executed.

  As described above, in this embodiment, the first event is generated based on the occurrence of a predetermined event (in this embodiment, the input of the IAT signal from the IAT 506a and the input of the timeout signal from the watchdog timer (WDT) 506b). Whether to generate a reset (system reset) or a second reset (user reset) can be set (see bit 7 of the reset setting (KRES) shown in FIG. 13). The security check is executed after the first reset occurs, while the security check is not executed after the second reset occurs. Therefore, the type of reset to be performed when a predetermined event occurs according to the situation of the slot machine 1 or the amusement store can be set to an optimum one, so that the security related to the main control unit 41 can be improved.

  In this embodiment, as the occurrence of the predetermined event, the case where the IAT signal from the IAT 506a is input and the case where the time-out signal is input from the watchdog timer (WDT) 506b are shown. Not limited to those shown, the main control unit 41 may be reset based on the occurrence of a predetermined event based on the occurrence of some error or other situation.

  In this embodiment, the occurrence of the predetermined event includes a timeout of the watchdog timer (WDT) 506b, and it is possible to set whether or not to activate the watchdog timer (WDT) 506b (shown in FIG. 13). “0000” is set to bits 3-0 of the reset setting (KRES)). Even when it is set not to activate the watchdog timer (WDT) 506b, it is possible to set whether to generate the first reset or the second reset based on the occurrence of the predetermined event. Specifically, in the reset setting (KRES) shown in FIG. 13, even if “0000” is set in bits 3-0, the type of reset can be set by setting bit 7. Therefore, regardless of the setting of the watchdog timer (WDT) 506b, the setting of the type of reset to be generated based on the occurrence of a predetermined event can be made common.

  Further, in the present embodiment, the occurrence of the predetermined event includes out-of-designated-area execution (execution outside designated area (IAT) for executing a program stored in an area other than the designated area, and main control). The unit 41 executes execution outside the specified area during execution of a timer interrupt process (main) executed in response to a timer interrupt process generated every predetermined time as a predetermined process (inputting an IAT signal from the IAT circuit 506a) ), The storage contents of the RAM 41c (backup RAM) are initialized (initialization 1 due to RAM abnormality), so that security can be improved when an unintended program is executed.

  Further, in this embodiment, when it is set that the first reset is generated, after the predetermined event occurs and the first reset is generated, is the first reset generated based on the occurrence of the predetermined event? Whether to generate the second reset is set again. Specifically, as shown in FIG. 47A, when a system reset occurs, step S1005 is executed, and various settings of the main control unit 41 are executed again in terms of hardware. The reset or user reset is set again. Therefore, it is possible to reliably recover from an abnormal state to a normal state.

  In this embodiment, specifically, an internal reset occurs after a predetermined event occurs (input of IAT signal from IAT 506a, input of timeout signal from watchdog timer (WDT) 506b) and system reset occurs. Is set again (see step S1005 in FIG. 47A), but when a user reset occurs, the same processing as in step S1005 is executed to set the internal reset setting again. You may do it.

  In this embodiment, the frequency of the random number clock signal (external clock signal) for updating the numerical data held by the numerical value holding means (hard latch random value register or soft latch random value register) of the 16-bit random number circuit 508b. Random number circuit monitoring means (update monitoring circuit 537) capable of monitoring the occurrence of the abnormality and the update state of the numerical data held by the numerical value holding means. Therefore, it is possible to monitor the occurrence of abnormality in the frequency of the random number clock signal and monitor the update state of the numerical data. Further, the main control unit 41 executes steps S1001 and S1011 when the power to the slot machine 1 is turned on to perform setting related to the random number circuits 508a and 508b in hardware, and then extracts a random number during execution of the user program. Execute the process. That is, in the present embodiment, the configuration relating to the monitoring of the random number circuit is performed prior to the timing of extracting the numerical data (random number value) from the random number circuit, so the random number circuit mounted in the slot machine 1 is configured. Security related to (16-bit random number circuit 508b) can be improved. Further, since it is determined whether or not the internal lottery, that is, the generation of a prize is permitted, using the random number generated by the highly secure random number circuit, the fairness of the game can be improved.

  In the present embodiment, the control CPU (CPU 41a) mounted on the main control unit 41 is based on the first information (the upper address of the data storage area) and the second information (the lower address of the data storage area). The address corresponding to the area where the data to be read is stored is specified, and the data to be read is read from the area corresponding to the specified address. In this case, when the data to be read is read, the first information is specified based on the specific value ("F0H" stored as a fixed value) stored in the storage means (Q register), and the control command The designated second information (in the example shown in FIG. 48, “20H” designated by the LDQ command (one of the programmed instructions)) is specified. For this reason, by using the storage means (Q register), there is no need to specify a fixed portion (higher address) of the address of the data storage area with a command each time. (Waste of a program for specifying a common part of an address) can be reduced.

  Further, in this embodiment, the control CPU (CPU 41a), after the power supply to the slot machine 1 is started, at the timing when access to the RAM 41c is permitted, the address corresponding to the work area provided in the RAM 41c. Is stored in the storage means (Q register) as a specific value. Therefore, by storing a specific value in the storage means at a timing when access to the RAM 41c is permitted, waste of a program for designating an address corresponding to a work area provided in the RAM 41c thereafter is reduced. Can do.

  In this embodiment, the specific value is stored as follows: (1) a process for storing the specific value in the storage means at a timing when access to the RAM 41c is permitted; and (2) a specific value is always stored in the storage means. The case where it has both the structure made into the state which is carrying out is shown. Specifically, in the present embodiment, when the execution of the user program is started and the startup process (main) is started, a process for setting the initial value F0H in the Q register is executed by the user program and a system reset is performed. It is sometimes assumed that the Q register n value is automatically set to the initial value F0H by being initialized by hardware. For example, when power is supplied to the slot machine 1 and power supply is started, the lower 4 bits of the Q register are initialized to 0, and the upper 4 bits are inverted by an inverting circuit so that all values are 1. Thus, F0H is automatically set as the initial value of the Q register. However, the initial value of the Q register may be set only by a user program executed at the start of the user program, or it may be performed by hardware when power is supplied to the slot machine 1 and power supply is started. Only automatic setting may be used.

  In this embodiment, a command that can be used as a control command in the main control unit 41 installed in the slot machine 1 is stored in a register data according to a predetermined rule and an address specified by another 2-byte register. There are RLD commands and RRD commands (both are one of programmed instructions) that can be exchanged with (stored) data. For example, if the RLD command is used to replace the data in register A with the data stored (stored) at the address specified by the 2-byte register, the upper 4 bits of data in register A remain unchanged. The lower 4 bits of data in A are transferred to the lower 4 bits of the address specified by the 2-byte register, and the lower 4 bits of the data stored (stored) at the address specified by the 2-byte register are stored in the 2-byte register. It is possible to move to the upper 4 bits of the address designated by the upper 4 bits of the data stored (stored) at the address designated by the 2-byte register to the lower 4 bits of the register A. In this case, for example, if data in a non-writable area (for example, data in the ROM area) is specified as data stored (stored) at an address specified by a 2-byte register, a 2-byte register is used. Only the operation of reflecting the upper 4 bits of the data stored (stored) at the address specified by the 2-byte register in the lower 4 bits of the register A while leaving the data stored (stored) at the specified address as it is Can also be executed.

  For example, when the data of the register A and the data stored (stored) at the address specified by the 2-byte register are exchanged using the RRD command, the upper 4 bits of the data of the register A are not changed. The lower 4 bits of data in register A are transferred to the upper 4 bits of the address specified by the 2-byte register, and the upper 4 bits of the data stored (stored) at the address specified by the 2-byte register are 2 bytes. It is possible to move to the lower 4 bits of the address designated by the register, and to move the lower 4 bits of the data stored (stored) at the address designated by the 2-byte register to the lower 4 bits of the register A. In this case, for example, if data in a non-writable area (for example, data in the ROM area) is specified as data stored (stored) at an address specified by a 2-byte register, a 2-byte register is used. The lower 4 bits of the data stored (stored) at the address specified by the 2-byte register is reflected in the lower 4 bits of the register A while the data stored (stored) at the specified address remains unchanged. It is also possible to execute only the operation.

  In the slot machine 1 according to the present embodiment, a winning is awarded when the winning symbols are aligned on any winning line. The types of winning combinations are determined according to the state of the game, but can be broadly divided into special roles with transition to big bonus and regular bonus, small roles with payout of medals, and setting of bet number. There is a re-player who can start the next game without needing.

  The big bonus may be indicated as BB and the regular bonus may be indicated as RB. In some cases, a big bonus or a regular bonus is simply referred to as a bonus. In order for winning of each combination determined according to the gaming state to occur, it is necessary to set a winning flag in the RAM 41c to win the internal lottery and allow winning of the winning combination.

  54 to 57 are diagrams for explaining the types of winning combinations, the symbol combinations of winning combinations, and technical matters related to winning combinations. 58 is a diagram for explaining the transition of the gaming state controlled by the main control unit 41, and FIG. 59 is a diagram showing an outline of the gaming state and RT.

  As shown in FIG. 58, the slot machine in this embodiment is controlled to one of RT0 to RT5, RB, and BB (RB).

  Referring to FIG. 54, among the winning combinations, special bonuses include big bonuses 1 to 4 (hereinafter, each big bonus is referred to as BB), regular bonuses 1 and 2 (hereinafter, each regular bonus is referred to as RB). ) 6 types of bonuses are included.

  BB1 is awarded when the combination of “network 7-network 7-network 7” is aligned on the winning line. BB2 is awarded when the combination of “white 7-white 7-white 7” is aligned on the winning line.

  When winning a prize in either BB1 or BB2, the game shifts to a big bonus that is controlled in every game for the regular bonus during BB (hereinafter referred to as BBRB).

  The big bonus generated due to the winning of either BB1 or BB2 ends on condition that 316 or more medals have been paid out.

  RB1 wins when a combination of “net 7-net 7-black 7” is aligned on the pay line. RB2 is awarded when the combination of “white 7-white 7-black 7” is aligned on the winning line.

  When winning one of RB1 and RB2, a transition is made to a regular bonus (hereinafter referred to as RB).

  The regular bonus generated due to the winning of either RB1 or RB2 ends on the condition that any winning combination has won 6 times or 12 games have been consumed.

  As shown in FIG. 58, it is controlled to RT4 from the internal winning of either BB1 or RB2 until winning, and it is controlled to RT5 from the internal winning of either BB2 or RB1 to winning. The As shown in FIG. 58, after the big bonus or regular bonus (collectively referred to as a bonus) is completed, the control is performed to RT3.

  Even if one of BB1, BB2, RB1, and RB2 is won in the internal lottery described above, if the stop switches 8L, 8C, and 8R are not operated at an appropriate timing to enable winning of these roles, these I won't win a role. The symbols that make up BB1, BB2, RB1, and RB2 ("Black 7" and "White 7" on the left and middle reels, "Black 7", "White 7", and "Net 7" on the right reel) are respectively This is because the left reel 2L, the middle reel 2C, and the right reel 2R are not arranged within 5 frames.

  Next, with reference to FIG. 55, the small combination among the winning combinations will be described. Among the winning combinations, the small combination includes a middle bell, a right-down bell, an upper bell 1-8, a lower cherry, a one-piece combination, and a right-up bell.

  The middle bell is awarded when the combination of “bell-bell-bell” is arranged on the winning line LN, and eight medals are paid out.

  Here, referring to FIG. 3, the bells are arranged within 5 frames in each of the left reel 2L, the middle reel 2C, and the right reel 2R. For this reason, it can be said that, in principle, when a middle bell is won in an internal lottery to be described later, it can be said that a winning can be made regardless of the operation timing of the stop switches 8L to 8R.

  A downward-sloping bell is when any combination of “Replay-Bell-Replay”, “Replay-Bell-Plum”, “Plum-Bell-Replay”, and “Plum-Bell-Plum” is aligned on the winning line LN. Wins and 8 medals are paid out.

  Here, referring to FIG. 3, the replay and plum of the left reel 2L are arranged at a position one below the bell, and the replay and plum of the right reel 2R are arranged at a position one above the bell. Therefore, when any combination of “Replay-Bell-Replay”, “Replay-Bell-Plum”, “Plum-Bell-Replay”, and “Plum-Bell-Plum” is prepared, “Bell-Bell-Bell” ”Are lowered to the right, that is, aligned with the invalid line LM3.

  Further, either the plum or the replay is arranged within 5 frames in each of the left reel 2L and the right reel 2R, and the bell is arranged within 5 frames in the middle reel 2C. For this reason, it can be said that, in principle, when a right-down bell is won in an internal lottery to be described later, it can be said that a winning can be made regardless of the operation timing of the stop switches 8L to 8R.

  Next, the upper bells 1 to 8 will be described. The upper bell 1 is awarded when the combination of “Replay-Orange-Orange” is aligned on the winning line LN. The upper bell 2 is awarded when the combination of “Replay-Orange-BAR” is aligned on the winning line LN. The upper bell 3 is awarded when the combination of “Replay-BAR-Orange” is aligned on the winning line LN. The upper bell 4 is awarded when the combination of “Replay-BAR-BAR” is aligned on the winning line LN. The upper bell 5 is awarded when a combination of “plum-orange-orange” is arranged on the winning line LN. The upper bell 6 is awarded when the combination of “Plum-Orange-BAR” is aligned on the winning line LN. The upper bell 7 is awarded when a combination of “Plum-BAR-Orange” is aligned on the winning line LN. The upper bell 8 is awarded when the combination of “Plum-BAR-BAR” is aligned on the winning line LN.

  Here, referring to FIG. 3, the replay and plum of the left reel 2L, the BAR and orange of the middle reel, and the BAR and orange of the right reel 2R are arranged at positions one level below the bell. “Orange-Orange”, “Replay-Orange-BAR”, “Replay-BAR-Orange”, “Replay-BAR-BAR”, “Plum-Orange-Orange”, “Plum-Orange-BAR”, “Plum-BAR-” When any combination of “Orange” and “Plum-BAR-BAR” is aligned, the “Bell-Bell-Bell” combination is aligned to the upper stage, that is, the invalid line LM1.

  In the left reel 2L, replays and plums are not arranged within 5 frames, and orange and BAR are not arranged within 5 frames for each of the middle reel 2C and the right reel 2R. Therefore, even if one of the upper bells 1 to 8 is won in the internal lottery to be described later, the stop switches 8L, 8C, and 8R corresponding to the winning upper bell configuration symbols must be operated at an appropriate timing. For example, you won't win the winning top bell.

  The lower cherries are awarded when the combination of “BAR-Orange-ANY (ANY can be any symbol)”, “BAR-BAR-ANY”, “BAR-Bell-ANY” on the winning line LN. . When the lower cherries win, two medals are paid out.

  Here, referring to FIG. 3, since the BAR of the left reel 2L is arranged one position above the cherry, “BAR-orange-ANY (ANY can be any symbol)”, “BAR- When any combination of “BAR-ANY” and “BAR-Bell-ANY” is prepared, “Cherry” on the left reel stops at the lower stage, and the combination of “Cherry-ANY-ANY” moves up and down to the right, That is, they are aligned with the invalid lines LM2 and LM4.

  In the middle reel 2C, any one of orange, BAR, and bell is arranged within 5 frames, but in the left reel 2L, BAR is not arranged within 5 frames. For this reason, even if the lower cherries are won in an internal lottery to be described later, the lower cherries will not be won if the stop switch 8L corresponding to the left reel 2L is not operated at an appropriate timing.

  One winning combination is awarded when the combination of “Black 7-Cherry-Net 7” is aligned on the winning line LN. When one winning combination wins, one medal is paid out.

  Here, referring to FIG. 3, the black 7 of the left reel 2L, the cherry of the middle reel, and the net 7 of the right reel are not arranged within 5 frames. For this reason, even if one winning combination is won in an internal lottery to be described later, the stop switches 8L, 8C, and 8R corresponding to the left reel 2L, the middle reel 2C, and the right reel 2R are not operated at an appropriate timing. I won't win a prize.

  The bells that go up to the right are "Black 7-Bell-Orange", "White 7-Bell-Orange", "Watermelon Bell-Orange", "Black 7-Bell-BAR", and "White 7-Bell-" on the winning line LN. When any combination of “BAR” and “Watermelon Bell-BAR” is completed, a prize is awarded and 10 medals are paid out.

  Here, referring to FIG. 3, black 7, white 7 and watermelon of the left reel 2L are arranged one position above the bell, and orange and BAR of the right reel 2R are one position below the bell. "Black 7-Bell-Orange", "White 7-Bell-Orange", "Watermelon Bell-Orange", "Black 7-Bell-BAR", "White 7-Bell-BAR" When any combination of “watermelon-bell-BAR” is aligned, the combination of “bell-bell-bell” goes up to the right, that is, aligns with the invalid line LM4.

  In the left reel 2L, one of black 7, white 7, and watermelon is arranged within 5 frames, in the middle reel 2C, the bell is arranged within 5 frames, and in the right reel 2R, orange, BAR One of these is arranged within 5 frames. For this reason, it can be said that, in principle, when a right-up bell is won in an internal lottery to be described later, it can be said that, as a rule, it can be awarded regardless of the operation timing of the stop switches 8L to 8R.

  Next, with reference to FIG. 56, the re-game combination among the winning combinations will be described. Among the winning combinations, the replaying role includes normal replay, lower stage replay, falling replay, promotion replays 1 and 2, special replay, 7 complete replay, and 7 uneven replay.

  The normal replay is awarded when a combination of “Replay-Replay-Replay”, “Replay-Replay-Plum”, “Plum-Replay-Replay”, and “Plum-Replay-Plum” is arranged on the winning line LN. Replays and plums are arranged within 5 frames in each of the left reel 2L, middle reel 2C, and right reel 2R. Therefore, as a general rule, it can be said that the normal replay is a role that can be won regardless of the operation timing of the stop switches 8L to 8R if the winning is made.

  The lower replay includes “Bell-Orange-Orange”, “Belle-Orange-Cherry”, “Belle-Orange-Watermelon”, “Belle-Orange-Black 7”, “Belle-Orange-Net 7”, "Bell-Orange-White 7", "Bell-BAR-Orange", "Bell-BAR-Cherry", "Bell-BAR-Watermelon", "Bell-BAR-Black 7", "Bell-BAR-Net 7" , “BELL-BAR-WHITE 7” combination is awarded.

  Here, referring to FIG. 3, the bell of the left reel 2L is arranged at a position one above the replay or plum, and the orange and BAR of the middle reel 2C are arranged at a position one above the replay. "Bell-orange-orange", "bell-orange-cherry", "bell-orange-watermelon", "bell-orange-black 7", "bell-orange-net 7", "bell-orange-" "White 7", "Bell-BAR-Orange", "Bell-BAR-Cherry", "Bell-BAR-Watermelon", "Bell-BAR-Black 7", "Bell-BAR-Net 7", "Bell-BAR" When any combination of “White 7” is prepared, “Replay-Replay-Watermelon / Replay / Plum / Cherry / Net 7 / White 7”, “Replay-Plum-Replay-Replay-Watermelon / Replay / Plum / Chi Lee / Net 7 / White 7 ”,“ Plum-Replay-Replay-Replay-Watermelon / Replay / Plum / Cherry / Net 7 / White 7 ”,“ Plum-Plum-Replay-Replay-Watermelon / Replay / Plum / Cherry / The combination of “net 7 / white 7” is aligned at the lower stage, that is, the invalid line LM2.

  Further, in the left reel 2L, the bell is arranged within 5 frames, in the middle reel, orange and BAR are arranged within 5 frames, and in the right reel 2R, orange, cherry, watermelon, black 7, net 7 , One of white 7 is arranged within 5 frames. For this reason, it can be said that, in principle, when the lower stage replay is won in an internal lottery to be described later, it can be said that the prize can be awarded regardless of the operation timing of the stop switches 8L to 8R.

  The tumble replay is awarded when the combination of “bell-replay-bell” is arranged on the winning line LN.

  Referring now to FIG. 3, the bell of the left reel 2L is located one position above the replay or plum, and the bell of the right reel 2R is located one position below the replay. So, when the combination of “bell-replay-bell” is complete, the combination of “replay-replay-replay”, “replay-replay-plum”, “plum-replay-replay”, “plum-replay-plum” goes up to the right. That is, they are aligned with the invalid line LM4.

  In the left reel 2L, the bell is arranged within 5 frames, in the middle reel, the replay is arranged within 5 frames, and in the right reel 2R, the bell is arranged within 5 frames. For this reason, it can be said that, in principle, when a fall replay is won in an internal lottery to be described later, it can be said that a prize can be awarded regardless of the operation timing of the stop switches 8L to 8R.

  As shown in FIG. 58, after winning the fall replay at RT0, it is controlled to RT1.

  The promotion replay 1 is awarded when a combination of “replay-replay-bell” and “plum-replay-bell” is arranged on the winning line LN. In the left reel 2L, one of the replays and plums is arranged within 5 frames, in the middle reel 2C, the replay is arranged within 5 frames, and in the right reel 2R, the bell is arranged within 5 frames. ing. Therefore, it can be said that, as a general rule, the promotion replay 1 can be awarded regardless of the operation timing of the stop switches 8L to 8R if it is won.

  Promotion Replay 2 is when any combination of “Bell-Orange-Replay”, “Bell-Orange-Plum”, “Bell-BAR-Replay”, and “Bell-BAR-Plum” is arranged on the winning line LN. Winning a prize.

  Here, referring to FIG. 3, the bell of the left reel 2L is arranged at a position one above the replay or plum, and the orange and BAR of the middle reel 2C are arranged at a position one above the replay. Since the replay and plum of the right reel 2R are arranged one position above the bell, “bell-orange-replay”, “bell-orange-plum”, “bell-BAR-replay”, “ When the combination of “bell-BAR-plum” is arranged, the combination of “replay-replay-bell” and “plum-replay-bell” is arranged in the lower stage, that is, the invalid line LM2.

  In the left reel 2L, the bell is arranged within 5 frames, in the middle reel, orange and BAR are arranged within 5 frames, and in the right reel 2R, replay and plum are arranged within 5 frames. ing. For this reason, it can be said that, in principle, when the promotion replay 2 is won in an internal lottery to be described later, it can be said that, as a rule, it can be awarded regardless of the operation timing of the stop switches 8L to 8R.

  As shown in FIG. 58, after winning a promotion replay (promotion replay 1 or promotion replay 2) in RT1, it is controlled to RT0. As will be described later, the promotion replay is set so as not to be won by itself in the internal lottery in RT2 and RT3. Further, when the special combination and the promotion replay are won at the same time in the internal lottery in RT2 and RT3, RT4 or RT5 is controlled at that time. For this reason, RT2 and RT3 do not win a promotion replay. As a result, it is configured not to be controlled from RT2 and RT3 to RT0, and it is configured to receive a promotion replay prize only when RT1 and to be controlled to RT0 only from RT1.

  The special replay is awarded when a combination of “bell-replay-replay” and “bell-replay-plum” is arranged on the winning line LN. In the left reel 2L, the bell is arranged within 5 frames, in the middle reel 2C, the replay is arranged within 5 frames, and in the right reel 2R, one of the replays and plums is arranged within 5 frames. ing. Therefore, as a general rule, special replays can be said to be a role that can be awarded regardless of the operation timing of the stop switches 8L to 8R if they are elected.

  As shown in FIG. 58, after winning the special replay at RT0, it is controlled to RT2. As will be described later, the special replay is set not to win by itself in the internal lottery at RT1 and RT3. Further, when the special combination and special replay are won at the same time in the internal lottery at RT1 and RT3, RT4 or RT5 is controlled at that time. For this reason, the special replay is not won at RT1 and RT3. As a result, it is configured not to be controlled from RT1 and RT3 to RT2, and special replay is awarded only when RT0, and is configured to be controlled by RT2 only from RT0.

  The 7-match replay is awarded when a combination of “black 7-black 7-black 7” is aligned on the winning line LN. In addition, the 7 irregular replays are “black 7-black 7-replay”, “black 7-black 7-plum”, “black 7-replay-black 7”, “replay-black 7-black 7” on the winning line LN. , “Plum-Black 7-Black 7”, “Black 7-Replay-Replay”, “Black 7-Replay-Plum”, “Replay-Black 7-Replay”, “Replay-Black 7-Plum”, “Plum-” A prize is awarded when the combinations of “Black 7-Replay”, “Plum-Black 7-Plum”, “Replay-Replay-Black 7”, and “Plum-Replay-Black 7” are complete.

  One of the replays and plums is arranged within 5 frames in all reels, but “black 7” is arranged over 5 frames in all reels. For this reason, even if the 7 lot replay or 7 misalignment replay is won in the internal lottery described later, in principle, if the stop switch corresponding to at least one reel is not operated at an appropriate timing, the 7 replay or 7 misalignment is performed in principle. Replays will not win, but 7 replays will be won at the same time as 7 irregular replays and normal replays as will be described later, and 7 irregular replays will be won at the same time as normal replays. When replay is won at the same time, regardless of the operation timing of the stop switches 8L to 8R, one of 7 replays, 7 uneven replays, and normal replays always wins, and 7 non-uniform replays and normal replays are won simultaneously. If it is, stop switch 8L ~ 8R One of the 7 irregular replay and normal replay, regardless of the operation timing is that you always win.

  Next, the transition outcome will be described with reference to FIG. As shown in FIG. 57, the transition items are “Replay-Orange-Bell”, “Replay-BAR-Bell”, “Plum-Orange-Bell”, “Plum-BAR-Bell”, “Replay-Bell-Orange”. ”,“ Replay-Bell-BAR ”,“ Plum-Bell-Orange ”,“ Plum-Bell-BAR ”,“ Black 7-Orange-Orange ”,“ Black 7-Orange-BAR ”,“ Black 7-BAR- ” "Orange", "Black 7-BAR-BAR", "White 7-Orange-Orange", "White 7-Orange-BAR", "White 7-BAR-Orange", "White 7-BAR-BAR", "Watermelon -Orange-orange "," Watermelon-orange-BAR "," Watermelon-BAR-orange "," Watermelon-BAR-BAR ". In this embodiment, left bells 1 to 4, middle bells 1 to 4 and right bells 1 to 4 which will be described later are elected, and the upper bells which are elected as the first stop other than the reels which become the winning conditions for the middle bells are elected. When the game is missed, the above-mentioned transition outcome is aligned with the winning line LN.

  As shown in FIG. 58, RT1 is controlled after RT0, RT2, and RT3 are aligned with the winning line LN. Note that RT1 is maintained when the transition outcomes are aligned with the winning line LN at RT1.

  Next, with reference to FIG. 60 to FIG. 63, combinations of lottery object combinations that are read as lottery object combinations for each gaming state will be described. In the present embodiment, the role to be subject to the internal lottery and its winning are determined depending on whether the gaming state is RT0-3, RT4, RT5, BB (RB), or RB. Probability is different. Furthermore, if the gaming state is RT0-3, at least one of the re-game player who is the target of the internal lottery and its winning probability differs depending on the type of RT0-3. As will be described later as a lottery target combination, a plurality of winning combinations can be read out simultaneously and can be won in duplicate. In FIG. 60 to FIG. 63, “+” is written between winning winning combinations to indicate that the winning combination is simultaneously read out in the internal lottery.

  In FIGS. 60 to 62, the lottery object combination is shown in the vertical column, and the gaming state is shown in the horizontal column. In the column where the gaming state intersects with the lottery target, a circle indicates that the lottery target is read out in the gaming state, and a cross indicates the lottery target when in the gaming state. This indicates that the combination is not read out.

  Further, the numerical value shown below the circle indicates the number of determination values of a predetermined set value (for example, set value 1). An internal lottery is performed using the number of determination values. The denominator of the number of determination values is set to “65536” corresponding to a random number for internal lottery (an integer from 0 to 65535). For this reason, for example, the winning probability of the lottery subject for which “300” is set as the number of determination values is 300/65536.

  FIG. 60 shows combinations of special combinations that are read out as lottery targets for each gaming state, FIG. 61 shows combinations of small roles that are read out as lottery targets for each gaming state, and FIG. 62 shows gaming states. A combination of re-playing combinations that are read out as lottery targets is shown. FIG. 63 shows combinations of the combinations constituting the simultaneous winning combinations shown in FIGS.

  When it is RT0, BB1, BB1 + weak cherry, BB1 + strong cherry, BB1 + normal replay, BB1 + fall replay, BB1 + promotion replay, BB1 + special replay, BB2, BB2 + weak cherry, BB2 + strong cherry, BB2 + normal replay, BB2 + fall replay, BB2 + Promotion replay, BB2 + special replay, RB1, RB1 + weak cherry, RB1 + strong cherry, RB2, RB2 + weak cherry, RB2 + strong cherry, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, medium Bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right bell 3, right bell 4, weak cherry, strong cherry, replay GR11, replay GR12, replay GR13, replay GR14, replay GR15 It becomes the target role of.

  When RT1, BB1, BB1 + weak cherry, BB1 + strong cherry, BB1 + normal replay, BB1 + fall replay, BB1 + promotion replay, BB1 + special replay, BB2, BB2 + weak cherry, BB2 + strong cherry, BB2 + normal replay, BB2 + fall replay, BB2 + Promotion replay, BB2 + special replay, RB1, RB1 + weak cherry, RB1 + strong cherry, RB2, RB2 + weak cherry, RB2 + strong cherry, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, medium Bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right bell 3, right bell 4, weak cherry, strong cherry, normal replay, replay GR1, replay GR2, replay GR3, replay GR4, replay GR5 , Replay GR6 is the target of internal lottery It made.

  When RT2, BB1, BB1 + weak cherry, BB1 + strong cherry, BB1 + normal replay, BB1 + fall replay, BB1 + promotion replay, BB1 + special replay, BB2, BB2 + weak cherry, BB2 + strong cherry, BB2 + normal replay, BB2 + fall replay, BB2 + Promotion replay, BB2 + special replay, RB1, RB1 + weak cherry, RB1 + strong cherry, left bell 2, left bell 3, left bell 4, middle bell 1, middle bell 2, middle bell 3, middle bell 4, right bell 1, right Bell 2, right bell 3, right bell 4, weak cherry, strong cherry, normal replay, replay GR21, and replay GR22 are subject to internal lottery.

  When it is RT3, BB1, BB1 + weak cherry, BB1 + strong cherry, BB1 + normal replay, BB1 + fall replay, BB1 + promotion replay, BB1 + special replay, BB2, BB2 + weak cherry, BB2 + strong cherry, BB2 + normal replay, BB2 + fall replay, BB2 + Promotion replay, BB2 + special replay, RB1, RB1 + weak cherry, RB1 + strong cherry, RB2, RB2 + weak cherry, RB2 + strong cherry, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, medium Bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right bell 3, right bell 4, weak cherries, strong cherries, and normal replays are subject to internal lottery.

  When it is RT4, RT5, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right Bell 3, right bell 4, weak cherry, strong cherry, normal replay, lower replay, fall replay, promotion replay, and special replay are targeted for internal lottery.

  When it is BB (RB) or RB, bells, weak cherries, strong cherries, and right-up bells are subject to internal lottery.

  As shown in FIG. 63, the weak cherry is the lower cherry alone, and the strong cherry is the lower cherry plus one piece. At the time of weak cherry winning, the strong cherry winning is controlled so that the combination of “BAR-BAR-ANY” can be derived when the left and middle reels are stopped at the timing when both are within the “BAR” pull-in range. However, when winning a weak cherry, if the left, middle, and right reels are stopped at a timing that is within the “BAR” pull-in range, the “BAR-BAR-BAR” combination is While it is controlled so that it does not align, when a strong cherry is won, if the operation of stopping the left, middle, and right reels is performed at the timing of the “BAR” pull-in range, “BAR-BAR-BAR” Are controlled so that the combinations of

  For this reason, when a stop operation is performed aiming at “BAR” on each of the left, middle, and right reels, when the cherry stops on the lower stage of the left reel 2L, the combination of “BAR-BAR-BAR” is displayed on the middle stage. Whether it is a strong cherry or a weak cherry can be recognized depending on whether they are aligned.

  In the following, the stop mode in which “cherry” stops at the lower stage of the left reel and the combination of “BAR-BAR-BAR” is arranged in the interruption is called strong cherry eyes, and “cherry” stops at the lower stage of the left reel. In addition, a stop mode in which the combination of “BAR-BAR-BAR” is not complete is called weak cherry eyes.

  Even when a strong cherry is won, only the left reel is stopped at the timing when “BAR” is in the pull-in range, and the right reel is not stopped at timing when “BAR” is in the pull-in range. The same outcome as when the weak cherry is won, that is, the weak cherry outcome is derived.

  In addition, in this embodiment, both the weak cherry and the strong cherry can be won simultaneously with the special role, and the probability of the weak cherry winning alone and the probability of the latter occupying the combined value of the probability that the weak cherry wins simultaneously with the special role is determined. However, since the probability of the strong cherry winning alone and the probability of the latter occupying the combined value of the probability of strong cherry winning simultaneously with the special role is set higher, the strong cherry is stronger than when the weak cherry eyes stop When your eyes stop, you can expect to win a special role.

  The bell is a middle bell + a downward-sloping bell. Left bell 1 is right falling bell 5 + upper bell 5 + upper bell 8, left bell 2 is right falling bell + upper bell 6 + upper bell 7, and left bell 3 is right falling bell + upper bell 2 + upper bell 3, left bell 4 is right falling bell + upper bell 2 + upper bell 4. The left bells 1 to 4 are also simply called left bells. The middle bell 1 is the middle bell + the upper bell 2 + the upper bell 5, the middle bell 2 is the middle bell + the upper bell 1 + the upper bell 6, and the middle bell 3 is the middle bell + the upper bell 4 + the upper bell. 7 and the middle bell 4 is the middle bell + the upper bell 3 + the upper bell 8. The middle bells 1 to 4 are also simply called middle bells. The right bell 1 is the middle bell + the upper bell 3 + the upper bell 5, the right bell 2 is the middle bell + the upper bell 1 + the upper bell 7, and the right bell 3 is the middle bell + the upper bell 4 + the upper bell. 6 and the right bell 4 is the middle bell + the upper bell 2 + the upper bell 8. The right bells 1 to 4 are also simply called right bells. The left bells 1 to 4, the middle bells 1 to 4, and the right bells 1 to 4 are also simply referred to as push order bells.

  The promotion replay is promotion replay 1 + promotion replay 2.

  Replay GR1 is normal replay + promotion replay 1, replay GR2 is normal replay + promotion replay 1 + promotion replay 2, replay GR3 is normal replay + promotion replay 1 + lower replay, and replay GR4. Is normal replay + promotion replay 1 + promotion replay 2 + lower replay, replay GR5 is normal replay + promotion replay 2, and replay GR6 is normal replay + promotion replay 2 + lower replay.

  Replay GR11 is tumble replay + special replay, replay GR12 is tumble replay + special replay + normal replay, replay GR13 is tumble replay + special replay + lower replay, and replay GR14 is Tumble replay + special replay + normal replay + lower replay. Replay GR15 is tumble replay + special replay + promotion replay 1.

  The replay GR21 is 7-match replay + 7-mismatch replay + normal replay, and the replay GR22 is 7-mismatch replay + normal replay.

  In RT0-3, the number of determination values of weak cherry, strong cherry, normal replay, fall replay, and promoted replay that can be won simultaneously with any of BB1, BB2, RB1, and RB2 is RT4 and RT5, respectively. Since it is added to weak cherries, strong cherries, normal replays, tumble replays, and promoted replays that are read separately from bonuses, the probability of winning each of weak cherries, strong cherries, normal replays, tumble replays, and promoted replays is constant. Is assured.

  In this way, the target role of the internal lottery varies depending on whether the gaming state is RT0-3, RT4, 5, BB (RB), or RB, and BB (RB) or RB Then, the internal lottery is performed using the lottery table in which the winning combination probability of the small role is set higher than RT0-5.

  If the gaming state is RT4 or 5, the internal lottery role does not change depending on whether it is RT4 or RT5, but the target game depends on whether it is RT4 or RT5. An internal lottery is performed using lottery tables with different winning probabilities for gamers.

  Also, when the gaming state is RT0-3, depending on whether it is RT0-3, the re-game player to be subject to the internal lottery differs, and depending on whether it is RT0-3, the target An internal lottery is performed using a lottery table with different re-game players and their winning probabilities.

  In this embodiment, when a plurality of types of re-game players are won at the same time, as shown in FIG. 64, a re-game player determined according to the types of re-game players won at the same time and the stop operation order is won. Control is performed so that the line is stopped within a maximum of 4 frames on the line. FIG. 64 is a diagram for explaining reel control when a plurality of replays are simultaneously won.

  When the replay GR1 (normal replay + promotion replay 1) is won and the stop operation is performed in the order of middle left and right, the combination of the promotion replay 1 among the selected replay players is aligned with the winning line LN and stopped. When the control is performed and the stop operation is performed in an order other than the left middle right, the control is performed so that the combination of the normal replays is aligned with the winning line LN and stopped.

  When replay GR2 (normal replay + promotion replay 1 + promotion replay 2) is won and the stop operation is performed in the order of left and right, the combination of promotion replay 1 among the selected replay players is aligned with the winning line LN Control to stop is performed, and when stop operation is performed in an order other than left and right middle, control is performed to align the combination of normal replays to the winning line LN and stop.

  If Replay GR3 (Normal Replay + Promotion Replay 1 + Lower Replay) is won and the stop operation is performed in the middle left or right order, the combination of Promotion Replay 1 among the selected replay players will be aligned to the winning line LN and stopped. When the stop operation is performed in an order other than middle left and right, control is performed so that the combination of normal replays is aligned with the winning line LN and stopped.

  If Replay GR4 (Normal Replay + Promotion Replay 1 + Promotion Replay 2 + Lower Replay) is won and a stop operation is performed in the middle right / left order, the combination of Promotion Replay 1 among the selected replaying players is placed on the winning line LN When the stop operation is performed in an order other than middle right and left, the control is performed so that the combination of the normal replays is aligned with the winning line LN and stopped.

  When replay GR5 (normal replay + promotion replay 2) is won and stop operation is performed in the order of the middle left and right, the combination of the promotion replay 2 among the selected replay players is stopped in line with the winning line LN When the stop operation is performed in an order other than the middle right and left, control is performed so that the combination of normal replays is aligned with the winning line LN and stopped.

  When Replay GR6 (Normal Replay + Promotion Replay 2 + Lower Replay) is won and the stop operation is performed in the order of middle right and left, the combination of Promotion Replay 2 of the selected replaying players is aligned with the winning line LN Control to stop is performed, and when stop operations are performed in an order other than right center left, control is performed to align the normal replay combination with the winning line LN and stop.

  As shown in FIG. 3, the symbols constituting the promotion replay 1, the promotion replay 2, and the normal replay are arranged at intervals of 5 frames or less on all of the left reel 2L, the middle reel 2C, and the right reel 2R. The reel control is performed so that the promotion replay 1, the promotion replay 2 or the normal replay always wins regardless of the stop operation timing of the stop switches 8L to 8R according to the operation order.

  In this way, different operation modes are set as the operation modes for allowing the replays GR1 to 6 to win the promoted replays 1 and 2.

  For this reason, if one of the replays GR1 to 6 is won in RT1 where the replays GR1 to 6 are subject to internal lottery, the promotion replay will be won with a probability of 1/6, and the transition to RT0 Become.

  When the replay GR11 (falling replay + special replay) is won and the stop operation is performed in the order of left, middle and right, the control of stopping the combination of the special replays in the winning replay combination in the winning line LN. If the stop operation is performed in an order other than the left middle right, control is performed to stop the combination of the fall replays aligned with the winning line LN.

  When replay GR12 (falling replay + special replay + normal replay) is won and the stop operation is performed in the order of left and right, the combination of special replays among the selected replay players is stopped in line with the winning line LN. When the control is performed and the stop operation is performed in an order other than right and left, the control is performed to stop the combination of the fall replays on the winning line LN.

  When replay GR13 (falling replay + special replay + lower replay) is won and a stop operation is performed in the middle / left / right order, the combination of special replays among the selected replay players is aligned with the winning line LN and stopped. When the control is performed and the stop operation is performed in an order other than the middle left and right, the control is performed so that the combination of falling replays is aligned with the winning line LN and stopped.

  If Replay GR14 (Tumble Replay + Special Replay + Normal Replay + Lower Replay) is won and the stop operation is made in the middle right / left order, the combination of special replays among the selected replay players is aligned to the winning line LN If the stop operation is performed in an order other than middle right and left, the combination of falling replays is aligned with the winning line LN and stopped.

  When replay GR15 (falling replay + special replay + promotion replay 1) is won and pressed right, that is, when the stop operation is performed in an operation mode in which the right reel 2R is first stopped, the special replay among the selected replay players When the stop operation is performed in the operation mode in which the combination of the above is aligned with the winning line LN and left-pressed, that is, the operation mode in which the left reel 2L is first stopped or in the middle mode, that is, the operation mode in which the middle reel 2C is first stopped In this case, a control is performed to stop the combination of falling replays in line with the winning line LN.

  As shown in FIG. 3, since the symbols constituting the special replay and the fall replay are arranged at intervals of 5 frames or less in all of the left reel 2L, the middle reel 2C, and the right reel 2R, Regardless of the stop operation timing of the stop switches 8L to 8R, the reel control is performed so that the special replay or the fall replay is always won.

  In this way, different operation modes are set as the operation modes in order to win special replays and avoid falling replays with the replays GR11 to 15.

  For this reason, if one of the replays GR11 to 15 is elected at RT0 where the replays GR11 to 15 are the targets of the internal lottery, the special replay wins with a probability of 1/5 and shifts to RT2. Then, the fall replay wins with a probability of 4/5 and shifts to RT1.

  Although not shown in particular, when replay GR21 (7-match replay + 7-mismatch replay + normal replay) is won, if the stop operation is performed within the pull-in range of “black 7”, “black 7” Is stopped at the winning line LN, and when the stop operation is performed outside the drawing range of “Black 7”, control is performed to stop “Replay” or “Plum” at the winning line LN.

  In this way, when the replay GR 21 is won, control is performed to stop the 7 replay combinations in priority to the winning line LN, and when the 7 replay combinations cannot be aligned, the 7 replay combinations are prioritized. The control for stopping the normal replay is performed when it is not possible to prepare a combination of 7 irregular replays.

  If Replay GR22 (7 Uneven Replay + Normal Replay) is selected, “Black 7” will be awarded when the stop operation is performed in the “Black 7” pull-in range until the second stop operation. When the line LN is stopped and the stop operation is performed outside the drawing range of “Black 7”, the control is performed to stop “Replay” or “Plum” on the winning line LN. If “Black 7” is stopped on the winning line LN for any reel that has been stopped by the stopping operation, “Replay” or “Plum” is stopped on the winning line LN regardless of the timing of the stopping operation. If “Replay” or “Plum” has been stopped on the winning line LN before the second stop operation, “Black 7” will be placed in the winning line LN when the stop operation is performed in the “Black 7” drawing range. To stop, "Black 7" If it is the stop operation outside pull-in range performs control to stop the winning line LN to "replay" or "Plum".

  As described above, when the replay GR 22 is won, the control for stopping the combination of the 7 irregular replays in preference to the winning line LN is performed, and the control for stopping the combination of the normal replay is performed when the combination of the 7 irregular replays cannot be aligned. I do. For this reason, when the replay GR 22 is won, seven replays will not be won. However, by performing the operation aiming at 7, the 7 will be a temper until the second stop operation. "Replay" or "Plum" will stop.

  Next, when a plurality of types of small combinations are won simultaneously, as shown in FIG. 65, a maximum of 4 small combinations determined according to the types of small combinations that are simultaneously selected and the order of stop operations are displayed on the winning line. Control is performed so as to stop evenly within the frame drawing range. FIG. 65 is a diagram for explaining reel control when a plurality of small combinations are simultaneously won.

  If left bell 1 (lower right bell + upper bell 6 + upper bell 7) wins and the stop operation is performed by pressing to the left, the combination of right down bells of the selected small roles is aligned with the winning line LN and stopped. When the stop operation is performed by middle pressing or right pressing, control is performed so that any combination of the upper bell 6, the upper bell 7, or the transition outcome is aligned with the winning line LN.

  If left bell 2 (lower right bell + upper bell 5 + upper bell 8) is elected and stopped by left-pressing, the combination of right-down bells in the selected small role is aligned with the winning line LN and stopped. When a stop operation is performed by middle pressing or right pressing, control is performed so that any combination of the upper bell 5, the upper bell 6 or the transitional outcome is aligned with the winning line LN.

  If left bell 3 (lower right bell + upper bell 2 + upper bell 3) is elected and the stop operation is performed by pressing the left button, the right falling bell combination of the selected small roles is aligned with the winning line LN and stopped. When the stop operation is performed by middle pressing or right pressing, control is performed such that any combination of the upper bell 2, the upper bell 3, or the transition outcome is aligned with the winning line LN.

  If left bell 4 (lower right bell + upper bell 2 + upper bell 4) is elected and the stop operation is performed by pressing the left button, the combination of the right falling bells of the selected small roles is aligned with the winning line LN and stopped. When the stop operation is performed by middle pressing or right pressing, control is performed so that any combination of the upper bell 2, the upper bell 4, or the transitional outcome is aligned with the winning line LN.

  As shown in FIG. 3, the configuration symbol of the right-down bell is arranged at intervals of 5 frames or less on all reels, and when the left bells 1 to 4 are elected, a stop operation is performed by pushing left. In this case, regardless of the timing of the stop operation, control is always performed so that the right lowering bell is aligned with the winning line LN, while the symbols constituting the upper bells 1 to 8 are at intervals of 5 frames or more on all reels. Even if the left bells 1 to 4 are elected because there are places that are arranged, if the stop operation is performed by pressing the middle or right, it becomes the drawing range of the constituent symbols of the elected upper bells 1 to 8 If the stop operation is not performed at an appropriate timing, the winning upper bell cannot be aligned with the winning line LN, and in this case, the control is performed so that the transition outcome is aligned with the winning line LN.

  When middle bell 1 (middle bell + upper bell 2 + upper bell 5) is elected and the stop operation is performed by pressing the middle bell, the control of stopping the combination of the middle bells of the elected small roles with the winning line LN is stopped. If a stop operation is performed by left-pressing or right-pressing, control is performed so that any combination of the upper bell 2, the upper bell 5, or the transition outcome is aligned with the winning line LN.

  When middle bell 2 (middle bell + upper bell 1 + upper bell 6) is elected and the stop operation is performed by pressing the middle bell, the control of stopping the combination of the middle bells of the elected small roles with the winning line LN is stopped. If the stop operation is performed by pressing left or right, control is performed so that any combination of the upper bell 1, the upper bell 6, or the transition outcome is aligned with the winning line LN.

  When middle bell 3 (middle bell + upper bell 4 + upper bell 7) is elected and the stop operation is performed by pressing the middle bell, the control of stopping the combination of the middle bells of the elected small roles on the winning line LN is stopped. If a stop operation is performed by left-pressing or right-pressing, control is performed so that any combination of the upper bell 4, the upper bell 7, or the transition outcome is aligned with the winning line LN.

  When middle bell 4 (middle bell + upper bell 3 + upper bell 8) is elected and the stop operation is performed by pressing the middle bell, the control of stopping the combination of the middle bells of the elected small roles on the winning line LN is stopped. If a stop operation is performed by left-pressing or right-pressing, control is performed so that any combination of the upper bell 3, the upper bell 8, or the transition outcome is aligned with the winning line LN and stopped.

  As shown in FIG. 3, the configuration symbols of the middle bell are arranged at intervals of 5 frames or less on all reels, and when the middle bell 1 to 4 is elected, when the stop operation is performed by middle push Regardless of the timing of the stop operation, control is always performed so that the middle bell is aligned with the winning line LN, while the symbols constituting the upper bells 1 to 8 are arranged at intervals of 5 frames or more on all reels. Even if the middle bells 1 to 4 are elected, if the stop operation is performed by pressing left or right, an appropriate range that will be drawn in the constituent symbols of the elected upper bells 1 to 8 will be used. If the stop operation is not performed at the timing, the selected upper bell cannot be aligned with the winning line LN, and in this case, control is performed so that the shift outcome is aligned with the winning line LN.

  When right bell 1 (middle bell + upper bell 3 + upper bell 5) is elected and the stop operation is performed by pressing right, the combination of middle bells of the selected small roles is stopped in alignment with the winning line LN. When a stop operation is performed by left-pressing or middle-pressing, control is performed so that any combination of the upper bell 3, the upper bell 5, or the transition outcome is aligned with the winning line LN and stopped.

  When right bell 2 (middle bell + upper bell 1 + upper bell 7) is elected and the stop operation is performed by pressing right, the combination of middle bells among the selected small roles is stopped in line with the winning line LN. When a stop operation is performed by left-pressing or middle-pressing, control is performed so that any combination of the upper bell 1, the upper bell 7, or the transition outcome is aligned with the winning line LN.

  When right bell 3 (middle bell + upper bell 4 + upper bell 6) is elected and a stop operation is performed by pressing right, the combination of middle bells among the selected small roles is stopped in alignment with winning line LN. When a stop operation is performed by left-pressing or middle-pressing, control is performed so that any combination of the upper bell 4, the upper bell 6, or the transitional outcome is aligned with the winning line LN.

  When right bell 4 (middle bell + upper bell 2 + upper bell 8) is elected and the stop operation is performed by pressing right, the combination of middle bells of the selected small roles is stopped in alignment with winning line LN. When a stop operation is performed by left-pressing or middle-pressing, control is performed so that any combination of the upper bell 2, the upper bell 8, or the transition outcome is aligned with the winning line LN.

  As shown in FIG. 3, the configuration symbols of the middle bell are arranged at intervals of 5 frames or less on all reels, and when the right bell 1 to 4 is elected, when the stop operation is performed by pushing right However, regardless of the timing of the stop operation, control is always performed so that the middle bell is aligned with the winning line LN, while the symbols constituting the upper bells 1 to 8 are arranged at intervals of 5 frames or more on all reels. Therefore, even if the right bells 1 to 4 are elected, if the stop operation is performed by left-pressing or middle-pressing, an appropriate drawing range of the constituent symbols of the elected upper bells 1 to 8 is appropriate. If the stop operation is not performed at the timing, the selected upper bell cannot be aligned with the winning line LN, and in this case, control is performed so that the shift outcome is aligned with the winning line LN.

  Thus, in this embodiment, when any of the left bell, middle bell, right bell, that is, the push order bell is won, by performing a stop operation in a specific operation mode according to the type of winning combination, While the right-down bell or middle bell always wins, if the stop operation is performed in an operation mode other than the specific operation mode according to the type of winning combination, the upper bell is aligned at 1/4, but at 3/4 In some cases, the upper bells are not aligned and the transition outcomes are aligned.

  For this reason, at the time of winning the push order bell, the expected value of the number of medals to be paid out can be changed depending on whether or not it is operated in a specific operation mode according to the type of winning combination. In other words, even if one of the push order bells is won, it is impossible to intentionally select a specific operation mode unless the type is known. Although a medal can be surely obtained by winning a prize, the upper bell can be won only by 1/4 at a ratio of 2/3, and a medal cannot be surely obtained.

  Although not particularly shown, when a bell (middle bell + lower right bell) is won, a combination of “bell-bell-bell” is arranged on the winning line LN regardless of the stop order of the reels and the operation timing. To be controlled.

  In the present embodiment, as shown in FIG. 58 and FIG. 59, the control is performed to any one of RT0 to RT5, RB, and BB (RB).

  RT0 ends when RT1 and RT2 are exhausted when the number of specified games has been reached when RT1 receives a promotion replay (when one of replays GR1 to GR6 wins and a stop operation is performed in the order that promotion replay wins) When to migrate. Regardless of the number of games since the transition to RT0, RT0 transitions to RT1 by winning a fall replay or stopping the transition, or transitions to RT2 by winning a special replay, or a special role is won And it complete | finishes by transfering to RT4 or RT5.

  The winning probability of the special role at RT0 is normal (about 1/239), the winning probability of the re-playing role is high (about 1 / 1.4), and the winning probability of the small role is normal (about 1 / 3.5, however, The winning probability is about 1 / 6.1), and the payout rate of medals per game is 1 or more. In RT0, except for the case where a winning combination is made at the same time as the special combination, only the replay GRs 11 to 15 among the re-playing combinations are targeted for internal lottery.

  RT1 shifts when the transition is stopped at RT0, RT2, RT3, or when the fall replay wins at RT0. Then, RT1 ends when the promotion replay wins and shifts to RT0, or when the special role is won and shifts to RT4 or RT5.

  The winning probability of the special role in RT1 is normal (about 1/239) as in RT0, the winning probability of the re-playing role is lower (normally about 1 / 7.3) than in RT0, and the winning probability of the small role is normal as in RT0 (About 1 / 3.5, but the winning probability is about 1 / 6.1), and the payout rate of medals per game is less than 1. In RT1, only normal replays and replays GR1 to GR6 among replaying players are targeted for internal lottery.

  RT2 shifts when a special replay wins at RT0. Then, RT2 ends when the transition outcome stops and shifts to RT1, or the special combination wins and shifts to RT4 or RT5.

  The winning probabilities for special roles in RT2 are normal (about 1/239) like RT0, the winning probabilities for re-playing players are almost the same as RT0 (about 1 / 1.4), and the winning probabilities for small roles are RT0. Similarly, it is normal (about 1 / 3.5, but the winning probability is about 1 / 6.1), and the payout rate of medals per game is 1 or more. In RT2, only the normal replay among the re-games is subject to internal lottery, except when winning at the same time as the special combination.

  RT3 shifts to the end of BB (RB) and RB. Then, regardless of the number of games since the transition to RT3, RT3 ends when the transition outcome stops and transitions to RT1, or the special combination wins and transitions to RT4 or RT5.

  The winning probability of the special role in RT3 is normal (about 1/239), the winning probability of the re-playing role is usually lower than RT0 (about 1 / 7.3), and the winning probability of the small role is normal (about 1) /3.5, where the winning probability is about 1 / 6.1), and the payout rate of medals per game is less than 1. In RT3, except for the case where the winning combination is won at the same time as the special combination, only the normal replay among the re-playing combinations is subject to internal lottery.

  RT4 shifts when BB1, BB3, RB2 among the special roles are won in RT0-3. RT4 ends when the special combination that triggered the transition to RT4 wins and shifts to BB (RB) or RB, regardless of the number of games since the transition to RT4.

  In RT4, special roles are not subject to internal lottery, and the winning probability of re-playing roles is lower than RT0 and RT2, but higher than RT1 and RT3 (about 1 / 2.5), winning of small roles The probability is normal (about 1 / 3.5, but the winning probability is about 1 / 6.1), and the payout rate of medals per game is less than 1. Further, in RT4, only the normal replay and the lower replay among the re-game players are targeted for internal lottery.

  RT5 shifts when BB2, BB4, RB1 among special roles are won in RT0-3. RT5 ends when the special combination that triggered the transition to RT5 wins and shifts to BB (RB) or RB regardless of the number of games after transition to RT5.

  In RT5, the special role is not subject to internal lottery, and the winning probability of the re-playing role is lower than RT0, RT2, but higher than RT1, RT3, RT4, high probability (about 1 / 2.0), small role The winning probability is normally (about 1 / 3.5, but the winning probability is about 1 / 6.1), and the medal payout rate per game is less than 1. In RT5, only the normal replay and the lower replay among the re-game players are targeted for internal lottery.

  RB shifts when RB1 or RB2 wins at RT5, RT5. And RB is complete | finished by digesting 6 games or winning 6 times.

  In RB, the special role and replaying role are not subject to internal lottery, and the winning probability of the small role is higher than RT0-5 and high probability (about 1 / 1.01), and the medal per game is The payout rate is 1 or more.

  BB (RB) shifts when BB wins at RT 4 and 5. Then, BB (RB) ends when the total number of medals paid out to BB (RB) exceeds the prescribed number, regardless of the number of games since the transition to BB (RB).

  In BB (RB), special roles and re-playing roles are not subject to internal lottery, and the winning probability of small roles is higher than RT0-5 and has a high probability (about 1 / 1.00) per game The medal payout rate is 1 or more.

  Among RT4, 5, RB, and BB (RB), RB and BB (RB) have the highest medal payout rate per game and are the most advantageous gaming state.

  RT0 and RT0 of RT0-3 have a higher probability of winning the re-gamer, and the payout rate of medals per game is higher than RT1 and 3, compared to RT1 and 3, the player. It can be said that this is an advantageous state.

  Further, in the slot machine according to the present embodiment, when the gaming state is RT0 to 3, the sub-control unit 91 provides an assist time (hereinafter referred to as AT) that is a notification period in which a navigation effect that notifies the internal lottery result can be executed. The production state can be controlled.

  Here, the transition state of the gaming state of the present embodiment will be described. As shown in FIG. 58, when RB or BB (RB) ends, the process proceeds to RT3.

  In RT3, when the transition outcome is stopped, the process proceeds to RT1, and when the special combination is won, the process proceeds to RT4 or RT5 depending on the type of the selected special combination.

  In RT3, if any of the left bells 1-4, middle bells 1-4, right bells 1-4 is won and the small role cannot be won, the transitional outcome will stop, In RT3 which moved after the end of RB or BB (RB), when any of left bell 1-4, middle bell 1-4, right bell 1-4 is won, and a small part could not be won , Transition to RT1.

  In RT1, when the promotion replay wins, the process shifts to RT0, and when the special combination is won, the process shifts to RT4 or RT5 depending on the type of the selected special combination.

  Since the replays GR1 to 6 are elected at RT1 and the replay order is correct and the promoted replay is won, at RT1, the replays GR1 to 6 are elected and the answer is RT0 by correctly answering in the order of stoppage. Become.

  At RT0, if the fall replay wins or the transitional outcome stops, it moves to RT1, if the special replay wins, it moves to RT2, and the special role is elected. Accordingly, the process proceeds to RT4 or RT5.

  At RT0, the replays GR11 to 15 are elected, the special replay is won when the stop order is correct, and the fall replay is won when the answer is incorrect. In addition, when one of the left bell 1 to 4, the middle bell 1 to 4, and the right bell 1 to 4 is won at RT 0 and the small role cannot be won, the transitional outcome stops. Therefore, at RT0, the replay GRs 11 to 15 are elected, and the stop order is correctly answered, the process proceeds to RT2, and the replay GRs 11 to 15 are elected and the stop order is incorrect, or the left bells 1 to 4, If any one of the bells 1 to 4 and the right bells 1 to 4 wins and the small combination cannot be won, the process proceeds to RT1.

  In RT2, when the special combination is won, the process proceeds to RT4 or RT5 depending on the type of the special combination selected.

  In RT2, when any one of the left bells 1 to 4, the middle bells 1 to 4 and the right bells 1 to 4 is won and the small role cannot be won, the transitional outcome stops. For this reason, in RT2, if any one of the left bells 1 to 4, the middle bells 1 to 4 and the right bells 1 to 4 is won and the small role cannot be won, the process proceeds to RT1.

  In RT4 and 5, when the special combination that triggered the transition to the inside wins, it shifts to RB or BB (RB).

  When controlled by the AT, which will be described later, the sub-control unit 91 performs a navigation effect by winning a navigation target combination corresponding to the gaming state. The navigation target combination corresponding to the gaming state is replay GR1 to 6 when RT1 and replay GR11 to 15 when RT0. Further, in any of RT0 to RT2, the push order bell is a common navigation target combination.

  The navigation effect of the present embodiment is performed by displaying a navigation image from the liquid crystal display 51 and outputting navigation sound from the speakers 53 and 54. For example, when the replay GR1 or the left bell is won as the navigation image, “123” (indicating that the reel 2L is the first stop, the reel 2C is the second stop, and the reel 2R is the third stop) or “132” A pressing order image indicating the pressing order of the stop switches 8L, 8C, and 8R, such as the reel 2L is the first stop, the reel 2C is the third stop, and the reel 2R is the second stop, and the motif of the slot machine 1 Character images tailored to the are displayed. Also, as the navigation voice, for example, “left middle right!” (Reel 2L indicates the first stop, reel 2C indicates the second stop, reel 2R indicates the third stop) and “left and right middle!” (Reel 2L). Indicates the first stop, the reel 2C is the third stop, and the reel 2R is the second stop). Note that the navigation voice is output only from the stop switch that the player should press first or next. Therefore, if all the reels are rotating, for example, “Left!” Is output first. When the reel 2L is stopped, “Middle!” Is output next. When the reels 2L and 2C are stopped, "Right!" Is output. Regarding the other replays GR2 to 36 and the push order bell, a navigation image corresponding to the replay GR is displayed from the liquid crystal display 51 and a navigation sound is output from the speakers 53 and 54.

  As a navigation effect when winning replays GR1 to GR6, a push order (see FIG. 64) for winning a promotion replay according to the winning situation is notified.

  As a navigation effect when the replays GR11 to 15 are won, a push order (see FIG. 64) for winning a special replay according to the winning situation is notified.

  Further, as a navigation effect when one of the push order bells is won, a push order (see FIG. 65) for surely winning the right-down bell or the middle bell is notified.

  As described above, in the navigation effect in the present embodiment, a message reminiscent of an operation mode advantageous to the player is notified in the same mode regardless of the type of the navigation target role. For this reason, the player can operate in an operation mode that is advantageous to the player without being conscious of the type of the winning navigation target combination.

  Then, by executing the navigation effect, it is possible to avoid the promotion replay winning, the special replay winning, the bell winning, and the falling replay winning that are intentionally won.

  In addition, the aspect of a navigation effect is not restricted to such an aspect, What kind of thing may be sufficient if a player is distinguishable according to a winning condition. In addition, the navigation effect is not limited to what is displayed on the liquid crystal display 51, and may be executed using the effect effect LED 52, the speakers 53 and 54, the reel LED 55, and the like.

  Also, in this embodiment, when winning the push order bell, only the stop switch to be stopped first is awarded if the correct answer (ie, 3 choices), but the push order replay is correct for the order of pressing the stop switches (ie, Since there is no winning unless the selection is made (6 selections), the pressing order of the stop switches for the second reel and the third reel when the pressing order bell is won is also determined by the pressing order lottery. Thus, although the navigation effect is performed as if the push order bell does not win if the answer is not correct in the 6-choice push order, if the push-bell is won, the push order is obtained if the correct answer is made in the 3-choice push order. Since the bell wins, the push order bell wins if only the first stop is answered correctly, even if it does not follow the pressing order notified by the navigation effect. In this way, by selecting 6 choices in all of the navigation target roles, the game content can be made uniform, and the game content can be easily understood by the player. In addition, since the push order bell wins if one of the three choices is correct, a lottery with six choices need not be performed.

  In the present embodiment, the sub-control unit 91 is set to ART (a state controlled by AT in RT2) when a target combination (Bell, weak cherry, strong cherry in this embodiment) is won in BB (RB) or RB. Navistock lottery to decide whether to control or not. In the navigation stock lottery at the time of winning the target role, by determining the number of navigation stocks including 0, whether or not to give the number of navigation stocks and the number of navigation stocks are determined.

  In addition, when the number of navigation stocks remains and when the number of navigation stocks is newly acquired, the number of navigation stocks acquired this time is added to the remaining number of navigation stocks.

  Navistock is the right to move to RT2 if RT1, and after the transition to RT2, a predetermined number of games (in this embodiment, 50 games which are the initial number of games and the number of games won in the extra lottery described later) The number of rights controlled by ART over the total number of games). After shifting to RT2, the navigation stock number is consumed (subtracted) by 1 to be controlled to ART for a predetermined number of games, during which a navigation effect described later is executed. For this reason, it can be said that the greater the determined number of navigation stocks, the higher the degree of advantage for the player.

  As shown in FIG. 66, the sub control unit 91 stores the number of navigation stocks in a predetermined area of the RAM 91c when one or more navigation stocks are determined in the navigation stock lottery. The sub-control unit 91 specifies whether to control to AT based on the presence / absence of navigation stock in the RAM 91c. When one or more navigation stocks remain, the control is performed by the AT after the ART winning notification is notified through the ART confirmation notification.

  When the sub control unit 91 starts the control of the AT, a navigation effect is executed when the target combination is won. At this time, in RT1, when the replays GR1 to 6 are won, the navigation effect is targeted, and when the replays GR1 to 6 are won, the push order for winning the promoted replay is notified by the navigation effect, so stop according to the notified push order. It is possible to shift from RT1 to RT0 by performing the operation. In addition, after the AT control is started, in any gaming state of RT0 to 2, when the push order bell is won, the push order for winning the bell is notified, so by performing the stop operation according to the notified push order It is also possible to win medals with certainty.

  After the promotion replay wins at RT1 and shifts to RT0, it becomes the target of the navigation effect when the replays GR11 to 15 are won, and the push order for winning the special replay when the replays GR11 to 15 are won is notified by the navigation effect. It is possible to shift from RT0 to RT2 by performing a stop operation in accordance with the notified pressing order. In addition, as described above, when the push order bell is won, the push order for winning the bell is notified, so by performing a stop operation according to the notified push order, it is possible to reliably acquire medals, It is possible to avoid the transition outcome and the transition to RT1.

  When the special replay wins at RT0 and shifts to RT2, the control of the ART starts. Unless the ART start effect has already been performed, the ART is triggered by the start operation of the next game that won the special replay. An ART start effect indicating the start of the game is executed, an initial value of the remaining number of ART games (50 games in this embodiment) is set in the RAM 91c, and counting of the remaining number of ART games is started. At this time, during the ART, it is interrupted by winning the special role, and the navigation stock is consumed (subtracted) by 1 except in the case of resuming when the bonus ends.

  After the ART starts, the push order for winning the bell when the push order bell is won will be notified. Therefore, by performing the stop operation in accordance with the notified push order, it is possible to reliably acquire medals and to make a transition. The outcome can be avoided and the transition to RT1 can be avoided.

  Also during the ART, in the winning of the replay GR21, winning of the BB1 or BB2, and the freeze state to be described later with these winnings, the winning combination (the combination of black 7-black 7-black 7 stops on the winning line LN) ) Will stop and increase the number of games. At this time, the number of games to be added is determined from a plurality of different game numbers, and the determined number of games is added to the remaining number of games in the RAM 91c.

  Also, after the start of ART, every time one game is consumed, the number of remaining games is decremented by 1, and if a special role is won before the remaining number of games reaches 0, the fact that the special role has been won is confirmed. The bonus confirmation notification shown is performed. At the same time that the special role is won, RT2 ends, ART is interrupted, and the number of ART games is also interrupted. Thereafter, the bonus is controlled by winning the winning special role, and the transition is stopped before the 32 games have passed in RT3 to which the transition is made after the bonus ends, and the transition is made to RT1 or the 32 games after the bonus is finished. When the time has elapsed, the ART confirmation notification is performed, the AT control is resumed, and by switching to RT 2 again, the ART start effect is performed, the ART is resumed, and the count of the remaining games of the ART is also resumed. In this case, the navigation stock is not consumed (subtracted) as described above. Note that when the ART confirmation notification is made at RT3, the navigation effect is not performed until the push order bell is won, and it is missed and the transition is stopped and the transition is made to RT1. Yes.

  In addition, when the number of remaining games becomes 0 after the start of ART, if the number of remaining navigation stocks is not 0, a latent lottery for determining whether or not to hide ART is performed and it is not to be hidden. If determined, after executing the ART end effect indicating the end of the ART at the end of the game, the ART start effect is performed in response to the betting number setting operation of the next game, and the ART is restarted. Consumption (subtraction) is performed, and an initial value of the remaining number of ART games (50 games in this embodiment) is set in the RAM 91c, and counting of the remaining number of ART games is started.

  Also, if it is determined to be hidden in the latent lottery, the number of latent games for a maximum of 32 games is determined, and after completion of the ART, an ART end effect indicating the end of the ART is executed, and then the AT control is terminated. Let

  In this state, since the navigation effect is not executed, it is impossible to avoid the transition outcome at the time of winning the push order bell, and the transition outcome stops and the transition to RT1 is performed. RT2 will be maintained until the game stops, and if the transition is not stopped before the number of latent games has elapsed, the ART start effect will be performed in response to the betting number setting operation for the next game, and the ART will be resumed. Then, the navigation stock is consumed (subtracted), an initial value of the remaining number of ART games (50 games in this embodiment) is set in the RAM 91c, and counting of the remaining number of ART games is started.

  In addition, when it is determined to be hidden in the latent lottery, and the AT control is finished, the transition is stopped before the number of latent games elapses. At the same time, the AT control is resumed, and by switching to RT2 again, the ART start effect is performed, the ART is resumed, the navigation stock is consumed (subtracted), and the RAM 91c stores the initial value of the remaining number of games (this book). In the embodiment, 50 games) are set, and counting of the remaining number of ART games is started.

  Further, after the start of ART, if the number of remaining games becomes 0 and the number of remaining navigation stocks is 0, an ART end effect is executed and the control of AT is ended. As a result, the navigation effect is not executed, so that it is impossible to avoid the transitional outcome when the push order is won, and a series of AT and ART control is performed by transitioning to RT1 by stopping the transitional outcome. Will end.

  In addition, after the ART confirmation notification, but before the ART start effect is performed, the push order other than the press order notified by the navigation effect is executed in spite of the navigation effect being executed when the replays GR1 to GR6 are won in RT1. If the promotion replay is not won as a result of the stop operation in, in the push order other than the push order informed by the navigation effect in spite of the fact that the navigation effect is executed at the time of winning the replays GR11 to 15 in RT0. As a result of the stop operation, if the special replay does not win and the fall replay wins and moves to RT1, the navigation effect is notified despite the fact that the navigation effect was executed at the time of winning the push order bell at RT0. As a result of performing stop operation in a push order other than the push order, if the transition start stops and transitions to RT1, the ART control is opened without transitioning to RT2. Unless the ART start effect has already been performed, the ART start effect is executed in response to the start operation of the next game, and the initial value of the remaining number of ART games (50 games in this embodiment) is stored in the RAM 91c. Set and start counting the number of remaining ART games. At this time, during the ART, it is interrupted by winning the special role, and the navigation stock is consumed (subtracted) by 1 except in the case of resuming when the bonus ends. During ART without transitioning to RT2, navigation effects are executed during the winning of the replay GR1-6, replay GR11-15, and push order bell until the transition to RT2, and replay is performed at RT1. When GR1-6 are elected, it is possible to make a transition to RT0 by performing a stop operation according to the navigation effect. Further, when replay GR11-15 is elected at RT0, the stop operation is performed according to the navigation effect. , It is possible to shift to RT2.

  In addition, as a result of performing the stop operation in the push order other than the push order notified by the navigation effect during the ART after the transition to RT2, the navigation effect was executed at the time of the push order bell winning, Even when the transition is stopped and the transition to RT1 is performed, the ART is controlled in a state where the transition to RT2 is not performed similarly to the above, but in this case, the ART start effect has already been performed. The ART start effect will not be performed again.

  In addition, even in ART without transitioning to RT2, the number of remaining games is decremented by 1 every time one game is consumed, and if a special role is won before the remaining number of games becomes 0, the special role is won. A bonus confirmation notification is made to indicate that is confirmed. At the same time that the special role is won, RT1 ends, ART is interrupted, and the count of the number of games of ART is also interrupted. Thereafter, the bonus is controlled by winning the winning special role, and the transition is stopped before the 32 games have passed in RT3 to which the transition is made after the bonus ends, and the transition is made to RT1 or the 32 games after the bonus is finished. When the time has elapsed, the ART confirmation notification is performed, the AT control is resumed, and by switching to RT 2 again, the ART start effect is performed, the ART is resumed, and the count of the remaining games of the ART is also resumed. In this case, the navigation stock is not consumed (subtracted) as described above. Note that when the ART confirmation notification is made at RT3, the navigation effect is not performed until the push order bell is won, and it is missed and the transition is stopped and the transition is made to RT1. Yes.

  In addition, if the number of remaining games becomes 0 after the start of ART in a state not shifted to RT2, if the number of remaining navigation stock is not 0, the latent lottery for determining whether or not to hide the ART If it is determined that the game is not to be hidden, an ART end effect indicating the end of the ART is executed at the end of the game, and then the ART start effect is performed with the betting number setting operation of the next game. Control is resumed without shifting to RT2, and the navigation stock is consumed (subtracted) by 1 and the initial value of the remaining number of games in ART 91 (50 games in this embodiment) is set in the RAM 91c. To start.

  Also, if it is determined to be hidden in the latent lottery, the number of latent games for a maximum of 32 games is determined, and after completion of the ART, an ART end effect indicating the end of the ART is executed, and then the AT control is terminated. Let

  Then, after the number of latent games has elapsed, the AT control is resumed, and by switching to RT2, the ART start effect is performed, the ART is resumed, the navigation stock is consumed (subtracted), and the remaining ART is stored in the RAM 91c. An initial value of the number of games (50 games in this embodiment) is set, and counting of the remaining number of games in the ART is started.

  In addition, after the start of ART in a state that does not shift to RT2, the number of remaining games is 0, and if the remaining number of navigation stock is 0, an ART end effect is executed, and a series of ATs is completed by terminating AT control. And the control of ART ends.

  As described above, in this embodiment, the sub-control unit 91 controls the ART, which is advantageous for the player, based on the navigation stock, separately from the BB that shifts in accordance with the winning of the special role. Compared to BB, ART has a lower expected increase in medals per game (the average increase per game minus the average decrease per game), but stays on the whole The ratio (the ratio of the number of games controlled by ART in a predetermined number of games (for example, 10,000 games)) is set high.

  In addition, in this embodiment, after RT notification with the highest rate of staying is performed, ART is not immediately transferred to RT2, which is advantageous to the player, but then replays GR1 to GR6 are elected at RT1, The promotion replay wins and moves to RT0, and replays GR11 to 15 are elected at RT0 and the special replay wins to shift to RT2 for the first time. At this point, ART control starts and the remaining number of games in ART Counting is started.

  In addition, after the ART confirmation notification is performed and the AT control is started, the replays GR1 to GR6 are won at RT1 in the stage until the transition to RT2, and the navigation effect is executed, and the promotion replay is performed by following this navigation effect. If the promotion replay does not win and does not move to RT0 even though it is possible to shift to RT0, the replays GR11 to 15 are elected at RT0 and the navigation effect is executed. Even if it is possible to shift to RT2 by winning a special replay by following the production, if the special replay does not win and does not move to RT2, the push order bell is won at RT0 and the navigation production is performed. Although executed, it is possible to avoid the stop of the transitional outcome by following this navigation effect, but stop the transitional outcome and go to RT1 In the case where the game is executed, the ART control is started without shifting to RT2, and counting of the remaining number of games in the ART is started with the medal payout rate being lower than that in the case of shifting to RT2. It is like that.

  If a special combination is won after the start of the ART control, the RT2 is terminated at that time, and the ART control is interrupted accordingly. After the bonus ends, when the ART is restarted, the ART confirmation notification is performed and the AT control is started, but in this case as well, the player does not immediately shift to RT2, which is advantageous to the player, but stays in RT3. If it is, the transition roll is stopped and the transition is made to RT1, and if it is staying at RT1, the replays GR1 to 6 are won, the promotion replay is won and the transition is made to RT0, and the replays GR11 to 15 are further performed at RT0. Is won and the special replay wins, the process proceeds to RT2. At this point, the ART control is started and the remaining number of ART games is started.

  In addition, if the navigation stock remains after the end of the ART control, the latent lottery is performed, and if it is determined that the latent lottery is not to be latent, the ART control is immediately resumed while the latent control is resumed. When it is determined that the latent game is to be latently determined, the ART control is not resumed immediately, but the AT control is terminated once, and after the number of latent games has elapsed, an ART confirmation notification is made. If it is maintained, the ART control will be resumed. However, if it has shifted to RT1, replays GR1 to GR6 will be elected, the promotion replay will win and shift to RT0, and further replay will be performed at RT0. When GR 11-15 wins and the special replay wins, the process shifts to RT 2 for the first time, and at this time, the ART control is resumed.

  As described above, in this embodiment, after the ART confirmation notification is performed in RT1, the stop operation is performed in accordance with the navigation effect, so that the winning probability of the re-gamer is high through RT0 and the process shifts to RT2, which is difficult to fall to RT1. As long as the stop operation is performed according to the navigation effect, the ART start effect is performed at the time of transition to RT2, and the counting of the number of ART games is also started from that point. As a result of performing the stop operation while ignoring the navigation effect even though the effect has been executed, if it is not possible to shift to RT0, if it shifts to RT0 and then falls to RT1, that is, the condition for shifting to RT2 If the condition for transition to RT2 is not satisfied even though is satisfied, the ART start effect is performed at that time, the ART control is started, and RT The count of the remaining number of games in the ART is started without shifting to the game, and if the navigation effect is not followed, the result is disadvantageous for the player. It is possible to prompt the user to perform a stop operation according to

  In this embodiment, the sub-control unit 91 determines the number of games from a plurality of games as described above when the replay GR 21 is won during the ART, or when the BB 1 or BB 2 is won. The number is added to the remaining number of games in ART.

  The sub-control unit 91 displays “Aim at 7 (black 7)!” On the liquid crystal display 51 as shown in FIG. 67A simultaneously with the start of the game in which the replay GR 21 has been won, Prompt for stop operation aiming at "Black 7". At this time, when the player performs a stop operation aiming at “black 7”, the combination of “black 7-black 7-black 7” is stopped on the winning line LN as shown in FIG. 67 (b). , “I did it! + XX (+50 in the figure)” is displayed on the liquid crystal display 51, and the number of added games is notified. As a result of the player performing a stop operation outside the “black 7” pull-in range, as shown in FIG. 67 (c), the combination of “black 7-black 7-black 7” is stopped on the winning line LN. Even if there is not, “Yay ~! + XX (+50 in the figure)” is displayed on the liquid crystal display 51, and the number of games added due to the winning of the replay GR 21 is notified.

  Also, in the game won by BB1 (or the game being carried over), simultaneously with the start of the game, “7 (net 7) is aimed!” Is displayed on the liquid crystal display 51, and the stop aiming at “net 7” is displayed. Encourage operation. At this time, when the player performs a stop operation aiming at “net 7”, the combination of “net 7-net 7-net 7” is stopped on the winning line LN, and “Yay ~! + XX” is displayed as a liquid crystal. The number of games displayed on the display 51 and added is notified. Similarly, in the game won by BB2 (or the game being carried over), simultaneously with the start of the game, “7 (white 7) is aimed!” Is displayed on the liquid crystal display 51, and “white 7” is aimed. Prompt for stop operation. At this time, when the player performs a stop operation aiming at “White 7”, the combination of “White 7-White 7-White 7” is stopped on the winning line LN, and “Ya ~! + XX” is displayed as a liquid crystal. The number of games displayed on the display 51 and added is notified.

  Further, the sub-control unit 91 performs the second stop operation not only when the replay GR21, BB1 or BB2 is won during ART but also when the replay GR22 is won, that is, by performing a stop operation aiming at “black 7”. Until then, “Black 7” will be the temper, but even if the combination of “Black 7-Black 7-Black 7” does not stop on the winning line LN, the game will not be stopped in the same way as when Replay GR21 is won. Simultaneously with the start, as shown in FIG. 67A, the liquid crystal display 51 displays “Aim at 7 (black 7)!” To prompt a stop operation aiming at “black 7”. Even if the player performs a stop operation aiming at “black 7”, as shown in FIG. 67 (d), the combination of “black 7-black 7-black 7” is finally stopped on the winning line LN. Without saying, “I ’m sorry…” is displayed on the LCD 51, That there was no plus of over-time number is notified.

  On the other hand, as shown in FIG. 69, the main control unit 41 advances the game for a predetermined period by delaying the timing at which the operation for advancing the game is activated when the replay GR21, BB1, or BB2 is won. A freeze lottery for determining whether or not to control to the freeze state in which the operation for making the operation invalidated is performed, and a freeze command for specifying the result of the freeze lottery is transmitted to the sub-control unit 91.

  In the present embodiment, the result of the freeze lottery is determined using the random number value generated by the channel RL1 of the random number circuit 508b.

  As already described with reference to FIG. 24, the channel of the random number circuit 508b is based on the signal (latch signal) from either terminal according to the setting contents of bits 6-4 of the RL0 hard latch selection register 1 (RL0LS1). Whether the RL0 hard latch random value register 1 (RL0HV1) of RL1 is to be latched is set. In this embodiment, the detection signal from the start switch 7 is input to the set terminal as a latch signal, and the channel RL1 of the random number circuit 508b is operated at the timing when the start switch 7 is operated. The RL0 hard latch random number value register 1 (RL0HV1) in FIG. 2 is configured to be able to latch a random number value, but the random number value generated by the channel RL1 of the random number circuit 508b is latched at the timing according to the detection signal from the operation means. In addition to the above, by setting “1” to bit 1 (RL1SL) of the random number soft latch register (RDSL) corresponding to the channel RL1 of the random number circuit 508b at a predetermined timing, the program sets the value in the channel RL1 of the random number circuit 508b RL1 soft latch random value register (RL1SV By latching the random number may be used in the determination result of the freeze lottery.

  When the main lottery is won, that is, when it is determined to control the freeze state, the main control unit 41 starts the control of the freeze state at the end of the game or simultaneously with the start operation of the next game.

  In the case of controlling to the freeze state at the end of the game when the replay GR 21 is won, one of the re-game players wins, and then the automatic setting of the bet number associated with the re-game player's win and the next game By delaying the timing at which the start operation is validated, the progress of the game is delayed for a predetermined period after the game ends.

  In addition, in the case of controlling the freeze state at the start of the next game triggered by the winning of the replay GR21, when the game start operation is performed in the next game, the timing at which the reel stop operation is validated for a predetermined period is set. By delaying, the progress of the game is delayed for a predetermined period after the game starts.

  In addition, in the case of controlling to the frozen state at the end of the game with the winning of BB1 or BB2, the winning BB1 or BB2 wins, and then the betting number setting operation (inserting medals or the MAXBET switch 6 By delaying the timing at which the betting number setting operation) is activated, the progress of the game is delayed for a predetermined period after the game ends.

  On the other hand, as shown in FIG. 67 (e), the sub-control unit 91 displays a message “Freeze start! Notify that the state has started.

  Also, when the freeze lottery is not won, that is, when it is determined that the control is not performed in the freeze state, the control is not performed in the freeze state, and the sub-control unit 91 is shown in FIG. As shown in f), a message “sorry ...” is displayed on the liquid crystal display 51 to notify that it is not controlled in the frozen state.

  The main control unit 41 performs a reel effect using the reels 2L, 2C, and 2R in the frozen state.

  In the reel effect, first, when a start operation of the game controlled to the freeze state is performed, a successful result is obtained in the freeze state (a stop mode in which the combination of “black 7-black 7-black 7” is aligned with the winning line LN). Successful lottery is performed to determine the number of successes within the range of 0 to 10 as the number of times of stopping, and the determined success number is set in the RAM 41c.

  In the present embodiment, the number of successes in the lottery for the success count is determined using the random number value generated by the channel RL2 of the random number circuit 508b.

  As already described with reference to FIG. 25, the channel of the random number circuit 508b is based on the signal (latch signal) from either terminal according to the setting contents of bits 2-0 of the RL0 hard latch selection register 2 (RL0LS2). Whether the RL0 hard latch random value register 2 (RL0HV2) of RL2 is to be latched is set. In this embodiment, the detection signal from the start switch 7 is input to the set terminal as a latch signal, and at the timing when the game start operation controlled to the freeze state is performed. A random number value can be latched in the RL0 hard latch random value register 2 (RL0HV2) in the channel RL2 of the random number circuit 508b. In this embodiment, the detection signal from the start switch 7 is input to the set terminal as a latch signal, and the channel RL2 of the random number circuit 508b is operated at the timing when the start switch 7 is operated. The RL0 hard latch random number value register 1 (RL0HV2) in FIG. 2 is configured to be able to latch the random number value, but the random number value generated by the channel RL2 of the random number circuit 508b is latched at the timing according to the detection signal from the operation means. Not limited to that, the bit 2 (RL2SL) of the random number soft latch register (RDSL) corresponding to the channel RL2 of the random number circuit 508b is set to “1” at a predetermined timing, so that the program in the channel RL2 of the random number circuit 508b RL2 soft latch random value register (RL2SV) The random number may be used in the determination result of the number of successful lottery by latching on.

  After the success number lottery, as shown in FIG. 67 (e), the reels 2L, 2C, 2R are rotated to detect the reference position, and then based on the detected reference position, as shown in FIG. 68 (a). The reels 2L, 2C, and 2R are slightly moved up and down to stand-by, with “Black 7” on each reel being a position above the upper stage (hereinafter referred to as “on the frame”). At this time, a preparation-out stop command is transmitted, and the sub-control unit 91 displays a message “Lit the lever!” On the liquid crystal display 51 and prompts the operation of the start switch 7. In this embodiment, the reference position is detected at the start of the reel effect, and the reel position is controlled based on the reference position. However, the stop position at the end of the previous game is held, and this stop position is set. The reel position may be controlled based on the above.

  When the operation of the start switch 7 is detected in the standby state of the above-described preparation or a certain time has elapsed, and the number of successes set in the RAM 41c is 1 or more, FIG. As shown in the figure, “black 7” on the frame is moved to the position of the winning line LN to derive the successful outcome. At this time, a result stop command is transmitted indicating that a successful result has been derived, and the sub-control unit 91 determines one of the number of games from a plurality of games, and based on the determined number of games, +! (XX in the figure +20) "is displayed on the liquid crystal display 51, and the fact that the number of games of ART has been added and the number of games is notified in accordance with the derivation of the successful outcome.

  Next, the main control unit 41 subtracts 1 from the number of successes set in the RAM 41c, and further suggests that there is a high possibility that the next time will be successful ("black 7" on the left and right reels is the upper row). And a success notice lottery for determining whether or not the “black 7” of the middle reel is to be derived).

  In this embodiment, the result of the success notice lottery is determined using the random number value generated by the channel RL3 of the random number circuit 508b.

  As already described with reference to FIG. 25, the channel of the random number circuit 508b is based on the signal (latch signal) from either terminal according to the setting contents of bits 6-4 of the RL0 hard latch selection register 2 (RL0LS2). Whether the RL0 hard latch random value register 3 (RL0HV3) of RL3 is to latch the random value is set. In this embodiment, the detection signal from the start switch 7 is input to the set terminal as a latch signal, and the timing at which the start switch 7 is operated in the standby state of the preparation output. The random number value can be latched in the RL0 hard latch random value register 3 (RL0HV3) in the channel RL3 of the random number circuit 508b. Further, even if the start switch 7 is not operated in the standby state of the preparation output, the program sets the bit 3 (RL3SL) of the random number soft latch register (RDSL) corresponding to the channel RL3 of the random number circuit 508b by a program when a certain time elapses. By setting “1”, the random number value can be latched in the RL3 soft latch random value register (RL3SV) in the channel RL3 of the random number circuit 508b.

  Then, when the success notice lottery is won, that is, when it is decided to derive the notice notice, the notice notice is derived as shown in FIG. At this time, a notice stoppage command is transmitted, and the sub-control unit 91 notifies the liquid crystal display 51 that a message “next time is a chance!” Is displayed, which indicates that there is a high possibility of success next time.

  The main control unit 41 then rotates the reels 2L, 2C, and 2R toward the preparation event, as shown in FIG. At this time, a change restart command is transmitted, and the sub-control unit 91 displays a message “one more time!” On the liquid crystal display 51 to notify that the reel effect is continued.

  Next, as shown in FIG. 68 (a), the main control unit 41 again sets each reel as a preparation output and stands by with the reels 2L, 2C, and 2R slightly moved up and down.

  In addition, when the success notice lottery is not won, that is, when it is decided not to derive the notice notice, the notice notice is not derived, and as shown in FIG. The reels 2L, 2C, and 2R are rotated.

  In the success notice lottery, when the number of successes is 1 or more, the derivation of the notice is determined with a higher probability than when the number of successes is 0, and the derivation of the notice is determined with a higher probability as the number of successes is larger. After a successful outcome is derived, a further advance notice is derived, so there is a higher possibility that a successful outcome will be derived the next time compared to when no advance outcome is derived. This suggests that there is a possibility that many successes remain compared to the case where the notice is not derived.

  Then, the main control unit 41 has the RAM 41c set to control the preparation output → start switch 7 operation or a certain time lapse → success output → success count subtraction → success notification lottery → (notification output →) preparation output. Repeat until the number of successes is zero. If the number of successes becomes 0 and the start switch 7 is operated in the standby state of the preparation outcome or if a certain time has elapsed, as shown in FIG. 68 (e), the failure outcome (winning line) LN is made to derive a stop mode in which the combination of “black 7-black 7-black 7” does not stop. At this time, a result stop command is transmitted to the effect that the failure outcome has been derived, and the sub-control unit 91 displays a message “sorry ...” on the liquid crystal display 51 to derive the failure outcome and add it. As shown in FIG. 68 (f), as a result of deriving a successful result in the reel production, the total number of ART games added (replay GR21 is won) as shown in FIG. 68 (f). (Including the number of games added together) is displayed on the liquid crystal display 51.

  Then, the freeze state ends when the failure outcome is derived, and if it is the freeze state at the end of the game due to the replay GR21 winning, the rotation of the reel is stopped and the bet number associated with the replay winning is automatically increased. After the setting, the start operation of the next game becomes valid, and if it is in a freeze state at the end of the game accompanying the BB1 or BB2 winning, the reel rotation is stopped and the setting operation of the betting number becomes effective, and the next operation following the winning of the replay GR21 If the game is in a frozen state at the start of the game, all the reels are once stopped, then the reels are started to rotate, and the constant speed rotation is performed, so that the stop operation becomes effective.

  As described above, in this embodiment, when the replay GR21, BB1 or BB2 is elected during the ART and is controlled to be in the freeze state, the reel effect is performed during the period in which the freeze state is controlled. Each time a successful outcome is derived, the number of ART games is added.

  In addition, it is possible to derive an advance notice that suggests that there is a high possibility that a successful outcome will be derived at a stage before entering the standby state of the ready outcome. As a result, it is possible to effectively increase the sense of expectation that success will be derived thereafter, that is, the number of ART games will be increased.

  In the present embodiment, the number of ART games is increased every time a successful result is derived in reel production, but the number of navigation stocks is increased every time a successful result is derived. It is also good. Furthermore, it is good also as a structure by which the effect that the special part is elected or the possibility is suggested by deriving a successful result in a reel production.

  In addition, in this example, after a successful outcome is derived once, a successful advance notice lottery is performed, and it is suggested that there is a high probability that the next successful outcome will be derived by deriving the advance notice outcome when winning. However, it is highly probable that the success notice lottery will be conducted even before the first and preparations are in standby state, and if the winner is selected, the advance notice will be derived and the next successful outcome will be derived. It is good also as a structure by which is suggested.

  Further, in the present embodiment, after the successful outcome is derived, the advance notice is derived, but at least the timing before the successful outcome is derived, and the standby state of the preparation outcome After that, the notice outcome may be derived at a timing before the success outcome or the failure outcome is derived.

  Further, in this embodiment, the reel effect is executed in the period controlled to the freeze state, and the freeze effect is controlled according to the result of the freeze lottery, and the success number and success notice lottery determined by the success number lottery are determined. The reel effect is executed according to the result. The random numbers generated by the random number circuit 508b mounted on the main control unit 41 are used for the freeze lottery, the success number lottery, and the success notice lottery. The random number circuit 508b uses channels RL0 to RL0 to generate separate random numbers. 4 circuits of RL3 are provided, and in the freezing lottery, the success number lottery, and the success notice lottery, the random numbers generated by the random number circuit 508b are different from the random numbers generated in the channel RL0 used for the internal lottery. Therefore, it is possible to prevent the random number used in the internal lottery from being synchronized with the random number used in the freezing lottery regarding the reel production, the successful number lottery, and the successful notice lottery.

  Also, in this embodiment, every time a successful outcome is derived in reel production, the number of ART games will be added, but the successful outcome will be derived according to the number of successful winning lotteries. Therefore, the success number lottery also functions as a lottery for determining the advantage for the player. The random number generated by the random number circuit 508b mounted on the main control unit 41 is used for the success number lottery. The random number circuit 508b includes four circuits RL0 to RL3 that generate separate random numbers. In the successful lottery, since the random number generated in the channel RL2 different from the random number generated in the channel RL0 used for the internal lottery among the random numbers generated by the random number circuit 508b is used, the random number used in the internal lottery And the random number used in the success number lottery for determining the advantage for the player can be prevented from synchronizing.

  In this embodiment, when random numbers are extracted from different channels (channel 0, channel 1, channel 2, and channel 3) of the 16-bit random number circuit 508b, internal lottery and freeze lottery are performed. In addition, although the case where the number of success times lottery is performed and the case where the lottery value for extracting the random numbers is different between the case where the lottery is performed and the case where the success notice lottery is performed are shown, it is not limited to the mode shown in this embodiment. For example, even in the same channel of the 16-bit random number circuit 508b, from different hard latch random number value registers used in the same channel (for example, RL0 hard latch random number value register 0 (RL0HV0) and RL0 hard latch random number value of the same channel 0) By extracting a random number value (from register 1 (RL0HV1)), the extracted random number value register may be different.

  In this embodiment, the random number generated by the 16-bit random number circuit 508b is used as the random number used by the freeze lottery, the success number lottery, and the success notice lottery, but the random number generated by the 8-bit random number circuit 508a is used. Also good.

  In this embodiment, the random numbers generated by the random number circuit 508b are used as random numbers used in the freeze lottery, the success number lottery, and the success notice lottery. An updated soft random number may be used.

  Further, in this embodiment, a configuration for determining the number of games of ART as a configuration for determining the advantage for the player, that is, a configuration for determining the advantage of the privilege given to the player is applied. The configuration may also be such that it is determined whether or not a privilege advantageous to the player is given.

  Further, although the number of ART games is applied as a privilege advantageous to the player, a right (advantageous gaming state is generated) that allows the player to shift to a gaming state (ART, bonus, etc.) advantageous to the player. Winning a lottery to determine whether or not (Navistock wins), winning to enter into an advantageous gaming state (special role winning), etc., and deriving display results that are advantageous to the player For example, a right to be notified of an operation mode for the game, a right to be controlled to a gaming state having a high expected value to which a gaming value is given, a right to be notified of whether or not the current gaming state is a gaming state advantageous to the player, etc. , It may be a privilege that is directly advantageous to the player, and it is not directly advantageous to the player, but for the player, for example, a condition for obtaining a privilege on the Internet. A indirectly advantageous benefits may be.

  Next, a modified example of the method for determining the successful outcome and the failed outcome in the reel production will be described. In this modification, the control of the reel effect itself includes a common configuration, and here, a configuration that is mainly different will be described.

  In the above example, when starting the reel production, the number of successes, which is the number of times that a successful outcome is derived in the reel production, is determined in advance. However, in this modification, as shown in FIG. When the start operation of the game controlled to the freeze state is performed, the unit 41 operates the start switch 7 in the standby state for the next preparation event, or derives a successful event when a certain time elapses. A successful lottery to determine whether or not to be performed. After that, when the start switch 7 is operated in a standby state with a preparation result, or when a predetermined time has elapsed, a success or failure result is derived based on the result of the last successful lottery.

  And if the start switch is operated in the standby state or if a successful outcome is derived when a certain time has elapsed, a further success lottery is performed to decide whether or not to derive the next successful outcome If a successful notice lottery is performed and the winner is elected, the notice notice is derived, and then a standby state is set for the preliminary notice. On the other hand, if the success notice lottery is not won, the notice notice is drawn. It will be in a standby state with a preparatory outcome without being derived.

  In this modification, the result of the successful lottery is determined using the random value generated by the channel RL2 of the random number circuit 508b.

  As already described with reference to FIG. 25, the channel of the random number circuit 508b is based on the signal (latch signal) from either terminal according to the setting contents of bits 2-0 of the RL0 hard latch selection register 2 (RL0LS2). Whether the RL0 hard latch random value register 2 (RL0HV2) of RL2 is to be latched is set. Further, in this modified example, the detection signal from the start switch 7 is input to the set terminal as a latch signal, and the timing at which the game start operation controlled to the freeze state is performed, Alternatively, the random number value can be latched in the RL0 hard latch random number value register 2 (RL0HV2) in the channel RL2 of the random number circuit 508b at the timing when the start switch 7 is operated in the standby state of the preparation stage. Further, even if the start switch 7 is not operated in the standby state of the preparation stage, the program sets the bit 2 (RL2SL) of the random number soft latch register (RDSL) corresponding to the channel RL2 of the random number circuit 508b by a program when a certain time elapses. By setting “1”, the random number value can be latched in the RL2 soft latch random value register (RL2SV) in the channel RL2 of the random number circuit 508b.

  In the present modification, the result of the success notice lottery is determined using the random value generated by the channel RL3 of the random number circuit 508b as in the above embodiment.

  In the standby state of this preparation event, when the start switch 7 is operated as in the first time or when a certain time has elapsed, the success event or the failure event is derived based on the result of the previous successful lottery.

  Then, the main control unit 41 fails in the success lottery by performing the control of preparation item → start switch 7 operation or a certain period of time → success item → success lottery → success notice lottery → (notice notice →) preparation item. Repeat until eyes are determined. Then, after the failure outcome is determined in the successful lottery, when the start switch 7 is operated in a standby state of the preparation outcome or when a certain time has elapsed, the failure outcome is derived. Along with this, the freeze state is also ended, and after all the reels are stopped once, the rotation of the reels is started and the constant speed rotation is performed, so that the stop operation becomes effective.

  In this modified example, in the success notice lottery, when the success number is determined in the success lottery, the probability of derivation of the notice number is determined as compared with the case where the failure number is decided. By raising the value, it is suggested that the possibility of a successful outcome being high after the next preliminary outcome is derived by deriving the advance notice. In addition, a configuration may be used in which different probabilities are applied as the probability of a successful lottery used for one reel production. In such a configuration, a higher probability is applied as the probability of a successful lottery. By setting a high probability of winning the outcome, it is possible to suggest that the probability of the successful lottery is preferentially obtained by deriving the advance notice.

  In addition, in this modification, the number of ART games is added each time a successful outcome is derived in the reel production, but the number of navigation stocks is increased every time a successful outcome is derived. It is also good. Furthermore, it is good also as a structure by which the effect that the special part is elected or the possibility is suggested by deriving a successful result in a reel production.

  In addition, in this modified example, after a successful outcome is derived once, a successful advance notice lottery is conducted, and it is suggested that there is a high possibility that the next successful outcome will be derived by deriving the advance notice outcome when winning. However, it is highly probable that the success notice lottery will be conducted even before the first and preparations are in standby state, and if the winner is selected, the advance notice will be derived and the next successful outcome will be derived. It is good also as a structure by which is suggested.

  In addition, in this modification, the number of ART games will be added each time a successful outcome is derived in the reel production, but the successful outcome is derived according to the result of the successful lottery. The successful lottery also functions as a lottery for determining the degree of advantage for the player. The random number generated by the random number circuit 508b mounted on the main control unit 41 is used for the successful lottery. The random number circuit 508b includes four circuits RL0 to RL3 that generate separate random numbers. In the freezing lottery, the successful lottery, and the successful notice lottery, random numbers generated in the channels RL1 to RL1 other than the random number generated in the channel RL0 used for the internal lottery among the random numbers generated by the random number circuit 508b are used. Therefore, it is possible to prevent the random numbers used by the internal lottery and the random numbers used by the freeze lottery, the successful lottery, and the successful notice lottery related to reel production from being synchronized.

  In this modification, the random number generated by the random number circuit 508b is used as the random number used in the freeze lottery, the successful lottery, and the successful notice lottery. However, a soft random number updated by the program is used as the random number used in the successful lottery. May be.

  Further, in this modified example, when random numbers are extracted from different channels (channel 0, channel 1, channel 2, and channel 3) of the 16-bit random number circuit 508b, internal lottery and freeze lottery are performed. Although the case where the random number for extracting the random number is different between the case where the successful lottery is performed and the case where the successful advance notice lottery is performed is shown, it is not limited to the mode shown in the present embodiment. For example, even in the same channel of the 16-bit random number circuit 508b, from different hard latch random number value registers used in the same channel (for example, RL0 hard latch random number value register 0 (RL0HV0) and RL0 hard latch random number value of the same channel 0) By extracting a random number value (from register 1 (RL0HV1)), the extracted random number value register may be different.

  In this modification, the random number generated by the 16-bit random number circuit 508b is used as the random number used by the freeze lottery, the successful lottery, and the successful notice lottery. However, the random number generated by the 8-bit random number circuit 508a is also used. good.

  In this modification, the random number generated by the random number circuit 508b is used as a random number used by the freeze lottery, the successful lottery, and the successful advance notice lottery. An updated soft random number may be used.

  Next, an explanation will be given of the reel acceleration process that is executed after the reel effect is executed when the main control unit 41 is controlled to be in the freeze state. This acceleration process is executed not only when the reel effect is executed at the start of the game but also when the reel effect is executed at the end of the previous game.

  FIG. 71 is a flowchart showing the control contents of the post-reel effect acceleration process executed after the reel effect is executed when the main control unit 41 is controlled to the frozen state.

  In the post-reel effect acceleration process, first, it is determined whether or not all reels are stopped (S1), and waits until all reels are stopped.

  After it is determined in step S1 that all reels are stopped, the left delay random value (Lr), the middle delay random value (Cr), and the right delay random value (Rr) are extracted (S2). ). As shown in FIG. 72, the left delay random number (Lr) is a random number for left delay that is incremented and updated by 1 in the range of 0 to 996 (total number 997) every time the timer interrupt process (main) is executed. The medium delay random number value (Cr) extracted from the counter is added from the random number counter for medium delay in the range of 0 to 997 (total number 998) every time the timer interrupt process (main) is executed. The extracted random number for right delay (Rr) is extracted from the random counter for left delay that is incremented and updated one by one in the range of 0 to 998 (total number 999) every time the timer interrupt process (main) is executed. The

  Next, based on the left delay random value (Lr), the middle delay random value (Cr), and the right delay random value (Rr) extracted in step S2, the left reel timer value (Lt), the middle reel A timer value (Ct) and a right reel timer value (Rt) are calculated and set in the RAM 41c (S3).

  Specifically, as shown in FIG. 73, the left reel timer value (Lt) is a value obtained by dividing the left delay random number value (Lr) by 21, and the middle reel timer value (Ct) is The middle delay random value (Cr) divided by 21 is a surplus value, and the right reel timer value (Rt) is a surplus value obtained by dividing the right delay random value (Rr) by 21. Both values are 0-20.

  Next, a reel delay command that can specify the left reel timer value (Lt), middle reel timer value (Ct), and right reel timer value (Rt) set in step S3 is set in the command queue (S4). ). The reel delay command set in the command queue is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main). Accordingly, the sub-control unit 91 can specify the timing at which each reel starts to rotate, the timing at which the reel rotates at a constant speed, and the timing at which the stop operation becomes effective by taking into account the acceleration time of the reels.

  Next, the rotation start of the left reel is set, and after starting the rotation of the left reel (S5), it is determined whether or not the acceleration of the left reel is completed, that is, whether or not the left reel is rotated at a constant speed. (S6).

  Here, a method for determining whether or not the reel has been rotated at a constant speed will be described. When the main control unit 41 starts to rotate the reel, the reel motor is accelerated by switching a plurality of control states with different step widths of the reel motor step by step, and finally the step width control state at constant speed rotation is performed. After reaching, control is performed to maintain this step width. At this time, the main control unit 41 sets a control flag indicating the control state of each stage in the RAM 41c, and switches the control state by referring to the control flag. Whether or not the reel has been rotated at a constant speed is determined based on whether or not a control flag indicating a control state of the step width at the time of constant speed rotation is set. If the control flag is set, the reel Is determined to have a constant speed rotation.

  The method for determining whether or not the reel has rotated at a constant speed is not limited to this. For example, the time from when the reference position of the reel is detected until the next reference position is detected is measured. Is configured to determine that the reel has been rotated at a constant speed by matching with the time during constant speed rotation more than the specified number of times, that is, whether the speed of the reel is physically detected and whether or not the constant speed rotation has been determined. It is good also as composition to do.

  After it is determined in step S6 that acceleration of the left reel has been completed, a value obtained by multiplying the timer value for left reel set in step S3 by 60 is set in the delay timer counter assigned to the RAM 41c (S7). ), And waits until the delay timer counter value becomes 0 (S8).

  When the counter value for delay becomes 0 in the step of S8, the rotation start of the middle reel is set, and after the rotation of the middle reel is started (S9), whether or not the acceleration of the middle reel is completed, that is, the middle reel is It is determined whether or not the rotation speed is constant (S10).

  The delay timer counter value is decremented by 1 every time the timer interrupt process (main) executed about every 0.56 ms is executed, so that (left reel timer value × 60 × 0. 56) The time of ms will be timed. Further, as described above, the left reel timer value is in the range of 0 to 20, and in this embodiment, it takes about 33.6 ms for the reel to move one symbol. Thereafter, the rotation of the middle reel starts at a timing from 0 to one reel.

  After it is determined in step S10 that the middle reel has been accelerated, the delay timer counter is set to a value obtained by multiplying the middle reel timer value set in step S3 by 60 (S11). Wait until the counter value reaches 0 (S12).

  When the counter value for delay becomes 0 in the step of S12, the rotation start of the right reel is set, and after the rotation of the right reel is started (S13), whether or not the acceleration of the right reel is completed, that is, the right reel is It is determined whether or not the rotation speed is constant (S14).

  As described above, the delay timer counter value is decremented by 1 every time the timer interrupt process (main) executed approximately every 0.56 ms is executed. (Timer value for middle reel × 60 × The time of 0.56) ms is counted, the timer value for the middle reel is a value in the range of 0 to 20, and it takes about 33.6 ms for the reel to move one symbol in this embodiment. Therefore, the rotation of the right reel starts at a timing from 0 to one reel after completion of acceleration of the middle reel.

  After determining that the acceleration of the right reel is completed in step S14, the delay timer counter is set to a value obtained by multiplying the timer value for right reel set in step S3 by 60 (S15), and the delay timer is set. Wait until the counter value reaches 0 (S16).

  When the delay counter value becomes 0 in the step of S16, the stop operation is set to be enabled. Accordingly, the stop operation of each reel is enabled (S17), and the post-reel acceleration processing is finished.

  As described above, the delay timer counter value is decremented by 1 every time the timer interrupt process (main) executed approximately every 0.56 ms is executed. (Right reel timer value × 60 × The time of 0.56) ms is counted, and the timer value for the right reel is a value in the range of 0 to 20, and it takes about 33.6 ms in this embodiment for the reel to move one symbol. Therefore, after the acceleration of the right reel is completed, the reel stop operation becomes effective at the timing from 0 to one reel.

  By executing the post-reel acceleration process after the reel effect associated with the controlled freeze state, the left reel is rotated from the state where all reels are stopped as shown in FIG. When the left reel delay time (left reel timer value × 60 × 0.56 ms) that fluctuates in the range from 0 to the first rotation of the reel has elapsed, the rotation of the middle reel starts. When the middle reel delay time (medium reel timer value × 60 × 0.56 ms), which varies from 0 to one reel rotation, has elapsed, the right reel When the right reel delay time (right reel timer value × 60 × 0.56 ms), which fluctuates in a range from the time when rotation starts at a constant speed to the time when the reel makes one revolution, each reel Stop operation is enabled.

  As described above, in this embodiment, in the freeze state in which the progress of the game is delayed, the relative positional relationship between the three reels is a specific positional relationship, that is, the combination of “black 7-black 7-black 7” is straightforward. Since the reel effect control is performed so that the positional relationship is aligned on the line, it is possible to perform an effect with an impact in the reel variation mode in the frozen state.

  In this embodiment, the rotation is performed as special variation control for performing variation control of the plurality of variable display regions so that the relative positional relationship between the display bands constituting the plurality of variable display regions becomes a specific positional relationship. Reel effect control is applied to stop the reels so that the same symbol combinations are aligned on three reels. However, the present invention is not limited to such effects. It is also possible to apply an effect that only rotates in a synchronized state in a line-up state. In addition, the combination of the same symbols is not only a straight line, but also a combination of different symbols, but with the symbols displayed in the perspective window, the player can win a specific role or a navigation stock. It is also possible to apply an effect that stops display modes (for example, reach eyes, chance eyes, etc.) that can be suggested, or performs synchronous rotation in that state.

  Further, as described above, after performing reel effect control in which the relative positional relationship between the three reels is a specific positional relationship, for example, “black 7-black 7-black 7” is arranged, the reels are maintained in the positional relationship as they are. If the player's stop operation is enabled, if the player operates the stop switches 8L, 8C, and 8R in an appropriate and continuous manner, the timing at which the stop operation is first performed by chance is within the “black 7” pull-in range. For example, the timing of the stop operation of the other reels is also likely to be the “black 7” pull-in range, and the reel positional control is not performed, that is, the relative positional relationship between the three reels is the specific positional relationship. If this is not the case, the possibility that “black 7-black 7-black 7” will be aligned will increase as compared with the case where the player appropriately operates the stop switches 8L, 8C, 8R. It becomes. As described above, by performing the reel effect control, a certain regularity is created between the relative positional relationship between the reels and the reel stop operation, thereby changing the degree of technical intervention of the reel stop operation. There is a risk that.

  On the other hand, in this embodiment, after the reel effect, all of the plurality of reels are temporarily stopped, and after that, the time from the start of rotation of one reel to the start of rotation of the next reel is randomly changed. As a result, after the reel production, before the stop operation is activated, the relative positional relationship between the three reels changes randomly, and the specific symbol is arranged in a straight line. Even if the reel effect is performed or such a reel effect is not performed, the difficulty level of the reel stop operation may change after the stop operation becomes effective. Absent. That is, even when the reel effect is performed, a certain regularity that does not occur if the reel effect is not performed does not occur, and the display result is derived by the technical intervention by the player by performing the reel effect. The gameplay of the slot machine is not compromised.

  In addition, the reel delay command that can determine the reel timer value that is randomly determined for each reel at a stage prior to the start of the rotation of the left reel that starts rotating first, and that can determine the determined reel timer value. Is transmitted to the sub-control unit 91. Further, since the reel acceleration time is constant, the sub-control unit 91 that has received the reel delay command adds the reel acceleration time to the timing to start rotation of each reel at a constant speed. And the timing at which the stop operation becomes valid can be specified. For this reason, the main control unit 41 does not transmit a command to that effect each time rotation of each reel starts or acceleration is completed, and the sub-control unit 91 performs constant-speed rotation at the timing at which each reel starts to rotate. It is possible to specify the timing and the timing at which the stop operation is effective, and to control the production in accordance with the specified timing.

  In this embodiment, after the reel effect, after all the reels are temporarily stopped, the relative positional relationship between the reels is made random by shifting the timing for starting the rotation of the reels. After reel production, all reels are set to the first speed slower than the constant speed rotation, and then the relative positional relationship between the reels is shifted by shifting the timing for accelerating the reel speed toward the constant speed rotation. After making the reels random, or after setting all reels to a second speed that is faster than the constant-speed rotation speed, shifting the timing of decelerating the reel speed toward the constant-speed rotation It is good also as a structure which makes the relative positional relationship of reels random.

  Further, in this embodiment, after the acceleration of the right reel that finally starts rotating, after the delay time for the right reel has elapsed, the stop operation becomes effective. Even when the stop operation is enabled immediately after the completion of acceleration, the relative positional relationship between the three reels is a random positional relationship. Therefore, the stop operation may be enabled at this point.

  In this embodiment, the rotation is started in the order of the left reel, the middle reel, and the right reel. However, the reel may be rotated in another predetermined order, or the reel rotation may be started. A configuration in which the order changes may be used.

  Further, in this embodiment, after the reel effect, the reel timer value that randomly varies for all the reels is determined at a stage before starting the rotation of the reel that starts the rotation first, and the determined reel The reel delay command that can specify the timer value is transmitted to the sub-control unit 91. However, the reel delay command varies at random for all reels at least before the rotation of the reel that starts rotating first is started. If the configuration is such that the reel timer value to be determined is determined and a reel delay command capable of specifying the determined reel timer value is transmitted to the sub-control unit 91, an effect similar to the above can be obtained. Each reel is labeled at the timing when the operation is started and the game is started, that is, before it is controlled to be frozen. Even when the reel timer value that fluctuates in the dam is determined and a reel delay command that can specify the determined reel timer value is transmitted to the sub-control unit 91, the main control unit 41, as described above, The sub-control unit 91 specifies the timing at which each reel starts to rotate, the timing at which the reel rotates at a constant speed, and the timing at which the stop operation becomes effective without transmitting a command to that effect every time rotation starts or acceleration is completed. Thus, it is possible to control production and the like in accordance with the specified timing.

  Further, in this embodiment, the delay time of each reel varies randomly within the range of the time that the reel makes 0 to 1 rotation, and the relative positional relationship can be shifted as much as possible. In addition, it is possible to prevent the reel delay time from becoming longer than necessary.

  In this embodiment, since the delay time is set until the rotation of the next reel is started after the acceleration of one reel is completed, a counter for measuring the delay time is set for each reel. There is no need to assign to the RAM 41c, and the delay time for each reel can be measured only by assigning a common delay timer counter to all reels. In particular, in the configuration in which the time is counted by subtracting the counter value every time the timer interrupt process (main) executed every 0.56 ms is executed as in the present embodiment, the maximum time for the reel to make one turn When setting the delay time, an 11-bit area capable of storing the maximum value (20) × 60 = 1260 of the reel timer value, which is substantially a 2-byte area, is required. However, although a 6-byte area is actually required, even if 1 byte is assigned to each of the left, middle, and right reel timer value areas as in this embodiment, the common delay timer counter Together with the area, an area of 4 bytes is sufficient.

  The present embodiment is not limited to this, and a configuration may be adopted in which a delay timer counter is assigned to each reel.

  In this embodiment, a value obtained by multiplying the reel timer value by 60, which is the number of times the timer interrupt process (main) executed while one symbol moves, is set in the delay timer counter, Every time the timer interrupt process (main) is executed, the delay timer counter value is decremented by one to count the delay time, so the timer interrupt process (main) It is not necessary to perform different processing for each execution count, and the processing can be made common without providing a branch with respect to the number of times of timer interrupt processing (main) with respect to timing of the delay time.

  The number of times the timer interrupt process (main) executed while one symbol moves is executed / N (N is a natural number, and the timer interrupt process (main) executed while one symbol moves) The value obtained by multiplying the number of executions by the reel timer value is set in the delay timer counter, and the delay timer counter value is decremented by 1 every time the timer interrupt process (main) is executed N times. By doing so, it is possible to have a configuration for measuring the delay time. With this configuration, there is no need to update the delay timer counter each time the timer interrupt process (main) is executed, and the timer for timing The load of the interrupt process (main) can be reduced, and the capacity of the RAM 41c allocated to the delay timer counter can be reduced.

  Further, the timer counter value for delay is decremented by 1 each time the timer interrupt process (main) is executed M times (number of times the timer interrupt process (main) executed while one symbol moves). In this configuration, the delay timer counter need not be updated every time the timer interrupt process (main) is executed, and the timer allocation related to timing is not necessary. The load of the loading process (main) can be reduced, and the capacity of the RAM 41c allocated to the delay timer counter can be further reduced.

  In this embodiment, the left reel timer value, the middle reel timer value, the right delay timer value (Lr) for setting the right reel timer value, the middle delay random value (Cr), and the right delay timer value are set. Since the random number value (Rr) is extracted by using a random number counter for left delay, a random number for middle delay, and a random number counter for right delay, each having a different update range, a random number counter having the same update range for each reel. The delay time corresponding to each reel can be made more varied as compared to the case where is used. As a result, even when a reel effect is performed in a positional relationship in which specific symbols are aligned on a straight line, there is regularity in the positional relationship after the reel effect when the stop operation is activated. Avoid as much as possible.

  In addition, as these random number counters, soft random number counters that are updated each time the timer interrupt process (main) is performed are used. Because it is used, it does not synchronize until the update cycle of each random number counter becomes the least common multiple of the total number of update ranges of each random number counter, compared with the case where a random number counter of the same cycle is used, Each time the reel effect is performed, it is possible to prevent the positional relationship between the reels from being biased when the stop operation is validated, that is, the positional relationship after the reel effect tends to be the same. As a result, even when a reel effect is performed in a positional relationship in which specific symbols are aligned on a straight line, there is regularity in the positional relationship after the reel effect when the stop operation is activated. It can be avoided more reliably.

  Further, the least common multiple that 997, 998, and 999, which are the total number of the random number counters, are synchronized is 994010994. In this embodiment, each random number is updated for each timer interrupt process (main), Since the interval is 0.56 ms and is updated about 1786 times per second, the next three random numbers will be synchronized after about 154.6 hours after synchronizing once, and the business hours of the amusement store are Since it is usually about 13 hours, the same random number combination is not extracted during the day and the left, middle and right reel timer values are not calculated.

  In other words, it takes a longer time than the general game store business hours to synchronize the values of the next three random number counters once synchronized, and the same player plays a game on the same day two or more times. Even when the reel effect is performed, the positional relationship after the reel effect is not the same. In addition, when setting the left, middle, and right reel timer values when performing reel production, it is a rare phenomenon that the same combination of the same random numbers as before is extracted. If it takes more than one game to synchronize the random numbers, that is, if three random numbers are not synchronized more than once during one game, the stop operation is effective every time the reel effect is performed. It is possible to prevent the positional relationship between the reels from being biased when being converted, that is, the positional relationship after the reel effect is likely to be the same positional relationship. As a result, even when a reel effect is performed in a positional relationship in which specific symbols are aligned on a straight line, there is regularity in the positional relationship after the reel effect when the stop operation is activated. Furthermore, it can avoid reliably.

  In this embodiment, the left delay timer value, the middle reel timer value, the left delay random value (Lr) for setting the right reel timer value, the middle delay random value (Cr), and the right delay timer value are set. The random number value (Rr) is extracted using a random number counter for left delay, a random number counter for middle delay, and a random number counter for right delay, each having a different update range. As in the case of the configuration to be used, as in the case described above, even when a reel effect is performed in a positional relationship where specific symbols are aligned on a straight line, the positional relationship after the reel effect is regulated when the stop operation is activated. It is possible to avoid as much as possible.

  An example in which random counter values having different update rules are used as the left reel timer value, the middle reel timer value, and the right reel timer value will be described below with reference to FIG.

  In this example, the current left reel timer value LT, the previous left reel timer value bLT, the current middle reel timer value CT, the previous middle reel timer value bCT, and the current right reel timer value RT are stored in the RAM 41c. The previous right reel timer value bRT is assigned. Each time the timer interrupt process (main) is executed, the calculation shown in FIG. 74 is performed, and the above values are updated.

  Specifically, first, the LT value is updated by adding 13 (which may be a predetermined prime number) to the bLT value, dividing the added value by 21, and updating it to a surplus value. Next, the value of CT is updated by adding the value of LT to the value of bCT and dividing the value after the addition by 21. Next, the RT value is updated to the value obtained by adding the CT value to the bRT value and dividing the added value by 21.

  The main control unit 41 extracts the left reel timer value, the middle reel timer value, and the right reel timer value when performing the post-reel acceleration process, and at the time of delaying these extracted values, respectively. Set to timer counter.

  In this example, the timer value for the left reel, the timer value for the middle reel, and the timer value for the right reel are extracted using random number counters having different update rules, so that the specific symbols are arranged in a straight line. Even when the reel effect is performed, it is possible to avoid the occurrence of regularity in the positional relationship after the reel effect when the stop operation is validated as much as possible.

  In addition, the value of the random number counter is 0 to 20, and can be used as it is as the timer value for the left reel, the timer value for the middle reel, and the timer value for the right reel, so that the load for calculating or processing the value can be reduced. .

  In the present embodiment, the left reel timer value, the middle reel timer value, and the right reel timer value are set to random values by using a random number counter value updated by a program. The random reel value generated by the random number circuit 508a or the random number circuit 508b may be used to set the left reel timer value, the middle reel timer value, and the right reel timer value to random values.

  Next, a modified example 1 of the reel acceleration process that is executed after execution of the reel effect accompanying the control of the main control unit 41 to the freeze state will be described. Here, the description will mainly focus on differences from the above embodiment.

  FIG. 76 is a flowchart showing the control contents of the post-reel effect acceleration process executed after execution of the reel effect associated with the main control unit 41 being controlled to be frozen in the first modification.

  In the post-reel effect acceleration process, first, it is determined whether or not all reels are stopped (S101), and waits until all reels are stopped.

  After it is determined in step S101 that all reels are stopped, the left delay random value (Lr), the middle delay random value (Cr), and the right delay random value (Rr) are extracted (S102). ).

  Next, based on the left delay random value (Lr), the middle delay random value (Cr), and the right delay random value (Rr) extracted in step S102, the left reel timer value (Lt), the middle reel A timer value (Ct) and a right reel timer value (Rt) are calculated and set in the RAM 41c (S103).

  Next, a reel delay command capable of specifying the left reel timer value (Lt), the middle reel timer value (Ct), and the right reel timer value (Rt) set in step S103 is set in the command queue (S104). ). The reel delay command set in the command queue is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main). Accordingly, the sub-control unit 91 can specify the timing at which each reel starts to rotate, the timing at which the reel rotates at a constant speed, and the timing at which the stop operation becomes effective by taking into account the acceleration time of the reels.

  Next, a value obtained by adding 240 to the value obtained by multiplying the timer value for the left reel set in step S103 by 60 in the delay timer counter assigned to the RAM 41c is set (S105), and the rotation start of the left reel is set. After setting and starting the rotation of the left reel (S106), it waits until the delay timer counter value becomes 0 (S107).

  Here, 240, which is added to the value obtained by multiplying the left reel timer value by 60, is a timer interrupt process (until acceleration is completed after the reel starts rotating, that is, until acceleration is completed). In step S107, the process waits until the time that is the sum of the reel acceleration time and the delay time based on the left reel timer value elapses.

  When the delay counter value becomes 0 in step S107, the delay timer counter is set to a value obtained by adding 240 to the value obtained by multiplying the intermediate reel timer value set in step S103 by 60 (S108). After setting the rotation start of the middle reel and starting the rotation of the middle reel (S109), it waits until the delay timer counter value becomes 0 (S110). That is, it waits until the time which combined the acceleration time of a reel and the delay time based on the timer value for middle reels passes.

  When the delay counter value becomes 0 in step S110, the delay timer counter is set to a value obtained by adding 240 to the value obtained by multiplying the right reel timer value set in step S103 by 60 (S111), After setting the start of rotation of the right reel and starting the rotation of the right reel (S112), it waits until the delay timer counter value becomes 0 (S113). That is, it waits until the time which combined the acceleration time of a reel and the delay time based on the timer value for right reels passes.

  When the delay counter value becomes 0 in the step of S113, the stop operation is set to be enabled, and accordingly, the stop operation of each reel is enabled (S114), and the post-reel acceleration processing is finished.

  In the first modification, after the reel effect accompanying the controlled freezing state, the above-described post-reel acceleration process is executed, so that all reels are stopped as shown in FIG. Rotation of the left reel is started, the acceleration time from the time when the rotation of the left reel starts until the left reel rotates at a constant speed, and the left reel delay time (the left reel varies from 0 to one revolution of the reel). (Timer value × 60 × 0.56 ms) when the total time has elapsed, the middle reel starts rotating, and the acceleration time from when the middle reel starts rotating until the middle reel reaches constant speed rotation When the time that is the sum of the intermediate reel delay time (medium reel timer value x 60 x 0.56 ms) that fluctuates in the range from 0 to the time when the reel makes one revolution has elapsed, Start spinning the reel, Acceleration time from the start of reel rotation until the right reel is rotated at a constant speed, and right reel delay time that varies from the time when the reel rotates at a constant speed to 0 to one reel rotation (right reel timer) The stop operation of each reel becomes effective at the time when the sum of (value × 60 × 0.56 ms) has elapsed.

  As described above, in the first modification, after the reel effect, all the plurality of reels are temporarily stopped, and after that, one reel starts to rotate, and then the time until the next reel starts rotating randomly changes. Thus, after the reel effect, before the stop operation is validated, the relative positional relationship between the three reels is changed randomly, and the specific symbols are arranged in a straight line. Even if the reel effect is performed or not, the difficulty level of the reel stop operation does not change after the stop operation becomes effective. . That is, even when the reel effect is performed, a certain regularity that does not occur if the reel effect is not performed does not occur, and the display result is derived by the technical intervention by the player by performing the reel effect. The gameplay of the slot machine is not compromised.

  In addition, the reel delay command that can determine the reel timer value that is randomly determined for each reel at a stage prior to the start of the rotation of the left reel that starts rotating first, and that can determine the determined reel timer value. Is transmitted to the sub-control unit 91. Further, since the reel acceleration time is constant, the sub-control unit 91 that has received the reel delay command adds the reel acceleration time to the timing to start rotation of each reel at a constant speed. And the timing at which the stop operation becomes valid can be specified. For this reason, the main control unit 41 does not transmit a command to that effect each time rotation of each reel starts or acceleration is completed, and the sub-control unit 91 performs constant-speed rotation at the timing at which each reel starts to rotate. It is possible to specify the timing and the timing at which the stop operation is effective, and to control the production in accordance with the specified timing.

  In the first modification, after the reel production, after all the reels are temporarily stopped, the relative positional relationship between the reels is made random by shifting the timing for starting the rotation of the reels. After reel production, all reels are set to the first speed slower than the constant speed rotation, and then the relative positions of the reels are shifted by shifting the timing for accelerating the reel speed toward the constant speed rotation. After making the relationship random, or after producing the reels, all reels are set to a second speed that is faster than the constant speed rotation, and then the timing for decelerating the reel speed toward the constant speed rotation is shifted. Thus, the relative positional relationship between the reels may be random.

  Further, in the first modification, the stop operation becomes effective after the sum of the acceleration time of the right reel and the delay time with respect to the right reel has elapsed after the start of rotation of the right reel, which finally starts rotating. However, even if the stop operation is enabled immediately after the acceleration time of the right reel that starts rotating at the end, the relative positional relationship between the three reels becomes a random positional relationship. It is good also as a structure which validates.

  In the first modification, the rotation is started in the order of the left reel, the middle reel, and the right reel. However, the reel may be rotated in another predetermined order, and the reel rotation may be performed. A configuration in which the starting order changes may be used.

  In the first modification, after the reel effect, the reel timer value that randomly varies for all the reels is determined and determined at the stage before starting the rotation of the reel that starts the rotation first. A reel delay command capable of specifying a reel timer value is transmitted to the sub-control unit 91, but at least at a stage before starting the rotation of the reel that starts the rotation first, each reel is randomly selected. An effect similar to the above can be obtained if the reel timer value that fluctuates is determined and a reel delay command capable of specifying the determined reel timer value is transmitted to the sub-control unit 91. Each of all reels at the timing when the start operation is performed and the game is started, that is, the timing before being controlled to be frozen. Even when the reel timer value that changes in a random manner is determined and a reel delay command capable of specifying the determined reel timer value is transmitted to the sub-control unit 91, the main control unit 41 performs the same operation as described above. The sub-control unit 91 specifies the timing at which each reel starts to rotate, the timing at which the reel rotates at a constant speed, and the timing at which the stop operation becomes effective without transmitting a command to that effect every time rotation starts or acceleration is completed. Thus, it is possible to control production and the like in accordance with the specified timing.

  Further, in the first modification, the delay time of each reel varies randomly within the time range in which the reel makes 0 to 1 rotation, and the relative positional relationship can be shifted to the maximum. In addition, it is possible to prevent the reel delay time from becoming longer than necessary.

  In the first modification, since the acceleration time and delay time for the next reel are set after the acceleration time and delay time for one reel are completed, the acceleration time and delay time are set for each reel. There is no need to assign a counter for measuring the time to the RAM 41c, and it is possible to measure the acceleration time and the delay time for each reel only by assigning a common delay timer counter to all the reels. In particular, in the configuration in which the time is counted by subtracting the counter value every time the timer interrupt process (main) executed every 0.56 ms is executed as in the present embodiment, the maximum time for the reel to make one turn When the time obtained by adding the acceleration time to the delay time is set, an 11-bit area capable of storing the maximum value (20) × 60 + 240 = 1500 of the reel timer value is required, which is substantially a 2-byte area. Yes, if it is provided for each reel, an area of 6 bytes is actually required, but even if 1 byte is assigned as the timer value area for the left, middle, and right reels as in this embodiment, Therefore, a 4-byte area is sufficient in combination with the common delay timer counter area.

  The first modification is not limited to this, and a configuration in which a delay timer counter is assigned to each reel may be employed.

  Next, a second modification of the reel acceleration process that is executed after execution of the reel effect associated with the main control unit 41 being controlled to the freeze state will be described. Here, the description will mainly focus on differences from the above embodiment.

  FIG. 78 is a flowchart showing the control contents of the post-reel effect acceleration process executed after execution of the reel effect associated with the main control unit 41 being controlled in the frozen state in the second modification.

  In the post-reel effect acceleration process, first, it is determined whether or not all the reels are stopped (S201), and waits until all the reels are stopped.

  After it is determined in step S201 that all reels are stopped, the left delay random value (Lr), the middle delay random value (Cr), and the right delay random value (Rr) are extracted (S202). ).

  Next, based on the left delay random value (Lr), the middle delay random value (Cr), and the right delay random value (Rr) extracted in step S202, the left reel timer value (Lt), the middle reel The timer value (Ct) and the right reel timer value (Rt) are calculated and set in the RAM 41c (S203).

  Next, a reel delay command that can specify the left reel timer value (Lt), the middle reel timer value (Ct), and the right reel timer value (Rt) set in step S203 is set in the command queue (S204). ). The reel delay command set in the command queue is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main). Accordingly, the sub-control unit 91 can specify the timing at which each reel starts to rotate, the timing at which the reel rotates at a constant speed, and the timing at which the stop operation becomes effective by taking into account the acceleration time of the reels.

  Next, a value obtained by multiplying the timer value for the left reel set in step S103 by 60 is set in the delay timer counter assigned to the RAM 41c (S205), and the process waits until the delay timer counter value becomes zero (S205). S206).

  In step S206, the process waits until a delay time based on the left reel timer value elapses.

  When the counter value for delay becomes 0 in the step of S206, the rotation start of the left reel is set, and after the rotation of the left reel is started (S207), for the intermediate reel set in the step of S203 in the delay timer counter A value obtained by multiplying the timer value by 60 is set (S208), and the process waits until the delay timer counter value becomes 0 (S209). That is, it waits until the delay time based on the timer value for the middle reel elapses.

  When the delay counter value becomes 0 in the step of S209, the rotation start of the middle reel is set, and after the rotation of the middle reel is started (S210), the delay timer counter is set for the right reel set in the step of S203. A value obtained by multiplying the timer value by 60 is set (S211), and the process waits until the delay timer counter value becomes 0 (S212). That is, it waits until the delay time based on the timer value for the right reel elapses.

  When the counter value for delay becomes 0 in the step of S212, the rotation start of the right reel is set, the rotation of the right reel is started (S213), and the acceleration of the right reel is continued until the right reel is rotated at a constant speed. Is completed (S214), and after the acceleration of the right reel is completed, the stop operation is set to be enabled. Accordingly, the stop operation of each reel is enabled (S215), and the post-reel acceleration processing is performed. finish.

  In the second modification, after the reel effect accompanying the controlled freezing state is executed, the post-reel effect acceleration process is executed, so that, as shown in FIG. When the left reel delay time (left reel timer value × 60 × 0.56 ms), which fluctuates in the range up to one revolution of the reel, elapses, the left reel starts rotating and the left reel starts rotating. When the middle reel delay time (middle reel timer value x 60 x 0.56 ms), which fluctuates in the range from 0 to one reel, has passed, the middle reel starts to rotate and the middle reel starts to rotate. After the right reel delay time (right reel timer value × 60 × 0.56 ms) that has fluctuated in the range from 0 to one reel, the right reel is rotated at a constant speed after each reel has reached a constant speed. Stop operation is enabled.

  As described above, in the second modification, after the reel effect, all of the plurality of reels are temporarily stopped, and after that, the time from the start of rotation of one reel to the start of rotation of the next reel is randomly changed. Thus, after the reel effect, before the stop operation is validated, the relative positional relationship between the three reels is changed randomly, and the specific symbols are arranged in a straight line. Even if the reel effect is performed or not, the difficulty level of the reel stop operation does not change after the stop operation becomes effective. . That is, even when the reel effect is performed, a certain regularity that does not occur if the reel effect is not performed does not occur, and the display result is derived by the technical intervention by the player by performing the reel effect. The gameplay of the slot machine is not compromised.

  In addition, the reel delay command that can determine the reel timer value that is randomly determined for each reel at a stage prior to the start of the rotation of the left reel that starts rotating first, and that can determine the determined reel timer value. Is transmitted to the sub-control unit 91. Further, since the reel acceleration time is constant, the sub-control unit 91 that has received the reel delay command adds the reel acceleration time to the timing to start rotation of each reel at a constant speed. And the timing at which the stop operation becomes valid can be specified. For this reason, the main control unit 41 does not transmit a command to that effect each time rotation of each reel starts or acceleration is completed, and the sub-control unit 91 performs constant-speed rotation at the timing at which each reel starts to rotate. It is possible to specify the timing and the timing at which the stop operation is effective, and to control the production in accordance with the specified timing.

  In the second modification, after the reel effect, after all the reels are temporarily stopped, the relative positional relationship between the reels is made random by shifting the timing for starting the rotation of the reels. After reel production, all reels are set to the first speed slower than the constant speed rotation, and then the relative positions of the reels are shifted by shifting the timing for accelerating the reel speed toward the constant speed rotation. After making the relationship random, or after producing the reels, all reels are set to a second speed that is faster than the constant speed rotation, and then the timing for decelerating the reel speed toward the constant speed rotation is shifted. Thus, the relative positional relationship between the reels may be random.

  In the second modification, the delay time is set before the rotation of the left reel that starts rotating first, and the left reel starts rotating after the delay time has elapsed. Even when a delay time is not provided before the rotation of the reel that starts rotation, the relative positional relationship of the three reels is a random positional relationship, so the delay before the rotation of the reel that starts rotation first is delayed. It is good also as a structure which starts rotation immediately, without providing time.

  In the second modification, the rotation is started in the order of the left reel, the middle reel, and the right reel. However, the reel may be rotated in another predetermined order, and the reel rotation may be performed. A configuration in which the starting order changes may be used.

  Further, in the second modification, after the reel effect, the stage before starting the rotation of the reel that starts the rotation first. Specifically, at the stage before measuring the delay time of the left reel, The reel timer value that varies at random is determined, and a reel delay command capable of specifying the determined reel timer value is transmitted to the sub-control unit 91, but at least the rotation of the reel that starts rotating first is started. If the configuration is such that the reel timer value that randomly varies for all the reels is determined at the previous stage and a reel delay command capable of specifying the determined reel timer value is transmitted to the sub-control unit 91, the same as above For example, when the game start operation is performed and the game is started, that is, before it is controlled to the frozen state. Even when the reel timer value that randomly varies for all reels is determined at the timing, and the reel delay command capable of specifying the determined reel timer value is transmitted to the sub-control unit 91, the main control is performed as described above. The unit 41 does not transmit a command to that effect each time rotation of each reel starts or acceleration is completed, and the sub-control unit 91 performs the timing at which each reel starts to rotate, the timing at which constant reel rotation occurs, and the stop operation. It becomes possible to specify the effective timing and control the production in accordance with the specified timing.

  Further, in the second modification, the delay time of each reel varies randomly within the range of the time that the reel makes 0 to 1 rotation, and the relative positional relationship can be shifted to the maximum. In addition, it is possible to prevent the reel delay time from becoming longer than necessary.

  In the second modification, the delay time for the next reel is set after the measurement of the delay time for one reel is completed. Therefore, a counter for measuring the delay time for each reel is stored in the RAM 41c. There is no need to assign, and it is possible to measure the delay time for each reel only by assigning a common delay timer counter to all reels. In particular, in the configuration in which the time is counted by subtracting the counter value every time the timer interrupt process (main) executed every 0.56 ms is executed as in the present embodiment, the maximum time for the reel to make one turn When setting the delay time, an 11-bit area capable of storing the maximum value (20) × 60 = 1260 of the reel timer value, which is substantially a 2-byte area, is required. However, although a 6-byte area is actually required, even if 1 byte is assigned to each of the left, middle, and right reel timer value areas as in this embodiment, the common delay timer counter Together with the area, an area of 4 bytes is sufficient.

  The second modification is not limited to this, and a configuration in which a delay timer counter is assigned to each reel may be employed.

  Next, a third modification of the reel acceleration process that is executed after the reel effect accompanying the main control unit 41 being controlled to the freeze state will be described. Here, the description will mainly focus on differences from the above embodiment.

  FIG. 80 is a flowchart showing the control contents of the post-reel effect acceleration process executed after execution of the reel effect associated with the main control unit 41 being controlled to be in the freeze state in the third modification.

  In the post-reel acceleration process, first, it is determined whether or not all reels are stopped (S301), and waits until all reels are stopped.

  After it is determined in step S301 that all reels are stopped, the left delay random value (Lr), the middle delay random value (Cr), and the right delay random value (Rr) are extracted (S302). ).

  Next, the left reel timer value (Lt) is calculated based on the left delay random value (Lr) extracted in the step of S302, and is set in the left delay timer counter assigned to the RAM 41c (S303). The intermediate reel timer value (Ct) is calculated based on the medium delay random number value (Cr) extracted in the above step, and is set in the medium delay timer counter assigned to the RAM 41c (S304). A right reel timer value (Rt) is calculated based on the extracted right delay random number value (Rr) and set in the right delay timer counter assigned to the RAM 41c (S305).

  Next, a reel delay command that can specify the left reel timer value (Lt), the middle reel timer value (Ct), and the right reel timer value (Rt) set in the steps of S303, S304, and S305, respectively. (S304). The reel delay command set in the command queue is transmitted to the sub-control unit 91 in the subsequent command transmission process of the timer interrupt process (main). Accordingly, the sub-control unit 91 can specify the timing at which each reel starts to rotate, the timing at which the reel rotates at a constant speed, and the timing at which the stop operation becomes effective by taking into account the acceleration time of the reels.

  Next, it is determined whether or not the left reel has started rotating (S307). If the left reel has started rotating, the process proceeds to step S310. On the other hand, if the rotation of the left reel has not started, it is determined whether or not the value of the left delay timer counter is 0 (S308).

  If the value of the left delay timer counter is not 0 in step S308, the process proceeds to step S310. On the other hand, if the value of the left delay timer counter is 0, the start of rotation of the left reel is set, the rotation of the left reel is started (S309), and the process proceeds to step S310.

  Here, the left delay timer counter value, the middle delay timer counter, and the right delay timer counter are each one each time the timer interrupt process (main) executed approximately every 0.56 ms is executed 60 times. Since the value is subtracted, the time of (left reel timer value × 0.56 × 60) ms is counted by the left delay timer counter. In addition, as described above, the timer value for the left reel is a value in the range of 0 to 20, and in this embodiment, it takes about 33.6 ms for the reel to move one symbol. The rotation of the left reel starts at a timing that randomly changes within a range from 0 to one full rotation of the reel after the reel has stopped.

  In step S310, it is determined whether or not the middle reel has started rotating. If the middle reel has started rotating, the process proceeds to step S313. On the other hand, if the middle reel has not started rotating, it is determined whether or not the value of the middle delay timer counter is 0 (S311).

  If the value of the middle delay timer counter is not 0 in step S311, the process proceeds to step S313. On the other hand, if the value of the middle delay timer counter is 0, the middle reel is set to start rotation. After the middle reel starts to rotate (S312), the process proceeds to step S313.

  Here, as described above, the timer counter value (main) that is executed approximately every 0.56 ms is executed 60 times for each of the left delay timer counter value, the middle delay timer counter, and the right delay timer counter. Since 1 is subtracted every time, the time of (timer value for left reel × 0.56 × 60) ms is counted by the timer counter for middle delay. Further, as described above, the timer value for the middle reel is a value in the range of 0 to 20, and in this embodiment, it takes about 33.6 ms for the reel to move one symbol. After the reels are temporarily stopped, the middle reel starts to rotate at a timing that randomly changes in a range from 0 to one reel.

  In step S313, it is determined whether or not the right reel has started rotating. If the right reel has started rotating, the process proceeds to step S316. On the other hand, if the rotation of the right reel has not started, it is determined whether or not the value of the right delay timer counter is 0 (S314).

  If the value of the right delay timer counter is not 0 in step S314, the process proceeds to step S316. On the other hand, if the value of the right delay timer counter is 0, the start of rotation of the right reel is set, the rotation of the right reel is started (S315), and the process proceeds to step S316.

  Here, as described above, the timer counter value (main) that is executed approximately every 0.56 ms is executed 60 times for each of the left delay timer counter value, the middle delay timer counter, and the right delay timer counter. Since 1 is subtracted every time, the time of (timer value for right reel × 0.56 × 60) ms is counted by the right delay timer counter. Also, as described above, the timer value for the right reel is a value in the range of 0 to 20, and in this embodiment, it takes about 33.6 ms for the reel to move one symbol. The rotation of the right reel starts at a timing that randomly changes in the range from 0 to one reel rotation after the reel has stopped.

  In step S316, it is determined whether or not all reels have started rotating. If any one of the reels has not started rotating, the process returns to step S307, and all reels have started rotating. For example, the process proceeds to step S317 and waits until the acceleration of all reels is completed.

  When the acceleration of all the reels is completed in the step of S317, the stop operation is set to be valid, and accordingly, the stop operation of each reel is validated (S318), and the post-reel effect acceleration processing is ended.

  In the third modification, after the reel effect accompanying the controlled freezing state is executed, the post-reel effect acceleration process is executed, so that as shown in FIG. When the left reel delay time (left reel timer value × 0.56 × 60 ms), which fluctuates in the range up to one revolution of the reel, has passed, the left reel starts rotating, and after all reels stop, When a medium reel delay time (timer value for medium reel × 0.56 × 60 ms) that fluctuates in the range until the reel makes one revolution has elapsed, rotation of the medium reel starts, and after all reels stop, After the right reel delay time (right reel timer value x 0.56 x 60 ms), which fluctuates in the range up to one revolution of the reel, the middle reel started to rotate, and all reels became constant speed. Stop operation of each reel is effective at the time It made.

  As described above, in the third modification, after the reel effect, all the plurality of reels are temporarily stopped, and the time until each reel rotates is changed randomly for each reel. The relative positional relationship between the three reels changes randomly before the stop operation is activated, and a reel effect is performed in which the specific symbols are aligned in a straight line. Even if such a reel effect is not performed, the difficulty level of the reel stop operation does not change after the stop operation becomes effective after that. That is, even when the reel effect is performed, a certain regularity that does not occur if the reel effect is not performed does not occur, and the display result is derived by the technical intervention by the player by performing the reel effect. The gameplay of the slot machine is not compromised.

  Also, before starting the rotation of any of the reels, a reel timer command that randomly determines a reel timer value that randomly varies for all reels, and a reel delay command that can specify the determined reel timer value is sub-control unit 91 is transmitted. Further, since the reel acceleration time is constant, the sub-control unit 91 that has received the reel delay command adds the reel acceleration time to the timing to start rotation of each reel at a constant speed. And the timing at which the stop operation becomes valid can be specified. For this reason, the main control unit 41 does not transmit a command to that effect each time rotation of each reel starts or acceleration is completed, and the sub-control unit 91 performs constant-speed rotation at the timing at which each reel starts to rotate. It is possible to specify the timing and the timing at which the stop operation is effective, and to control the production in accordance with the specified timing.

  In the third modification, after the reel effect, after all the reels are temporarily stopped, the relative positional relationship between the reels is made random by shifting the timing for starting the rotation of the reels. After reel production, all reels are set to the first speed slower than the constant speed rotation, and then the relative positions of the reels are shifted by shifting the timing for accelerating the reel speed toward the constant speed rotation. After making the relationship random, or after producing the reels, all reels are set to a second speed that is faster than the constant speed rotation, and then the timing for decelerating the reel speed toward the constant speed rotation is shifted. Thus, the relative positional relationship between the reels may be random.

  Further, in the third modification, after the reel effect, the left reel timer value, the middle reel timer value, and the right reel timer that change randomly at a stage before starting the rotation of the reel that starts the rotation first. The reel delay command capable of specifying the determined left reel timer value, middle reel timer value, and right reel timer value is transmitted to the sub-control unit 91. Before the start of rotation, the left reel timer value, middle reel timer value, and right reel timer value that change randomly are determined, and the determined left reel timer value, middle reel timer value, and right reel timer value are determined. If it is the structure which transmits the reel delay command which can specify to the sub-control part 91, the effect similar to the above is acquired, for example, game start operation Left reel timer value, middle reel timer value, and right reel timer value that change randomly at the timing when the game is started, that is, the timing before being controlled to the freeze state, and the determined left reel timer value, middle Even when a reel delay command capable of specifying the reel timer value and the right reel timer value is transmitted to the sub-control unit 91, the main control unit 41 performs the rotation of each reel or the completion of acceleration in the same manner as described above. Without transmitting a command to that effect, the sub-control unit 91 identifies the timing at which each reel starts to rotate, the timing at which the reels rotate at a constant speed, and the timing at which the stop operation becomes valid, and matches these identified timings. It is possible to control the production.

  In the third modification, the delay time of each reel varies randomly within the range of the time for which the reel makes 0 to 1 rotation, and the relative positional relationship can be shifted to the maximum. In addition, it is possible to prevent the reel delay time from becoming longer than necessary.

  In the third modification, the timer interrupt process (main) is executed for the left delay every time M (the number of times the timer interrupt process (main) executed while one symbol moves) is executed. Since the delay time is counted by subtracting the timer counter, the middle delay timer counter, and the right delay timer counter one by one, the left delay timer counter each time the timer interrupt process (main) is executed It is not necessary to update the middle delay timer counter and right delay timer counter, and the load on timer interrupt processing (main) related to timing can be reduced, while the left delay timer counter, middle delay timer counter, right The capacity of the RAM 41c assigned to the delay timer counter can also be reduced.

  The number of times the timer interruption process (main) executed while one symbol moves to each of the left reel timer value, the middle reel timer value, and the right reel timer value / N (N is a natural number, In addition, the value obtained by multiplying the number of times the timer interrupt process (main) executed while one symbol moves is divisible) is assigned to the left delay timer counter, the middle delay timer counter, and the right delay timer counter. Set and count each delay time by decrementing the left delay timer counter, the middle delay timer counter, and the right delay timer counter by one each time the timer interrupt processing (main) is executed N times Even in such a configuration, each time the timer interrupt process (main) is executed, the left delay timer counter, the middle delay timer counter, and the right delay timer counter There is no need to update, the load of timer interrupt processing (main) related to timing can be reduced, and the capacity of the RAM 41c allocated to the left delay timer counter, middle delay timer counter, and right delay timer counter can be reduced. Can do.

  The left reel timer value, the middle reel timer value, and the right reel timer value are each delayed by a value obtained by multiplying the number of times the timer interrupt process (main) executed while one symbol moves is executed. Timer counter, middle delay timer counter, and right delay timer counter are set to the left delay timer counter, middle delay timer counter, and right delay timer counter each time the timer interrupt process (main) is executed. The delay time may be timed by subtracting one by one. With this structure, there is no need to perform different processing for each time of execution of the timer interrupt processing (main) for the timekeeping of the delay time. The processing can be shared without providing a branch with respect to the number of times of the timer interrupt processing (main) regarding the time measurement of the delay time.

  The embodiments of the present invention have been described with reference to the drawings. However, the present invention is not limited to these embodiments, and modifications and additions within the scope of the present invention are included in the present invention. Needless to say.

  In the above embodiment, the present invention is applied to a slot machine in which bets are set using medals and credits as game values. However, slots for setting bets using game balls as game values are described. The present invention may be applied to a machine or a fully credit type slot machine that sets a bet amount using only credit as a gaming value. In the case of using a game ball as a game value, for example, one medal can correspond to five game balls, and when three bets are set in the first embodiment, 15 game balls are used. This is equivalent to setting the number of bets using.

  Further, the present invention is not limited to the use of only one of a plurality of types of game values such as medals and game balls, for example, a combination of a plurality of types of game values such as medals and game balls. It may be. That is, it is possible to play a game by setting the number of bets using any of a plurality of types of gaming values such as medals and game balls, and a plurality of types of games such as medals and game balls when a winning occurs. You may apply the slot machine which can pay out all of utility values.

  In the above-described embodiment, the variable display device is configured such that the symbols are continuously changed and displayed on the see-through window 3 by rotating a reel having a plurality of types of symbols arranged on the outer periphery. Alternatively, a variable display device may be used in which a belt on which a plurality of types of symbols are arranged is moved and displayed while the symbols are continuously changed in the see-through window 3. Furthermore, by displaying an image in which identification information such as a pattern image is periodically moved in a predetermined order on an image display device such as a liquid crystal display, the identification information is displayed on the display screen while being continuously changed. A display device may be applied.

1 slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 start switch 8L, 8C, 8R stop switch 41 main control unit 91 sub control unit 508b random number circuit 525b random number generation circuit 537 update monitoring circuit

Claims (1)

The game can be started by setting a predetermined number of bets for one game using the gaming value, and a plurality of types of identification information that can be distinguished from each other can be displayed in a variable display device that can be displayed in a variable manner. Is a slot machine in which one game is completed by being derived and winning can be generated according to the display result of the variable display device,
A game control means for controlling the game with a built-in random number circuit for generating numerical data to be a random value;
Start operation means operated when starting the game,
With
The random number circuit includes numerical value holding means for holding numerical data updated when the start operation means is operated,
The game control means includes
A pre-determining unit that determines whether or not to allow the generation of a prize using the numerical data held by the numerical value holding unit when detecting the operation of the start operation unit in a state where the game can be started;
Random number circuit monitoring means capable of monitoring the occurrence of abnormality in the frequency of the random number clock signal for updating the numerical data held by the numerical value holding means and the update state of the numerical data held by the numerical value holding means;
Random number circuit setting means for setting a monitoring target by the random number circuit monitoring means;
Including
The slot machine characterized in that the random number circuit setting means performs setting related to monitoring by the random number circuit monitoring means before the timing of extracting numerical data from the random number circuit.

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