JP2014085908A - Information processor, starting method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem where the startup time is long because a hibernation start by a kernel function requires processing time involved in a normal start sequence.SOLUTION: In performing hibernation start processing, an information processor suppresses the size of a memory management area to a size required for kernel initialization; enables the use of a work area by reading work area data; and reads compressed data to the work area in parallel with hardware initialization. After the kernel initialization, it expands the compressed data.

Description

  The present invention relates to a technique for rapidly starting an information processing apparatus having a hibernation mechanism.

  In recent years, hibernation that can reduce power consumption in a standby state in an information processing apparatus has attracted attention. Hibernation is a system interruption mechanism. While the system is activated, memory, CPU register, and device information (hereinafter referred to as a hibernation image) is saved in a non-volatile storage device such as a hard disk. Even if the power is turned off, the hibernation image is restored to the same state as before by reading the saved hibernation image at the next startup (hereinafter referred to as hibernation startup). Hibernation is sometimes used for the purpose of shortening the startup time of the system.

  There are two main types of system activation methods by hibernation. There are a method of performing recovery using a BIOS function or a boot loader function, and a method of performing recovery using a kernel function of an operating system.

  In the hibernation activation by the kernel function, after the kernel is initialized, the hibernation image stored in advance in the nonvolatile storage device is read to restore the state before the hibernation transition. Compared with BIOS hibernation, the device is initialized by executing a normal startup sequence, which is superior in versatility.

  Here, the hibernation by the kernel function requires a longer processing time than the hibernation by the BIOS or the boot loader, so that the startup time is long. Therefore, as in Patent Document 1, there is a method of compressing the entire hibernation image and saving it in a nonvolatile storage device.

JP 2001-022464 A

  When a DMA controller (direct memory access controller) is used, information can be read and written between storage devices in parallel with specific processing by the CPU. Therefore, if the DMAC can be incorporated in the hibernation activation, the hibernation image can be read in parallel with the kernel initialization, and the hibernation activation time can be shortened. However, on a kernel having a complicated memory management mechanism such as Linux (registered trademark), it is difficult for the DMA controller to access an unspecified area specified by the kernel or an area managed by the kernel. It is difficult to write data in Therefore, in the conventional hibernation activation method, it is difficult to read the hibernation image in parallel with kernel initialization and DMAC.

  For example, in order to realize the reading of compressed data in parallel with the kernel initialization using the technology for compressing the hibernation image as in Patent Document 1, an area to be read is necessary. It is difficult to simply secure from the free space at the time of kernel initialization. This is because the decompressed data must be arranged at the same address as before the hibernation transition, and this decompression destination may collide with the read destination of the compressed data.

  In order to achieve the above-described problems, an information processing apparatus according to the present invention includes a volatile memory, a compression unit that compresses data in an area in use of the volatile memory, the compressed data, and the volatile memory. A non-volatile memory that holds area information including addresses of unused areas as a hibernation image, and is held in the non-volatile memory in parallel with a kernel initialization performed using at least a part of the volatile memory. Reading means for reading the compressed data into at least a part of the unused area based on the area information, decompressing means for decompressing the compressed data to the volatile memory, and data decompressed by the decompressing means And starting means for starting the system based on the above.

  According to the present invention, it is possible to efficiently decompress the read compressed data while pre-reading the compressed data in parallel with the initialization of the kernel, so that faster startup is possible.

It is the schematic which shows the structure of information processing apparatus. It is the schematic which shows the function structure of the hibernation mechanism of this invention. It is a flowchart which shows the production | generation process of a hibernation image. It is a figure which shows the format of a hibernation image. It is a figure which shows the format of the work area data of a hibernation image. It is a figure which shows the format of the uncompressed data of a hibernation image. It is a figure which shows the format of the compression data of a hibernation image. It is a flowchart which shows the starting process of a system. It is a figure which shows about the difference of the access area of a kernel and a DMA controller. It is a flowchart which shows the return process of a hibernation image. It is a figure shown about the virtual memory at the time of hibernation starting.

  FIG. 1 shows a schematic configuration of the information processing apparatus 100. The CPU 101 and the direct memory access controller (hereinafter referred to as DMAC) 102 read / write data from / to the volatile memory 103 including a DRAM (including a DDR SDRAM). The DMAC 102 can access the volatile memory 103, the nonvolatile storage device 105, and the device 106 by direct memory access. An input / output control unit (hereinafter referred to as an I / O controller) 104 reads / writes data in / from a nonvolatile storage device (flash memory, HDD, SSD, etc.) 105 as a nonvolatile memory based on a request from the CPU 101 or the DMAC 102. . The device 106 is a peripheral device that is initialized by the CPU 101, and various devices such as a PCI-connected graphic board, a USB-connected scanner, and a printer can be used as the device 106. The device 106 includes a status register that holds its own state and a configuration register that holds values used for processing (values corresponding to image processing parameters and values indicating processing modes). Note that there may be a plurality of devices 106.

  The CPU 101 expands the program included in the nonvolatile storage device 105 in the memory 103, fetches the program from the memory 103, and executes processing described later.

  Hibernation is a technique for saving the system state and restoring the saved system state, and data indicating the saved and restored system state is called a hibernation image (the format of the hibernation image will be described later). The hibernation image is stored in the nonvolatile storage device 105.

  Here, the flow of a general hibernation process is shown. When a user (or user application) requests a system interruption, a hibernation image is generated based on the data written in the memory 103, the data indicating the state of the other device 106, and the register value of the CPU 101. Is written to the volatile storage device 105. When the information processing apparatus is turned off and restarted, kernel initialization is started. Immediately after the initialization of the kernel, the hibernation image is read from the nonvolatile storage device 105 to the memory 103, and the state immediately before the system interruption is restored. In the following description, the activation sequence using the hibernation image is referred to as hibernation activation.

  In this embodiment, the speedup of hibernation activation will be described using Linux (registered trademark) version 2.6.18 as a conventional method.

  In Linux (registered trademark), memory management is performed in units of pages. The area described below means a memory range composed of one or a plurality of pages.

  FIG. 2 is a diagram illustrating a configuration of the hibernation mechanism according to the present embodiment. States 201a-201d show different states of the same memory. Specifically, the state 200a is a state at the time of hibernation image generation, the state 200b is a state at the time of kernel initialization, the state 200c is a state after the kernel initialization, and the state 200d is a state after the hibernation is activated.

  Reference numeral 204 denotes a compression unit. The used area in the memory 201a is compressed page by page, and is output to the nonvolatile storage device 202 as a part of the hibernation image. However, some pages have a low compression ratio, and it is desirable that compression is not performed. Therefore, if the page has a low compression rate, it is output to the nonvolatile storage device 202 as a part of the hibernation image without being compressed. However, an area for storing a variable for performing hibernation processing (hereinafter referred to as a hibernation processing area) is not included in the hibernation image. In order to prevent the address value from changing even when the system is restarted, the hibernation processing area is statically secured from an area (described later) that is used for kernel management when hibernation starts.

  Reference numeral 203 denotes a work area data generation unit (area information generation unit). In this embodiment, since all compressed data is read during kernel initialization, an area for the reading is secured from an unused area when the hibernation image is generated. Therefore, the work area data generation unit 203 collects addresses of unused areas in the memory 201a, collects this information in a page conversion table, and outputs it to the nonvolatile storage device 202 as a part of the hibernation image. The data of the page conversion table is called work area data (or area information), and the area indicated by the data is called a work area.

  Reference numeral 205 denotes a memory restriction unit, and 206 denotes a memory initialization mechanism. The memory restriction unit 205 instructs the memory initialization mechanism 206 to restrict the memory area managed by the operating system, and the memory initialization mechanism 206 initializes the memory 201b based on this information. Due to this limitation, the memory 201b is divided into a kernel management area and a non-kernel management area. The purpose of this restriction is to allow data to be read into the non-kernel management area in parallel with the initialization process of the kernel by intentionally creating a non-kernel management area.

  Reference numeral 207 denotes a kernel initialization mechanism. The kernel is initialized within the range of the kernel management area initialized by the memory initialization mechanism 206 of the memory 201b.

  Reference numeral 208 denotes a work area validation unit. First, the work area data generated by the work area data generation unit 203 is read into a non-kernel management area of the memory 201b. A part of this information is overwritten on the currently used page conversion table, so that a work area for storing the compressed data can be secured and used.

  Reference numeral 209 denotes an initialization data reading unit (first reading unit), and 210 denotes a DMAC. The initialization data reading unit 209 uses the DMAC 210 to read hibernation images stored in the nonvolatile storage device 202 sequentially into the work area in parallel with the initialization process by the kernel initialization mechanism 207. However, uncompressed data is read into the area where the data originally existed when the hibernation image was generated.

  Reference numeral 211 denotes a data reading unit after initialization. First, when the initialization data reading unit 209 has not finished reading data other than uncompressed data, reading of the corresponding data is completed. Reference numeral 212 denotes an expansion unit. The compressed data read into the memory 201c is expanded to the area of the memory 201c where the data originally existed when the hibernation image was generated. In parallel with the decompression by the decompression unit 212, the post-initialization data reading unit 211 (second reading unit) uses the DMAC 210 to store uncompressed data in the memory 201c in which the data originally existed when the hibernation image was generated. Read into the area. The post-initialization data reading unit 211 need not distinguish between the kernel management area and the non-kernel management area. By these operations, the memory 201c is restored to the same state as the memory 201a (excluding the hibernation processing area). In the following description, the process of the post-initialization data reading unit 211 is referred to as a memory restoration process.

  In addition, the work area data generation unit 203 and the compression unit 204, the memory restriction unit 205, the memory initialization mechanism 206, the kernel initialization mechanism 207, the work area validation unit 208, the initialization data reading unit 209, and the initialization data reading The unit 211 and the decompressing unit 212 are processed based on a program stored in the nonvolatile storage device.

  Next, the flow of hibernation image generation in the present embodiment will be shown.

  FIG. 3 is a flowchart showing the processing flow of the CPU 101 from when the user (or user application) requests to enter the system interruption state until the system stops. First, the outline will be described. In step S300, the CPU 101 stops the process scheduler. In step S301, the CPU 101 stops each device and restricts interrupts to the CPU 101. In step S302, the CPU 101 saves the CPU register. In step S303, the CPU 101 generates and outputs a hibernation image. In step S304, the CPU 101 stops the system.

  In the following description, step S300, step S301, and step S302 are referred to as system interruption processing, and the details of the flowchart of FIG. 3 will be described. In step S300, when the CPU 101 stops all processes, the memory contents are not changed by process processing thereafter. In step S301, the CPU 101 stores the state of each device in the memory, and invalidates access to the subsequent devices. In step S302, the CPU 101 saves the contents of the CPU register on the memory. By this system interruption process, all information representing the system state is stored in the memory. Therefore, save this memory content in a nonvolatile storage device, read it to the memory as necessary, reset the state of each saved device and CPU register, restart the interrupt and process scheduler, The system state can be restored.

  In step S303, the CPU 101 generates a hibernation image from the memory area where the system state is held by the system interruption process, and outputs the hibernation image to the nonvolatile storage device. FIG. 4 is a diagram showing the format of the hibernation image. The header 400 is information regarding the hibernation image, and includes an identifier indicating whether the image is a valid hibernation image, the size of uncompressed data, and the size of compressed data. The work area data 401 stores page conversion table data. The compressed data 403 stores a compressed page, a size after compression, and an expansion destination address. Uncompressed data 404 stores an uncompressed page, and uncompressed data address 402 stores a read destination address of uncompressed data 404.

  Next, the format of the work area data 401 is shown.

  The work area data 401 is data indicating a work area into which a hibernation image is read when hibernation is activated, and is stored as a page conversion table. By storing in this way, discontinuous unused pages on the physical memory can be handled as a continuous area on the virtual memory. The page conversion table is composed of one or more conversion pages in stages. In the following description, the first conversion page is referred to as a page global directory, and the second and subsequent conversion pages are referred to as page tables.

  FIG. 5 is a diagram showing the format of the work area data 401. In the items corresponding to the work area of the page global directory 500, the physical memory addresses and status flags of the page tables 501a, 501b,. Then, according to the stage as the page conversion table, they are arranged and connected in order from the first stage conversion page.

  Furthermore, the page conversion table of the work area data 401 includes mapping information of the kernel management area when the hibernation image is generated. This information is used to access the decompression destination of the compressed data when hibernation is activated.

  Next, the formats of the uncompressed data address 402 and the uncompressed data 404 are shown.

  The non-compressed data address 402 and the non-compressed data 404 are in a correspondence relationship, and the location where the Nth stored data of the uncompressed data 404 is the Nth stored address of the uncompressed data address 402. FIG. 6 is a diagram showing this correspondence. The non-compressed page address 600 stored in the Nth and the non-compressed page 601 stored in the Nth are in a correspondence relationship. The number of information of the uncompressed data address 402 is equal to the number of information of the uncompressed data 404.

  The uncompressed data 404 includes two types of data: uncompressed data 404a that is restored to the non-kernel management area and uncompressed data 404b that is restored to the kernel management area. The reason for this division is that the hibernation image that can be read at the time of kernel initialization is limited to the header 400 to the non-compressed data 404a, and the non-compressed data 404b can be read only after the kernel initialization. . For this reason, the uncompressed data 404a is arranged in front of the uncompressed data 404b.

  Finally, the format of the compressed data 403 will be described.

  FIG. 7 is a diagram showing the format of the compressed data 403. Compression is performed in units of pages. Reference numeral 700 denotes information generated when one page of data is compressed, and includes a compressed page size 701, a compressed page address 702, and a compressed page 703. Based on these pieces of information, data for one page can be restored to the memory.

  For example, in a CPU having an address size of 32 bits, the compressed page size 701 is set to 12 bits, and the compressed page address 702 is set to 20 bits (size that can specify a page of 4 GB). In this case, the compressed page 703 must be less than 4096 bytes that can be expressed in 12 bits. When the size after compression is 4096 bytes or more, the page before compression is stored in the uncompressed data 404.

  Hereafter, pages stored in the compressed data 403 and the uncompressed data 404 are shown.

  The size of the compressed data 403 may be specified in advance by the user (or user application) as an upper limit size. In the work area, not only the compressed data 403 but also the non-compressed data address 402 and the stack at the time of decompressing the compressed data are stored. Therefore, the size of the compressed data 403 must be smaller than the value obtained by removing these sizes from the work area size. When the size of the compressed data 403 reaches the upper limit and no more pages can be stored, an unstored page is stored in the uncompressed data 404.

  After the non-volatile storage device is enabled, the hibernation image generated as described above is stored in a specified area in a physically continuous state in a format independent of the file system.

  A flow of hibernation activation in the present embodiment is newly shown.

  When the information processing apparatus is turned on, the BIOS and the boot loader perform processing as necessary, and kernel initialization is started.

  FIG. 8 is a flowchart showing the process from the start of kernel initialization to the restoration of the hibernation image in this embodiment. First, in brief, in step S800, the DMAC 102 reads information on a predetermined area of the nonvolatile storage device, and checks whether or not a valid hibernation image exists in the information read by the CPU 101. In step S801, the CPU 101 initializes the memory management mechanism. In step S802, the CPU 101 initializes the interrupt mechanism. In step S803, the CPU 101 starts parallel reading of the hibernation image. In step S804, the CPU 101 initializes other functions, and in parallel, the DMAC 102 reads the uncompressed data address 402, the compressed data 403, and the uncompressed data 404a in order. In step S805, the CPU 101 and the DMAC 102 perform memory restoration processing and preparation.

  Next, details of the flowchart of FIG. 8 will be described. In step S <b> 800, the CPU 101 initializes the DMAC 102 and the I / O controller 104, and the DMAC 102 reads the hibernation image header 400 stored in a predetermined area of the nonvolatile storage device into the memory 103. If the identifier included in the header 400 is valid, the CPU 101 determines that the hibernation image is stored in the nonvolatile storage device. FIG. 8 is a flowchart showing processing when a hibernation image exists in the non-volatile storage device. When it is determined that the hibernation image is not stored in the non-volatile storage device, processing for normally starting the system (not possible) (Shown).

  In step S801, the CPU 101 limits the memory range managed by the kernel to a specified size, and initializes the memory management mechanism. Specifically, the range of the kernel management area is limited by changing the memory map. This limit size is determined from the minimum necessary memory size required for the kernel initialization process, and the limit size secures at least a size necessary for kernel initialization. With this process, two types of areas, a kernel management area and a non-kernel management area, are secured in the memory. This restriction is removed by completing the memory restoration process.

  In step S801, the CPU 101 generates a page conversion table for accessing the kernel management area. The page global directory of this page conversion table is referred to as a kernel PGD (Page Global Directory). Further, the page conversion table of the work area data 401 is read into the memory. The page global directory of this page conversion table is referred to as hibernation PGD. The work area can be used by overwriting information related to the work area of the hibernation PGD into an area not used in kernel initialization of the kernel PGD.

  However, the page conversion table of the work area data 401 read into the memory must not be overwritten with kernel initialization data, compressed data, uncompressed data, and decompressed data. Therefore, since there is always one page global directory in the work area data 401, it is read into the hibernation processing area. Thereby, overwriting can be prevented. However, since the number of page tables in the work area data 401 is not fixed, it is difficult to reserve an area for holding in the kernel management area. Therefore, each page table is read into the kernel management area, and then the non-kernel management area is temporarily made available from the kernel, and each page table is moved to a predetermined area of the kernel management area.

  In step S803, the DMAC 102 is used as a means for performing parallel reading. In the DMAC, it is necessary to specify a physical address instead of a virtual address. Therefore, using the page conversion table, the virtual address that is the reading destination of the work area is converted into a physical address and specified in the DMAC 102.

  FIG. 9 is a diagram showing parallel reading at the time of kernel initialization. A memory 900 includes a kernel management area 900a and a non-kernel management area 900b. Reference numeral 901 denotes a kernel executed by the CPU 101, which accesses only the kernel management area 900a. Reference numeral 902 denotes a DMAC, and reference numeral 903 denotes a non-volatile storage device. The DMAC 902 reads the uncompressed data address 402 and the compressed data 403 in order from the beginning of the work area of the non-kernel management area 900b during the kernel initialization in step S804. When all the data is read, next, the uncompressed data 404a is read according to the uncompressed data address. As described above, the page of the non-compressed data 404a returns to the area excluding the work area and the non-kernel management area 900b, so that the work area and the kernel management area are not overwritten.

  When the DMAC specifies parameters (transfer source address, transfer destination address, data size) used for data transfer by the CPU, the DMAC transfers data from the nonvolatile storage device to the memory asynchronously with the CPU. Since the DMAC has a size that can be transferred at a time, it is necessary to designate a new parameter again by the CPU for each transfer of a specific size. Therefore, in the present embodiment, the transfer completion interrupt of the DMAC 102 is used to specify data to be read next and execute a new read. In addition, an interrupt is generated at regular intervals using a timer, and the CPU 101 confirms the reading status of the DMAC 102, and if reading is completed, designates data to be read next and executes a new reading. May be.

  The parallel reading at the time of kernel initialization by the DMAC 102 is continuously performed until the uncompressed data address 402, the compressed data 403, and the uncompressed data 404a are read, or until the compressed data is decompressed after the initialization of the kernel.

  FIG. 10 shows details of step S805, which is a flow of hibernation image restoration processing in the present embodiment. In step S1000, the CPU 101 stops the process scheduler, and in step S1001, the CPU 101 stops each device and restricts interrupts. In step S1002, the CPU 101 switches the virtual memory from the kernel PGD to the hibernation PGD. In step S1003, the CPU 101 switches the stack. In step S1004, the CPU 101 stops parallel reading by the DMAC 102. In step S1005, the CPU 101 and the DMAC 102 restore the memory. I do.

  In step S1002, the page conversion table is switched. In the x86 environment, the switching is completed by rewriting the value of the CPU register CR3 from the address of the kernel PGD to the address of the hibernation PGD. There are two reasons for this process. The first point is that the kernel PGD is a mapping that reflects memory limitations and is insufficient for accessing the decompression destination. Since the hibernation PGD is a mapping before the memory limit, it is possible to access all the expansion destinations by switching to this page conversion table. The second point is that the kernel PGD is rewritten during the memory restoration process. As described above, the hibernation PGD is secured in the hibernation processing area, so that it is not rewritten during the memory restoration process.

  FIG. 11 is a diagram showing an example of a virtual memory at the time of hibernation activation when the present embodiment is applied to an x86 environment. 1100 is a CPU register CR3, 1101 is a kernel PGD, 1102 is a hibernation PGD. Reference numeral 1103a denotes mapping information of the kernel management area where the memory is restricted. Reference numeral 1103b denotes mapping information of the kernel management area where the memory is not restricted. Reference numeral 1104 denotes mapping information of the work area. The CPU register CR3 1100 before step S1001 indicates the kernel PGD 1101, and the CPU register CR3 1100 indicates the hibernation PGD 1102 by step S1002.

  In step S1003 of FIG. 10, the stack usage destination is switched. This is because the contents of the conventional stack are rewritten during the memory restoration process. In addition, since the stack at the switching destination needs to be prevented from being overwritten, the end of the work area is designated. Note that the stack is restored in S1006.

  Further, in step S1004 in FIG. 10, the standby is performed until the DMAC 102 in operation is stopped. However, when the parallel reading by the DMAC 102 has already been completed, the standby may not be performed.

  Also, in step S1005 in FIG. 10, when all the uncompressed data address 402 and the compressed data 403 are not read, the reading is completed. Then, the compressed data is expanded for each page, and uncompressed data is read in parallel with the expansion. Since the interruption has already stopped, the completion of DMAC is sequentially checked in the loop processing for expanding each page. The data reading destination is the same as the parallel reading at the time of kernel initialization. The compressed page 703 is expanded according to the compressed page size 701 and the compressed page address 702. Since the compressed page address 702 indicates a region other than the work area, uncompressed compressed data is not overwritten. The above processing is repeated until both decompression of all compressed data and reading of all uncompressed data are completed.

  With the above processing, the memory is returned to the same state as that immediately after step S301 except for the hibernation processing area. After the memory is restored, the CPU register value is restored, each device information is restored, the interrupt is resumed, and the process scheduler is resumed by the processing of the CPU 101 to complete the hibernation activation. .

  As described above, in the present embodiment, when the system is restarted using the hibernation image, the compressed data is read in parallel with the initialization by the kernel, and the uncompressed data is read in parallel with the expansion. Compared with this method, the system can be restored at high speed.

  Note that the initialization data reading unit (first reading unit) 209 and the post-initialization data reading unit (second reading unit) 211 may be integrated, in which case the DMAC is configured integrally. It is preferable to do.

The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and the computer (or CPU, MPU, etc.) of the system or apparatus reads the computer. This is a process of reading and executing a possible program.

Claims (17)

Volatile memory,
Compression means for compressing at least a portion of data held in the volatile memory into compressed data;
A non-volatile memory that holds compressed data compressed by the compression means and area information including an address of an unused area of the volatile memory as a hibernation image;
In parallel with the kernel initialization performed using at least a part of the volatile memory, the compressed data held in the nonvolatile memory is converted into at least one of the unused areas based on the area information. Reading means to read
Decompression means for decompressing the compressed data read into the volatile memory;
An information processing apparatus comprising: an activation unit that activates a system based on data decompressed by the decompression unit.   The information according to claim 1, further comprising memory management means for allocating a kernel management area used for initialization of the kernel and a non-kernel management area not used for initialization of the kernel to the volatile memory. Processing equipment.   The information processing apparatus according to claim 1, further comprising a normal activation unit that performs normal activation when the hibernation image is not saved in the nonvolatile memory.   The information processing apparatus according to claim 1, further comprising a saving unit that saves the hibernation image in the nonvolatile memory.   The information processing apparatus according to claim 4, wherein the saving unit does not assign an area for storing the area information and an area indicated by the area information as an area for holding the hibernation image.   6. The information processing apparatus according to claim 4, wherein the saving unit saves a hibernation image of a file type independent of a file system in the nonvolatile memory.   The information processing apparatus according to claim 1, wherein the compression unit does not compress a part of the data in the volatile memory.   The information processing apparatus according to claim 2, wherein the memory management unit sets the size of the kernel management area to be equal to or larger than a size necessary for initialization of the kernel.   The information according to any one of claims 1 to 8, wherein the reading means uses DMAC to read the compressed data held in the nonvolatile memory into an area indicated by the area information. Processing equipment.   The decompression unit reads all the compressed data into the volatile memory when reading of all the compressed data held in the nonvolatile memory is not completed. The information processing apparatus according to any one of 9.   The information processing apparatus according to any one of claims 1 to 10, wherein the activation unit activates the system by restoring the volatile memory to a state before the hibernation image is generated. .   The system further comprises work area validation means for reading area information held in the nonvolatile memory into the volatile memory and securing a work area in the volatile memory based on the area information. Item 12. The information processing apparatus according to any one of Items 1 to 11.   13. The information according to claim 12, wherein the work area validation unit reads the area information into an area of the volatile memory in which the compressed data and the decompressed data of the compressed data are not written. Processing equipment.   The information processing apparatus according to claim 2, further comprising region information generation means for generating the region information.   The area information generation means does not include an area in use at the time of hibernation image generation, an area for storing the area information at startup, and an area allocated to the kernel management area at startup in the area indicated by the area information. The information processing apparatus according to claim 14, wherein the information processing apparatus is generated as described above. An information processing apparatus startup method comprising: a volatile memory; and a non-volatile memory that holds a hibernation image including area information and compressed data.
In parallel with the initialization of the kernel expanded in the volatile memory, the compressed data held in the nonvolatile memory is not used for the initialization of the kernel in the area of the volatile memory based on the area information. Initialization data reading process to read into the area,
A booting method comprising: a booting step of decompressing the compressed data read into the volatile memory after the kernel initialization and booting the system based on the decompressed data. A computer comprising: a volatile memory; and a non-volatile memory that holds a hibernation image including area information and compressed data.
In parallel with the initialization of the kernel expanded in the volatile memory, the compressed data held in the nonvolatile memory is not used for the initialization of the kernel in the area of the volatile memory based on the area information. Initialization data reading process to read into the area,
A program that, after initialization of the kernel, decompresses the compressed data read into the volatile memory, and executes a startup step of starting the system based on the decompressed data.

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