JP2014021821A - Peripheral device and host device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To seamlessly switch a communication speed between a host device of USB(Universal Serial Bus) 3.0 and a peripheral device connected to the host device to be used.SOLUTION: A peripheral device 120 is allowed to look like a special USB 3.0 hub to which a USB 3.0 peripheral device having similar functions in two DSP(Down Stream Port) and a USB 2.0 peripheral device are respectively connected with respect to a host device 110 of USB 3.0. This USB 3.0 hub is made different from a normal USB 3.0 hub in that those two DSP exclusively operate. The host device 110 switches the object of communication between the USB 3.0 peripheral device and the USB 2.0 peripheral device in accordance with the amounts of communication data.

Description

  The present invention relates to USB (Universal Serial Bus) communication, for example, communication with a peripheral device used in connection with a host device conforming to USB 3.0.

With respect to the USB communication system, technologies from various viewpoints have been proposed.
For example, Patent Document 1 discloses a technique for reducing power consumption in a USB 2.0 communication system. This technique switches to a transfer mode with a high transfer rate before starting to transfer more than a predetermined amount of data, and switches to a transfer mode with a low transfer rate after the end of the data transfer.

  Patent Document 2 discloses a technique for switching between a High-Speed connection and a Full-Speed connection in accordance with the amount of communication in a USB 2.0 communication system. This technique is also for reducing power consumption. For example, when status information is exchanged from a USB host device, a Full-Speed connection is maintained, and when a job is received from the USB host device, that is, the communication amount is low. In the case of increase, the Full-Speed connection is temporarily disconnected and reconnected with High-Speed.

JP-A-2005-208811 JP 2001-134186 A

  With the birth of the USB 3.0 standard, the USB communication mode has been added to the SS (Super Speed) mode in addition to the various modes defined by the USB 2.0 standard. In the SS mode, the communication speed is about 10 times that of the High-Speed mode, but the power consumption is also large.

  The USB 3.0 peripheral device and the USB 3.0 host device are normally connected in the SS mode. However, the amount of communication between the host device and the peripheral device is not always large. Therefore, in order to achieve both ensuring the communication speed and suppressing the power consumption, for example, the technology described in Patent Document 1 or Patent Document 2 is applied, and the connection between the host device and the peripheral device is made according to the amount of communication. Switching between SS connection and Non-SS connection (connection such as High-Speed other than SS connection) can be considered.

  However, such connection mode switching is realized by temporarily disconnecting an already established connection and reconnecting in another mode, which takes time. In this case, when communication such as periodic transfer such as isochronous transfer is performed, transfer is performed at a constant transfer speed and a constant cycle. Therefore, there is a possibility that the communication may fail due to the time required for switching the connection mode. is there.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  One embodiment relates to a communication method for a peripheral device used in connection with a USB 3.0 host device. In this communication method, the peripheral device establishes an SS connection and a Non-SS connection in parallel with the host device, and the host device itself is similar to two DSPs (Down Stream Port). It appears that the USB 3.0 peripheral device and the USB 2.0 peripheral device having the above functions are connected to each other.

  The present invention also includes a peripheral device to which the communication method is applied, a semiconductor integrated circuit for realizing the peripheral device, a program for causing the semiconductor integrated circuit to execute the communication method, a host device corresponding to the peripheral device, and the like. This aspect is effective.

  According to the above-described embodiment and each embodiment described later, it is possible to seamlessly switch the communication speed with the peripheral device connected to the USB 3.0 host device.

It is a figure which shows the USB communication system concerning one Embodiment. It is a flowchart which shows the process of the USB communication system shown in FIG. 3 is a timing chart showing an example of switching of communication speed in the USB communication system shown in FIG. 1.

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

  Further, the above-described program can be stored using various types of non-transitory computer readable media and supplied to a computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROM (Read Only Memory) CD-R, CD -R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  FIG. 1 shows a USB communication system 100 according to an embodiment. The USB communication system 100 includes a host device 110 and a peripheral device 120 connected via a USB cable 170.

The host device 110 and the USB cable 170 conform to the USB 3.0 standard.
The peripheral device 120 includes a host system 130 and a semiconductor integrated circuit 150 connected via a bus 140.

  The host system 130 performs processing of each layer above the protocol layer defined by the USB 3.0 standard. The CPU (Central Processing Unit) 132, the RAM (Random Access Memory) 134, and the ROM (Read Only Memory). 136 and a peripheral circuit 138.

  The ROM 136 stores various processing programs including a startup program and application programs, and the RAM 134 temporarily stores programs and data. Peripheral circuit 138 is typically provided in this type of device and provides inherent control. The CPU 132 loads the program stored in the ROM 136 into the RAM 134 and executes it, and sometimes cooperates with the peripheral circuit 138.

  The semiconductor integrated circuit 150 includes a USP (Up Stream Port) 160 for connection with the host device 110, an SS processing unit 200 that performs processing related to SS communication, and a Non-SS processing unit that performs processing related to Non-SS communication. 300.

  The SS processing unit 200 includes an SSP / L circuit 210 (P / L: Rhytical / Link) that handles SS link layer and physical layer processing, and an SS protocol circuit 220 that performs SS protocol layer processing.

  The SS protocol circuit 220 includes an SS hub circuit 230 and an SS peripheral device circuit 240 that process packets for the SS hub.

  The SS hub circuit 230 includes a data processing circuit 232 and an address determination circuit 234. The address determination circuit 234 stores a first address ADDR1 given by the host device 110 at the time of initialization described later. The data processing circuit 232 processes a packet for the SS hub, and is the same as a circuit for processing a packet for the SS hub provided in a normal USB 3.0 hub.

  The SS peripheral device circuit 240 includes a data processing circuit 242 and an address determination circuit 244. The address determination circuit 244 stores a third address ADDR3 given by the host device 110 at the time of initialization described later. The data processing circuit 242 is for processing a packet at the time of SS communication by a USB 3.0 peripheral device, and is similar to a circuit for processing a packet at the time of SS communication provided in a normal USB 3.0 peripheral device. .

  The Non-SS processing unit 300 includes a USB 2.0 P / L circuit 310 that handles USB 2.0 link layer and physical layer processing, and a USB 2.0 protocol circuit 320 that performs USB 2.0 protocol layer processing.

  The USB 2.0 protocol circuit 320 includes a USB 2.0 hub circuit 330 and a USB 2.0 peripheral device circuit 340 that process packets for a USB 2.0 hub.

  The USB 2.0 hub circuit 330 includes a data processing circuit 332 and an address determination circuit 334. The address determination circuit 334 stores a second address ADDR2 given by the host device 110 at the time of initialization described later. The data processing circuit 332 processes a packet for a USB 2.0 hub, and is the same as a circuit for processing a packet for a USB 2.0 hub provided in a normal USB 3.0 hub or USB 2.0 hub. .

  The USB 2.0 peripheral device circuit 340 includes a data processing circuit 342 and an address determination circuit 344. The address determination circuit 344 stores a fourth address ADDR4 given by the host device 110 at the time of initialization described later. The data processing circuit 342 is the same as a circuit that is provided in a normal USB 3.0 peripheral device or a normal USB 2.0 peripheral device and processes a packet during Non-SS communication.

  Note that the SS peripheral device circuit 240 and the USB 2.0 peripheral device circuit 340 correspond to the same type of peripheral device among the types of USB peripheral devices such as a USB camera and a USB speaker.

  Before a specific operation of the USB communication system 100, a data path in the USB communication system 100 of the present embodiment will be described. In the present embodiment, there are four data paths.

<First data path>
This data path is a data path when the host device 110 and the peripheral device 120 perform SS communication. The path is configured by the host system 130, the SS hub circuit 230, the SSP / L circuit 210, the USP 160, and the host device 110.

  At the time of transmission from the peripheral device 120 to the host device 110, the host system 130 outputs data to the SS hub circuit 230, and the data processing circuit 232 in the SS hub circuit 230 packetizes the data and sends it to the address determination circuit 234. A packet including the stored first address ADDR1 is transmitted to the host device 110 via the SSP / L circuit 210 and the USP 160.

  When receiving from the host device 110, the address determination circuit 234 in the SS hub circuit 230 determines that the address included in the packet received via the USP 160 and the SSP / L circuit 210 is the first address ADDR1. The packet is output to the data processing circuit 232, and the data processing circuit 232 processes the packet as a packet for the SS hub and outputs the processing result to the host system 130. Note that when the address included in the received packet is not the first address ADDR1, the address determination circuit 234 ignores the packet.

<Second data path>
This data path is also a data path when the host device 110 and the peripheral device 120 perform SS communication. The path includes the host system 130, the SS peripheral device circuit 240, the SSP / L circuit 210, the USP 160, and the host device 110.

  At the time of transmission from the peripheral device 120 to the host device 110, the host system 130 outputs data to the SS peripheral device circuit 240, and the data processing circuit 242 in the SS peripheral device circuit 240 performs packetization of the data, and an address determination circuit The packet including the third address ADDR3 stored in the H.244 is transmitted to the host apparatus 110 via the SSP / L circuit 210 and the USP 160.

  When receiving from the host device 110, the address determination circuit 244 in the SS peripheral device circuit 240 has the third address ADDR3 when the address included in the packet received via the USP 160 and the SSP / L circuit 210 is The packet is output to the data processing circuit 242, and the data processing circuit 242 processes the packet as a packet for the peripheral device and outputs the processing result to the host system 130. Note that when the address included in the received packet is not the third address ADDR3, the address determination circuit 244 ignores the packet.

<Third data path>
This data path is a data path when the host device 110 and the peripheral device 120 perform Non-SS communication. The path is configured by the host system 130, the USB 2.0 hub circuit 330, the USB 2.0 P / L circuit 310, the USP 160, and the host device 110.

  At the time of transmission from the peripheral device 120 to the host device 110, the host system 130 outputs data to the USB 2.0 hub circuit 330, and the data processing circuit 332 in the USB 2.0 hub circuit 330 performs packetization of the data, and addresses A packet including the second address ADDR2 stored in the determination circuit 334 is transmitted to the host device 110 via the USB 2.0P / L circuit 310 and the USP 160.

  When receiving from the host device 110, the address determination circuit 334 in the USB 2.0 hub circuit 330 receives the second address ADDR2 when the address included in the packet received via the USP 160 and the USB 2.0 P / L circuit 310 is the second address ADDR2. In addition, the packet is output to the data processing circuit 332, and the data processing circuit 332 processes the packet as a packet for the USB 2.0 hub and outputs the processing result to the host system 130. Note that when the address included in the received packet is not the second address ADDR2, the address determination circuit 244 ignores the packet.

<Fourth data path>
This data path is also a data path when the host device 110 and the peripheral device 120 perform Non-SS communication. The path is configured by the host system 130, the USB 2.0 peripheral device circuit 340, the USB 2.0 P / L circuit 310, the USP 160, and the host device 110.

  At the time of transmission from the peripheral device 120 to the host device 110, the host system 130 outputs data to the USB 2.0 peripheral device circuit 340, and the data processing circuit 342 in the USB 2.0 peripheral device circuit 340 performs packetization of the data. Then, the packet including the fourth address ADDR4 stored in the address determination circuit 344 is transmitted to the host device 110 via the USB 2.0P / L circuit 310 and the USP 160.

  When receiving from the host device 110, the address determination circuit 344 in the USB 2.0 peripheral device circuit 340 includes the address included in the packet received via the USP 160 and the USB 2.0P / L circuit 310 as the fourth address ADDR4. Sometimes, the packet is output to the data processing circuit 342, and the data processing circuit 342 processes the packet as a packet for the peripheral device and outputs the processing result to the host system 130. Note that when the address included in the received packet is not the fourth address ADDR4, the address determination circuit 344 ignores the packet.

The operation of the USB communication system 100 will be described in detail with reference to FIG.
At the time of connection, first, link-up is performed between the peripheral device 120 and the host device 110 (S100).

  Specifically, the SS connection is established between the peripheral device 120 and the host device 110 via the SSP / L circuit 210. This is performed according to a procedure in which the host device 110 turns on VBUS (not shown), the SSP / L circuit 210 detects it and turns on Rx Termination as defined in the standard.

  In parallel, a Non-SS connection is established between the peripheral device 120 and the host device 110 via the USB 2.0 P / L circuit 310. This is also performed by a procedure in which the USB 2.0 P / L circuit 310 detects when the host device 110 turns on VBUS and pulls up D + or D− of USB 2.0 as defined in the standard. .

  After linking up, the host apparatus 110 gives two addresses (first address ADDR1 for SS hub and second address ADDR2 for USB 2.0 hub) to the peripheral device 120 (S102). The third address ADDR3 is assigned to the USB 3.0 peripheral device, and the fourth address is assigned to the USB 2.0 peripheral device (S104). This is also an operation as defined in the standard.

  Then, the peripheral device 120 notifies the host device 110 that it is a special USB 3.0 hub (S106). This notification is made by, for example, the SS protocol circuit 220 or the USB 2.0 protocol circuit 320 in response to a get descriptor device (Get Descriptor-Device) command from the host device 110.

  By the notification from the peripheral device 120, the host device 110 has a USB 3.0 peripheral in which the peripheral device 120 is a USB 3.0 hub, has two DSPs (Down Stream Port), and the two DSPs have similar functions. Recognize that the device and the USB 2.0 peripheral device are connected. Furthermore, the host device 110 recognizes that the two DSPs operate exclusively as a special feature of the USB 3.0 hub.

  That is, by the notification from the peripheral device 120 in step S100, the host apparatus 110 converts the peripheral device 120 into one USB3.0 hub, one USB3.0 peripheral device connected to the USB3.0 hub, and one A peripheral device of the same type in which the two peripheral devices operate exclusively, for example, a device that is a USB camera.

  Note that the host device 110 recognizes that the two DSPs operate exclusively, that is, the two peripheral devices connected to the two DSPs are the same type of peripheral devices operating exclusively. This is an application implemented in a computer that carries the host device 110.

  Steps S110 and after show processing at the time of communication between the peripheral device 120 and the host device 110.

  When there is no communication data (S110: No), the host device 110 performs control so that both the SS processing unit 200 and the Non-SS processing unit 300 are in a low power state (Low Power State) (S112: Yes, Or S112: No, S114). The low power state of the SS processing unit 200 is any one of U1, U2, and U3 defined by the USB 3.0 standard. The low power state of the Non-SS processing unit 300 is “sleep” (L1) and “suspend” (L2) defined by the USB 2.0 standard.

  On the other hand, when there is communication data (S110: Yes), the host device 110, when the amount of communication data exceeds the threshold T (S120: Yes), if the SS processing unit 200 is not in the low power state (S120: Yes) S122: No), the SS processing unit 200 is left as it is, and if the SS processing unit 200 is in the low power state, the SS processing unit 200 is returned from the low power state to the active state “U0” (S122: Yes, S124). . If the Non-SS processing unit 300 is in a low power state (S126: Yes), the Non-SS processing unit 300 is left as it is. If the Non-SS processing unit 300 is not in a low power state, the Non-SS processing is performed. The unit 300 is changed to the low power state (S126: No, S128). Then, the host device 110 performs SS communication with the peripheral device 120 and transfers data via the SSP / L circuit 210 and the SS hub circuit 230 (S130).

  If there is communication data but the amount of communication data is equal to or less than the threshold value T (S110: Yes, S120: Yes), the host device 110 determines that the Non-SS processing unit 300 is not in a low power state ( S142: No), leaving the Non-SS processing unit 300 as it is, and if the Non-SS processing unit 300 is in the low power state, the Non-SS processing unit 300 is returned from the low power state to the active state “L0” ( S140: Yes, S142). If the SS processing unit 200 is in the low power state (S144: Yes), the SS processing unit 200 is left as it is, and if the SS processing unit 200 is not in the low power state, the SS processing unit 200 is shifted to the low power state. (S144: No, S146). Then, the host device 110 performs Non-SS communication with the peripheral device 120 and transfers data via the USB 2.0 P / L circuit 310 and the USB 2.0 hub circuit 330 (S148).

  That is, the host device 110 performs non-non-operation when the amount of communication data is equal to or less than the threshold T during SS communication, that is, communication with the SS P / L circuit 210 and the SS peripheral device circuit 240. The SS processing unit 300 is returned from the low power state and switched to non-SS communication, that is, communication with the USB 2.0 P / L circuit 310 and the USB 2.0 peripheral device circuit 340. At the same time, the SS processing unit 200 is shifted to the low power state.

  Further, when the host device 110 performs non-SS communication, that is, communication with the USB 2.0 P / L circuit 310 and the USB 2.0 peripheral device circuit 340, the amount of communication data exceeds the threshold T. In addition, the SS processing unit 200 is returned from the low power state and switched to SS communication, that is, communication with the SSP / L circuit 210 and the SS peripheral device circuit 240. At the same time, the non-SS processing unit 300 is shifted to the low power state.

  FIG. 3 is a diagram illustrating an example of a timing chart when the USB communication system 100 switches from Non-SS communication to SS communication.

  From time t0 to time t1, the amount of communication data is less than the threshold T, and the host device 110 is performing Non-SS communication with the Non-SS processing unit 300 of the peripheral device 120. The SS processing unit 200 of the peripheral device 120 is In a low power state.

Time t1 is a time when the communication data amount exceeds the threshold T.
Therefore, from time t1 to time t2, the host device 110 returns the SS processing unit 200 of the peripheral device 120 from the low power state to the active state.

  At time t2, the host device 110 switches the Non-SS communication to the SS communication and controls the Non-SS processing unit 300 of the peripheral device 120 that is not used for the SS communication so as to transition to the low power state.

  From time t2 to time t3, the Non-SS processing unit 300 transitions to the low power state. During this time, the host device 110 performs SS communication with the SS processing unit 200 of the peripheral device 120.

  After time t3, the Non-SS processing unit 300 is in a low power state, and the SS processing unit 200 continues to perform SS communication.

  As described above, in the USB communication system 100, the peripheral device 120 establishes the SS connection and the Non-SS connection in parallel with the host device 110, and the USB device 3.0 and the USB 2.0 peripheral device itself. Is notified to the host device 110 that the USB 3.0 hub is connected. Therefore, while performing Non-SS communication with the Non-SS processing unit 300 of the peripheral device 120 via the USB 3.0 hub, the SS processing unit 200 of the peripheral device 120 is returned from the low power state and seamlessly SS. Switch to communication. Similarly, when switching from SS communication to Non-SS communication, while performing SS communication with the SS processing unit 200 of the peripheral device 120 via the USB 3.0 hub, the Non-SS processing unit 300 of the peripheral device 120 is also used. Can be restored from the low power state and seamlessly switched to Non-SS communication.

  As a result, even for a USB peripheral device that uses periodic transfer such as isochronous transfer, power saving can be achieved without communication failure.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

1 First address ADDR
2 Second address ADDR
3 Third address ADDR
4 Fourth address ADDR
100 USB communication system 110 Host device 120 Peripheral device 130 Host system 132 CPU
134 RAM
136 ROM
138 Peripheral circuit 140 Bus 150 Semiconductor integrated circuit 160 USP
170 USB cable 200 SS processing unit 210 SS P / L circuit 220 SS protocol circuit 230 SS hub circuit 232 data processing circuit 234 address determination circuit 240 SS peripheral device circuit 242 data processing circuit 244 address determination circuit 300 Non-SS processing unit 310 USB2 0P / L circuit 320 USB 2.0 protocol circuit 330 USB 2.0 hub circuit 332 Data processing circuit 334 Address determination circuit 340 USB 2.0 peripheral device circuit 342 Data processing circuit 344 Address determination circuit

Claims (3)

A peripheral device used by connecting to a USB (Universal Serial Bus) 3.0 host device,
An SS processing unit for performing processing related to SS (Super Speed) communication;
A Non-SS processing unit that performs processing related to Non-SS communication;
The SS processing unit
SSP / L circuit responsible for SS link layer and physical layer processing;
An SS hub circuit for processing packets for the SS hub;
An SS peripheral device circuit for processing a packet during SS communication provided in a USB 3.0 peripheral device;
The Non-SS processing unit
USB 2.0 P / L circuit responsible for USB 2.0 link layer and physical layer processing;
A USB 2.0 hub circuit that processes packets for a USB 2.0 hub;
A USB 2.0 peripheral device circuit for processing a packet during Non-SS communication provided in a USB 3.0 or USB 2.0 peripheral device;
When connecting to the host device, the SSP / L circuit and the USB 2.0P / L circuit establish SS connection and Non-SS connection with the host device, respectively, and two DSPs (Down) A USB 3.0 hub to which a USB 3.0 peripheral device and a USB 2.0 peripheral device having a similar function are connected to the two DSPs.
Peripheral device. When the SS hub circuit, the USB 2.0 hub circuit, the SS peripheral device circuit, and the USB 2.0 peripheral device circuit are connected to the host device, the host device causes the first SS hub circuit to , A second address for a USB 2.0 hub, a third address for a USB 3.0 peripheral device, and a fourth address for a USB 2.0 peripheral device, respectively.
The peripheral device according to claim 1. A USB (Universal Serial Bus) 3.0 host device,
A special USB3.0 hub that has two DSPs (Down Stream Port) that operate exclusively, and a USB3.0 peripheral device and a USB2.0 peripheral device that have the same type of function connected to the two DSPs. Corresponding to
Upon connection, an SS (Super Speed) connection and a Non-SS connection are established with the special USB 3.0 hub, and a first address for the SS hub and a second address for the USB 2.0 hub are established. And a third address for a USB 3.0 peripheral device and a fourth address for a USB 2.0 peripheral device,
When performing SS communication with the USB 3.0 peripheral device via the SS hub in the USB 3.0 hub, when the communication amount becomes a predetermined threshold value or less, the USB 2.0 hub in the USB 3.0 hub The USB 2.0 peripheral device is returned from the low power state, the communication target is switched to the USB 2.0 peripheral device, and the SS hub and the USB 3.0 peripheral device in the USB 3.0 hub are shifted to the low power state. ,
When communicating with the USB 2.0 peripheral device via the USB 2.0 hub, when the communication amount exceeds the predetermined threshold, the SS hub and the USB 3.0 peripheral in the USB 3.0 hub The device is returned from the low power state, the communication target is switched to the USB 3.0 peripheral device, and the USB 2.0 hub and the USB 2.0 peripheral device in the USB 3.0 hub are transitioned to the low power state.
Host device.

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