JP2013219247A - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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Abstract
【解決手段】電子部品1の端子は、複数の金属層を有しており、且つ、複数の金属層は最も外側に配置される最表層である第3金属層203及び該最表層よりも下層側に位置する第2層である第1金属層201の少なくとも2層を有し、最表層は、第2層及び配線層よりもイオン化傾向が小さい。
【選択図】図11
Description
上述した本実施形態は、電子部品を含む構成であるけれども、本発明が適用される実施形態はこれに限られるものではない。具体的には、イオン化傾向の小さい金属を配置する効果は、電子部品を構成する端子電極のみに限定されるものではない。具体的には、図10に示す状態において、ビア導体42よりもイオン化傾向の小さい金属を、ビア導体42の上面及び側面に設けることで、隣接するビア導体42間の絶縁性向上に資することができる。特に、完成状態における配線基板の最表層電極よりも、吸湿する絶縁体で覆われている内側層電極の方がより絶縁性向上の効果を期待できる。
2:端子電極
10:基体
11:絶縁層
12:ビア導体
13:配線層
14:絶縁層
20:基板
31:絶縁層
32:導体層
33:導体マスク
41:導体層
42:ビア導体
43:配線層
100:電子部品内蔵基板
201:第1金属層(第2層)、
202:第2金属層(エッチストッパ層)
203:第3金属層(最表層)
V:ビアホール(開口)
P1:機能層
P2:パッシベーション膜
Claims (9)
- 基板と、
前記基板上に形成された配線層又は電子部品の端子と、を備える配線基板であって、
前記端子又は前記配線層は、複数の金属層を有しており、前記複数の金属層は絶縁層で覆われ、且つ、前記複数の金属層は最も外側に配置される最表層及び該最表層よりも下層側に位置する第2層の少なくとも2層を有し、前記最表層は、前記第2層及び前記端子又は前記配線層に繋がる第2配線層よりもイオン化傾向が小さいことを特徴とする配線基板。 - 前記最表層は、Pd、Au、NiB合金、及びNiP合金の少なくとも一種を含むものである、請求項1記載の配線基板。
- 前記最表層がPdを含み、前記第2層がCuを含むものであって、前記最表層と前記第2層とが直接当接するように配置され、
前記絶縁層と接するように前記最表層が形成されており、前記第2配線層と接する部位においては前記最表層が形成されておらず、
前記第2配線層が前記第2層と直接接続され、前記最表層を介さずに電気的に接続している、請求項2に記載の配線基板。 - 前記最表層がNiB合金を含み、前記第2層がCuを含むものであって、前記最表層と前記第2層とが直接当接するように配置されている、請求項2に記載の配線基板。
- 配線層を基板上に形成する形成工程と、
端子又は前記配線層を覆うように絶縁層を形成する絶縁層形成工程と、
前記端子又は前記配線層の一部が露出するように前記絶縁層に開口を形成する開口形成工程と、
前記端子又は前記配線層と電気的に接続するように少なくとも前記開口の内部に第2配線層を形成する配線層形成工程と、を備える配線基板の製造方法であって、
前記端子又は前記配線層は、複数の金属層を有しており、且つ、前記複数の金属層は最も外側に配置される最表層及び該最表層よりも下層側に位置する第2層の少なくとも2層を有し、前記最表層は、前記第2層及び前記第2配線層よりもイオン化傾向が小さい、配線基板の製造方法。 - 前記最表層は、Pd、Au、NiB合金、及びNiP合金の少なくとも一種を含むものである、請求項5記載の配線基板の製造方法。
- 前記最表層がPdを含み、前記第2層がCuを含むものであって、前記最表層と前記第2層とが直接当接するように配置され、
前記絶縁層と接するように前記最表層が形成されており、前記第2配線層と接する部位においては前記最表層が形成されておらず、
前記第2配線層が前記第2層と直接接続され、前記最表層を介さずに電気的に接続されている、請求項6に記載の配線基板の製造方法。 - 前記最表層がNiB合金を含み、前記第2層がCuを含むものであって、前記最表層と前記第2層とが直接当接するように配置されている、請求項6に記載の配線基板の製造方法。
- 前記開口形成工程においては、ウェットブラスト処理により前記開口を形成する、請求項5〜8のいずれか1項に記載の配線基板の製造方法。
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JP2021019169A (ja) * | 2019-07-24 | 2021-02-15 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
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JPH1154919A (ja) * | 1997-08-04 | 1999-02-26 | Toagosei Co Ltd | 多層プリント配線板およびその製造方法 |
JP2003133737A (ja) * | 2001-10-29 | 2003-05-09 | Kyocera Corp | 多層配線基板及びその製造方法 |
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JP2007080858A (ja) * | 2005-09-09 | 2007-03-29 | Fujikura Ltd | 多層プリント配線板及びその製造方法 |
JP2008166479A (ja) * | 2006-12-28 | 2008-07-17 | Kobe Steel Ltd | 配線基板、および、配線の形成方法 |
JP2009516388A (ja) * | 2005-11-18 | 2009-04-16 | レプリソールス テクノロジーズ アーベー | 多層構造の形成方法 |
JP2010177592A (ja) * | 2009-01-30 | 2010-08-12 | Tdk Corp | 電子部品内蔵基板、その製造方法、及びその検査方法 |
JP2011003884A (ja) * | 2009-05-20 | 2011-01-06 | Fujitsu Ltd | 回路基板及びその製造方法 |
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JPS61142438U (ja) * | 1985-02-25 | 1986-09-03 | ||
JPH1154919A (ja) * | 1997-08-04 | 1999-02-26 | Toagosei Co Ltd | 多層プリント配線板およびその製造方法 |
JP2003133737A (ja) * | 2001-10-29 | 2003-05-09 | Kyocera Corp | 多層配線基板及びその製造方法 |
JP2006086341A (ja) * | 2004-09-16 | 2006-03-30 | Tdk Corp | 多層基板及びその製造方法 |
JP2007080858A (ja) * | 2005-09-09 | 2007-03-29 | Fujikura Ltd | 多層プリント配線板及びその製造方法 |
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JP2008166479A (ja) * | 2006-12-28 | 2008-07-17 | Kobe Steel Ltd | 配線基板、および、配線の形成方法 |
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JP2011003884A (ja) * | 2009-05-20 | 2011-01-06 | Fujitsu Ltd | 回路基板及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2021019169A (ja) * | 2019-07-24 | 2021-02-15 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
JP7363158B2 (ja) | 2019-07-24 | 2023-10-18 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
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