JP2013182456A - Automobile electronic controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an automobile electronic controller that can shorten a time required for writing a plurality of pieces of data transmitted from an outside collectively to a nonvolatile memory.SOLUTION: The automobile electronic controller is provided with the nonvolatile memory of a writing size of 256 bytes, and is configured so as to gather two pieces of sub-data of 128 bytes transmitted from the outside and write the two pieces thereof collectively in the nonvolatile memory. Each time the sub-data is received, a status signal indicative of a verification result of writing is configured so as to be output to the outside, and when the two pieces of sub-data are gathered and right before the writing, a status signal indicative of a verification result of previous writing is configured so as to be output as the status signal. During a period until two pieces of sub-data are gathered, a provisional status signal is configured so as to be output to the outside as the status signal, and in parallel with the writing in the nonvolatile memory, sub-data waiting for next writing is configured so as to be received.

Description

  The present invention relates to an automotive electronic control device that includes a nonvolatile memory capable of electrically erasing and writing data, and writes data transferred from the outside to the nonvolatile memory.

  In Patent Document 1, when the size of the divided data transferred from the outside is half or less of the write size of the nonvolatile memory, the transferred divided data is temporarily stored, and the plurality of divided data are collected together. An automotive electronic control device is disclosed in which the writing size is written in a non-volatile memory at once.

JP 2011-248558 A

  By the way, when writing a plurality of divided data transferred from the outside to the non-volatile memory, a temporary end response is output every time the divided data is received until a plurality of divided data are prepared, Requests transfer of divided data, writes the divided data transferred in response to the request to the nonvolatile memory, outputs an end response to the outside after the writing is completed, and The divided data will be transferred.

However, when division data reception processing and division data writing processing are performed in time series without overlapping, there is a problem that it takes time to complete data writing to the nonvolatile memory. .
If the verification result of the actual writing process is not output to the outside, the transfer of the next divided data cannot be received. Therefore, if the verification result of the writing process is transmitted to the outside immediately after the writing process, the writing process There is a problem that a time lag occurs between completion and reception of the next divided data, and the processing time becomes long.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an automotive electronic control device capable of reducing the time required for processing a plurality of pieces of divided data transferred from the outside and writing them into a nonvolatile memory. To do.

Therefore, the automotive electronic control device according to the present invention includes a nonvolatile memory capable of electrically erasing and writing data,
When the write size data of the non-volatile memory is transferred from outside to be divided into a plurality of divided data, and when a plurality of divided data for the write size is prepared, the plurality of divided data are collected together into the non-volatile memory. While writing to
Whenever the divided data is received, a status signal indicating a verification result of writing is output to the outside, and when a plurality of divided data for the writing size are ready and immediately before the next writing, the status signal is A status signal indicating the result of verifying the previous writing is output, and a temporary status signal is output to the outside as the status signal until a plurality of divided data for the writing size is prepared,
In parallel with the writing to the nonvolatile memory, the divided data for the next writing is received.

  According to the above invention, when the data of the write size of the nonvolatile memory is transferred to the plurality of divided data from the outside, the divided data receiving process and the process of collectively writing the plurality of divided data to the nonvolatile memory Can be performed in parallel to reduce the time required for the writing process.

It is explanatory drawing of the ECU manufacturing process and application program writing process in embodiment of this invention. It is a block diagram of ECU and writing tool in embodiment of this invention. It is a figure which shows the sequence of the transfer and write-in process of an application program in embodiment of this invention. It is a flowchart which shows the procedure of the transfer process of the divided data of the writing tool in embodiment of this invention. It is a flowchart which shows the procedure of the write-in process of the division data of ECU in embodiment of this invention. It is a figure which shows the sequence of the transfer and write-in process of an application program in embodiment of this invention. It is a figure which shows the sequence of the transfer and write-in process of an application program in embodiment of this invention. It is a figure shown with the flowchart which shows the procedure of the transfer process of the division | segmentation data of the writing tool in embodiment of this invention. It is a flowchart which shows the procedure of the write-in process of the division data of ECU in embodiment of this invention. It is a flowchart which shows the procedure of the write-in process of the division data of ECU in embodiment of this invention.

Embodiments of the present invention will be described below.
FIG. 1 shows a manufacturing process 10 of an ECU (Electronic Control Unit) 100 that is an electronic control device for an automobile mounted on an automobile and controls an in-vehicle apparatus such as an engine fuel injection device, an automatic transmission, and various pumps, The application program writing process 20 with respect to ECU100 is shown.
The ECU 100 includes a flash ROM (Read-Only Memory) 110 as an example of a nonvolatile memory capable of electrically erasing and writing data, and controls the in-vehicle device by a control program stored in the flash ROM 110.

In the manufacturing process 10, a hardware inspection program is executed on the flash ROM 110 of the ECU 100, and a program for executing writing of an application program is written in a later process to perform hardware inspection. Note that the manufacturing process 10 is a part of work performed by a supplier of the ECU 100, for example.
In the application program writing step 20, an application program corresponding to the vehicle type on which the ECU 100 is mounted is written into the flash ROM 110 of the ECU 100 by using an external writing tool 200.

  Thereby, ECU100 supplied from the manufacturing process 10 becomes a specification adapted to a specific vehicle type. In a later inspection process, it is inspected whether an application program corresponding to the automobile is written in the flash ROM 110 of the ECU 100 assembled in the automobile. The application program writing process 20 is an operation performed in association with an ECU assembly process in an automobile assembly factory, for example.

Next, the configuration of the ECU 100 and the writing tool 200 will be described with reference to FIG.
The ECU 100 includes a flash ROM (flash memory) 110 that is a nonvolatile memory, a microcomputer 120, a RAM (Random Access Memory) 130 that is a volatile memory, a communication circuit 140, and the like.
The writing tool 200 is detachably connected to the ECU 100 via a communication line 300 such as a CAN (Controller Area Network).

The microcomputer 120 includes a CPU, a cache memory, and the like, and executes various programs stored in the flash ROM 110 and the RAM 130.
A first buffer area 133 and a second buffer area 134 are set in the RAM 130. The first buffer area 133 and the second buffer area 134 are used for temporarily storing divided data when data is written to the flash ROM 110.
Note that, instead of the first buffer area 133 and the second buffer area 134 set in the RAM 130, a first buffer memory and a second buffer memory can be provided separately from the flash ROM 110 and the RAM 130. That is, the buffer in the present application is a storage device or storage area that temporarily stores data.

The writing tool 200 includes a storage 210 that is a hard disk, for example, and a communication circuit 240. The writing tool 200 includes a terminal such as a personal computer and a device for connecting to the ECU 100, for example, and an operator operating the writing tool 200 can interactively give instructions to the writing tool 200.
The writing tool 200 transfers divided data such as an application program stored in the storage 210 to the ECU 100.

Here, the flash ROM 110 of the ECU 100 has a write size of 256 bytes, and data can be written with 256 bytes as one block for a block from which data has been erased.
In the flash ROM 110, the size of the erase block is larger than the size of the write block, and erasure is performed in batches in units of a plurality of write blocks (for example, 64). In the flash ROM 110, when data is erased for each erase block, all bytes of a plurality of write blocks constituting the erase block are replaced with FFs. In other words, the flash ROM 110 cannot perform a process of erasing data for only one writing block and writing data for one writing block that has been erased.
In the present embodiment, the flash ROM 110 has a specification (element characteristics) in which each byte is replaced with FF by data erasure, but can be in a specification in which each byte is replaced by 00 by data erasure. The replacement data is not limited to FF.
On the other hand, the writing tool 200 sets 128 bytes, which is half the writing size of the flash ROM 110, as the size of the divided data to be transferred.

Next, the writing process of the application program to the flash ROM 110 by the writing tool 200 will be described with reference to FIG.
The writing tool 200 encodes the 128-byte divided data (1) read from the storage 210 and transfers it to the ECU 100 via the communication line 300 together with address information and the like.
The microcomputer 120 of the ECU 100 that has received the divided data (1) decodes the divided data (1), and temporarily stores the decoded divided data (1) in a buffer (buffer area of the RAM 130).

Next, the microcomputer 120 returns a temporary write end response as a status signal indicating the write verification result (and the verification result of the received data) to the writing tool 200, and requests transfer of the next divided data. To do.
Here, the provisional write end response is a signal output from the microcomputer 120 in order to transfer the next divided data from the writing tool 200 although the data writing to the flash ROM 110 is not actually finished. If there is no problem with the received data, the microcomputer 120 recognizes that the data is correctly transferred and the writing is correctly performed even if the writing is not actually performed. The writing end response (OK response) is transmitted to the writing tool 200.

That is, the writing tool 200 is set to transfer the next divided data after confirming the completion of writing the 128-byte divided data every time the 128-byte divided data is transferred. For this reason, if the microcomputer 120 writes data to the flash ROM 110 with 128 bytes as one block, by sending a “write end response” to the writing tool 200 when the writing is actually finished, the 128 bytes of data can be obtained. As a unit, data can be transmitted and written sequentially.
However, as described above, the flash ROM 110 is a memory in which data can be written with 256 bytes as one block. Therefore, when data is actually written when 128-byte divided data is received, the flash ROM 110 has 256 bytes. 128 bytes of data will be written to the block.

Therefore, the microcomputer 120 combines the two 128-byte data (divided data) transferred by the writing tool 200 in two times into one into 256-byte divided data, and the two 128-byte data are batched. Thus, the data is written in the flash ROM 24.
Thus, data such as an application program can be written to the flash ROM 24 capable of writing data with 256 bytes as one block by using the writing tool 200 that transfers divided data in units of 128 bytes.

  However, unless the “write end response” is transmitted from the microcomputer 120, the writing tool 200 does not transfer the next divided data. For this reason, when the first 128-byte data of the two-byte 128-byte data is received (until the two are collected), the next 128-byte data is transferred although no actual writing is performed. Therefore, a “write end response” is transmitted to the writing tool 200. As described above, the “write end response” that is transmitted to transfer the next 128-byte data and is not actually finished is referred to as a “temporary write end response” in this embodiment. And

If the microcomputer 120 transmits a “temporary write end response”, the writing tool 200 operates in the same manner as the case where the flash ROM 110 that writes data with 128 bytes as one block is written, and as a result, Data can be written to the flash ROM 110 capable of writing data with 256 bytes as one block.
It should be noted that the “writing end response” transmitted when the writing is actually ended and the “temporary writing end response” transmitted to transmit the next 128-byte data are the same signals received by the writing tool 200. It is. Therefore, the writing tool 200 does not distinguish between the actual writing end and the provisional (false) writing end, but the microcomputer 120 transmits the “writing end response” transmitted when the microcomputer 120 is not actually writing. For the sake of explanation, this is referred to as a “provisional write end response”, and is distinguished from a “write end response” that is transmitted when writing is actually ended.

When the microcomputer 120 returns a provisional write end response to the writing tool 200 and makes a transfer request for the next divided data, the writing tool 200 reads the 128-byte divided data (2) following the 128-byte data transferred last time. The encoded divided data (2) is transferred to the ECU 100 via the communication line 300.
The microcomputer 120 that has received the divided data (2) decodes the divided data (2), and temporarily stores the decoded divided data (2) in a buffer.

As a result, 256-byte write data composed of the divided data (1) and the divided data (2) is stored in the buffer. In other words, two pieces of divided data corresponding to 256 bytes corresponding to the writing size are prepared.
When the microcomputer 120 receives the second divided data constituting the 256-byte write data, the microcomputer 120 sends a status signal (response) indicating the verification result when the 256-byte data was written to the flash ROM 110 last time. It is set to output. However, since there is no previous write here, if the divided data (2) is correctly received, as in the case of receiving the first 128-byte divided data (1), a temporary write end response is received. Is output.

Then, after outputting the provisional write end response, the microcomputer 120 collects the divided data (1) and the divided data (2) and writes them together in the flash ROM 110.
On the other hand, after transmitting the divided data (2), the writing tool 200 that has received the (temporary) write end response performs a transfer process of the subsequent divided data (3) and receives the divided data (3) from the microcomputer 120 that has received the divided data (3). The temporary write end response is output to the writing tool 200, and based on this response, the divided data (4) is output from the writing tool 200, and data transfer and storage processing for the next writing is performed. The

The division data (3) and the division data (4) are stored in a buffer area different from the buffer area in which the division data (1) and the division data (2) are saved.
In parallel with the transfer and storage processing of the above-mentioned divided data (3) and divided data (4), the 256-byte data including the previously stored divided data (1) and divided data (2) is batched. Thus, the process of writing to the flash ROM 110 and the process of verifying the result of the write process are performed.

As described above, when the divided data transfer / storage process and the writing process are performed in parallel, the time required for the writing process can be reduced.
For example, the microcomputer 120 that has received the divided data (1) and the divided data (2) performs a process of writing the divided data (1) and the divided data (2) to the flash ROM 110, and verifies the writing after the writing is completed. When the next divided data (3) is transferred by transmitting the result to the writing tool 200, the data from the writing tool 200 to the microcomputer 120 (ECU 100) is written during the writing process. Cannot be transferred, and the time required for the writing process becomes long.

On the other hand, when the divided data (3) and the divided data (4) are transferred and stored in preparation for the next writing while the divided data (1) and the divided data (2) are written, the writing process is performed. Can be shortened.
Here, when the result of verifying the writing of the divided data (1) and the divided data (2) is transmitted to the writing tool 200, the above parallel processing is performed when the divided data (3) is transferred. become unable.

Therefore, as described above, when the second divided data is received, in other words, when the end of the previous writing is expected and the preparation for the next writing is completed, the 256-byte data for the flash ROM 110 is previously stored. A status signal (response) indicating the verification result when writing is performed is output.
Therefore, the result of verifying the writing of the divided data (1) and the divided data (2) is that after the microcomputer 120 receives the divided data (4) and the divided data (3) and the divided data (4). Sent to writing tool 200 before starting writing.

The writing tool 200 that has received the write end response as a result of verifying the writing of the divided data (1) and the divided data (2) transfers the divided data (5) to the microcomputer 120, while parallel to the transfer processing. The microcomputer 120 writes the divided data (3) and the divided data (4) to the flash ROM 110. When the microcomputer 120 receives the divided data (6), the microcomputer 120 transmits a write end response as a result of verifying the writing of the divided data (3) and the divided data (4) to the writing tool 200. .
Thereafter, all the data of the application program is written in the flash ROM 110 by repeating the above processing.

The flowchart of FIG. 4 shows the flow of processing of the writing tool 200 in the writing processing sequence illustrated in FIG.
First, in step S501, when starting data transfer, the ECU 100 (microcomputer 120) is notified of transfer start.
In the next step S502, the first divided data is transferred.

Thereafter, in step S503, it is determined whether or not there is a write end response from the ECU 100 (microcomputer 120). Every time the write end response is received, the process proceeds to step S504, and the next divided data is sequentially sent to the ECU 100 (microcomputer 120). ).
Note that the writing tool 200 performs a retransfer process of divided data in response to a response from the ECU 100 (microcomputer 120) notifying the abnormality of the transfer data and the writing abnormality.

The flowchart of FIG. 5 shows the flow of processing of the ECU 100 (microcomputer 120) in the write processing sequence illustrated in FIG.
In step S601, it is determined whether or not the divided data has been transferred from the writing tool 200. When the divided data is transferred, the process proceeds to step S602, and the transferred divided data is stored in the buffer.

In step S603, it is determined based on the address information whether the divided data transferred this time is the second divided data to be written together with the previously transferred divided data.
If the divided data transferred this time is the first, not the second, and it is necessary to write together with the divided data transferred later, in other words, the divided data required for writing is If not, the process proceeds to step S604, and a temporary write end response is output to the writing tool 200 to request transfer of the next divided data.

On the other hand, when the divided data transferred this time is the second and writing can be performed together with the previously transferred divided data, in other words, when the divided data necessary for writing is prepared, the process proceeds to step S605. Then, a status signal indicating the result of verifying the previous writing is output to the writing tool 200.
Here, when the previous writing is normally performed and a write end response is output to the writing tool 200 as a status signal, the next divided data is transferred from the writing tool 200. .

  When the status signal is output in step S605, the process returns to step S601 in preparation for the transfer of the next divided data, and the process proceeds to step S606, where the previously transferred divided data and the currently transferred divided data are combined into the flash ROM 110. Are written in a batch and a process for verifying the writing result is performed. Thereby, the writing of the divided data to the flash ROM 110 and the transfer of the divided data in preparation for the next writing are performed in parallel.

By the way, in the application program stored in the storage 210 of the writing tool 200, if each byte of one block of 128 bytes is FF, transferring such data wastes processing time. End up. Therefore, the writing tool 200 can be set not to transfer the data of the block when one block of 128 bytes is all FF.
The case where one block of 128 bytes is all FF is the case where the data content is the same as that at the time of data erasure and the data content does not change even after writing. For example, when each byte is replaced with 00 by data erasure. When one block of 128 bytes is all 00, the data of the block is not transferred. That is, whether or not to perform data transfer depends on data at the time of erasing that differs depending on the specifications (element characteristics) of the flash ROM 110. When data is erased and replaced with FF, one block that is all FF does not transfer When the block is replaced with 00 by erasing data, one block which is all 00 becomes a block which is not transferred. Therefore, the blocks that are not transferred from the writing tool 200 are not limited to FF blocks.
In this case, the ECU 100 (microcomputer 120) performs the writing process as shown in FIG. 6 so that the transfer of the divided data and the data writing can be performed in parallel as described above even if a block that is not transferred occurs. I do.

In FIG. 6, when divided data (5), which is the 128-byte divided data corresponding to the first one, is transferred from the writing tool 200, a temporary writing end response is output from the microcomputer 120 to the writing tool 200. Is done.
Receiving the provisional write end response, the writing tool 200 performs the next data transfer, but since all the bytes of the next block of the divided data (5) are all FFs, the data for the blocks that are all FFs The divided data (6) stored in the block next to the block that is all FF is transferred without performing the transfer.

The microcomputer 120 that has received the divided data (6) determines whether or not data transfer is performed by skipping one block (128 bytes) based on the address information transferred together with the divided data (6).
When the microcomputer 120 skips one block and transfers the data, the microcomputer 120 adds 128 bytes that are all FFs after the previously received divided data (5), and the data is transferred by two. 256 bytes data, and writing to the flash ROM 110 is performed.

In addition, when one block that should become the second divided data is skipped and data transfer is performed, the result of verifying the previous writing that normally responds to the reception of the second divided data The write end response cannot be output.
Therefore, when the microcomputer 120 next receives the divided data, that is, in the example shown in FIG. 6, the result of verifying the previous writing as a response when the first divided data (6) is received. Write end response as

In addition, the writing tool 200 that has received a write end response to the transfer of the divided data (6) transfers the next divided data (7), so that 128 bytes which are all FFs after the divided data (5). The writing of 256-byte data to which data is added to the flash ROM 110 and the transfer processing of the divided data (7) are performed in parallel.
The microcomputer 120 that has received the divided data (7) outputs a status signal indicating the result of verifying the writing of 256-byte data in which 128 bytes that are all FFs are added after the divided data (5). 6) and the divided data (7) are collectively written in the flash ROM 110.

Upon receiving the status signal, the writing tool 200 transfers the next divided data. In the example shown in FIG. 6, each 128-byte block next to the block in which the divided data (7) is stored. Since all the bytes are FF, the divided data (8) of the next block is transferred without transferring the data for 128 bytes.
The microcomputer 120 that has received the divided data (8) is not transferred because the data for one block immediately before the divided data (8) is FF based on the address information of the divided data (8). This is detected from the address information, and 128 bytes, which are all FFs, are added before the divided data (8) to form 256 bytes of data, and writing to the flash ROM 110 is performed.

In addition, the microcomputer 120 transmits a status signal indicating the result of verifying writing of the divided data (6) and the divided data (7) to the writing tool 200 as a response to the divided data (8). Thereafter, 128 bytes, which are all FFs, are added before the divided data (8) to 256 bytes, and the data is written to the flash ROM 110.
As described above, the microcomputer 120 determines from the address information of the transmitted data whether there is one block (128-byte block) that has not been transferred because it is all FF, and data for one block that has not been transferred. Is added to the transferred divided data and written to the flash ROM 110.

Therefore, it is possible to correctly write the application program stored in the storage 210 to the flash ROM 110 while eliminating waste of the writing tool 200 transmitting 128 bytes of data in which all bytes are FF.
When the second divided data is not transmitted because it is all FF, the microcomputer 120 receives a status signal indicating the verification result of the previous write when the next first divided data is received. Since it is transmitted, the result of verifying the actual writing can be notified to the writing tool 200 without interruption, and the microcomputer 120 receives the divided data and writes to the flash ROM 110 in parallel. Can be made.

Next, a writing process when two blocks, all of which are FFs, are described with reference to FIG.
In the example illustrated in FIG. 7, when the divided data (9) corresponding to the first is transferred from the writing tool 200 to the microcomputer 120, the microcomputer 120 transmits a provisional writing end response to the writing tool 200. This prompts the transfer of the next divided data.

The writing tool 200 that has received the (provisional) write end response after the transfer of the divided data (9) transfers the next divided data, but all the bytes of the next block of the divided data (9) are all FFs. Further, since each byte in the next block is all FF, two blocks are skipped (256-byte data transfer is canceled), and the divided data (10) is transferred to the microcomputer 120.
The microcomputer 120 that has received the divided data (10) detects that the divided data has been transferred by skipping two blocks from the address information of the divided data (10). Then, the microcomputer 120 writes data of 256 bytes by adding 128-byte data, which is all FFs, after the divided data (9) to the flash ROM 110.

In addition, the microcomputer 120 that has received the divided data (10) adds the verification result when the data before the divided data (9) is written, and 128-byte data that is all FF after the divided data (9). The result of verifying the writing of the 256-byte data is output to the writing tool 200 as a reception response of the divided data (10).
After that, the microcomputer 120 writes 128 bytes data, which is all FF, before the divided data (10) to 256 bytes, and writes the data to the flash ROM 110.

As described above, even if two consecutive blocks having all bytes of FF are consecutive, the application program stored in the storage 210 can be correctly written into the flash ROM 110 while omitting transfer of the blocks having all FFs. .
In addition, since a plurality of status signals indicating the verification result of writing are output collectively when the divided data is received, the result of verifying the actual writing can be notified to the writing tool 200 without interruption, The microcomputer 120 can receive the divided data and write to the flash ROM 110 in parallel.

The flowchart of FIG. 8 shows the flow of processing of the writing tool 200 in the sequence of the writing processing in the case where the data in which all the bytes are FF illustrated in FIGS. 6 and 7 is not transferred.
First, in step S701, when starting the data transfer, the ECU 100 (microcomputer 120) is notified of the transfer start.
In the next step S702, the first divided data is transferred.

Thereafter, in step S703, it is determined whether or not there is a write end response from the ECU 100 (microcomputer 120). When the write end response is received, the process proceeds to step S704.
In step S704, it is determined whether or not each byte of the next block to which data was transferred last time is FF.
If all the bytes of the next block are not FF, the process proceeds to step S705, and the 128-byte data of the next block is transferred to the ECU 100 (microcomputer 120) as divided data.

On the other hand, if all the bytes in the next block are FF, the process proceeds to step S706, where the data transfer for the block in which each byte is all FF is canceled, and then the process returns to step S704, so that each byte is changed. For the block next to the block that is determined to be all FF, it is determined whether or not each byte is a block that is FF.
If all the bytes of the next block are not FF, the process proceeds to step S705, and the 128-byte data of the next block is transferred to the ECU 100 (microcomputer 120) as divided data.

The flowcharts of FIGS. 9 and 10 illustrate the flow of processing of the ECU 100 (microcomputer 120) in the write processing sequence illustrated in FIGS. 6 and 7 when a block (128 bytes) in which all bytes are FFs is not transferred. Show.
In step S801, it is determined whether or not the divided data is transferred from the writing tool 200. When the divided data is transferred, the process proceeds to step S802, and the transferred divided data is stored in the buffer.

Next, in step S803, based on the address information of the divided data received last time and the address information of the divided data received this time, it is determined whether or not there is a block to which data has not been transferred. , It is determined that all bytes are FF.
If there is no block for which data transfer has not been performed and the divided data of the block next to the previously received divided data is received this time, the process proceeds to step S804.

In step S804, it is determined whether or not the divided data transferred this time is the second divided data to be written together with the previously transferred divided data.
If the divided data transferred this time is the first, not the second, and it is necessary to perform writing together with the divided data transferred later, the process proceeds to step S805, and the temporary writing is completed. By outputting the response to the writing tool 200, a transfer of the next (second) divided data is requested.

On the other hand, if the divided data transferred this time is the second data and can be written together with the previously transferred divided data, the process proceeds to step S806, and a status signal indicating the result of verifying the previous writing is written. Output to the tool 200.
Here, when the previous writing is normally performed and a write end response is output to the writing tool 200 as a status signal, the next divided data is transferred from the writing tool 200. .

When the status signal is output in step S806, the process returns to step S801 in preparation for the transfer of the next divided data, and proceeds to step S807, where the previously transferred divided data and the currently transferred divided data are combined into the flash ROM 110. Are written in a batch and a process for verifying the writing result is performed. As a result, the writing of the divided data to the flash ROM 110 and the transfer and reception of the divided data for the next writing are performed in parallel.
If it is determined in step S803 that there is a block in which all bytes are FF between the block of divided data received last time and the block of divided data received this time, the process advances to step S808. move on.

In step S808, it is determined whether there is a single block in which all bytes are FF, or whether there are two consecutive blocks.
If there is only one, that is, if there is 128 byte data in which all bytes are FF between the previously transferred divided data and the currently transferred divided data, The process proceeds to S809.

In step S809, it is determined whether the block that has not been transferred corresponds to the second divided data.
That is, when the previously transferred divided data is stored as the first data, when the first divided data and the currently transferred divided data are collectively written in the flash ROM 110, the previous transferred data is transferred. The 128-byte data that originally exists between the divided data and the divided data transferred this time and whose bytes are all FFs will be lost.

Therefore, in this case, it is necessary to write the divided data transferred to the flash ROM 110 as the first divided data and the 128-byte data in which all the bytes are FF as the second divided data.
If it is determined in step S809 that the block that has not been transferred corresponds to the second divided data, the process advances to step S810 to output a status signal indicating the previous writing verification result to the writing tool 200. .

The divided data transferred this time corresponds to the first data, but the divided data corresponding to the second data that should have been transferred before that is not transferred because each byte is all FF, Since the status signal output opportunity indicating the previous write verification result has been lost, the status signal indicating the previous write verification result is written at the timing when the divided data of the block next to the block that was not transferred is transferred. Output to the tool 200.
When the status signal is output in step S810, the process returns to step S801 to prepare for the transfer of the next divided data, and at the same time, the writing process in step S811 is performed.

In step S811, 128-byte data in which each byte is all FF is added after the previously transferred divided data, and the data is combined into 256-byte data. The 256-byte data is written to the flash ROM 110, and the verification of the writing is performed. I do.
On the other hand, if it is determined in step S809 that the block not transferred corresponds to the first divided data, the divided data transferred this time corresponds to the second. In this case, the process proceeds to step S812, a status signal indicating the verification result of the previous writing is output to the writing tool 200, and then the process proceeds to step S801 to prepare for the transfer of the next divided data.

Further, since the block that has not been transferred corresponds to the first divided data and the divided data transferred this time corresponds to the second divided data, in the next step S813, each byte is transferred before the divided data transferred this time. 128 bytes data, all of which are FFs, is added to collect the data into 256 bytes, and the 256 bytes of data are written to the flash ROM 110 and the writing is verified.
If it is determined in step S808 that there are two consecutive blocks in which all bytes are FF, the process proceeds to step S814.

As a case where there are two consecutive blocks in which all the bytes are FF, there are cases where all the bytes are FF in both the first and second when collecting 128-byte data. However, if all the write areas of the flash ROM 110 are initialized to FF, the data write operation in which all 256 bytes are FF is unnecessary, and therefore the process proceeds to step S814 where the first divided data is transferred. It is assumed that there are two blocks that are not transferred continuously.
Therefore, when the process proceeds to step S814, the previously transferred divided data corresponds to the first one, and thereafter, 128-byte data in which each byte is all FF exists as the second divided data. 128-byte data whose bytes are all FF exists as the first divided data, and the divided data transferred this time corresponds to the second.

Therefore, in step S814, 128 bytes data in which all bytes are all FFs are added after the previously transferred divided data, and the data is combined into 256 bytes data. The 256 bytes data is written to the flash ROM 110, and the writing is performed. Perform verification.
Then, in the next step S815, a status signal indicating two verification results, that is, the verification result in the step S814 and the verification result of the previous write with respect to the write in the step S814 is directed to the writing tool 200. Output.

The verification result of the previous write with respect to the write in step S814 this time is transferred this time because there was no continuous output because there are two consecutive blocks in which all bytes are FF. Output as the response of the divided data.
The divided data transferred this time corresponds to the second data, and is a timing to output a status signal indicating the verification result of the previous writing. The previous writing here refers to the divided data transferred last time. Since the data is written by adding 128-byte data in which each byte is all FF, a status signal indicating two verification results is output to the writing tool 200 after the verification of the writing is completed.

  When the status signals indicating the two verification results are output to the writing tool 200, the process returns to step S801 in preparation for the transfer of the next divided data, and the process proceeds to step S816, where each byte is sent before the divided data transferred this time. 128 bytes data, all of which are FFs, is added to collect the data into 256 bytes, and the 256 bytes of data are written to the flash ROM 110 and the writing is verified.

  In addition, even when there are three or more blocks in which all the bytes are FF continuously, the 128 bytes data in which each byte is all FF is added before the divided data transferred this time, and the data is combined into 256 bytes. By writing 256-byte data to the flash ROM 110, or by adding 128-byte data in which each byte is all FF after the previously transferred divided data, and combining the 256-byte data into the flash ROM 110. Data can be written to the flash ROM 110 without omission.

Although the preferred embodiments have been specifically described above, it is obvious that those skilled in the art can take various modifications.
For example, in the above embodiment, the size of the divided data transferred by the writing tool 200 is 128 bytes and the writing size in the flash ROM 110 is 256 bytes. However, if the writing size data is divided and transferred from the writing tool 200, The present invention can be applied, and the data size is not limited to that of the embodiment.

Further, it is apparent that writing can be performed on a 128-byte block, which is all FF, by transferring the block from the writing tool 200 to the microcomputer 120 in the same manner as the example shown in FIG.
Further, data transfer from the outside to the ECU 100 may be performed wirelessly, and the transferred data is not limited to the application program.

Here, technical ideas other than the claims that can be grasped from the above embodiment will be described together with effects.
(A) The automobile electronic control unit according to claim 2, wherein the divided data in which each byte is all FF is not transferred from the outside.
According to the above invention, the divided data in which each byte is all FF is not transferred from the outside, and the divided data to be combined with the divided data that has not been transferred has each byte on the front side or the rear side. Data that is all FF is added to obtain the write size of the nonvolatile memory.

(B) The automotive electronic control device according to any one of claims 1 and 2, wherein the divided data having a size half the write size of the nonvolatile memory is transferred from the outside.
According to the above invention, two pieces of divided data transferred from the outside are collected and written to the nonvolatile memory at once.

(C) The automotive electronic control device according to any one of claims 1 and 2, wherein the divided data transferred from the outside is data of an application program for controlling the in-vehicle device.
According to the above-described invention, an application program corresponding to a vehicle type to be installed can be written into an automobile electronic control device manufactured as a common device, whereby a device having a specification suitable for a specific vehicle type can be obtained.

DESCRIPTION OF SYMBOLS 100 ... ECU (electronic control apparatus for motor vehicles), 110 ... Flash ROM (nonvolatile memory), 120 ... Microcomputer, 130 ... RAM, 200 ... Writing tool (external device)

Claims (2)

Including a non-volatile memory capable of electrically erasing and writing data;
When the write size data of the non-volatile memory is transferred from outside to be divided into a plurality of divided data, and when a plurality of divided data for the write size is prepared, the plurality of divided data are collected together into the non-volatile memory. While writing to
Whenever the divided data is received, a status signal indicating a verification result of writing is output to the outside, and when a plurality of divided data for the writing size are ready and immediately before the next writing, the status signal is A status signal indicating the result of verifying the previous writing is output, and a temporary status signal is output to the outside as the status signal until a plurality of divided data for the writing size is prepared,
An automotive electronic control device that receives the divided data for the next writing in parallel with the writing to the nonvolatile memory.   Based on the address information of the divided data, the presence / absence of divided data that has not been transferred from the outside is determined, and if there is divided data that has not been transferred, the divided data is regarded as predetermined data. The vehicle electronic control device according to claim 1, wherein the electronic data is written together with other divided data in the nonvolatile memory.