JP2013172098A - Semiconductor nonvolatile memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an electrically rewritable semiconductor nonvolatile memory device which inhibits deterioration of a tunnel insulation film without increasing an occupied area to achieve high reliability.SOLUTION: In a semiconductor nonvolatile memory device, a floating gate electrode includes an amorphous silicon region and a polysilicon region. The amorphous silicon region is arranged on a part on an upper side surface and lateral face of the floating gate electrode, which contacts a control insulation film. The polysilicon region is arranged in a region of the floating gate electrode, which contacts a tunnel insulation film. A fine convexoconcave is formed on the surface part of the floating gate electrode, which contacts the control insulation film.

Description

  The present invention relates to an electrically rewritable semiconductor nonvolatile memory device used in electronic equipment.

  An electrically rewritable semiconductor non-volatile memory cell (hereinafter abbreviated as an EEPROM cell) has an N-type source region and an N-type drain region arranged on a P-type silicon substrate via a channel region. A floating gate electrode is formed through a tunnel insulating film made of a thin silicon oxide film having a thickness of about 100 mm or less or a composite film of a silicon oxide film and a silicon nitride film, etc. on the floating gate electrode. A control gate electrode is formed through a control insulating film made of a thin insulating film, and the floating gate electrode is strongly capacitively coupled to the control gate electrode.

  The floating gate electrode and the control gate electrode are extended on the channel region, and the conductance of the channel region varies depending on the potential of the floating gate electrode.

  Therefore, information can be stored in a nonvolatile manner by changing the amount of electrification in the floating gate electrode. By applying a potential difference of about 15 V or more with respect to the control gate to the drain region also serving as the tunnel region, electrons of the floating gate are discharged to the drain region through the tunnel insulating film of the tunnel region, or conversely to the floating gate electrode. Or can be injected.

  In this way, the charge amount of the floating gate is changed to function as a nonvolatile memory. Many such EEPROM cells are arranged in a matrix to form a memory array, thereby obtaining a large-capacity nonvolatile memory semiconductor device. Here, a tunnel region having a tunnel insulating film that allows electrons to pass through is particularly important, and it enables rewriting of memory cell information of hundreds of thousands of times, and long-term storage of memory information for several decades ( It plays a dominant role in the charge retention requirements.

  As a measure for improving the reliability of the tunnel region and the tunnel insulating film, an example in which a tunnel region having a different impurity concentration is provided adjacent to the drain region to improve the rewrite characteristics and the retention characteristics has been proposed (for example, see Patent Document 1). .

Japanese Patent Laid-Open No. 1-160058

  However, in the semiconductor device in which a dedicated tunnel region is provided separately from the drain region as in the improved example, there is a problem that the occupied area increases and the cost of the semiconductor device increases. In addition, there is still room for improvement in rewriting characteristics and retention characteristics.

In order to solve the above problems, the present invention is configured as follows.
A channel which is the surface of the semiconductor region between the source region and the drain region, and the source region and the drain region of the second conductivity type provided on the surface of the semiconductor surface region of the first conductivity type and spaced apart from each other A forming region, a floating electrode provided on the source region, the drain region, and the channel forming region via a gate insulating film, a control gate electrode capacitively coupled via the floating gate electrode and the control insulating film, In the electrically rewritable semiconductor nonvolatile memory, a tunnel insulating film is provided between the tunnel region in the drain region and the floating gate electrode, and the floating gate electrode is connected to the amorphous silicon region. Amorphous silicon comprising a polysilicon region The region is disposed in a portion of the upper surface of the floating gate electrode that is in contact with the control insulating film, and the polysilicon region is disposed in a region of the floating gate electrode that is in contact with the tunnel insulating film, and the floating gate electrode An electrically rewritable semiconductor non-volatile memory device in which fine irregularities are formed on the surface portion in contact with the control insulating film is obtained.

The amorphous silicon region has a thickness of 1000 angstroms or less and is an electrically rewritable semiconductor nonvolatile memory device.
In addition, an electrically rewritable semiconductor nonvolatile memory device in which the depth of fine irregularities formed on the surface portion of the floating gate electrode in contact with the control insulating film is 500 angstroms or less.
2. The electrically rewritable semiconductor nonvolatile memory device according to claim 1, wherein at least one of the tunnel insulating film or the control insulating film is a composite film of a silicon oxide film and a silicon nitride film.

  Since the surface area of the floating gate electrode in contact with the control insulating film is increased by increasing the surface area, the capacitance between the floating gate electrode and the control gate electrode is greatly increased and the capacitive coupling becomes stronger. It is possible to increase a so-called coupling ratio, which is an index for comparing the capacitance between the control gate electrode and the drain region via the tunnel insulating film.

  The conventional floating gate electrode is formed of polysilicon, but the floating gate electrode of the present invention is composed of an amorphous silicon region and a polysilicon region, and the amorphous silicon region is the upper surface or upper side of the floating gate electrode. In addition to the surface, it is arranged at the part in contact with the control insulating film on the side surface.

  As a result, the control insulating film formed with fine unevenness between the floating gate and the control gate is uniformly processed along the fine uneven shape without being affected by the crystal grain boundary of the floating gate electrode as a base, As a result, it is possible to form a highly reliable and high-quality insulating film, and the capacitance between the floating gate electrode and the control gate electrode can be further increased.

  Therefore, since the voltage applied to the control gate electrode is more efficiently transmitted to the floating gate electrode, it is easy to finally obtain a potential difference between the floating gate electrode and the drain region via the tunnel insulating film. As a result, the voltage applied to the control electrode necessary for the data rewrite operation can be made smaller than in the prior art. Further, since it is not necessary to form a large floating gate electrode and control electrode in order to ensure the coupling ratio, it is effective for miniaturization of the memory cell.

On the other hand, a polysilicon region is arranged in a region of the floating gate electrode that is in contact with the tunnel insulating film. The polysilicon region has high conductivity due to the introduction of impurities, and the number of data rewrites and data retention without impairing the reliability of the tunnel insulating film. An increase in time can be achieved. Furthermore, the work function difference between the channel region sandwiched between the source region and the drain region and the floating gate electrode can be set to be equivalent to that of the conventional semiconductor nonvolatile memory device.
In addition, at least one of the tunnel insulating film and the control insulating film is further improved in reliability as a composite film of a silicon oxide film and a silicon nitride film.

  By these means, when data is rewritten in an electrically rewritable semiconductor non-volatile memory device, it can be rewritten efficiently at a lower voltage, and the deterioration of the tunnel insulating film is suppressed and high reliability is achieved. Rewritable semiconductor nonvolatile memory device can be obtained.

1 is a schematic cross-sectional view showing a first embodiment of an electrically rewritable semiconductor nonvolatile memory device according to the present invention. FIG. 6 is a schematic cross-sectional view showing a second embodiment of the electrically rewritable semiconductor nonvolatile memory device according to the present invention.

  A mode for carrying out the invention will be described with reference to the drawings in accordance with an embodiment.

FIG. 1 is a schematic cross-sectional view showing a first example of an electrically rewritable semiconductor nonvolatile memory device according to the present invention.
A second conductivity type N-type source region 201 and a drain region 202 are provided on the surface of the first conductivity type P-type silicon substrate 101 so as to be spaced apart from each other, and between the source region 201 and the drain region 202. A polysilicon region is formed on the channel formation region, which is the surface of the P-type silicon substrate 101, the source region 201, the drain region 202, and the channel formation region via a gate insulating film 301 made of, for example, a silicon oxide film. A floating gate electrode 501 composed of a laminated film of 503 and an amorphous silicon region 502 is provided, and fine irregularities 571 are formed on the upper surface of the floating gate electrode 501 to increase the surface area.

  Further, a control gate electrode 701 made of polysilicon or the like capacitively coupled through a control insulating film 601 made of a silicon oxide film, a silicon nitride film, or a composite film thereof is formed along the fine unevenness 571, and the drain region 202. A tunnel insulating film 401 made of a silicon oxide film, a silicon nitride film, or a composite film thereof is formed between the inner tunnel region 801 and the floating gate electrode 501.

  Here, the floating gate electrode 501 is composed of an amorphous silicon region 502 and a polysilicon region 503. The amorphous silicon region 502 is disposed at a portion in contact with the control insulating film 601 on the upper surface of the floating gate electrode 501, and the polysilicon region. Reference numeral 503 is arranged in a region of the floating gate electrode 501 in contact with the tunnel insulating film 401, and fine irregularities 571 are formed on the surface portion of the amorphous silicon region 502 in contact with the control insulating film 601 of the floating gate electrode 501.

  In addition, the floating gate electrode 501 itself has higher conductivity, and the work function difference between the floating gate electrode 501 and the channel region sandwiched between the source region 201 and the drain region 202 is reduced by a conventional semiconductor. It is desirable that the bottom surface portion of the floating gate electrode 501 is formed by the polysilicon region 503 into which impurities are introduced so that it can be set to be equivalent to that of the nonvolatile memory device.

  The amorphous silicon region 502 is provided in order to suppress the influence of the grain boundary of the polysilicon material, and the floating gate electrode 501 itself is a polysilicon region 503 into which impurities having higher conductivity are introduced, and the entire large region is formed. Since it is desirable to form the amorphous silicon region, the thickness of the amorphous silicon region is set to 1000 angstroms or less, and the pitch and height of the fine unevenness 571 formed on the surface thereof is about several hundreds angstroms, preferably 500 angstroms or less. This is desirable because the surface area of the fine irregularities 571 can be further increased.

  According to the first embodiment of the present invention shown in FIG. 1, since the surface area of the floating gate electrode 501 in contact with the control insulating film 601 is increased by forming fine irregularities 571, the floating gate electrode 501 Between the control gate electrode 701 and the drain region 202 via the tunnel insulating film 401, the capacitance between the control gate electrode 701 and the control gate electrode 701 is greatly increased. The coupling ratio can be increased.

  The conventional floating gate electrode 501 is made of only a polysilicon material. However, the floating gate electrode 501 of the present invention is composed of an amorphous silicon region 502 and a polysilicon region 503, and the amorphous silicon region 502 is a floating gate. The electrode 501 is disposed on the upper surface of the electrode 501 in a portion in contact with the control insulating film 601.

  As a result, the control insulating film 601 formed with fine irregularities between the floating gate electrode 501 and the control gate electrode 701 is affected by the grain boundary when the underlying floating gate electrode 501 is a conventional polysilicon material. Can be uniformly processed and formed along a fine concavo-convex shape without being subjected to, and a highly reliable high-quality insulating film can be formed. The floating gate electrode 501 and the control gate electrode The capacity between 701 can be increased.

Therefore, since the voltage applied to the control gate electrode 701 is more efficiently transmitted to the floating gate electrode 501, finally, the potential difference between the floating gate electrode 501 and the drain region 202 via the tunnel insulating film 401 is reduced. Since it becomes easy to obtain, the voltage applied to the control electrode 701 necessary for the data rewrite operation can be made smaller than in the conventional case.
Further, since it is not necessary to form the floating gate electrode 501 and the control electrode 701 large in order to ensure the coupling ratio, it is effective for miniaturization of the memory cell.

On the other hand, a polysilicon region 503 is arranged in a region in contact with the tunnel insulating film 401 of the floating gate electrode 501, and has high conductivity by introducing impurities and data rewrite without impairing the reliability of the tunnel insulating film 401. Increase in the number of times and data retention time can be achieved.
Further, at least one of the tunnel insulating film 401 and the control insulating film 601 is further improved in reliability as a composite film of a silicon oxide film and a silicon nitride film.

  By these means, when data is rewritten in an electrically rewritable semiconductor nonvolatile memory device, it can be rewritten efficiently at a lower voltage, and deterioration of the tunnel insulating film 401 is suppressed and high reliability is achieved. An electrically rewritable semiconductor nonvolatile memory device can be obtained.

FIG. 2 is a schematic cross-sectional view showing a second example of the electrically rewritable semiconductor nonvolatile memory device according to the present invention.
A different point from the first embodiment shown in FIG. 1 is that the amorphous silicon region 502 in the floating gate electrode 501 is disposed not only on the upper surface of the floating gate electrode 501 but also in the portion in contact with the control insulating film 601 on the side surface. Accordingly, the fine unevenness 571 is also formed on the side surface in addition to the upper surface of the floating gate electrode 501.

In the second embodiment shown in FIG. 2, fine irregularities 571 are formed also on the side surface of the floating gate 501, and a capacitance is formed between the control gate electrode 701 through the control insulating film 601. Compared with the first embodiment, the capacitance between the floating gate electrode 501 and the control gate electrode 701 is further increased, and the coupling ratio can be further increased.
Other descriptions will be replaced by the same reference numerals as those in FIG.

  By these means, when data is rewritten in an electrically rewritable semiconductor nonvolatile memory device, it can be rewritten efficiently at a lower voltage, and deterioration of the tunnel insulating film 401 is suppressed and high reliability is achieved. An electrically rewritable semiconductor nonvolatile memory device can be obtained.

101 P-type silicon substrate 201 Source region 202 Drain region 301 Gate insulating film 401 Tunnel insulating film 501 Floating gate electrode 502 Amorphous silicon region 503 Polysilicon region 571 Fine irregularities 601 on the surface of the floating gate electrode Control insulating film 701 Control gate electrode 801 Tunnel region

Claims (3)

A source region and a drain region of a second conductivity type provided on the surface of the semiconductor surface region of the first conductivity type and spaced apart from each other;
A channel formation region which is a surface of the semiconductor region between the source region and the drain region;
A floating gate electrode provided on the source region, the drain region, and the channel formation region via a gate insulating film;
A control gate electrode capacitively coupled to the floating gate electrode via a control insulating film;
A tunnel insulating film provided between the tunnel region in the drain region and the floating gate electrode;
Have
The floating gate electrode is composed of an amorphous silicon region and a polysilicon region,
The amorphous silicon region is disposed in a portion in contact with the control insulating film on the upper surface of the floating gate electrode,
The polysilicon region is disposed in a region in contact with the tunnel insulating film of the floating gate electrode,
An electrically rewritable semiconductor nonvolatile memory device in which fine irregularities are formed on a surface portion of the floating gate electrode in contact with the control insulating film.   The electrically rewritable semiconductor nonvolatile memory device according to claim 1, wherein the amorphous silicon region is further disposed in a portion of the side surface of the floating gate electrode that is in contact with the control insulating film.   3. The electrically rewritable semiconductor nonvolatile memory device according to claim 1, wherein at least one of the tunnel insulating film or the control insulating film is a composite film of a silicon oxide film and a silicon nitride film.

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