JP2013140870A5 - - Google Patents

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JP2013140870A5
JP2013140870A5 JP2012000335A JP2012000335A JP2013140870A5 JP 2013140870 A5 JP2013140870 A5 JP 2013140870A5 JP 2012000335 A JP2012000335 A JP 2012000335A JP 2012000335 A JP2012000335 A JP 2012000335A JP 2013140870 A5 JP2013140870 A5 JP 2013140870A5
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Japan
Prior art keywords
power semiconductor
power
control
semiconductor device
die pad
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JP2012000335A
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Japanese (ja)
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JP5800716B2 (en
JP2013140870A (en
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Priority claimed from JP2012000335A external-priority patent/JP5800716B2/en
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Publication of JP2013140870A5 publication Critical patent/JP2013140870A5/ja
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Claims (7)

主電力を制御する電力用半導体素子と、前記電力用半導体素子を制御する制御素子とを矩形板状の封止体に内包するとともに、前記封止体の対向する側面のうち、一方から前記電力用半導体素子と接続するための電力用端子が、他方から前記制御素子と接続するための制御用端子が突出する電力用半導体装置であって、
それぞれの面が略平行になるように形成されたリードフレーム内のパターンのうちの、前記電力用端子に延在する電力リードパターンと、前記制御用端子に延在する制御リードパターンと、少なくとも前記制御リードパターンの面に対して垂直な方向に段差付されるとともに前記制御リードパターンに近い方の面に前記電力用半導体素子の裏面電極が接合されたダイパッドと、
絶縁基板に配線パターンを積層して構成され、前記制御素子が搭載されるとともに、少なくとも一方の面に、前記電力用半導体素子の表面電極と接続するための電力配線パターンと、前記制御素子の電極と電気接続される制御配線パターンとが形成されたインターポーザ基板と、を備え、
前記リードフレームに対して前記インターポーザ基板が平行に位置するように、前記電力用半導体素子の表面電極に対して前記電力配線パターンを、前記制御リードパターンに対して前記制御配線パターンを対向させて接合するとともに、前記ダイパッドの少なくとも周縁部には、前記ダイパッドと前記インターポーザ基板との間隔を維持する間隔維持部材が配置されていることを特徴とする電力用半導体装置。
The power semiconductor element for controlling the main power and the control element for controlling the power semiconductor element are encapsulated in a rectangular plate-shaped sealing body, and the power is applied from one of the opposing side surfaces of the sealing body. A power semiconductor device in which a power terminal for connecting to a semiconductor element for use projects from a control terminal for connecting to the control element from the other,
Of the patterns in the lead frame formed so that each surface is substantially parallel, the power lead pattern extending to the power terminal, the control lead pattern extending to the control terminal, and at least the A die pad having a step in a direction perpendicular to the surface of the control lead pattern and having a back electrode of the power semiconductor element bonded to a surface closer to the control lead pattern;
The control element is mounted by laminating a wiring pattern on an insulating substrate, and a power wiring pattern for connecting to a surface electrode of the power semiconductor element on at least one surface, and an electrode of the control element And an interposer substrate on which a control wiring pattern to be electrically connected is formed,
The power wiring pattern is bonded to the surface electrode of the power semiconductor element, and the control wiring pattern is bonded to the control lead pattern so that the interposer substrate is positioned in parallel to the lead frame. In addition, a power semiconductor device is characterized in that an interval maintaining member for maintaining an interval between the die pad and the interposer substrate is disposed at least at a peripheral portion of the die pad.
前記電力用半導体素子の表面電極と前記電力配線パターンとの接合、および前記ダイパッドと前記インターポーザ基板との接合のうちの少なくとも一方は、
はんだ材と、前記はんだ材よりも融点が高く、所定の代表径を有して前記はんだ材に内包され、前記間隔維持部材として機能する核体と、で構成されたはんだバンプが用いられていることを特徴とする請求項1に記載の電力用半導体装置。
At least one of the bonding between the surface electrode of the power semiconductor element and the power wiring pattern, and the bonding between the die pad and the interposer substrate,
A solder bump composed of a solder material and a core that has a higher melting point than the solder material, has a predetermined representative diameter, is included in the solder material, and functions as the gap maintaining member is used. The power semiconductor device according to claim 1.
前記ダイパッドには、
前記ダイパッドから延在するとともに前記インターポーザ基板を支え、前記間隔維持部材として機能する支柱部が形成されていることを特徴とする請求項1または2に記載の電力用半導体装置。
In the die pad,
3. The power semiconductor device according to claim 1, wherein a post portion extending from the die pad and supporting the interposer substrate and functioning as the spacing maintaining member is formed. 4.
前記インターポーザ基板と前記ダイパッドとの間に、所定厚みを有し、前記間隔維持部材として機能するポッティング樹脂が設けられていることを特徴とする請求項1ないし3のいずれか1項に記載の電力用半導体装置。 Between the Daipa' de and the interposer substrate has a predetermined thickness, according to any one of claims 1 to 3, characterized in that potting resin that serves as the space maintaining members are provided Power semiconductor device. 前記制御素子は、前記インターポーザ基板の前記一方の面側に搭載されており、
所定厚みを有して前記制御素子を封止するとともに、前記ダイパッドに対向して前記間隔維持部材として機能する封止樹脂を設けたことを特徴とする請求項1ないし4のいずれか1項に記載の電力用半導体装置。
The control element is mounted on the one surface side of the interposer substrate,
5. The sealing resin according to claim 1, wherein the control element is sealed with a predetermined thickness, and a sealing resin that functions as the gap maintaining member is provided opposite to the die pad. The power semiconductor device described.
前記電力用半導体素子がワイドバンドギャップ半導体材料により形成されていることを特徴とする請求項1ないし5のいずれか1項に記載の電力用半導体装置。   6. The power semiconductor device according to claim 1, wherein the power semiconductor element is formed of a wide band gap semiconductor material. 前記ワイドバンドギャップ半導体材料は、炭化ケイ素、窒化ガリウム系材料、およびダイヤモンド、のうちのいずれかであることを特徴とする請求項6に記載の電力用半導体装置。   The power semiconductor device according to claim 6, wherein the wide band gap semiconductor material is any one of silicon carbide, a gallium nitride-based material, and diamond.
JP2012000335A 2012-01-05 2012-01-05 Power semiconductor device Active JP5800716B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012000335A JP5800716B2 (en) 2012-01-05 2012-01-05 Power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012000335A JP5800716B2 (en) 2012-01-05 2012-01-05 Power semiconductor device

Publications (3)

Publication Number Publication Date
JP2013140870A JP2013140870A (en) 2013-07-18
JP2013140870A5 true JP2013140870A5 (en) 2014-01-09
JP5800716B2 JP5800716B2 (en) 2015-10-28

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Publication number Priority date Publication date Assignee Title
JP6274986B2 (en) * 2014-06-26 2018-02-07 三菱電機株式会社 Power semiconductor module and manufacturing method thereof
JP6269573B2 (en) 2015-05-18 2018-01-31 株式会社デンソー Semiconductor device
WO2024013998A1 (en) * 2022-07-15 2024-01-18 日立Astemo株式会社 Semiconductor device

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* Cited by examiner, † Cited by third party
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JPH07226422A (en) * 1994-02-14 1995-08-22 Sumitomo Electric Ind Ltd Package of electronic component
JP3080049B2 (en) * 1997-11-17 2000-08-21 日本電気株式会社 Integrated circuit chip mounting structure and method
JP3674333B2 (en) * 1998-09-11 2005-07-20 株式会社日立製作所 Power semiconductor module and electric motor drive system using the same
JP2003100924A (en) * 2001-09-21 2003-04-04 Kyocera Corp Semiconductor device
JP2004172211A (en) * 2002-11-18 2004-06-17 Yaskawa Electric Corp Power module
JP4022758B2 (en) * 2003-03-31 2007-12-19 株式会社デンソー Semiconductor device
TWI226110B (en) * 2004-03-17 2005-01-01 Cyntec Co Ltd Package with stacked substrates
JP2008066026A (en) * 2006-09-05 2008-03-21 Fuji Electric Holdings Co Ltd Method for manufacturing organic el display panel
JP5193777B2 (en) * 2008-09-26 2013-05-08 株式会社東芝 Power semiconductor module and inverter system using it
JP2011044452A (en) * 2009-08-19 2011-03-03 Denso Corp Electronic device and method of manufacturing the same

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