JP2013135984A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which can carry out a high-degree image performance.SOLUTION: A game machine includes a main control section 21 which carries out lottery processing induced by a predetermined switch signal and controls game actions according to the lottery result, and a sub-control section 23 which carries out performance operations according to instructions from the main control section 21. The sub-control section 23 is constituted so that it attains performance operations based on the control of a computer circuit operated at a power voltage lower than a power voltage of the computer circuit constituting the main control section 21. A monitoring means ST16 which constantly monitors the rotation rate of a blowing fan FAN which air-cools a processor 41 controlling performance operations is mounted to the machine.

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine capable of high-level image effects.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passing of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display time is changed in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a gaming state is determined by a jackpot lottery executed on the condition that a game ball wins at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing.

  For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. In addition, before the final result is finalized, a notice effect is also performed in which various characters appear in a unique manner, so that a big hit state is informed.

  As described above, in a gaming machine, an image effect by a display device is very important, and a powerful effect is desired by a high-quality display device (Patent Documents 1 to 4).

JP 2010-2221045 A JP 2010-188174 A JP 2010-172742 A JP 2010-162418 A

  However, if an image effect such as a 3D moving image is to be executed with high image quality using a display device with high resolution, a circuit configuration corresponding to this is required. That is, a processor that can cope with an increase in processing load is necessary, and a circuit configuration that can cope with an increase in power consumption is also essential. And the structure which excludes the runaway of the circuit element accompanying heat_generation | fever is also needed.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a gaming machine capable of high-level image effects such as 3D moving images.

  In order to achieve the above object, the present invention executes a lottery process caused by a predetermined switch signal, and controls a game operation centrally based on the lottery result, and a main control unit And a sub-control unit that executes a production operation based on the instruction of the game machine, and a game machine that can shift to a gaming state advantageous to a player when winning a lottery process executed by the main control unit, The sub-control unit is configured to realize the rendering operation based on the control of the computer circuit that operates at a power supply voltage lower than the power supply voltage of the computer circuit constituting the main control unit, and blows air to cool the processor that controls the rendering operation Monitoring means for constantly monitoring the number of rotations of the fan is provided.

  The power supply voltage of the computer circuit of the main control unit is preferably 5V, and the power supply voltage of the computer circuit of the sub control unit is preferably 70% or less (3.5V or less).

  Preferably, the computer circuit of the sub-control unit is a single unit in which an image processor that generates image data to be displayed on the display device and a control processor that controls image effects based on an instruction from the main control unit are integrated. Should be configured with a chip. Moreover, it is preferable that the sub-control unit is executing a moving image effect in which a three-dimensional image moves smoothly.

  A single chip of the sub-control unit has a first level power supply voltage for operating the control processor and a second level power supply voltage for operating the access circuit for accessing the image data and the control program. It is preferable that the power supply is configured from the viewpoint of low power consumption. Similarly, the computer circuit of the sub-control unit includes a volatile memory that forms a work area for image display operation of the display device, and the access circuit for accessing the volatile memory includes image data and In view of reducing power consumption, it is preferable that the access circuit is configured independently of the access circuit for accessing the control program.

  In any case, when the monitoring means detects a decrease in the rotational speed of the blower fan, it is preferable to stop the subsequent production operation and execute an alarm operation. It is preferable that the motor is driven by a DC motor whose rotational speed varies corresponding to In this case, the monitoring means can monitor including abnormality of the power supply voltage. Note that the gaming machine of the present invention is typically a bullet ball game machine or a revolving game machine.

  As described above, according to the present invention, it is possible to realize a gaming machine that can execute a high-quality image effect without any problem.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the circuit structure of a power supply board. It is a time chart explaining a system reset signal. It is a block diagram showing circuit configurations of an effect control unit and an image control unit. It is a block diagram which shows the circuit structure of an image control part. It is a block diagram which shows the connection part with the production | presentation interface board | substrate in an image control part. It is a block diagram which shows the connection relationship with ROM in an image control part. It is a block diagram which shows the internal structure of ROM for control. It is a block diagram which shows the internal structure of CGROM. It is a time chart which shows the read-out operation | movement of CGROM. It is a flowchart explaining operation | movement of an image control part.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a speaker is disposed below the glass door 6.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided in an annular shape on the surface of the game board 5, and a central opening HO extending toward the back side is provided in the approximate center. It has been. A display device DISP composed of a liquid crystal color display is arranged at the bottom of the central opening HO. In the display device DISP, a 3D image is displayed at the time of a notice effect.

  A symbol starting port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged at appropriate positions in the game area 5a. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The display device DISP is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DISP has a special symbol display part Da to Dc in the center and a normal symbol display part 19 in the upper right part. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  The symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws, and when the stop symbol after the fluctuation of the normal symbol display unit 19 hits and the symbol is displayed, the opening and closing claws are displayed. It is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM receives AC24V and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. The main control board 21 that is centrally responsible, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 An image control board 23 for driving the display device DISP, a payout control board 24 for controlling the payout motor M based on a control command CMD "received from the main control board 21, and paying out a game ball; And a launch control board 25 for launching game balls in response to the above.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is the main board relay board. It is transmitted to the payout control board 24 via 28.

  These main control board 21, effect control board 22, image control board 23, and payout control board 24 are a one-chip microcomputer having a Z80 CPU or 16-bit CPU as a core, or an SOC (system-on-) with a 32-bit CPU. Each is equipped with a computer circuit with a-chip). Thus, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the image control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 is a sub-control unit.

  In addition, the production interface board 27 and the production control board 22 are integrated in this embodiment. Similarly, the image control board 23 is configured by integrating a control main body board 23a that drives the display device DISP to execute an image effect, and an interface board 23b that receives a control command CMD ′ from the effect control board 22. ing.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display device DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  FIG. 4 is a circuit diagram showing a power supply circuit of the power supply board 20. This power supply circuit includes a second power supply unit SD that generates a DC voltage supplied to the production interface board 27, and a first power supply unit FR that generates a DC voltage supplied to the main control unit 21 and the payout control unit 24. A power monitoring unit MNT that monitors power-on and power-off, and a power-cut-off unit CUT that cuts off the ground line when an excessive AC voltage is received. Note that illustration of other DC voltages (DC 32 V) supplied to the payout control unit 24 and other DC voltages (DC 32 V, DC 15 V) supplied to the production interface board 27 is omitted.

<Second power supply unit SD>
The second power supply unit SD includes a full-wave rectifier circuit including diodes D1 to D4, a smoothing capacitor C1, a DC-DC converter that generates a DC voltage VB (12V), and a DC-DC that generates a DC voltage Vcc (5V). The converter includes smoothing capacitors C2 and C3. Each of the two DC-DC converters is a chopper type, and operates in common with the smoothing capacitor C1. The direct-current voltage generated by the second power supply unit SD is transmitted to the effect interface board 27 and then stepped down as appropriate to be used by the effect interface board 27, the effect control board 22, and the image control board 23. Is done.

<First power supply FR>
The first power supply unit FR generates a full-wave rectifier circuit using diodes D1, D2, D5, and D6, a smoothing capacitor C4, a DC-DC converter that generates a DC voltage VB (12V), and a DC voltage Vcc (5V). The power storage unit BK is configured by a DC-DC converter, smoothing capacitors C5 and C6, a diode D7, and a capacitor Cb. These two DC-DC converters are also of a chopper type and operate in common with the smoothing capacitor C4. The DC voltage generated by the power storage unit BK serves as a backup power supply BAK that holds data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24.

  The DC voltage VB and the DC voltage Vcc generated by the first power supply unit FR are supplied only to the main control unit 21 and the payout control unit 24, and the DC voltage transmitted to the effect interface board 27 is on the wiring. It is distinguished. Therefore, the main control unit 21 and the payout control unit 24 are not connected to the other sub-control units 22 and 23 via the power line, and transmission of high-frequency noise and the like is prevented.

  The total current in the main control unit 21 and the payout control unit 24 does not exceed 600 mA on the power supply voltage VB line and does not exceed 300 mA on the power supply voltage Vcc line. The voltage drop of the VB and Vcc power supply lines is not a problem at all.

<Power cutoff unit CUT>
The power cut-off unit CUT corresponds to the rectifying unit 51 that generates a DC voltage of a predetermined level from the AC voltage AC24V, the AC monitoring unit 52 that is turned on when the AC power supply lines LN1 and LN2 are overvoltage, and the AC monitoring unit 52 that is turned on. And a switch circuit 53 that performs an OFF operation.

  The rectifier 51 includes a diode D12 that receives an AC voltage from the AC power supply line LN2, a current limiting resistor R1, and a parallel circuit of a capacitor C8 and a Zener diode ZD2, which are connected in series. During normal operation, the voltage across the capacitor C8 is constant at the breakdown voltage of the Zener diode ZD2.

  The switch circuit 53 includes a MOS transistor Q2 having a large current capacity and a bias resistor R5 connected in parallel to the capacitor C8. Here, the transistor Q2 is in an ON state as long as the voltage across the capacitor C8 is at a predetermined level, and connects the ground line of all the circuits of the gaming machine and the frame ground FG.

  The AC monitoring unit 52 includes two diodes D8 and D9 connected to the AC power supply lines LN1 and LN2, a Zener diode ZD1 connected to the connection point of the diodes D8 and D9, a bias resistor R2 and R3, and a capacitor C7 in parallel. The circuit includes a transistor Q1 that is turned on when the voltage across the bias resistor R3 increases, and a current limiting resistor R4 of the transistor Q1.

  Zener diode ZD1 is normally in an OFF state, but when an excessive AC voltage (for example, AC 100V) is applied to AC power supply lines LN1 and LN2, it enters a breakdown state. In this breakdown state, the voltage at both ends of the bias resistor R3 increases and the transistor Q1 is turned on, so that the voltage at both ends of the capacitor C8 decreases.

  Then, the transistor Q2 that has been in the ON state until then is turned OFF, whereby the circuit ground and the frame ground FG are disconnected, and all the power supply voltages of all the gaming machines are cut off. The operation content of the power cut-off unit CUT is as described above. When the voltage across the AC power supply lines LN1 and LN2 exceeds the limit value, the power cut-off unit CUT functions to cut off all the power supply voltages of all the gaming machines at once.

<Power supply monitoring unit MNT>
Next, the power supply monitoring unit MNT will be described. The power supply monitoring unit MNT includes a power supply monitoring unit 54 that monitors the voltage levels of the AC power supply lines LN1 and LN2, a comparison voltage unit 55 that receives the power supply voltage Vcc and outputs a comparison reference voltage Vo, and a power supply monitoring unit 54. An abnormality detection unit 56 that detects a power supply abnormality by comparing output voltages of the unit 55, and a power supply reset unit 57 that generates a TTL-level system reset signal SYS.

[Power supply monitoring unit 54]
The power supply monitoring unit 54 includes two diodes D10 and D11 connected to the AC power supply lines LN1 and LN2, a series circuit of a resistor R6 and a Zener diode ZD3 connected to a connection point of the diodes D10 and D11, and a Zener diode ZD3. A series circuit of a diode D13 and a smoothing capacitor C9 connected in parallel, a series circuit of resistors R7 and R8 connected in parallel to the smoothing capacitor C9, and a comparator A3 that short-circuits the resistor R8 are configured.

  In this embodiment, the breakdown voltage of the Zener diode ZD3 is about 5.1V, and the Zener diode ZD3 receives the AC voltage AC24V through the current limiting resistor R6. For this reason, when the AC input power supply is in a power supply state, the voltage across the smoothing capacitor C9 is a constant value of about 4.5V. Since the resistance values of the two resistors R7 and R8 are set to R8 >> R7, the both-ends voltage Vs of the resistor R8 is about 4.5V corresponding to the normal level AC voltage AC24V. However, if the output of the comparator A3 is at L level, the voltage Vs across the resistor R8 is substantially 0V correspondingly. The resistor R7 functions as a current limiting resistor for the comparator A3 when the L level is output.

  The comparator A3 is composed of a QUAD comparator (NJM2901) together with other comparators A1 to A4. This QUAD comparator includes four comparators A1 to A4, but each of the comparators A1 to A4 is an open collector type (see FIG. 5F).

  The output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminal of the comparator A3, and the comparison voltage V1 of about 2.8V is supplied to the plus terminal in the steady state. The comparison voltage V1 is generated by dividing the two types of power supply voltages Vcc and VB generated by the first power supply unit FR with resistors.

  As will be described later, when the power is turned on, the output voltage Vo of the comparison voltage unit 55 becomes a level corresponding to the power supply voltage Vcc whose level is rising (Vo = Vcc−Vf−Δ). Vf and Δ are voltage drops in the diodes D14 and D15 and the resistor R9.

  On the other hand, since the comparison voltage V1 is generated by dividing the power supply voltages Vcc and VB, immediately after the power is turned on, it is lower than the output voltage Vo of the comparison voltage unit 55. Therefore, in a transient state immediately after the power is turned on, the output of the comparator A3 becomes L level to short-circuit the resistor R8. As a result, the output voltage Vs of the power supply monitoring unit 54 becomes almost 0V.

  On the other hand, in a steady state in which the power supply voltages Vcc and VB have reached a predetermined level, the comparison voltage V1 is about 2.8V, while the output voltage Vo of the comparison voltage unit 55 is kept constant at about 2.5V. That is, the comparator A3 has a magnitude relationship of [input voltage to plus input]> [input voltage to minus terminal], but the output part of the comparator A3 is an open collector (see FIG. 5 (f)). As shown in FIG. 4, since the output terminal is not pulled up, the output section of the comparator A3 is opened and does not affect other circuits.

  The operation of the power supply monitoring unit 54 described above is organized as follows.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the resistor R8 is short-circuited by the output part of the comparator A3, so that the voltage Vs across the resistor R8 becomes approximately 0V.

  (2) Thereafter, when the power supply voltage Vcc increases to near the normal level, the output part of the comparator A3 is opened, so that the voltage Vs across the resistor R8 is approximately 4.5 V corresponding to the voltage across the Zener diode ZD3. It becomes.

  (3) When the AC voltage AC24V is cut off, the voltage Vs across the resistor R8 quickly drops to 0V. However, even if the AC voltage AC24V is cut off, the power supply voltages Vcc and VB maintain a predetermined level for a while, so that the output unit of the comparator A3 maintains the open state as it is.

[Comparison voltage unit 55]
The comparison voltage unit 55 includes diodes D14 and D15 that receive two power supply voltages Vcc and Vcc generated separately by the first power supply unit FR and the second power supply unit SD at respective anode terminals, and cathodes of the diodes D14 and D15. A current limiting resistor R9 connected to the terminal and the voltage generator GN are connected in series. In this embodiment, a shunt regulator (HA17431: RENESAS) is used as the voltage generator GN.

  This shunt regulator has an anode terminal A, a cathode terminal K, and a comparison terminal REF. In the state shown in the figure, in which the anode terminal A and the cathode terminal K are connected, the shunt regulator functions in the same manner as a Zener diode. A constant reference voltage Vo (2.5 V) is output between the anode and cathode terminals (see FIG. 5E). On the other hand, during the non-breakdown operation, the internal circuit is turned OFF, and the anode and cathode terminals are opened.

  Therefore, when the power is turned on, until the power supply voltage Vcc reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 (voltage generation unit GN) corresponds to the power supply voltage Vcc whose level is rising, Vo = Vcc−Vf. −Δ. On the other hand, when the power supply voltage Vcc reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 becomes a constant comparison reference voltage (2.5 V).

[Abnormality detection unit 56]
The abnormality detection unit 56 includes a comparator A1 that generates a power supply abnormality signal ABN1 to the main control unit 21, a comparator A2 that generates a power supply abnormality signal ABN2 to the payout control unit 24, and pull-up resistors R10 of the comparators A1 and A2. , R11 and a capacitor Cs connected between the input terminals of the comparators A1, A2. The output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminals of the comparators A1 and A2, and the voltage Vs across the resistor R8 is supplied to the plus terminal. The comparators A1 and A2 are built in the QUAD comparator (NJM2901) described above.

  Although not shown, power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 are supplied to input ports of the main control unit 21 and the payout control unit 24. An appropriate capacitor is connected between the input terminal of each input port and the ground, and each input port receives a power supply abnormality signal via an appropriate resistor to ensure noise resistance. . In addition, the effects of spike noise are eliminated by appropriate software processing.

  Since the power supply monitoring unit 54 operates as described above in (1) to (3), the abnormality detection unit 56 operates as follows in response to this.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the voltage Vs across the resistor R8 is almost 0V, while the output voltage Vo of the comparison voltage unit 55 corresponds to the power supply voltage Vcc whose level is rising. Vcc−Vf−Δ. Therefore, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 stably maintain the L level without changing the level. Timings T0 to T1 in FIG. 5C show a stable L level state when the power is turned on.

  (2) Thereafter, after the power supply voltage Vcc whose level is rising exceeds a predetermined level, the output voltage Vo of the comparison voltage unit 55 is maintained at 2.5V. Further, when the power supply voltage Vcc increases to near the normal level, the output part of the comparator A3 is opened, so that the voltage Vs across the resistor R8 becomes approximately 4.5V corresponding to the voltage across the Zener diode ZD3.

  Therefore, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 transition to the H level, and thereafter the H level indicating the normal state is constantly maintained. After timing T1 in FIG. 5C, the power supply abnormality signals ABN1 and ABN2 at normal levels are shown.

  (3) Thereafter, when the AC voltage AC24V is cut off for some reason, the voltage Vs across the resistor R8 quickly drops to 0V. However, since the power supply voltages Vcc and VB are maintained at a predetermined level for a while, the comparator A3 and the comparison voltage unit 55 maintain the operation so far.

  Therefore, when the AC voltage AC24V is cut off at the timing T2 in FIG. 5A, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 immediately transition from the H level to the L level to cause an abnormal situation. Indicates occurrence. The main control unit 21 and the payout control unit 24 regularly check the power supply abnormality signals ABN1 and ABN2, and immediately confirm that the power supply abnormality signals ABN1 and ABN2 have transitioned to the L level. It is supposed to start.

[Power reset unit 57]
Next, the power reset unit 57 composed of the comparator A4 will be described. As illustrated, a pull-up resistor R12 is connected to the output terminal of the comparator A4, and a series circuit of a resistor Rf and a capacitor Cf is connected between the output terminal and the plus terminal. Further, the output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminal of the comparator A4, and the comparison voltage V2 of about 2.95V is supplied to the plus terminal in the steady state. The comparison voltage V2 is generated by dividing the two types of power supply voltages Vcc and VB generated by the second power supply unit SD with resistors.

  Since the power reset unit 57 is configured as described above, it operates as follows.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the output voltage Vo of the comparison voltage unit 55 becomes Vcc−Vf−Δ corresponding to the power supply voltage Vcc whose level is rising. On the other hand, since the comparison voltage V2 is generated by dividing the power supply voltages Vcc and VB of the second power supply unit SD, it is lower than the output voltage Vo during the level increase. Therefore, in such a transient state, the system reset signal SYS output from the comparator A4 becomes L level (see FIG. 5A).

  (2) Thereafter, after the power supply voltage Vcc whose level is rising reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 is maintained at 2.5V. Further, when the power supply voltages Vcc and VB increase to near the normal level, the comparison voltage V2 approaches the steady value 2.95V. Therefore, the system reset signal SYS output from the comparator A4 transitions from the L level to the H level at an appropriate timing. The system reset signal SYS has a voltage value of TTL level.

  The system reset signal SYS generated in this way is transmitted to the effect control unit 22 and the image control unit 23 via the effect interface board 27, and is provided in each control unit 22 and control unit 23. The power of the CPU and other ICs is reset via the delay circuit. Note that the series circuit of the resistor Rf and the capacitor Cf also exhibits a function of delaying the transition operation.

  As described above, since the system reset signal SYS is generated based on the DC voltage, the system reset signal SYS does not change to the active level in the instantaneous power failure state where the AC power supply is momentarily stopped. Therefore, even if the AC power supply is cut off, the sub-control units 22 and 23 continue to operate as long as the DC power supply is maintained.

  Returning to FIG. 3, the circuit configuration will be described. The main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 28, while the payout control unit 24 receives a game ball. The award ball counting signal indicating the payout operation, the status signal CON related to the abnormality of the payout operation, and the operation start signal BGN are received as the status signal CON. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the dispensing control unit 24 has been completed after the power is turned on.

  Here, the one-chip microcomputers of the main control unit 21 and the payout control unit 24 operate with a power supply voltage of 5 V, and the control commands CMD, CMD "and other signals are all at the TTL level.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with a power supply voltage VB (12 V) supplied from the main control unit 21. Each switch signal indicating a winning state to the symbol starting port 15 is converted to a TTL level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). Then, the data is transmitted to the main control unit 21.

  As shown in FIG. 6, the effect control unit 22 stores a one-chip microcomputer 22A for executing processing such as voice effect, lamp effect, notice effect by effect movable body, and data transfer, and a control program for the one-chip microcomputer 22A. EPROM 61 to perform, audio reproduction output circuit (audio IC) 62 that reproduces and outputs an audio signal based on an instruction from the one-chip microcomputer 22A, and audio that stores compressed audio data that is original data of the audio signal to be reproduced A memory (audio ROM) 63 and a reset circuit 64 for resetting the one-chip microcomputer 22A.

  The reset circuit 64 receives the system reset signal SYS from the power supply board 20 to reset the power supply of the one-chip microcomputer 22A, and abnormally resets the one-chip microcomputer 22A based on the operation of the watchdog timer WDT1 when the program runs away. The audio reproduction circuit 62 may be reset by the reset circuit 64, or may be reset by the one-chip microcomputer 22A receiving the system reset signal SYS outputting a reset signal.

  The one-chip microcomputer 22A has a parallel output port P1 and a parallel input port P2. The output port P1 also outputs drive data Φ1 to Φ4 for causing the effect movable body to function together with the control command CMD ′ and the strobe signal STB ′. The effect movable body is rotated by a stepping motor MT driven by the driver circuit DR to execute a movable effect. An origin switch ORG is provided in relation to the stepping motor MT, and the switch signal SN is input to the input port P2.

  As shown in FIG. 6, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 pass through the buffer 67 of the presentation interface board 27 to the one-chip microcomputer 22A of the presentation control board 22. Is supplied. The interrupt signal STB is supplied to the interrupt terminal INT of the one-chip microcomputer, and the effect control unit 22 acquires the control command CMD by the reception interrupt process activated by the strobe signal STB.

  The control command CMD acquired by the effect control unit 22 includes (1) an abnormality notification and other notification control commands, and (2) a control for specifying an outline of various effect operations resulting from winning at the symbol start opening. Commands (variation pattern commands) are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of winning or failing in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 acquires the variation pattern command CMD, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified.

  For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking the LED group and a sound effect preparation operation by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. The control command CMD ′ related to the rendered symbol effect is output.

  In order to realize such a symbol effect synchronized with the effect operation, the effect control unit 22 outputs a control command CMD ′ to the effect interface board 27 together with a strobe signal (interrupt signal) STB ′ for the image control unit 23. To do. When the notification control command related to the display device or other control commands is received, the effect control unit 22 outputs the control command to the effect interface board 27 together with the interrupt signal STB ′. .

  Corresponding to the configuration of the effect control board 22 described above, an output buffer circuit 65 capable of outputting an 8-bit control command CMD ′ and a 1-bit strobe signal STB ′ is provided, and these data CMD ′ and STB ′ are provided. Is output to the image control board 23. Here, the control command CMD ′ and the strobe signal STB ′ output from the output buffer circuit 65 are transmitted at a TTL level with a power supply voltage of 5 V, and a sufficient noise margin is provided in the transmission path to the image control unit 23. have. This also applies to the system reset signal SYS.

  The effect interface board 27 receives a signal for driving the lamp output from the effect control unit 22, supplies the signal to the LED lamp group via the lamp connection board 68, and the sound output from the sound reproduction output circuit 62. The signals AOR and AOL are supplied to the speaker via the digital amplifier 66. As described above, the effect control unit 22 of the present embodiment realizes the lamp effect and the sound effect corresponding to the control command CMD received from the main control unit 21 via the interface board 27.

  Next, the configuration of the image control board 23 will be described. As shown in FIG. 6, the image control unit 23 includes a composite chip 41 (SOC: system-on-a-chip) that includes a computer circuit that controls the image effect operation and a computer circuit that drives the display device DISP. It is structured in the center. The composite chip 41 of the embodiment is composed of TC8520XBG (TOSHIBA), which incorporates ARM1176 (ARM Advanced RISC Machines) as a built-in processor and a 3D-graphics processor, and is based on a three-dimensional image. The image production is executed.

  Then, the image control unit 23 resets the composite chip 41 and other ICs based on a power supply unit 42 that generates a DC voltage for operation of the composite chip 41 and a system reset signal SYS received from the effect interface board 27. A reset unit 43, a control ROM 44 for storing a control program for image production, a CGROM 45 for storing graphics data in a data compression state, a VRAM (Video RAM) 46 for image output, and the composite chip 41. And an LVDS interface unit 47 (low voltage differential signaling) that converts the RGB signal to a differential signal.

  FIG. 7 is a configuration diagram illustrating the internal configuration of the composite chip 41 together with other ICs connected thereto. As described above, the composite chip 41 according to the embodiment includes the embedded processor 70 (ARM 1176) and the 3D graphics processor 71. The inside of the composite chip 41 is composed of a 3.3V power supply line for realizing input / output operations with an external device such as a ROM, a 1.2V power supply line for operating processors, and an SDRAM (Dynamic Random Access Memory). The VRAM 46 is separated into a 1.8V power supply line that realizes DDR (Double Data Rate) operation and a 2.5V power supply line for the built-in DRAM 76 (Embedded DRAM), realizing high speed with low power. doing.

  As shown in the figure, the composite chip 41 is connected to a control ROM 44 and a CGROM 45 having a power supply voltage of 3.3 V via a ROM interface unit 73. Here, the control ROM 44 is accessed in units of a data length of 32 bits based on a 23-bit length address signal, and has a storage capacity of 8,388,608 × 16 × 2 bits. The CGROM 45 is accessed in units of a data length of 32 bits based on a 26-bit length address signal and has a storage capacity of 4 Gbits × 4 bits.

  On the other hand, the composite chip 41 is connected to a VRAM 46 having a power supply voltage of 1.8 V via a DDR2 interface unit 74. The VRAM 46 is accessed in units of a data length of 32 bits and has a storage area of 4 Gbit length. Here, the address signal line and the data signal line for the VRAM 46 are provided separately from the address signal line and the data signal line for the control ROM 44 and the CGROM 45, and the difference in the power supply voltage does not cause a problem. Electricity is realized.

  The embedded processor 70 receives the control command CMD ′ and the strobe signal STB ′ from the effect interface board 27 via the parallel port 79. On the other hand, the graphics processor 71 operates by being connected to the built-in DRAM 76, and outputs RGB signals and synchronization signals to the LVDS unit 47 via the LCD interface unit 77.

  In addition, the composite chip 41 includes a DMAC unit (Direct Memory Access Controller) 75, an audio output audio interface unit 78, a GPIO unit (General Purpose I / O) 80, a UART unit (Universal Asynchronous Receiver Transmitter) 81, and an SPI unit. (Serial Peripheral Interface) 82 is provided, but is not particularly used in this embodiment.

  FIG. 8 is a diagram for explaining the connection relationship between the composite chip 41 and the effect interface board 27 and the operation of the composite chip 41. As shown in the drawing, the 8-bit control command CMD 'and the 1-bit strobe signal STB' transmitted from the effect interface board 27 are supplied to the image control board 23 via the connector CN1. Since all these 9-bit signals are at the TTL level in order to secure a noise margin on the transmission path, it is necessary to convert them to a level that can be recognized by the parallel port 79 of the composite chip 41.

  Therefore, all 9-bit signals are pulled up to 3.3V by 9 pull-up resistors PU, and then passed through filter circuits CR each composed of 9 capacitors C and resistors R. It is supplied to the buffer BUF1. The three-state buffer BUF1 is a Schmitt trigger type in which the power supply voltage is 3.3V.

  Here, the time constant C * R of the filter circuit is set to about 0.5 to 2.0 μS, and high frequency noise superimposed on the transmission line is eliminated without dulling all 9-bit signal edges so much. doing. Further, since the tristate buffer BUF1 is a Schmitt trigger type, the waveform dulled by the CR circuit is correctly shaped, and the logic level of each signal CMD ′, STB ′ that has dropped from the TTL level is the parallel port 79 of the composite chip 41. Is recognized correctly.

  As shown in the middle part of FIG. 8, the DC voltages 12V and 5V and the system reset signal SYS are transmitted to the connector CN2 of the image control board via the effect interface board 27. The DC voltage 12V is supplied to a fan motor (DC motor) FAN that constantly air-cools the composite chip 41. Further, the sensor output indicating that the fan motor FAN is rotating is lowered in level via a resistor R20 pulled up to a DC voltage of 3.3 V, a resistor R21 and a capacitor C21 constituting a filter circuit. . The sensor signal FNPLS is supplied to the input port of the composite chip 41 through two NOT gates G1 and G2 having a power supply voltage of 3.3V.

  Here, the fan motor FAN of the embodiment is set to rotate at a rotational speed of 5500 rpm (error ± 20%) upon receiving a DC 12V power supply. Further, since the sensor signal FNPLS is configured to output two pulses (duty ratio 50%) for one rotation of the fan motor FAN, the pulse period of the sensor signal FNPLS is 60/5500 / 2≈5 when normal. .45 mS (error ± 20%).

  By the way, in this embodiment, the single composite chip 41 is used to execute the image control operation by the embedded processor 70 and the generation of the image signal by the graphics processor 71. Since the circuit elements are integrated on a single chip, the total power loss is not small even though each part operates with a low power supply voltage. For this reason, if the rotational speed of the fan motor FAN is reduced due to a drop in the power supply voltage (12V) or clogging with dust, a predetermined air cooling function cannot be exhibited. Therefore, in this embodiment, the rotation speed of the fan motor FAN is constantly monitored, and the normal operation of the composite chip 41 is maintained. The control process based on the sense signal FNPLS will be described finally with reference to FIG.

  By the way, the system reset signal SYS supplied from the effect interface board 27 to the connector CN2 is supplied to the NOT gate G3 via the filter circuit including the resistor R23 and the capacitor C22. The resistor R23 is pulled up to a DC voltage of 5V by the resistor R22. The output of the NOT gate G3 is supplied to the control terminal EN of the power sequencer 83 after the logic level is converted by the NOT gate G4 in the next stage. The control terminal EN is pulled up to a DC voltage of 5V by a pull-up resistor R24.

  The power sequencer 83 is realized by, for example, LM3881 (Power Sequencer). When the voltage of the control terminal EN rises, the first control signal EN1 rises after a predetermined time t1, and the second control signal EN2 is delayed by t2 after that. It is configured to stand up. On the other hand, when the voltage at the control terminal EN falls, the second control signal EN2 first falls after a predetermined time t3, and the first control signal EN1 falls after t4 (see FIG. 8B). )reference).

  Here, the first control signal EN1 is supplied to the control terminal of the DC / DC converter 84 to control the conversion operation. This DC / DC converter 84 is a circuit that converts 5V DC received from the production interface board into 1.2V DC. The converted 1.2V is used as the power supply voltage for the embedded processor 70 of the composite chip 41. The composite chip 41 is supplied.

  On the other hand, the first control signal EN2 is supplied to the control terminals of the DC / DC converters 85 and 87 and the voltage regulator 86, respectively, to permit or prohibit the operation of each element. Here, the DC / DC converter 85 and the DC / DC converter 86 convert the direct current 5V received from the effect interface board into direct current 1.8V and direct current 3.3V, respectively. The direct current 1.8V is supplied to the composite chip 41 as the power supply voltage of the DDR2 interface unit 74, and the direct current 3.3V is supplied to the composite chip 41 as the power supply voltage of the ROM interface unit 73. It is also used as a power supply voltage for the ROM 45 for the machine. Further, the voltage regulator 86 drops the direct current 5V received from the effect interface board to the direct current 2.5V, and the lowered direct current 2.5V is supplied to the composite chip 41 as the power supply voltage of the built-in DRAM 76.

  As described above, in this embodiment, the power sequencer 83 controls the power activation sequence and the power shutdown sequence for each power voltage required for the composite chip 41. Specifically, the power supply voltage 1.2V is first supplied to the composite chip 41 to start up the embedded processor 70, and then other circuits are started up. On the other hand, when the power is shut off, the DC power source 1.2V of the embedded processor 70 is maintained until the end (see FIG. 8B).

  The power supply voltage start-up sequence and shut-off sequence have been described above, but the control signal EN for controlling them is also supplied to the input terminal of the negative logic OR gate G5. Here, the power supply voltage of the negative logic OR gate G5 is 3.3V, but the abnormal signal ERR of the watchdog timer WDT is supplied to the other input terminals. The watchdog timer WDT receives the clear pulse WDLR periodically from the composite chip 41. However, when the clear pulse WDLR is interrupted due to a program runaway or the like, the watchdog timer WDT outputs an L level abnormal signal ERR. Has been.

  Therefore, when the system reset signal SYS is at L level or the abnormal signal ERR is at L level, the output of the negative logic OR gate G5 is also at L level. The L level signal is supplied to the reset terminals of the control ROM 44 and the CGROM 45 via two NOT gates G6 and G7. The output of the NOT gate G7 is further supplied to the reset terminal SYSRESET of the composite chip 41 via the NOT gates G8 and G9.

  Here, the delay time τ caused by the control signal EN passing through the five gates G5 to G9 is set longer than the delay time t1 + t2 of the second control signal EN2 with respect to the control signal EN (FIG. 8C). reference). Therefore, a necessary reset time TM (= τ−t1) is ensured from the start of the power supply voltage 1.2V controlled by the first control signal EN1 to the rise of the reset signal SYSRESET to the composite chip 41. In addition, since a margin time (τ−t1−t2) from when all the power supply voltages are stabilized is ensured, normal startup operations of the embedded processor 70 and the graphics processor 71 are ensured (FIG. 8C). reference).

  Further, even when the system reset signal SYS falls at the time of power shutoff (T2 in FIG. 5) (T3 in FIG. 5), the power supply voltage (= 1.2V) of the embedded processor 70 is maintained longer than other power supply voltages. Therefore, the occurrence of an abnormal screen or the like of the display device DISP is prevented even during a power failure. Since all the power supply voltages 1.2V to 3.3V are maintained for a predetermined time by charging the power supply capacitor, the embedded processor 70 and the graphics processor 71 are normally reset even when the power is shut off.

  FIG. 9 is a circuit block diagram showing a connection relationship between the composite chip 41, the CGROM 45, the control ROM 44, and the address decoding unit 50 that generates a chip select signal of each memory IC. As illustrated, the composite chip 41 is connected to each IC via a 29-bit address bus and a 32-bit data bus. FIG. 9 shows only the 3.3V system memory circuit, and does not show the VRAM 46 connected by the 1.8V system address bus or data bus.

  First, the control ROM 44 will be described. The control ROM of the embodiment is composed of two flash memory ICs (MX29GL128EHMC-90G) that operate with a power supply voltage of 3.3V. This memory IC has the internal configuration shown in FIG. 10A and has a storage capacity of 8,388,608 × 16 bits. Further, when the output control signal OE is set to L level while the chip select signal CE is at L level, a 16-bit length data read operation selected by the 23-bit length address signal (A0 to A22) is realized ( (Refer FIG.10 (b)).

  Therefore, in this embodiment, the control signal of the composite chip 41, the output signal of the decoder 52, and the 3-bit length address signals A23 to A25 are supplied to the logic circuit 51 constituting a part of the address decoding unit 50. Thus, the chip select signal CE and the output control signal OE shown in FIG. 10B are generated. The power supply voltage of the logic circuit 51 is 3.3V.

  Here, in the case of a normal circuit configuration, the output of the logic circuit 51 is supplied to the flash memory IC as it is, but in this embodiment, the chip select signal CE and the output control signal OE are supplied via the collective resistor ARY0. ing. In such a configuration, when a memory IC having a low power supply voltage (power supply voltage = 3.3 V) is accessed at high speed, the control signals CE and OE are controlled regardless of the signal line length of the control signals CE and OE. In order to suppress ringing, an aggregate resistor ARY0 of about 50 to 100Ω is connected in series as a damping resistor to two signal lines. Therefore, according to the present embodiment, even if the control ROM 44 is accessed at a high speed in order to execute complicated and sophisticated image effects, malfunctions such as reading errors in the control program do not occur regardless of the low power supply voltage.

  Conversely, when the configuration of this embodiment is not employed, a high level undershoot occurs at the rising edge of the signal due to the L component of the signal line and the stray capacitance component between the signal line and the ground. There is a risk of erroneously recognizing data at the L level. Note that even if a smoothing capacitor is arranged between the signal line and the ground, the duration of the undershoot is prolonged, and there is a concern about the same problem.

  The control signals CE and OE are supplied in parallel to the two flash memory ICs constituting the control ROM 44. Correspondingly, a common 23-bit length address signal is supplied to each memory IC. Yes. Therefore, each memory IC outputs the data of the same address selected by the address signal in a 16-bit length, and is supplied to the data bus, so that the 32-bit length of data (actually a program code) and Become.

  As described above, it is necessary to supply a 23-bit address signal to the control ROM 44. Therefore, in relation to this point, in this embodiment, the 26-bit length (A0 to A25) of the address bus of the composite chip 41 is changed from the 16-bit length (A0 to A15) and the 10-bit length (A16 to A25). A part (A0 to A22) is supplied to the control ROM 44 via the bus buffers 55 and 56 and the collective resistor ARY, respectively. As the bus buffers 55 and 56, for example, a 16-bit bus buffer SN74LVCH16244A is used and operates at a power supply voltage of 3.3V.

  By the way, the address signals (A0 to A22) are supplied to the control ROM via the collective resistor ARY in the high-speed memory access with the low power supply voltage regardless of the length of the address signal line A0. This is in order to suppress ringing of .about.A22. Here again, each signal line is connected in series with a collective resistance ARY of about 50 to 100 .OMEGA. As can be seen from the time chart of FIG. 10B, in a high-speed memory access with a low power supply voltage, if a high level undershoot occurs at the rising edge of the address signal, the target address may not be accessible.

  As shown in FIG. 9, the 26-bit address signals (A0 to A25) output from the collective resistor ARY are supplied to the CGROM 45. Here, the CGROM 45 is a PROM (Programmable Read Only Memory) having a storage capacity of 4 Gbits, and for example, MSP88LV040 (FUJITSU) is used. The power supply voltage of the memory IC constituting the CGROM 45 is 3.3V.

  As shown in the block diagram of FIG. 11, the MSP 88LV040 is divided into four blocks (H1, H0, L1, L0) each having a storage capacity of 1 Gbit length. Each storage block is addressed from address 0 to address 67108863 by address signals A0 to A25, and 16-bit data can be read from each address.

  Which of the four storage blocks (H1, H0, L1, L0) is selected is controlled by the chip select signal CE and the output control signal OE. In this embodiment, the H1 block and the L1 block are simultaneously selected. In order to access, the CEH1 terminal and the CEL1 terminal are externally connected, and the OEH1 terminal and the OEL1 terminal are externally connected.

  Further, in order to simultaneously access the H0 block and the L0 block, the CEH0 terminal and the CEL0 terminal are externally connected and the OEH0 terminal and the OEL0 terminal are externally connected.

  Therefore, for example, when the chip select signal CE7 (see FIG. 11) becomes L level, the H1 block and the L1 block are simultaneously selected, and the 16-bit length data selected by the address signals A0 to A25 is the L level of the output control signal OE7. The signals are output to the output terminals DQH0 to 15 and the output terminals DQL0 to 15, respectively, at the timing when the level is reached.

  As shown in FIG. 9, since the output terminals of the memory IC constituting the CGROM 45 are connected to a 32-bit data bus, this embodiment eventually has a 32-bit length based on the address signals A0 to A25. CG data is read out. In the address space of the CGROM 45, addresses 67, 108, and 864 selected by the chip select signal CE0 are the lowest order, and hereinafter, in the order of addresses 67108864 selected by the chip select signal CE1 → CE2... → CE7. In total, 67,108,864 × 8 × 32 = 16 Gbits.

  FIG. 12 is a time chart showing the operation of the CGROM 45 when reading data. As shown in the figure, when the output control signal OE is set to L level in a state where the chip select signal CE is at L level, the 16-bit length selected by the 26-bit length address signal (A0 to A25) (32 in the configuration of the embodiment). (Bit length) data read operation is realized (see FIG. 12A).

  In addition, the CGROM 45 is configured to allow not only the normal memory read operation described above but also a page read operation. In this case, by changing the lower 3 bits of the address signals A0 to A2 in a state where the upper 20 bits of the address signals A3 to A24 are fixed, the data at the 8 consecutive addresses in one page read cycle is changed. Can be read sequentially. In FIG. 12B, for the sake of convenience, the address change (Aa → Ab → Ac) is three times, but by changing the address signals A0 to A2 from 000 → 001 → 010 →. , Eight address changes are possible.

  In order to smoothly move a clear 3D image and realize a novel moving image effect, the amount of data handled becomes enormous. However, in this embodiment, by utilizing the above-described memory read operation, a large amount of necessary CG data is quickly read out from the CGROM 45, and is output to the display device DISP through a predetermined calculation. Realized.

  By the way, in order to realize such a moving image effect, data access in units of 32 bits is required, and for that purpose, eight types of chip select signals CEi and eight types of output control signals OEi are required. Therefore, the address decoding unit 50 receives a 3-bit length address signal A26-A28 and generates eight types of chip select signals CEi, a collective resistor ARY1 that receives the 8-bit output of the decoder 52, and a collective resistor The logic circuit 53 that receives the output of ARY1 and the control signal of the composite chip 41 and generates eight types of output control signals OEi and the collective resistor ARY2 that receives the output of the logic circuit 53 are connected.

  Here, the decoder 52 is a general-purpose 3-8 decoder, and for example, SN74LVC138A is used and operates at a power supply voltage of 3.3V. The collective resistors ARY1 and ARY2 are composed of eight resistors of about 50 to 100Ω, and each function as a damping resistor that suppresses undershoot of the signal line. In the embodiment, 75Ω is adopted as the collective resistors ARY, ARY0 to ARY2.

  The logic circuit 53 is a circuit that operates at a power supply voltage of 3.3 V and generates an output control signal OE based on the chip select signal CE.

  As shown in FIG. 9, the eight types of chip select signals CE and the eight types of output control signals OE are all supplied to the corresponding terminals of the CGROM 45 via the collective resistors ARY1 and ARY2. The 26-bit address signals A0 to A25 are also supplied to the corresponding terminals of the CGROM 45 via the collective resistor ARY.

  Therefore, as described above, even when the CGROM 45 is accessed at high speed by a page read operation or the like at a low power supply voltage of 3.3 V, no malfunction occurs.

  The 32-bit CG data read out in this way is transmitted to the data bus of the composite chip 41 via the bus buffer 54. Here, the bus buffer 54 is composed of two general-purpose 16-bit bus buffers (SN74LVCH16244A), each operating at a power supply voltage of 3.3V. The bus buffer 54 is pulled down to the ground by a collective resistor ARY3 of about 1 to 5 KΩ. With this configuration, impedance matching between the output impedance of the bus buffer 54 and the signal line (data bus) is taken. Therefore, the reflection of the signal (CGROM data) can be prevented regardless of the length of the signal line of the data bus, and the reliability of the generated high-quality moving image is ensured.

  FIG. 13 is a flowchart for explaining the operation of the embedded processor 70 of the composite chip 41 constituting the image control unit 23. As illustrated, the image control unit 23 is activated every 10 mS, the main process (a) that is started when the embedded processor 70 is reset, the first timer interrupt process (c) that is activated every 50 μS. Second timer interrupt processing (d). Note that the reception interrupt processing of the control command CMD 'is not shown in FIG.

  As shown in FIG. 13A, in the main process (the reset process of the embedded processor 70), the initial setting in the composite chip 41 is executed (ST1), and then the backup determination process is executed (ST2). The backup determination process is a process for determining the validity of the data stored in the backup process (ST14). The data stored in the backup process (ST14) is not particularly limited. For example, (1) the sum value of the checksum operation for the predetermined data in the RAM work area, (2) the specific data stored discretely in the RAM work area Data, (3) Backup data in which predetermined data in the RAM work area is stored in another area can be exemplified.

  In the backup determination process, it is also determined whether an important operation flag indicating the operation state is irrational. The irrationality in the operation flag is, for example, a case where both the operation flag indicating that the variation effect is being performed and the operation flag indicating that the jackpot operation is being set. In this gaming machine, after the variation effect is finished, the game shifts to a big hit operation, so the two operation flags cannot be set at the same time. If such a situation is detected, other saved data is stored. Even if legitimacy is recognized, it judges that it is not normal.

  If the validity cannot be confirmed in the determination of step ST2 including such an exceptional case, the entire area of the RAM is initialized, and the image control unit 23 is cold-started to perform the process of step ST7. Transition (ST6). Conversely, if the backup determination is normal, the abnormality counter is incremented and it is then determined whether or not the value of the abnormality counter exceeds a predetermined value (for example, 2) (ST4 to ST5). When the value of the abnormality counter exceeds a predetermined value, the process proceeds to the RAM clear process in step ST6 to perform a cold start (ST5). This is because not all data is determined in the backup determination process (ST2), and therefore, when the embedded processor 70 is repeatedly reset, the operation of the image control unit 23 is returned to the initial state.

  Conversely, even if the embedded processor 70 is reset, if the backup determination (ST2) makes a correct determination and the number of abnormal resets is equal to or less than the predetermined value, the image control unit 23 is hot-started, The game operation is continued.

  When the above processing is completed, the embedded processor 70 is set to the interrupt permitting state (ST7), and then the random number value is updated (ST8), and a timer interrupt at an interval of 10 ms is waited (ST9). The updated random value is used to randomize the image effect operation.

  As shown in FIG. 13 (d), an interrupt flag is set every time the second timer interrupt occurs at an interval of 10 ms (ST40), so that the interrupt flag is repeatedly turned ON in step ST9 of the main process. To check. When the interrupt flag is turned ON, after resetting it to OFF, timer update processing is executed for various timers that manage the progress of the production scenario and the like (ST10).

  Subsequently, a command analysis process is executed for the control command received in the reception interrupt process (not shown) (ST11). The received command includes a notice command for specifying a notice effect in addition to a variation pattern command for specifying a series of image effects.

  When the command analysis process (ST11) is finished, an error process is executed (ST12), and an effect scenario for the image effect is created or updated (ST13). Next, the backup process (ST14) is executed. As the backup process, for example, not only the checksum calculation but also the process of storing specific data discretely, the process of storing all data in the work area, etc. Illustrated.

  Following the backup process, a clear process of the watchdog timer WDT (see FIG. 8) is executed (ST15). Finally, an air cooling check process for confirming that the fan motor FAN is operating normally is executed (ST16).

  FIG. 13B is a flowchart showing the air cooling check process (ST16). In the air cooling check process (ST16), first, the counter variable CT is incremented (ST20), and it is determined whether the incremented counter variable CT has reached the upper limit value MAX (ST21). Here, the upper limit value MAX is set to 100, for example, and in this case, 10 mS * 100 = 1 second has elapsed since the previous determination.

  Thus, when a predetermined time (1 second) has elapsed since the previous determination, the value of the count counter NUM is then determined (ST22). As shown in FIG. 13C, the count counter NUM is updated by the first timer interrupt process that is started every 50 μS. In the first timer interrupt, first, the output (sensor signal FNPLS) of the NOT gate G2 (FIG. 8) is acquired (ST30). Then, it is determined whether or not the sensor signal FNPLS has risen by comparison with the previous acquired value OLD (ST31). If a rising edge is detected, the count counter NUM is incremented (ST32). Next, the acquired value of the current sensor signal FNPLS is stored in the variable OLD, and the interrupt process is finished (ST33).

  As is apparent from the above processing, in the first timer interrupt processing (FIG. 13C), the sensor signal FNPLS is sampled at a sampling period of 50 μS, and the number of detections of the rising edge of the sensor signal FNPLS is counted.

  On the other hand, the determination in step ST22 of FIG. 13B is executed at intervals of 1 second, for example. Therefore, after all, the value of the count counter NUM determined in step ST22 is nothing but the number of rising edges of the sensor signal FNPLS detected in one second.

  As described above, the rotational speed of the fan motor FAN is set to 5500 rpm (error ± 20%) in this embodiment. Accordingly, at the time of the determination in step ST22, the value of the count counter NUM is originally within the range of 73 (= 0.8 * 5500/60) to 110 (= 1.2 * 5500/60).

  Therefore, when the rotational speed is clearly deviating from the normal range (73 to 110), it is determined that the fan motor FAN is not rotating normally, and error processing is executed (ST23). . As the error process (ST23), for example, an emergency measure such as outputting a warning screen to the display device DISP and stopping the rendering operation is taken. Then, including the normal time, the counter variable CT and the count counter are cleared (ST24).

  As described above, in this embodiment, since the air cooling process of the composite chip 41 is checked at intervals of 1 second, it is possible to prevent thermal runaway and damage of the IC element. In addition, since the fan motor FAN is comprised with the direct current motor, abnormality of direct current power supply can also be detected by determination of step ST22.

  As mentioned above, although the Example of this invention was described concretely, the concrete description content does not specifically limit this invention. In particular, the check time interval (1 second) of the fan motor FAN is merely an example and can be changed as appropriate. In the embodiment, the configuration in which the fan motor FAN is arranged on the composite chip 41 is exemplified. However, the fan motor may be arranged on the one-chip microcomputer of the effect control unit, and in this case, the rotational speed is checked. Is preferred.

  Note that circuit elements such as ICs constituting the image control unit are merely examples, and other circuit elements that function in a similar manner can be used. In the above embodiment, the power supply voltage of the one-chip microcomputer 22A of the effect control unit 22 is 5V. However, it is also preferable to set the power supply voltage to about 3.3V in order to reduce the power consumption. In such a case, the control command CMD received from the main control unit 21 and the system reset signal SYS received from the power supply board 20 are supplied to the one-chip microcomputer 22A by appropriately dropping the level from the TTL level. The circuit configuration for level drop is substantially the same as the circuit configuration of the image control unit 23.

  When the power supply voltage of the one-chip microcomputer 22A is set to 3.3 V, for simplicity, the control command CMD ′ transmitted through the path of the production control board 22 → the production interface board 27 → the image control board 23 has a power supply voltage of It may be transmitted at a low level of 3.3V. However, even in such a case, the system reset signal SYS is transmitted at the TTL level. This is to secure a noise margin in view of the importance of the system reset signal SYS. That is, if the system reset signal SYS falls to the L level due to noise, the rendering operation of the image control unit 23 and the rendering control unit 22 may be reset, and importance is placed on the importance of avoiding such an abnormality. .

  Needless to say, the present invention is not limited to a ball game machine, but can also be suitably applied to a slot machine (rotating-type game machine) or the like.

GM gaming machine 21 main control unit 23 sub control unit FAN blower fan monitoring means ST16

In order to achieve the above object, the present invention provides a main control means having a first computer circuit that executes a lottery process caused by a predetermined switch signal and centrally controls gaming operations based on the lottery result. A sub-control unit having a second computer circuit including a control processor for controlling the image effect based on an instruction from the main control unit , and an image processor for generating image data to be displayed on the display device, and an AC voltage And a power supply means having a plurality of power supply circuits that generate DC voltages of various voltage levels based on the rectified voltage obtained by rectifying the first computer circuit , the first computer circuit having a basic logic level While the second computer circuit operates with a DC power supply voltage, the second computer circuit is configured to operate with a plurality of low-level DC power supply voltages that are 70% or less of the basic logic level. Is, the sub-control means includes a blower fan for cooling the second computer circuit, monitoring means for continuously monitoring the rotation of the blower fan, and a DC motor for rotating the blowing fan based on the DC voltage received from power supply means, The monitoring means is realized by the control processor receiving a sensor signal output from the blower fan in response to the rotation of the blower fan, and the control processor determining the sensor signal, and the direct current motor The display device can be notified of abnormal rotation of the blower fan, including the case of abnormal voltage of the DC voltage supplied to the fan.

  The gaming machine of the present invention is typically a ball game machine or a revolving game machine.

Claims (7)

A main control unit that executes a lottery process caused by a predetermined switch signal and centrally controls the gaming operation based on the lottery result, and a sub-control that executes an effect operation based on an instruction from the main control unit A gaming machine that is capable of shifting to a gaming state advantageous to the player when winning the lottery process executed by the main control unit,
The sub-control unit is configured to realize the rendering operation based on the control of the computer circuit that operates at a power supply voltage lower than the power supply voltage of the computer circuit that constitutes the main control unit, and blows air to the processor that controls the rendering operation A gaming machine characterized in that monitoring means for constantly monitoring the number of revolutions is provided.   The computer circuit of the sub-control unit has a single chip in which an image processor that generates image data to be displayed on the display device and a control processor that controls image effects based on instructions from the main control unit are integrated. The gaming machine according to claim 1 configured as described above.   The gaming machine according to claim 1 or 2, wherein the sub control unit executes a moving image effect in which a three-dimensional image moves smoothly.   A single chip of the sub-control unit is supplied with a first level power supply voltage for operating the control processor and a second level power supply voltage for operating the access circuit for accessing the image data and the control program. The gaming machine according to claim 2 or 3, wherein the gaming machine is configured as described above. The computer circuit of the sub-control unit includes a volatile memory that forms a work area for image display operation of the display device,
The gaming machine according to any one of claims 1 to 4, wherein an access circuit for accessing the volatile memory is configured independently of an access circuit for accessing image data and a control program.   The gaming machine according to any one of claims 1 to 5, wherein when the monitoring unit detects a decrease in the rotational speed of the blower fan, the monitoring unit stops the subsequent effect operation and executes an alarm operation.   The game machine according to any one of claims 1 to 6, wherein the blower fan is driven by a DC motor whose rotation speed varies in accordance with fluctuations in the supplied DC voltage.