JP2013128030A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form trench structures having different depth in a semiconductor layer composed of SiC in the same process.SOLUTION: A present manufacturing method is a manufacturing method of a semiconductor device having a configuration in which trenches having different depths are formed in a semiconductor layer composed of a silicon carbide (SiC) single crystal. The manufacturing method comprises the steps of: forming an amorphous layer in the semiconductor layer; and forming the trenches by wet etching the amorphous layer. The manufacturing method uses irradiation of light (laser beams) for forming the amorphous layer. On the semiconductor layer, absorption layers absorbing light are formed by patterning. Depths of the amorphous layers (trenches) are defined by pattern widths of the absorption layers.

Description

  The present invention relates to a method for manufacturing a semiconductor device using silicon carbide (SiC). The present invention also relates to a semiconductor device manufactured by this manufacturing method.

MOSFETs are used as various switching elements. Among them, a trench gate structure is known as an element (power MOSFET) driven by a large current.

When manufacturing such a semiconductor device, trenches having different depths may be formed in the semiconductor substrate. For example, in Patent Document 1, the outermost periphery trench in the actual operation region is formed deeper than the trench in the actual operation region, thereby reducing the electric field concentration at the bottom of the gate electrode in the outermost periphery of the actual operation region. (Or collector-emitter) is disclosed. If the same etching conditions are used, the larger opening width makes use of the property that the trench depth becomes deeper, and by changing the mask pattern for trench etching, trenches with different depths are formed in the same process. is there.
Further, in Patent Document 2, by forming a trench at the outermost periphery of the actual operation region shallower than the trench at the actual operation region, the electric field concentration at the bottom of the gate electrode at the outermost periphery of the actual operation region is alleviated, and the drain-source (or A technique for suppressing the breakdown voltage degradation between the collector and the emitter) is disclosed. By narrowing the outermost trench opening, trenches having different depths are formed in the same process.

    On the other hand, MOSFETs in which silicon carbide (SiC) is used instead of Si have been developed in recent years. Since SiC has a wider forbidden band than Si and it is easy to increase the breakdown voltage, this MOSFET is particularly used as a power element. Even when SiC is used, the trench gate type MOSFET described above is effective. However, since SiC has a crystal structure different from that of Si, has a close interatomic distance, and has a large bond energy between atoms, its etching is more difficult than Si.

For this reason, the etching time required in order to form the above trenches becomes long. Alternatively, the etching resistance of the mask is insufficient when a photoresist is used as a mask during dry etching. For this reason, when performing trench etching on SiC, dry etching using SF ₆ or HCl as a reactive gas and a metal such as nickel (Ni), tungsten (W) or cobalt (Co) as a mask is used. Has been done. Such a metal material can be used as a mask because it is resistant to dry etching using the above reaction gas.

  Patent Document 3 describes a technique in which ion implantation is locally performed on a semiconductor layer made of SiC, and an ion irradiation damaged layer formed by ion implantation is chemically removed by wet etching. In this technique, an ion irradiation damaged layer mainly composed of an amorphous layer in which the order of the crystal arrangement is disordered by locally ion-implanting a large amount of an electrically inactive element in SiC such as Ar. Form. In this ion irradiation damaged layer, since the bond energy between atoms becomes small, etching can be performed easily. In particular, it is possible to selectively chemically etch only the ion irradiation damaged layer without damaging the semiconductor layer by wet etching using hydrofluoric acid or the like.

  Using such a manufacturing method, a trench gate type MOSFET using SiC can be manufactured. The trench structure in the semiconductor layer is used for, for example, element isolation in addition to the trench gate type MOSFET. It is clear that this manufacturing method is effective even in such a case.

JP 2004-158680 A JP 2003-174166 A US Patent No. US-A1-5436174

  In the case of performing dry etching using a metal as a mask, it is necessary to etch the metal serving as a mask before etching the semiconductor layer. However, it is not easy to etch a metal material having high resistance in dry etching of SiC as described above, and it is particularly difficult to perform processing with high accuracy. In addition, since such a metal material becomes an electrically active impurity in SiC, it is necessary to use a configuration or process in which such a metal material does not diffuse into the active region of the MOSFET in the manufacturing process.

  On the other hand, in the technique described in Patent Document 3 using ion implantation, the depth of the ion irradiation damaged layer formed by ion implantation depends on the energy of the implanted ions. However, if the depth is set to about 1 μm, for example, a sufficient ion current cannot be obtained and the implantation time becomes long. Therefore, in practice, in order to form a trench having a depth of about 1 μm, it is necessary to repeat ion implantation and wet etching a plurality of times.

  Thus, it has been difficult to form a trench structure in a semiconductor layer made of SiC by a simple manufacturing process. In addition, it has been difficult to form trenches having different depths in the same process in a semiconductor layer made of SiC.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a structure in which at least two kinds of first and second grooves having different depths are formed in a semiconductor layer made of silicon carbide (SiC). In the method, the absorption layer forming step of locally forming an absorption layer for absorbing light on the surface of the semiconductor layer, and the absorption layer formation step, the openings in the first groove and the second groove Correspondingly, an absorption layer having a different pattern width is formed, an irradiation step of irradiating the semiconductor layer with light from the side on which the absorption layer is formed, and an amorphous formed on the semiconductor layer by the irradiation step An amorphous layer removing step of forming the groove by removing the layer by wet etching.
The semiconductor device of the present invention is manufactured by the method for manufacturing a semiconductor device.

  Since the present invention is configured as described above, trenches having different depths can be formed in the same process in a semiconductor layer made of SiC.

It is the result of having calculated the temperature distribution in a semiconductor layer at the time of irradiating a laser beam to the structure which formed the carbon cap layer on the semiconductor layer (SiC). ~ It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.

Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. This manufacturing method is a method for manufacturing a semiconductor device having a structure in which grooves having different depths are formed in a semiconductor layer formed of a single crystal of silicon carbide (SiC). Here, similarly to the technique described in Patent Document 3, an amorphous layer is formed in the semiconductor layer, and the groove is formed by wet etching the amorphous layer. In order to form this amorphous layer, the technique described in Patent Document 3 uses ion implantation, whereas in the method of manufacturing a semiconductor device according to the embodiment of the present invention, light (laser light) is used. ) Irradiation is used. As a result, the temperature of the semiconductor layer (SiC) rises rapidly and the crystal arrangement order is broken. Further, when the irradiation with the laser beam is completed, the heated portion is rapidly cooled, so that it is made amorphous. The heating temperature required for this is 1600 ° C. or higher.

  An absorption layer that absorbs light is formed on the semiconductor layer by patterning. The shape of the formed amorphous layer (groove) in plan view is defined by this absorption layer. When ion implantation is used as in the technique described in Patent Document 3, an ion irradiation damaged layer (amorphous layer) is formed only in a region where a mask is not formed. In this manufacturing method, An amorphous layer can be formed immediately below the absorption layer.

  This setting can be performed in consideration of the temperature distribution caused by the absorption layer absorbing the laser light and the wavelength of the light. As the light used here, laser light that can obtain high brightness and is monochromatic and easily controls absorption in the semiconductor layer is preferably used. In general, the laser beam has a small spot size, and by scanning this, for example, the entire surface of the semiconductor layer can be irradiated.

  A temperature distribution when a laser beam having a wavelength of 532 nm was irradiated with respect to a configuration in which an absorption layer made of graphite was formed on a semiconductor layer (SiC) was calculated. Since this wavelength is longer than the wavelength of light having an energy corresponding to the band gap of SiC (about 380 nm), it is not absorbed by SiC but is absorbed by graphite. For this reason, when using laser light of this wavelength, the laser light can be absorbed by the absorption layer to generate heat, and the semiconductor layer immediately below can be made amorphous.

  FIG. 1 shows a temperature distribution in a semiconductor when an absorption layer having a thickness of 100 nm is irradiated with laser light (with the absorption layer / SiC interface as the origin). The temperature at which SiC can be made amorphous is about 1600 ° C. From the results of FIG. 1, it can be seen that the surface of the semiconductor layer can be set to about 2800 ° C., and further, can be set to 1600 ° C. or more from the surface to a depth of about 1 μm. That is, an amorphous layer having a depth of 1 μm or more from the surface can be formed immediately below the absorption layer. As described in Patent Document 3, this amorphous layer can be easily removed by wet etching, and a groove having this depth can be formed.

  However, since SiC sublimes at a temperature of 2800 ° C. or higher, it is preferable that the surface of the semiconductor layer is set not to be 2800 ° C. or higher. Such setting can be performed by adjusting the spot diameter of the laser beam as shown in FIG. Alternatively, it can be performed by adjusting other irradiation conditions (scanning speed, etc.), wavelength, and absorption layer thickness of the laser beam. When the absorption layer becomes thick, the laser light is absorbed only at the upper part of the absorption layer, so that the heat generating part is only at the upper part of the absorption layer. In this case, since the distance from the heat generating portion to the surface of the semiconductor layer is increased, it is clear that the temperature of the surface of the semiconductor layer is lowered. For this reason, it is preferable to make the thickness of the absorption layer thin as long as the laser beam is sufficiently absorbed by the absorption layer. In other words, the wavelength of the laser beam is set to a wavelength at which absorption by SiC is small (a wavelength exceeding the wavelength of light having energy corresponding to the forbidden band width of SiC), and the absorber is within a range that can sufficiently absorb the laser beam. It is preferable to make it thin.

  Hereinafter, as an embodiment of the present invention, an example in which trenches having different depths are formed using the above-described absorption layer to manufacture a trench gate type MOSFET will be described. The material of the semiconductor layer constituting this MOSFET is SiC.

(First embodiment)
2A to 2J are process cross-sectional views illustrating the method for manufacturing the semiconductor device. FIG. 2 is a cross-sectional view in a direction perpendicular to the groove extending in the direction in which the gate extends in this trench gate type MOSFET, and MOSFETs having the same shape are manufactured in the cell side by side. The source electrodes in adjacent MOSFETs are shared. In addition, a plurality of trenches shallower than the trenches formed in the cell part are formed in the outer peripheral part surrounding the cell part.

First, as shown in FIG. 2A, a pre-implantation oxide film 2 for surface protection is formed on an n-type (first conductivity type) semiconductor substrate 1. Thereafter, as shown in FIG. 2B, an implantation mask for forming the p-type well region 4 is formed with a film thickness of 2 μm with the photoresist 3, and an energy of 200 to 400 keV, 5 × 10 ¹³ cm ^−. Al ions are implanted stepwise with a dose of about ² .
Next, as shown in FIG. 2C, an n ⁺ layer 5 is locally formed on the surface of the p-type well region 4 (source region forming step). The n ⁺ layer 5 is a region that becomes a source of the MOSFET, and an element that becomes a donor (for example, phosphorus (P)) has an energy of 50 to 200 keV using the photoresist layer 3 as a mask, and a dose of about 1 × 10 ¹⁵ cm ^−2. It is formed by ion implantation in quantity. The implantation mask in this case is formed with a film thickness of 1 μm. Further, as shown in FIG. 2D, a p ⁺ layer 6 is formed between the n ⁺ layers 5. The p ⁺ layer 6 is formed by ion-implanting, for example, aluminum (Al) with an energy of 50 to 150 keV and a dose of about 2 × 10 ¹⁵ cm ⁻² using the photoresist layer 3 having a thickness of 1 μm as an implantation mask. Is done.

As described above, the p-type well region 4, the n ⁺ layer 5 and the p ⁺ layer 6 are formed by ion implantation. Here, immediately after the ion implantation for forming the p-type well region 4 and the ion implantation for forming the n ⁺ layer 5 and the p ⁺ layer 6, the portions corresponding to these layers are due to irradiation damage due to ions. At this point, the p-type well region 4, the n ⁺ layer 5, and the p ⁺ layer 6 do not function electrically. In order to recrystallize these layers and activate the implanted acceptor and donor, a heat treatment step is performed. The temperature of this heat treatment step is, for example, about 1800 ° C., and these layers can function electrically as the p-type well region 4, n ⁺ layer 5, and p ⁺ layer 6 after this heat treatment step.

  Next, as shown in FIG. 2 (e), a carbon cap layer (absorption layer) 30 is formed at a location on the surface of the semiconductor substrate 1 where a trench is to be formed (absorption layer formation step). The carbon cap layer 30 is a layer made of graphite (graphite). As the formation method, for example, a graphite material is formed on the entire surface of the semiconductor substrate 1 by sputtering, and then a photoresist is applied, and exposure and etching are performed so that the carbon cap layer 30 is formed at a predetermined position. I do. Thereafter, the photoresist remaining on the formed carbon cap layer 30 can be removed with an organic solvent or the like. Conversely, after forming a photoresist layer at a location where the carbon cap layer 30 is to be formed, the photoresist layer is carbonized by performing a high-temperature heat treatment in an inert gas to thereby convert the photoresist layer into the carbon cap layer 30. Can also be altered. The thickness of the carbon cap layer 30 is, for example, about 100 nm.

  The carbon cap layer (absorption layer) 30 defines a pattern width so as to correspond to the depth of the trench to be formed. As shown in FIG. 1, the larger the laser diameter, the more amorphous SiC can be made to a deeper position at the same temperature. Therefore, by widening the carbon cap layer 30 in plan view, a trench having a wide opening width and a deep depth can be formed. Here, since the trench in the cell portion is formed deeper than the trench in the outer peripheral portion, the width of the carbon cap layer 30 in the cell portion in plan view is formed wider than that in the outer peripheral portion. Specifically, in order to be able to form a trench having a depth of 2 μm in the cell portion, the width in plan view of the carbon cap layer 30 is set to 4 μm, and a trench having a depth of 1 μm can be formed in the outer peripheral portion. Therefore, the width of the carbon cap layer 30 in plan view is 2 μm.

Next, as shown in FIG. 2 (e), in this state, the laser beam 100 is irradiated vertically from above to the substrate surface of the semiconductor substrate 1 (irradiation process). The laser beam 100 is in the form of a beam having a small spot size, and this is scanned over the entire upper surface. Further, the wavelength of the laser beam 100 is such that it is absorbed by the carbon cap layer 30 but is not absorbed by SiC, for example, 532 nm and 808 nm, which are longer wavelengths than the light of energy corresponding to the forbidden bandwidth of SiC. To do. For this reason, the laser beam 100 is absorbed only by the carbon cap layer 30 in FIG. 2E and passes through the exposed n ⁺ layer 5, p ⁺ layer 6, and the semiconductor substrate 1 immediately below them. The temperature of the carbon cap layer 30 that has absorbed the laser light 100 rises rapidly. If this temperature is lower than the melting point of graphite having a temperature of 3000 ° C. or higher, the carbon cap layer 30 becomes high temperature while maintaining its form. This heat is transferred to the n ⁺ layer 5 directly below, the p-type well region 4 and the like below, and these layers also have a high temperature.

As a result, immediately below the carbon cap layer 30, the n ⁺ layer 5, the p-type well region 4, and the semiconductor substrate 1 are locally heated. If this temperature is 1600 ° C. or higher, the crystallinity of SiC in these layers changes. Further, after the irradiation of the laser beam 100 is stopped, this region is rapidly cooled. Thereby, SiC in this region becomes amorphous. That is, as shown in FIG. 2E, the amorphous layer 7 is formed immediately below the carbon cap layer (absorbing layer) 30. The width of the amorphous layer 7 in plan view is defined by the carbon cap layer 30, and the depth of the amorphous layer 7 is also defined by the carbon cap layer 30 as described above.

Next, the carbon cap layer 30 is removed (absorbing layer removing step). The carbon cap layer 30 can be removed as CO ₂ (gas) by heat treatment in an oxygen atmosphere or oxygen plasma treatment. At this time, the semiconductor substrate 1 made of SiC is not affected.

Similar to the ion irradiation damaged layer in the technique described in Patent Document 3, the amorphous layer 7 does not maintain a crystal structure, so that it can be easily etched. For this reason, as shown in FIG. 2 (f), the amorphous layer 7 can be selectively removed chemically by, for example, wet etching using hydrofluoric acid (amorphous layer removing step). As a result, a trench 20 is formed at a location where the amorphous layer 7 has been formed. If the heat treatment after the source region formation step (heat treatment after ion implantation) has not been performed after the irradiation step, the ion-implanted layers (n ⁺ layer 5, p ⁺ layer 6, etc.) The corresponding region) is also removed simultaneously with the amorphous layer 7. In addition, when this heat treatment is performed after the irradiation step and before the amorphous layer removing step, the amorphous layer 7 is recrystallized and it is difficult to remove the amorphous layer 7 by wet etching. It becomes. For this reason, it is necessary to perform this heat treatment before the irradiation step.

Next, as shown in FIG. 2G, heat treatment is performed in an oxidizing atmosphere in this state to form a gate oxide film 8 (gate oxidation step). The gate oxide film 8 is formed by reacting SiC with O ₂ at a high temperature. At this time, CO and CO ₂ are also formed, but these are scattered as gas, so that the gate oxide film 8 becomes a layer mainly composed of SiO 2. Since this oxidation reaction occurs on the entire surface of SiC, the gate oxide film 8 is also formed on the side and bottom surfaces in the trench 20. This heat treatment is performed, for example, as dry or wet oxidation at a temperature of about 1300 ° C., and in order to use the gate oxide film 8 as a gate insulating layer of a MOS, the thickness is set to, for example, about 50 nm. This thickness can be adjusted by the heat treatment time.
In addition to the gate oxide film, a thermal nitride film, a CVD oxide film, a nitride film, Al ₂ O ₃ , or a combination thereof may be used as an insulator.

Next, a polycrystalline silicon layer (gate electrode) 9 is formed in the trench 20 in the cell portion (gate formation step). In order to form the polycrystalline silicon layer 9 in this form, after the polycrystalline silicon film is formed on the upper surface side of the semiconductor substrate 1, an etch-back is performed in which the polycrystalline silicon is anisotropically etched (dry etching) from the upper side. Just do it. At this time, it is preferable to form a polycrystalline silicon film by a CVD method or the like excellent in step coverage so that the trench 20 is filled with polycrystalline silicon. Polycrystalline silicon is doped with phosphorus or the like to impart conductivity. The polycrystalline silicon layer 9 functions as a MOS gate. A gate oxide film 8 exists between the polycrystalline silicon layer 9 and the semiconductor substrate 1, the p-type well region 4, the n ⁺ layer 5, and the p ⁺ layer 6, and the polycrystalline silicon layer 9 and the semiconductor substrate 1, The p-type well region 4, the n ⁺ layer 5, and the p ⁺ layer 6 are not in direct contact with each other.

Next, as shown in FIG. 2H, the interlayer insulating layer 10 is formed on the upper surface (interlayer insulating layer forming step). The interlayer insulating layer 10 is mainly composed of SiO ₂ like the gate oxide film 8, but the interlayer insulating layer 10 is used for insulation between the electrodes and between the electrodes and the semiconductor layer. It is formed sufficiently thicker than the gate oxide film 8.

Next, a source opening is formed as an opening for contact in the interlayer insulating layer 10 (contact opening process). This step is performed by dry etching of SiO ₂ using a photoresist as a mask.

Next, as shown in FIG. 2 (i), Ni electrodes are formed on both surfaces of the semiconductor substrate 1 at 1000 mm, contact annealing is performed at 950 ° C./2 min, and the n ⁺ layer 5, the p ⁺ layer 6, and A silicide layer 16 is formed on the semiconductor substrate 1 (silicidation process). Since the Ni electrode on the interlayer insulating layer 10 does not cause silicidation, it is removed with an etching solution such as persulfuric acid.
Thereafter, a gate opening is formed as an opening for contact in the interlayer insulating layer 10 in the same manner as when the source opening is formed.

  Finally, as shown in FIG. 2J, the source wiring 11 is formed so as to cover the source opening, the gate wiring is covered (not shown) so as to cover the gate opening, and the drain electrode 12 is formed on the back surface side (see FIG. 2J). Electrode forming step).

  A trench gate type MOSFET is manufactured by the above manufacturing method. Here, the source region forming step, the gate oxidation step, the gate forming step, the interlayer insulating layer forming step, the contact opening step, the silicidation step, and the electrode forming step are the same as the conventionally known manufacturing methods.

  However, in the above manufacturing method, in order to form the trench 20, an absorption layer forming step, an irradiation step, an absorption layer removing step, and an amorphous layer removing step are performed. Thereby, the trench 20 can be formed without using dry etching. This is the same as the technique described in Patent Document 3. However, in the technique described in Patent Document 3, it is difficult to implant ions deeply from the surface of the semiconductor layer, so that it is difficult to form a deep ion irradiation damaged layer. On the other hand, in the above manufacturing method, the amorphous layer 7 can be formed deeply by setting the film thickness of the carbon cap layer 30 and the irradiation conditions of the laser light 100. Therefore, the trench 20 can be easily formed by wet etching the amorphous layer 7.

  Further, in the absorption layer forming step, by forming the carbon cap layer 30 wide, a trench having a wide opening width and a deep depth can be formed, and by forming the carbon cap layer 30 narrow, the opening width can be reduced. Since a narrow and shallow trench can be formed, trenches having different depths can be easily formed in the same process.

  In the above example, the carbon cap layer 30 is used as the absorption layer. However, the laser light 100 can be absorbed, and the heat generated thereby can be transmitted to the semiconductor layer directly below to cause amorphization. If it is a material, it is also possible to use the absorption layer which consists of another material. However, since the carbon cap layer 30 is made of carbon (C) which is one of the elements constituting the semiconductor layer (SiC), unlike the metal mask conventionally used when forming the trench by dry etching, The semiconductor layer is not adversely affected as an impurity. Further, as shown in the absorption layer forming step and the absorption layer removing step, the formation and removal thereof are extremely easy. For this reason, it is particularly preferable to use the carbon cap layer 30.

(Second Embodiment)
FIG. 3 shows a second embodiment. In the first embodiment, the trench in the cell portion is formed deeper than the trench in the outer peripheral portion. However, in the present embodiment, the trench gate type in which the trench in the outer peripheral portion is formed deeper than the trench in the cell portion. MOSFET. By deepening the trench in the outer peripheral portion with respect to the trench in the cell portion, electrolytic concentration can be caused in the outer peripheral portion, and the leak portion can be made into the outer peripheral portion.

  In the above example, an example of manufacturing a trench gate type MOSFET has been described. However, it is obvious that a semiconductor device using a trench structure can be manufactured in the same manner.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Pre-implantation oxide film 3 Resist 4 p-type well region 5 n ⁺ layer 6 p ⁺ layer 7 Amorphous layer 8 Gate oxide film 9 Polycrystalline silicon layer 10 Interlayer insulating layer 11 Source wiring 12 Drain electrode 16 Silicide layer 20 Trench 30 Carbon cap layer 100 Laser light

Claims (7)

A method of manufacturing a semiconductor device comprising a configuration in which at least two kinds of first and second grooves having different depths are formed in a semiconductor layer made of silicon carbide (SiC),
An absorption layer forming step of locally forming an absorption layer for absorbing light on the surface of the semiconductor layer;
In the absorption layer forming step, absorption layers having different pattern widths are formed corresponding to the openings of the first groove and the second groove,
An irradiation step of irradiating the semiconductor layer with light from the side on which the absorption layer is formed;
An amorphous layer removing step of forming the groove by removing the amorphous layer formed in the semiconductor layer by the irradiation step by wet etching;
A method for manufacturing a semiconductor device, comprising: The semiconductor device comprises a cell portion including a plurality of transistor cells in which a trench-type gate is formed in a semiconductor layer and diffusion layers are formed on both sides of the gate, and an outer peripheral portion surrounding the cell portion.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the pattern width of the absorption layer is formed narrower in an outer peripheral portion than in the cell portion. The semiconductor device comprises a cell portion including a plurality of transistor cells in which a trench-type gate is formed in a semiconductor layer and diffusion layers are formed on both sides of the gate, and an outer peripheral portion surrounding the cell portion.
2. The method of manufacturing a semiconductor device according to claim 1, wherein a pattern width of the absorption layer is formed wider in an outer peripheral portion than in the cell portion. The wavelength of the light is a wavelength exceeding the wavelength of the light of energy corresponding to the forbidden bandwidth of the material constituting the semiconductor layer,
By setting the thickness of the absorption layer so that the heat generation of the absorption layer that has absorbed the light is transmitted to the semiconductor layer, the semiconductor layer becomes amorphous.
4. The method of manufacturing a semiconductor device according to claim 1, wherein, in the irradiation step, the amorphous layer is formed in the semiconductor layer immediately below the absorption layer. 5.   The method for manufacturing a semiconductor device according to claim 1, wherein the absorption layer is made of graphite.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. 7. The semiconductor device according to claim 6, wherein the semiconductor device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which a gate oxide film and a gate electrode are formed in the trench.

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